CN112582265B - Semiconductor structure and forming method thereof - Google Patents
Semiconductor structure and forming method thereof Download PDFInfo
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- CN112582265B CN112582265B CN201910927414.1A CN201910927414A CN112582265B CN 112582265 B CN112582265 B CN 112582265B CN 201910927414 A CN201910927414 A CN 201910927414A CN 112582265 B CN112582265 B CN 112582265B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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Abstract
A semiconductor structure and a method for forming the same, the method for forming the same includes: providing a substrate for forming a first type transistor, the substrate having one or more stacked channel stacks formed thereon; forming a gate structure on the substrate across the channel stack; etching channel lamination at two sides of the grid structure to form a groove; etching the sacrificial layer at the side part of the groove along the length direction of the channel layer to form a groove, wherein the groove is surrounded by the channel layer and the rest sacrificial layer; filling a diffusion source doping layer doped with doping ions of a second type which is different from the first type in the groove; performing heat treatment on the diffusion source doping layer to diffuse second type doping ions into the channel layer to form an inversion doping region; and forming a source-drain doped region in the groove. The doping of the second type doping ions in the channel layer is beneficial to reducing the flicker noise of the device, and the doping is carried out in a solid source diffusion mode, so that the damage to the channel layer is reduced.
Description
Technical Field
Embodiments of the present disclosure relate to semiconductor manufacturing, and more particularly, to a semiconductor structure and a method for forming the same.
Background
With the rapid development of semiconductor manufacturing technology, semiconductor devices are being developed toward higher element density and higher integration, and the development trend of semiconductor process nodes following moore's law is continuously decreasing. Transistors are currently being widely used as the most basic semiconductor devices, and therefore, as the element density and integration level of the semiconductor devices are increased, the channel length of the transistors has to be continuously shortened in order to accommodate the reduction of process nodes.
To better accommodate the demand for device scaling, semiconductor processes are increasingly beginning to transition from planar transistors to three-dimensional transistors with higher power, such as Gate-all-around (GAA) transistors. In the fully-enclosed gate transistor, the gate encloses the region where the channel is located from the periphery, and compared with a planar transistor, the gate of the fully-enclosed gate transistor has stronger control capability on the channel and can better inhibit the short channel effect.
In addition, flicker noise (e.g., 1/f noise) of a transistor is one of important design requirements. One current method of forming low flicker noise devices is to form Buried channels (Buried channels) in the transistor such that carriers in the Buried channels are less affected by trapping and de-trapping.
Disclosure of Invention
The embodiment of the invention solves the problem of providing a semiconductor structure and a forming method thereof, and improves the performance of the semiconductor structure.
In order to solve the above problems, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate for forming a first type transistor, wherein one or more stacked channel stacks are formed on the substrate, and each channel stack comprises a sacrificial layer and a channel layer positioned on the sacrificial layer; forming a gate structure on the substrate across the channel stack, the gate structure covering a portion of a top and a portion of a sidewall of the channel stack; etching channel lamination layers on two sides of the gate structure, and forming grooves in the channel lamination layers on two sides of the gate structure; etching the sacrificial layer with the thickness of the side part of the groove along the length direction of the channel layer to form a groove, wherein the groove is surrounded by the channel layer and the rest sacrificial layer; filling a diffusion source doping layer in the groove, wherein doping ions with a second type of conductivity are doped in the diffusion source doping layer, and the second type is different from the first type; performing heat treatment on the diffusion source doping layer to diffuse the second type doping ions into the channel layer, and forming an inversion doping region in the channel layer; and after the diffusion source doping layer is subjected to heat treatment, source and drain doping regions are formed in the grooves.
Correspondingly, the embodiment of the invention also provides a semiconductor structure, which comprises: a substrate for forming a first type transistor; the channel structure layer is positioned on the substrate and is arranged at intervals with the substrate, and the channel structure layer comprises one or more channel layers arranged at intervals; a metal gate structure crossing the channel structure layer and covering a part of the top of the channel structure layer, wherein the metal gate structure also surrounds the channel layer, the metal gate structure between the channel layers and between the channel layer and the substrate is a first part, and the side wall of the first part is retracted relative to the side wall of the channel layer along the length direction of the channel layer; an inversion doped region located in the channel layer; the diffusion source doping layers are positioned on the side walls of the two sides of the first part along the length direction of the channel layer, doped ions with the second type of conduction type are doped in the diffusion source doping layers, the second type of conduction type is different from the first type of conduction type, and the diffusion source doping layers are used for diffusing the doped ions with the second type into the channel layer to form the inversion type doped region; and the source-drain doped region is positioned at two sides of the metal gate structure and covers the channel layer and the diffusion source doped layer.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following advantages:
in the method for forming the semiconductor structure, firstly, the sacrificial layer at the side part of the groove is etched along the length direction of the channel layer to form the groove, the diffusion source doping layer is filled in the groove, and then the diffusion source doping layer is subjected to heat treatment, so that the second type doping ions diffuse into the channel layer to form the inversion doping region. Compared with the scheme that the second type doping ions are doped in the channel layer in an ion implantation mode to form the inversion doped region, the method is implemented to dope the second type doping ions in the channel layer in a solid source diffusion mode, so that the damage of the solid source diffusion to the channel layer is small, the interface state of the channel layer is improved, the lattice defects generated in the channel layer are reduced, and the performance of the semiconductor structure is improved.
Drawings
Fig. 1 to 13 are schematic structural views corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention.
Detailed Description
As known from the background art, one current approach to reduce device flicker noise is to form buried channels in transistors. Specifically, the method adopts an ion implantation mode to dope ions in the channel layer of the fully-enclosed grid transistor so as to form an inversion doped region, and the channel layer where the inversion doped region is positioned is used as a buried channel.
However, the use of ion implantation tends to cause large implantation damage to the channel layer, for example: larger lattice defects are generated on the channel layer, the surface quality of the channel layer is reduced, and further the performance of the device is easily reduced.
Moreover, as the device size is further reduced, the damage to the channel layer caused by the ion implantation has more and more significant effect on the device performance, and is more likely to cause poor device performance.
In order to solve the technical problem, in the method for forming the semiconductor structure of the embodiment of the invention, the diffusion source doping layer is filled in the groove, and then the diffusion source doping layer is subjected to heat treatment, so that the second type doping ions diffuse into the channel layer to form an inversion doping region, that is, the second type doping ions are doped in the channel layer in a solid source diffusion manner to form the inversion doping region, and the channel layer where the inversion doping region is located is used as a buried channel, so that the conducting channel is away from the surface of the channel layer in the operation of the device, the problem of carrier scattering on the surface of the channel layer in the operation of the device is solved, and the flicker noise of the device is reduced. Compared with the scheme that the second type doping ions are doped in the channel layer in an ion implantation mode to form the inversion doped region, the method is implemented to dope the second type doping ions in the channel layer in a solid source diffusion mode, so that the damage of the solid source diffusion to the channel layer is small, the interface state of the channel layer is improved, the lattice defects generated in the channel layer are reduced, and the performance of the semiconductor structure is improved.
In order that the above objects, features and advantages of embodiments of the invention may be readily understood, a more particular description of the invention will be rendered by reference to specific embodiments thereof which are illustrated in the appended drawings.
Fig. 1 to 13 are schematic structural views corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention.
Referring to fig. 1 and 2, which show a cross-sectional view along the extension of the channel stack and a cross-sectional view along the extension of the vertical channel stack, respectively, a substrate is provided for forming a first type transistor, on which one or more stacked channel stacks 120 are formed, each channel stack 120 comprising a sacrificial layer 10 and a channel layer 11 on the sacrificial layer 10.
The substrate provides a process platform for forming a Gate-all-around (GAA) transistor.
The substrate is used for forming a first type transistor. Wherein the first type refers to the doping type of the source-drain doping region in the transistor. Specifically, the first type transistor may be an N-type MOS transistor or a P-type MOS transistor.
In this embodiment, the substrate is a three-dimensional substrate, and the substrate includes a substrate 100 and a fin portion 110 protruding from the substrate 100. In other embodiments, when the base is a planar structure, the base includes only the substrate, respectively.
In this embodiment, the substrate 100 is a silicon substrate.
The fins 110 protrude from the substrate 100 to provide a process basis for forming isolation structures.
In this embodiment, the material of the fin 110 is the same as that of the substrate 100, and the material of the fin 110 is silicon.
In this embodiment, the channel stack 120 is located on top of the fin 110, and the extending direction of the channel stack 120 is the same as the extending direction of the fin 110.
The stacking direction of the plurality of stacked channel stacks 120 is perpendicular to the surface of the substrate 100.
In the present embodiment, two stacked channel stacks 120 are taken as an example, and the two stacked channel stacks 120 are a bottom channel stack and a top channel stack, respectively.
The bottom channel stack and the top channel stack each comprise a sacrificial layer 10 and a channel layer 11 on the sacrificial layer 10, so that the channel layer 11 can be formed in a floating spaced apart arrangement after subsequent removal of the sacrificial layer 10. Specifically, the sacrificial layer 10 is used to support the channel layer 11, and also occupies a space for the formation of a subsequent metal gate structure, and the channel layer 11 is used to provide a channel of the fully-enclosed gate transistor.
In this embodiment, the material of the channel layer 11 is Si, and the material of the sacrificial layer 10 is SiGe. In the subsequent process of removing the sacrificial layer 10, the etching selection of SiGe and Si is relatively high, so that the effect of the removal process of the sacrificial layer 10 on the channel layer 11 can be effectively reduced by setting the material of the sacrificial layer 10 to SiGe and the material of the channel layer 11 to Si, thereby improving the quality of the channel layer 11 and further being beneficial to improving the device performance. In other embodiments, to enhance the performance of the PMOS device when formed, siGe channel technology may be used, where the fin and channel layer are SiGe and the sacrificial layer is Si.
In this embodiment, the number of channel stacks 120 is two. In other embodiments, the number of channel stacks may also be more than two.
In this embodiment, an isolation structure 115 is further formed on the substrate 100 at the side of the fin 110, and the isolation structure 115 exposes the channel stack 120.
The isolation structures 115 are used to isolate adjacent devices.
In this embodiment, the material of the isolation structure 115 is silicon oxide.
In this embodiment, the top surface of the isolation structure 115 is flush with the top surface of the fin 110.
Referring to fig. 3, a gate structure is formed on the substrate across the channel stack 120, the gate structure covering a portion of the top and a portion of the sidewalls of the channel stack 120.
In this embodiment, the gate structure is a dummy gate structure, and the gate structure occupies a space for a subsequently formed metal gate structure.
In this embodiment, the gate structure is a stacked structure, and the gate structure includes a gate oxide layer 125 and a gate electrode layer 130 on the gate oxide layer 125. Wherein the gate oxide 125 is located on the surface of the channel stack 120, and the gate electrode 130 is located on the gate oxide 125 and spans the channel stack 120.
In this embodiment, the gate oxide layer 125 is made of silicon oxide.
In this embodiment, the material of the gate electrode layer 130 is polysilicon.
In this embodiment, the step of forming the gate electrode layer 130 includes: forming a gate electrode material layer (not shown) over channel stack 120; forming a gate mask layer 135 on the gate electrode material layer; with the gate mask layer 135 as a mask, a portion of the gate electrode material layer is removed and the remaining gate electrode material layer on the channel stack 120 serves as the gate electrode layer 130.
Wherein the gate mask layer 135 is used as an etching mask when forming the gate electrode layer 130, the gate mask layer 135 can also protect the top of the gate electrode layer 130 in a subsequent process.
In this embodiment, the material of the gate mask layer 135 is silicon nitride.
In this embodiment, the gate structure further includes a sidewall 140 on the sidewall of the gate electrode layer 130.
The side wall 140 is used as an etching mask for a subsequent etching process to define a formation region of the source/drain doped region, and the side wall 140 is also used to protect the side wall of the gate electrode layer 130.
In this embodiment, the side wall 140 is a single-layer structure, and the material of the side wall 140 is silicon nitride.
Referring to fig. 4, the channel stack 120 on both sides of the gate structure is etched, forming a recess 200 in the channel stack 120 on both sides of the gate structure. The sidewalls of the recess 200 expose the channel stack 120 remaining under the gate structure.
The recess 200 is used to provide a space for the subsequent formation of source-drain doped regions.
The sidewalls of the recess 200 expose the channel stack 120 remaining under the gate structure in preparation for subsequent etching of portions of the sacrificial layer 10 along the length of the channel layer 11.
In this embodiment, the fin 110 is exposed at the bottom of the recess 200.
In this embodiment, the channel stack 120 on both sides of the gate structure is etched using an anisotropic dry etching process. The dry etching process has the characteristic of anisotropic etching, has good etching profile control, is beneficial to improving the profile shape quality of the groove 200, and is also beneficial to improving the etching efficiency.
Referring to fig. 5, the sacrificial layer 10 of the side portion of the recess 200 is etched in the direction of the length of the channel layer 11 to form a trench 300, and the trench 300 is surrounded by the channel layer 11 and the remaining sacrificial layer 10.
In this embodiment, the trenches 300 are formed between the adjacent channel layers 11, and between the channel layers 11 and the substrate. The trenches 300 are used to provide spatial locations for the subsequent formation of diffusion source dopant layers.
The depth of the trench 300 is not too small nor too large along the length of the channel layer 11. If the depth of the trench 300 is too small, the space provided by the trench 300 for forming the diffusion source doped layer later is too small, and the volume of the formed diffusion source doped layer is too small, so that the total amount of the doping ions provided in the diffusion source doped layer is insufficient, and further, when the diffusion source doped layer is subjected to heat treatment later, the concentration and the doping profile of the doping ions in the diffusion source doped layer diffused to an inversion doped region formed in the channel layer 11 are difficult to meet the process requirements; if the depth of the trench 300 is too large, the dimensions of the remaining sacrificial layer 10 are correspondingly too small along the length of the channel layer 11, and the subsequent steps include forming a metal gate structure at the location of the sacrificial layer 10, which easily results in a difficulty in filling the metal gate structure between adjacent channel layers 11, and an undersize of the metal gate structure along the length of the channel layer 11, which easily results in an excessively small effective channel length of the device. For this reason, in the present embodiment, the depth of the trench 300 is 1nm to 4nm along the length direction of the channel layer 11.
In this embodiment, the gate structure includes a gate electrode layer 130; after etching the sacrificial layer 10 at the side part of the groove 200 to form the trench 300, along the length direction of the channel layer 11, the side wall of the remaining sacrificial layer 10 is flush with the side wall of the gate electrode layer 130, or the side wall of the remaining sacrificial layer 10 protrudes out of the side wall of the gate electrode layer 130, so that the size of the sacrificial layer 10 between adjacent channel layers 11 is not too small, and further, after the sacrificial layer 10 is removed later, the space between the adjacent channel layers 11 is larger, which is beneficial to the Gap filling (Gap filling) of the subsequent metal gate structure between the adjacent channel layers 11, and is also beneficial to preventing the size of the subsequent metal gate structure between the adjacent channel layers 11 from being too small, and further, the effective channel length of the device meets the process requirements.
In this embodiment, a wet etching process is used to etch a portion of the sacrificial layer 10 on the side of the recess 200. The wet etching process is an isotropic etching process, so that the sacrificial layer 10 can be etched along the length direction of the channel layer 11, and the wet etching process is easy to realize a larger etching selection ratio, thereby being beneficial to reducing the difficulty of etching the sacrificial layer 10 and reducing the probability of damaging other film structures.
In this embodiment, the material of the sacrificial layer 10 is SiGe, the material of the channel layer 11 is Si, and the exposed sacrificial layer 10 is wet etched by HCl vapor. The etching rate of HCl vapor to the SiGe material is much greater than that to the Si material, so that the use of HCl vapor to etch a portion of the sacrificial layer 10 at the side of the recess 200 can effectively reduce the probability of damage to the channel layer 11.
In other embodiments, when the material of the channel layer is SiGe and the material of the sacrificial layer is Si, the etching solution used in the wet etching process is a tetramethylammonium hydroxide (TMAH) solution. The difference between the etching rate of the tetramethyl ammonium hydroxide solution to the Si material and the etching rate to the SiGe material is large, so that the probability of loss of the channel layer can be effectively reduced by adopting the tetramethyl ammonium hydroxide solution to etch the sacrificial layer.
It should be noted that, in the semiconductor field, the step of forming the inner wall layer on the side wall of the sacrificial layer 10 is generally further included, and the step of forming the inner wall layer generally needs to etch the sacrificial layer 10 exposed by the groove 200 to form a trench, so in this embodiment, the trench 300 can be formed by using the process of etching the sacrificial layer 10 exposed by the groove 200 when forming the inner wall layer, the process of forming the diffusion source doping layer and the process of forming the inner wall layer are integrated, the process compatibility is high, the process of etching the sacrificial layer 10 is mature, the process difficulty is low, and the process risk and the process variation are reduced.
Referring to fig. 6, a diffusion source doping layer 150 is filled in the trench 300, and the diffusion source doping layer 150 is doped with doping ions having a second type of conductivity, which is different from the first type.
The diffusion source doping layer 150 is used as a solid diffusion source for a subsequent thermal diffusion doping process. That is, the subsequent heat treatment of the diffusion source doping layer 150 further includes diffusing the second type doping ions into the channel layer 11 to form an inversion doping region in the channel layer 11.
The channel layer 11 where the inversion doped region is located is used as a buried channel, which is favorable for enabling a conductive channel to be far away from the surface of the channel layer 11 when the device works, so that the problem of carrier scattering on the surface of the channel layer 11 when the device works is solved, and the flicker noise of the device is reduced.
In addition, compared with the scheme that the second type doping ions are doped in the channel layer in an ion implantation mode to form an inversion doped region, the second type doping ions are doped in the channel layer 11 in a solid source diffusion mode, so that the damage of the solid source diffusion to the channel layer 11 is small, the interface state of the channel layer 11 is improved, the lattice defects generated in the channel layer 11 are reduced, and the performance of the semiconductor structure is further improved.
In this embodiment, the material of the diffusion source doping layer 150 includes silicon oxide doped with a second type of doping ions.
The silicon oxide is an insulating material commonly used and easily obtained in the semiconductor process, which is beneficial to reducing the process cost of forming the diffusion source doping layer 150 and improving the process compatibility; moreover, by selecting an insulating material, and performing a subsequent heat treatment to diffuse the second type doped ions into the channel layer 11 to form an inversion doped region, the diffusion source doped layer 150 has a small influence on the electrical properties of the semiconductor structure, and the diffusion source doped layer 150 can be kept in the semiconductor structure without removal, which is beneficial to simplifying the process and reducing the complexity of the process.
In this embodiment, the first type transistor is an N type MOS transistor, and the diffusion source doping layer 150 is doped with P type doping ions. That is, the second type is P-type, and the second type doping ions are P-type ions, for example: and (3) phosphorus ions. Accordingly, the material of the diffusion source doping layer 150 may include phosphorus doped silicon oxide (PSG)
In the step of forming the diffusion source doping layer 150, the doping concentration of the second type of doping ions in the diffusion source doping layer 150 should not be too small or too large. If the doping concentration is too small, the difference between the doping ion concentrations of the diffusion source doping layer 150 and the channel layer 11 is too small, so that the effect of diffusing the second type doping ions into the channel layer 11 during the subsequent heat treatment is easily reduced, the concentration and doping profile of the formed inversion doping region are easy to cause that the process requirement is difficult to be met, and the effect of improving the flicker noise of the device is difficult to be achieved; if the doping concentration is too high, the ion doping concentration in the inversion doped region is correspondingly too high, and the risk of electric leakage of the device is easily increased. For this reason, in the embodiment, the first type transistor is an N type MOS transistor, the second type dopant ions are P type dopant ions, and in the step of forming the diffusion source dopant layer 150, the doping concentration of the second type dopant ions in the diffusion source dopant layer 150 is 1.0e19 atoms per cubic centimeter to 8.0E20 atoms per cubic centimeter.
In other embodiments, when the first type transistor is a P-type MOS transistor, the diffusion source doped layer is doped with N-type dopant ions. That is, the second type is N-type, and the second type dopant ions are N-type dopant ions, for example: boron ions. The material of the diffusion source doped layer may include boron doped silicon oxide (BSG).
Correspondingly, when the second type doping ions are N type doping ions, in order to ensure that the concentration and the doping profile of the inversion doping region formed in the channel layer meet the process requirements, in the step of forming the diffusion source doping layer, the doping concentration of the second type doping ions in the diffusion source doping layer is 2.0E19 atoms per cubic centimeter to 2.0E21 atoms per cubic centimeter.
In this embodiment, filling the diffusion source doping layer 150 in the trench 300 means that the diffusion source doping layer 150 is filled in the trench 300 in a direction along the bottom of the trench 300 toward the top of the trench 300, that is, the diffusion source doping layer 150 contacts with the upper and lower surfaces of the adjacent channel layer 11 and the side surface of the sacrificial layer 10, so that the second type doping ions in the diffusion source doping layer 150 can diffuse into the channel layer 11 during the subsequent heat treatment.
In this embodiment, the step of forming the diffusion source doping layer 150 includes: forming a doped material layer (not shown) in the trench 300, the doped material layer also being formed on the top and sidewalls of the gate structure, the sidewalls of the channel layer 11, and the substrate surface; the doped material layer on the top and sidewalls of the gate structure, the sidewalls of the channel layer 11, and the substrate surface is removed, and the remaining doped material layer in the trench 300 serves as the diffusion source doped layer 150.
In this embodiment, the doped material layer is formed by a deposition process, which includes an atomic layer deposition process. The gap filling performance and the step coverage capability of the atomic layer deposition process are good, which is beneficial to improving the conformal coverage capability of the doped material layer and the filling capability in the groove 300, and the atomic layer deposition process comprises multiple atomic layer deposition cycles to form a film layer with a required thickness, which is beneficial to improving the thickness uniformity of the doped material layer and is easy to accurately control the thickness of the doped material layer.
Specifically, along the length of the channel layer 11, a doped material layer is deposited on the sidewall and bottom of the trench 300, and as the deposited thickness of the doped material layer increases, the doped material layer on the sidewall of the trench 300 gradually contacts, thereby gradually filling the trench 300. The sidewalls of the trench 300 refer to the lower and upper surfaces of the channel layer 11 exposed by the trench 300.
In other embodiments, the process of forming the doped material layer may further include a chemical vapor deposition process. The process cost of chemical vapor deposition is low.
In this embodiment, a dry etching process is used to remove the doped material layer on the top and side walls of the gate structure, the side walls of the channel layer 11, and the surface of the substrate. Specifically, by adjusting the process parameters such as the etching bias power of the dry etching process, the ratio of isotropic etching to anisotropic etching can be adjusted, so that the doped material layer on the top of the gate structure and the substrate surface, and the doped material layer on the side wall of the gate structure and the side wall of the channel layer 11 can be removed.
Referring to fig. 7 in combination, in this embodiment, after the diffusion source doped layer 150 is formed, the method for forming a semiconductor structure further includes: and thinning the diffusion source doping layer 150.
The process further includes a step of forming an inner wall layer in the trench 300, by thinning the diffusion source doped layer 150, to provide a spatial location for forming the inner wall layer. Wherein the inner wall layer also protects the second type dopant ions in the diffusion source dopant layer 150 during subsequent heat treatment.
After the thinning process, the thickness of the remaining diffusion source doped layer 150 is not preferably too small or too large along the length of the channel layer 11. If the thickness of the remaining diffusion source doping layer 150 is too small, the total amount of doping ions in the diffusion source doping layer 150 is too small, which easily results in difficulty in meeting the process requirements in the concentration and doping profile of the inversion doping region formed in the channel layer 11 later; if the thickness of the remaining diffusion source doping layer 150 is too large, the formation space of the subsequent inner wall layer is too small, and the inner wall layer is too thin, so that the protection effect of the inner wall layer on the doping ions in the diffusion source doping layer 150 in the subsequent heat treatment process is easily reduced. For this reason, in the present embodiment, after the thinning process, the thickness of the remaining diffusion source doped layer 150 is one third to two thirds of the depth of the trench 300 along the length direction of the channel layer 11.
In this embodiment, the step of thinning the diffusion source doped layer 150 includes: the diffusion source doping layer 150 is etched by an isotropic dry etching process to a partial thickness in a direction along the length of the channel layer 11.
By adopting the isotropic etching process, the diffusion source doping layer 150 can be etched along the length direction of the channel layer 11, and the etching precision and the profile controllability of the dry etching process are good, so that the etching amount of the diffusion source doping layer 150 can be accurately controlled, and the thickness of the rest diffusion source doping layer 150 can meet the process requirement. Specifically, parameters such as bias voltage and pressure of the dry etching process are adjusted, for example: and a dry etching process with low bias power and high pressure is selected, so that isotropic etching can be realized.
In this embodiment, the main etching gas of the isotropic dry etching process may include a fluorine-based gas, for example: CF (compact flash) 4 、NF 3 Or SF 6 Etc.
Accordingly, referring to fig. 8, after the thinning process, an inner wall layer 155 is formed on the remaining sidewall of the diffusion source doping layer 150, and the trench 300 is filled.
After the metal gate structure is formed at the positions of the gate electrode layer 130 and the sacrificial layer 10, the Inner wall layer 155 serves as an Inner spacer (Inner spacer), which increases the distance between the metal gate structure and the source-drain doped region between the channel layers 11, thereby being beneficial to reducing parasitic capacitance between the metal gate structure and the source-drain doped region.
Further, the subsequent step further includes heat treating the diffusion source doped layer 150. In this embodiment, after the thinning treatment and before the heat treatment, the inner wall layer 155 is formed, and the inner wall layer 155 can protect the second type doped ions in the diffusion source doped layer 150 during the heat treatment, so as to prevent the problem of Out diffusion (Out diffusion) of the second type doped ions in the diffusion source doped layer 150, thereby preventing the loss of the second type doped ions in the diffusion source doped layer 150, and correspondingly improving the effect of the diffusion of the second type doped ions into the channel layer 11.
The material of the inner wall layer 155 may be silicon nitride, silicon oxide, silicon oxynitride, a low-k dielectric material, or an ultra-low-k dielectric material. In this embodiment, the material of the inner wall layer 155 is silicon nitride.
The silicon nitride is a dielectric material commonly used in the semiconductor process, the solid solubility of the silicon nitride is low, and the probability of diffusing the second type doping ions into the inner wall layer 155 in the subsequent heat treatment process is low, so that the protection effect of the inner wall layer 155 on the second type doping ions in the diffusion source doping layer 150 is improved.
Referring to fig. 9, the diffusion source doping layer 150 is subjected to a heat treatment 250 to diffuse the second type doping ions into the channel layer 11, thereby forming an inversion doping region in the channel layer 11.
The channel layer 11 where the inversion doped region is located is used as a buried channel, so that a conductive channel is away from the surface of the channel layer 11 when the device works, the problem that carriers are scattered on the surface of the channel layer 11 when the device works is solved, and the flicker noise of the device is reduced.
In addition, compared with the scheme that the second type doping ions are doped in the channel layer in an ion implantation mode to form an inversion doped region, the second type doping ions are doped in the channel layer 11 in a solid source diffusion mode, so that the damage of the solid source diffusion to the channel layer 11 is small, the interface state of the channel layer 11 is improved, the lattice defects generated in the channel layer 11 are reduced, and the performance of the semiconductor structure is further improved.
The formation of the source-drain doped regions in the recess 200 is further included, and the heat treatment 250 is performed before the formation of the source-drain doped regions in this embodiment, so as to prevent the influence of the heat treatment 250 on the ion distribution and the doping profile in the source-drain doped regions.
Specifically, the diffusion source doping layer 150 serves as a solid diffusion source, and when driven by thermal motion, the second type doping ions in the diffusion source doping layer 150 diffuse from the diffusion source doping layer 150 having a higher doping concentration into the channel layer 11, form a certain distribution in the channel layer 11, and further form an inversion doping region in the channel layer 11. The inversion doped region is formed by the way of diffusing impurity ions, so that the damage to the channel layer 11 is small, the interface state of the channel layer 11 is good, and the doping uniformity and the process safety of solid source diffusion are high.
In this embodiment, during the heat treatment 250, the second type dopant ions also diffuse into the middle region of the channel layer 11 under the gate electrode layer 130 along the direction of the channel layer 11. Thus, after heat treatment, the inversion doped regions are distributed throughout the channel layer 11 along the length of the channel layer 11, thereby providing a conductive channel for carriers during device operation.
The temperature of the heat treatment 250 is not too low nor too high. If the temperature is too low, the diffusion rate of the second type dopant ions is easily lowered, or insufficient diffusion of the second type dopant ions into the channel layer 11 in the diffusion source dopant layer 150 is easily caused; if the temperature is too high, the doping profile of other doped regions in the semiconductor structure is easily affected, or larger damage is easily caused to the semiconductor structure, and the process risk is easily increased. For this reason, in the present embodiment, the temperature of the heat treatment 250 is 850 ℃ to 1100 ℃.
In this embodiment, the heat treatment 250 is performed by annealing.
In this embodiment, the process time of the heat treatment 250 is 0 to 20 seconds, and the process pressure is one atmosphere, so that the diffusion rate of the second type doping ions and the uniformity of the doping ion distribution in the inversion doping region are improved in cooperation with the temperature of the heat treatment 250, and meanwhile, the doping ion concentration and the doping profile in the inversion doping region meet the process requirements, and the generated side effects are small.
The process time of the heat treatment 250 refers to the time that the heat treatment 250 is maintained at the highest temperature (Peak temperature), that is, the Peak Residence time (composition time). Wherein, when the process time of the heat treatment 250 is 0 seconds, the process of the heat treatment 250 is a Spike annealing (Spike antenna) process, and 0 seconds means that the peak residence time of the Spike annealing at the highest temperature is 0 seconds.
Referring to fig. 10, after the diffusion source doping layer 150 is subjected to a heat treatment 250, source drain doping regions 160 are formed in the grooves 200.
In this embodiment, the step of forming the source-drain doped region 160 includes: a stress layer is formed in the recess 200 using an epitaxial process, and the source-drain doped regions 160 are formed in situ from the dopant ions during formation of the stress layer. The doping ions in the source/drain doped region 160 are of the first type.
When the fully-surrounding grid transistor is a P-type MOS transistor, the stress layer is made of Si or SiGe, and the first type of doping ions are P-type ions; when the fully-surrounding grid transistor is an N-type MOS transistor, the stress layer is made of Si or SiC, and the first type doped ions are N-type ions.
In this embodiment, the top surface of the source-drain doped region 160 is higher than the top surface of the channel stack 120, and the source-drain doped region 160 also covers a portion of the sidewall 140. In other embodiments, the top surface of the source-drain doped region may also be flush with the top surface of the channel stack.
In this embodiment, after the source-drain doped layer 160 is formed, the following process steps further include:
referring to fig. 11, an interlayer dielectric layer 165 is formed on the substrate at the side of the gate structure.
The interlayer dielectric layer 165 is used to achieve electrical isolation between adjacent semiconductor structures.
In this embodiment, the interlayer dielectric layer 165 is made of silicon oxide.
In this embodiment, the step of forming the interlayer dielectric layer 165 includes: forming a dielectric material layer (not shown) on the substrate at the side of the gate structure, wherein the dielectric material layer also covers the top of the gate structure; the dielectric material layer above the gate electrode layer 130 is removed and the remaining dielectric material layer serves as an interlayer dielectric layer 165.
In this embodiment, the dielectric material layer covers the top of the gate mask layer 135 (as shown in fig. 10), and thus, in the step of removing the dielectric material layer higher than the gate electrode layer 130, the gate mask layer 135 is also removed.
Referring to fig. 12, the gate electrode layer 130 and the gate oxide layer 125 at the bottom of the gate electrode layer 130 are removed, and a gate opening 170 exposing the channel stack 120 is formed in the interlayer dielectric layer 165; the sacrificial layer 10 in the channel stack 120 is removed, and a through groove 175 is formed, wherein the through groove 175 is surrounded by the adjacent channel layer 11 and the source-drain doped region 160, or the through groove 175 is surrounded by the substrate and the channel layer 11 and the source-drain doped region 160, and the through groove 175 is communicated with the gate opening 170.
The gate opening 170 and the via 175 provide a spatial location for the subsequent formation of a metal gate structure.
In this embodiment, the gate electrode layer 130 and the gate oxide layer 125 located at the bottom of the gate electrode layer 130 are removed by a dry etching process.
In this embodiment, a wet etching process is used to remove the sacrificial layer 10. Specifically, the material of the channel layer 11 is Si, and the material of the sacrificial layer 10 is SiGe, so that the sacrificial layer 10 exposed by the gate opening 350 is removed by HCl vapor, and the etching rate of the sacrificial layer 10 by the wet etching process is much greater than the etching rate of the channel layer 11 and the fin 110.
The sacrificial layer 10 is removed after the source-drain doped region 160 is formed, so that after the sacrificial layer 10 is removed, two ends of the channel layer 11 are connected with the source-drain doped region 160 along the extending direction of the fin portion 110 and suspended in the gate opening 170, thereby providing a foundation for surrounding the channel layer 11 by a subsequent metal gate structure.
After the sacrificial layer 10 is removed, the channel layers 11 are arranged at intervals, the rest of the channel layers 11 form a channel structure layer 180, and the channel structure layer 180 is positioned on the substrate and is arranged at intervals with the substrate.
Referring to fig. 13, a metal gate structure 190 is formed in the gate opening 170 and the via 175.
The metal gate structure 190 is used to control the opening and closing of the conductive channel during operation of the device.
The gate opening 170 is in communication with the via 175, so that during formation of the metal gate structure 190 in the gate opening 170, the metal gate structure 190 also fills the via 175.
Specifically, the metal gate structure 190 spans the channel structure layer 190 and covers a portion of the top of the channel structure layer 190, the metal gate structure 190 also surrounding the channel layer 11. Wherein the metal gate structure 190 in the via 175 is a first portion 191 and the metal gate structure 190 in the gate opening 170 is a second portion 192.
The metal gate structure 190 includes a high-k gate dielectric layer (not shown) and a metal gate electrode layer (not shown) on the high-k gate dielectric layer. Specifically, the high-k gate dielectric layer is located on the upper, lower, and sides of the channel layer 11, and also covers portions of the top and portions of the sidewalls of the fin 110.
In this embodiment, the material of the high-k gate dielectric layer is HfO 2 。
In this embodiment, the material of the metal gate electrode layer is W.
The metal gate structure may also include other functional layers, such as: work function layers, and the like.
Correspondingly, the invention further provides a semiconductor structure. Referring to fig. 13, a schematic structure diagram of an embodiment of the semiconductor structure of the present invention is shown.
The semiconductor structure includes: a substrate for forming a first type transistor; a channel structure layer 180 on and spaced apart from the substrate, the channel structure layer 180 including one or more channel layers 11 spaced apart; a metal gate structure 190 crossing the channel structure layer 180 and covering a portion of the top of the channel structure layer 180, the metal gate structure 190 further surrounding the channel layer 11, the metal gate structure 190 being a first portion 191 located between the channel layers 11 and between the channel layer 11 and the substrate, sidewalls of the first portion 191 being recessed with respect to sidewalls of the channel layer 180 along a length direction of the channel layer 11; an inversion doped region (not shown) in the channel layer 11; the diffusion source doping layers 150 are located on two side walls of the first portion 191 along the length direction of the channel layer 11, doped ions with a second type of conductivity are doped in the diffusion source doping layers 150, the second type is different from the first type, and the diffusion source doping layers 150 are used for diffusing the doped ions with the second type into the channel layer to form the inversion doping region; the source-drain doped region 160 is located at two sides of the metal gate structure 190 and covers the channel layer 11 and the diffusion source doped layer 150.
The semiconductor structure comprises an inversion doped region, and the channel layer 11 where the inversion doped region is located is used as a buried channel, so that a conducting channel is away from the surface of the channel layer 11 when the device works, the problem that carriers are scattered on the surface of the channel layer 11 when the device works is solved, and the flicker noise of the device is reduced.
In addition, in the present embodiment, the inversion doped region is formed by diffusing the second type doped ions in the diffusion source doped layer 150 into the channel layer 11, that is, the inversion doped region is formed in the channel layer 11 by solid source diffusion, and compared with the solution in which the inversion doped region is formed in the channel layer by ion implantation, the damage of the solid source diffusion to the channel layer 11 is small, which is beneficial to improving the interface state of the channel layer 11, reducing the lattice defects generated in the channel layer 11, and further improving the performance of the semiconductor structure.
The substrate provides a process platform for forming a fully-surrounding gate transistor.
The substrate is used for forming a first type transistor. Wherein the first type refers to the doping type in the source drain doped region 160 in the transistor. Specifically, the first type transistor may be an N-type MOS transistor or a P-type MOS transistor.
In this embodiment, the substrate is a three-dimensional substrate, and the substrate includes a substrate 100 and a fin portion 110 protruding from the substrate 100. In this embodiment, the substrate 100 is a silicon substrate.
The fins 110 protrude from the substrate 100 to provide a process basis for forming isolation structures.
In this embodiment, the material of the fin 110 is the same as that of the substrate 100, and the material of the fin 110 is silicon.
The channel layer 11 is used to provide the channel of the fully surrounding gate transistor.
In this embodiment, the material of the channel layer 11 is the same as that of the fin 110, and the material of the channel layer 11 is Si.
In this embodiment, the channel structure layer 180 is located at the top of the fin 110, and the extending direction of the channel structure layer 180 is the same as the extending direction of the fin 110.
The stacking direction of the plurality of stacked channel layers 11 is perpendicular to the surface of the substrate 100.
In this embodiment, the number of channel layers 11 is two. In other embodiments, the number of channel layers may also be not limited to just two.
The semiconductor structure further includes: isolation structures 115 are located on substrate 100 on the sides of fin 110, isolation structures 115 exposing channel structure layer 180. Isolation structures 115 are used to isolate adjacent devices.
In this embodiment, the material of the isolation structure 115 is silicon oxide.
In this embodiment, the top surface of the isolation structure 115 is flush with the top surface of the fin 110.
The metal gate structure 190 is used to control the turning on and off of the conduction channel when the transistor is in operation.
The metal gate structure 190 includes a high-k gate dielectric layer (not shown) and a metal gate electrode layer (not shown) on the high-k gate dielectric layer. Specifically, the high-k gate dielectric layer is located on the upper, lower, and sides of the channel layer 11, and also covers portions of the top and portions of the sidewalls of the fin 110.
In this embodiment, the material of the high-k gate dielectric layer is HfO 2 。
In this embodiment, the material of the metal gate electrode layer is W.
Along the length direction of the channel layer 11, the sidewall of the first portion 191 is retracted relative to the sidewall of the channel layer 11, so that the adjacent channel layer 11 and the first portion 191, and the channel layer 11 and the substrate and the first portion 191 enclose the trench 300 (as shown in fig. 5), thereby providing a space position for forming the diffusion source doped layer 150.
The dimension of the sidewall of the first portion 191 which is recessed with respect to the sidewall of the channel layer 11 in the direction of the length of the channel layer 11 is not preferably too small nor too large. If the size of the recess is too small, the space provided by the trench 300 for forming the diffusion source doping layer 150 is too small, and the volume of the diffusion source doping layer 150 is too small, so that the concentration and doping profile of the second type doping ions in the diffusion source doping layer 150 diffused into the inversion doping region formed in the channel layer 11 are liable to be difficult to meet the process requirements; if the dimensions of the indentations are too large, the dimensions of the first portion 191 are correspondingly too small, which in turn tends to result in an effective channel length of the device that is too small. For this reason, in the present embodiment, the sidewall of the first portion 191 is recessed 1nm to 4nm with respect to the sidewall of the channel layer 11 in the direction of the length of the channel layer 11.
In this embodiment, the metal gate structure 190 on top of the channel structure layer 180 is a second portion 192; along the length direction of the channel layer 11, the side wall of the first portion 191 is flush with the side wall of the second portion 192, or the side wall of the first portion 191 protrudes from the side wall of the second portion 192, so that the size of the first portion 191 is not too small, and the difficulty of gap filling between adjacent channel layers 11 by the metal gate structure 190 is low when the metal gate structure 190 is formed.
The second portion 192 also includes a metal gate structure 190 that spans the channel structure layer 180 and covers the sides of the channel layer 11.
The semiconductor structure further includes: and a sidewall 140 on a sidewall of the second portion 192.
The sidewall 140 is used to define a formation region of the source drain doped region 160, and the sidewall 140 is also used to protect the sidewall of the second portion 192.
In this embodiment, the side wall 140 has a single-layer structure, and the material of the side wall 140 is silicon nitride.
In this embodiment, the metal gate structure 190 is formed by a process of forming a metal gate electrode (High k last metal gate last) after forming a high-k gate dielectric layer, and the gate structure adopted before forming the metal gate structure 190 is a stacked structure, so the semiconductor structure further includes: gate oxide 125 is located between sidewall 140 and channel structure 180. Wherein the gate oxide layer 125 between the sidewall 140 and the channel structure layer 180 is preserved under the coverage of the sidewall 140 during the process of removing the gate structure to form the metal gate structure 190.
The diffusion source doping layer 150 is used as a solid diffusion source for the thermal diffusion doping process. That is, the inversion doped region is formed by performing heat treatment on the diffusion source doped layer 150 to diffuse the second type doped ions into the channel layer 11, so that the solid source diffusion has small damage to the channel layer 11, which is beneficial to reducing the lattice defect generated in the channel layer 11 and improving the interface state of the channel layer 11, thereby improving the performance of the semiconductor structure.
Accordingly, the inversion doped region is located in the channel layer 11, and the doping ions in the inversion doped region are the same type as the doping ions in the diffusion source doped layer 150. In this embodiment, the inversion doped regions are distributed throughout the channel layer 11 along the length of the channel layer 11 to provide a conductive path for carriers during operation of the device.
In this embodiment, the material of the diffusion source doping layer 150 includes silicon oxide doped with a second type of doping ions.
The silicon oxide is an insulating material commonly used and easily obtained in the semiconductor process, which is beneficial to reducing the process cost of forming the diffusion source doping layer 150 and improving the process compatibility, and the diffusion source doping layer 150 has small influence on the electrical property of the semiconductor structure by selecting the insulating material, so that the diffusion source doping layer 150 can be kept in the semiconductor structure without being removed, the process is beneficial to simplifying the process and reducing the process complexity, and in addition, the diffusion source doping layer 150 can also play a role of isolating between the first part 191 and the source-drain doping region 160, correspondingly increasing the distance between the first part 191 and the source-drain doping region 160, and further being beneficial to reducing the parasitic capacitance between the metal gate structure 190 and the source-drain doping region 160.
In this embodiment, the first type transistor is an N type MOS transistor, and the diffusion source doping layer 150 is doped with P type doping ions, that is, the second type doping ions are P type ions, for example: and (3) phosphorus ions. The material of the diffusion source doped layer may comprise phosphorus doped silicon oxide (PSG)
In other embodiments, when the first type doped transistor is a P-type MOS transistor, the diffusion source doped layer is doped with N-type doped ions, that is, the second type doped ions are N-type ions. The material of the diffusion source doped layer may include boron doped silicon oxide (BSG).
In this embodiment, the thickness of the diffusion source doped layer 150 is smaller than the dimension of the sidewall of the first portion 191 that is retracted relative to the sidewall of the channel layer 11 along the length direction of the channel layer 11; the semiconductor structure further includes: an inner wall layer 155 on a sidewall of the diffusion source doping layer 155.
The thickness of the diffusion source doped layer 155 is less than the dimension of the sidewall of the first portion 191 that is recessed relative to the sidewall of the channel layer 11, thereby providing a spatial location for the formation of the inner wall layer 155.
The thickness of the diffusion source doping layer 150 is not preferably too small or too large along the length of the channel layer 11. The inversion doped region is formed by diffusing second type doped ions in the diffusion source doped layer 150 into the channel layer 11, and if the thickness of the diffusion source doped layer 150 is too small, the total amount of doped ions in the diffusion source doped layer 150 is too small before diffusion, so that the concentration and the doping profile of the inversion doped region formed in the channel layer 11 are difficult to meet the process requirements; if the thickness of the diffusion source doping layer 150 is too large, the formation space of the inner wall layer 155 is too small, and the inner wall layer 155 is too thin, so that the protection effect of the inner wall layer 155 on the doping ions in the diffusion source doping layer 155 in the heat treatment process is easily reduced. For this reason, in the present embodiment, the thickness of the diffusion source doping layer 150 is one third to two thirds of the size of the sidewall of the first portion 191 which is retracted with respect to the sidewall of the channel layer 11 in the direction of the length of the channel layer 11.
The inner wall layer 155 serves as an inner wall, which increases the distance between the first portion 191 and the source drain doped region 160, and is beneficial to reducing parasitic capacitance between the metal gate structure 190 and the source drain doped region 160. Moreover, the inner wall layer 155 can also protect the second type dopant ions in the diffusion source dopant layer 150 from being outwardly diffused during the heat treatment of the diffusion source dopant layer 150, thereby improving the effect of diffusing the second type dopant ions in the diffusion source dopant layer 150 into the trench layer 11.
The material of the inner wall layer 155 is a dielectric material. In this embodiment, the material of the inner wall layer 155 is silicon nitride. Silicon nitride is a dielectric material commonly used in semiconductor processes, and the silicon nitride material has a low solid solubility, which is beneficial to improving the protection effect of the inner wall layer 155 on the second type doped ions in the diffusion source doped layer 150.
In this embodiment, the source-drain doped layer 160 includes a stress layer doped with first type doping ions. Specifically, when the fully-surrounding gate transistor is a P-type MOS transistor, the stress layer is made of Si or SiGe, and the first type of doped ions are P-type ions; when the fully-surrounding grid transistor is an N-type MOS transistor, the stress layer is made of Si or SiC, and the first type doped ions are N-type ions.
In this embodiment, the top surface of the source-drain doped region 160 is higher than the top surface of the channel structure layer 120, and the source-drain doped region 160 also covers a portion of the sidewall 140.
The semiconductor structure further includes: an interlayer dielectric layer 165 is located on the substrate on the side of the metal gate structure 190. Interlayer dielectric layer 165 is used to achieve electrical isolation between adjacent devices. In this embodiment, the material of the interlayer dielectric layer 165 is silicon oxide.
The semiconductor structure may be formed by the forming method described in the foregoing embodiments, or may be formed by other forming methods. For a specific description of the semiconductor structure in this embodiment, reference may be made to the corresponding description in the foregoing embodiment, which is not repeated here.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.
Claims (20)
1. A method of forming a semiconductor structure, comprising:
providing a substrate for forming a first type transistor, wherein one or more stacked channel stacks are formed on the substrate, and each channel stack comprises a sacrificial layer and a channel layer positioned on the sacrificial layer;
Forming a gate structure on the substrate across the channel stack, the gate structure covering a portion of a top and a portion of a sidewall of the channel stack;
etching channel lamination layers on two sides of the gate structure, and forming grooves in the channel lamination layers on two sides of the gate structure;
etching the sacrificial layer at the side part of the groove along the length direction of the channel layer to form a groove, wherein the groove is surrounded by the channel layer and the rest sacrificial layer;
filling a diffusion source doping layer in the groove, wherein doping ions with a second type of conductivity are doped in the diffusion source doping layer, and the second type is different from the first type;
performing heat treatment on the diffusion source doping layer to diffuse the second type doping ions into the channel layer, and forming an inversion doping region in the channel layer;
and after the diffusion source doping layer is subjected to heat treatment, source and drain doping regions are formed in the grooves.
2. The method of forming a semiconductor structure of claim 1, wherein after forming the diffusion source doped layer, prior to heat treating the diffusion source doped layer, the method of forming a semiconductor structure further comprises: thinning the diffusion source doping layer;
And forming an inner wall layer on the side wall of the rest diffusion source doping layer, and filling the groove.
3. The method of forming a semiconductor structure of claim 2, wherein the step of thinning the diffusion source doped layer comprises: and etching part of the thickness of the diffusion source doping layer along the length direction of the channel layer by adopting an isotropic dry etching process.
4. The method of claim 2, wherein after said thinning, a thickness of said remaining diffusion source doped layer is one third to two thirds of a depth of said trench along a length of said channel layer.
5. The method of forming a semiconductor structure of claim 1, wherein the gate structure comprises a gate electrode layer that spans the channel stack;
and etching the sacrificial layer at the side part of the groove, and forming a groove, wherein the side wall of the residual sacrificial layer is flush with the side wall of the gate electrode layer along the length direction of the channel layer, or protrudes out of the side wall of the gate electrode layer.
6. The method of forming a semiconductor structure of claim 1, wherein the trench has a depth of 1nm to 4nm along a length of the channel layer.
7. The method of forming a semiconductor structure of claim 1, wherein the first-type transistor is an N-type MOS transistor, and the diffusion source doping layer is doped with P-type dopant ions;
or the first type transistor is a P-type MOS transistor, and N-type doping ions are doped in the diffusion source doping layer.
8. The method of forming a semiconductor structure of claim 1, wherein the material of the diffusion source doped layer comprises silicon oxide doped with dopant ions of a second conductivity type.
9. The method of claim 1, wherein when the second type dopant ions are P-type dopant ions, the second type dopant ions in the diffusion source dopant layer are formed at a dopant concentration of 1.0e19 atoms per cubic centimeter to 8.0E20 atoms per cubic centimeter;
or when the second type doping ions are N type doping ions, in the step of forming the diffusion source doping layer, the doping concentration of the second type doping ions in the diffusion source doping layer is 2.0E19 atoms per cubic centimeter to 2.0E21 atoms per cubic centimeter.
10. The method of forming a semiconductor structure of claim 1, wherein the process parameters of the heat treatment comprise: the temperature is 850-1100 ℃, the process time is 0-20 seconds, and the process pressure is one atmosphere.
11. The method of forming a semiconductor structure of claim 1, wherein the heat treatment is performed by way of an annealing treatment.
12. The method of forming a semiconductor structure of claim 1, wherein forming the diffusion source dopant layer comprises: forming a doped material layer in the trench, the doped material layer also being formed on top and sidewalls of the gate structure, sidewalls of the channel layer, and the substrate surface;
and removing the doped material layers positioned at the top and the side wall of the gate structure, the side wall of the channel layer and the surface of the substrate, and taking the residual doped material layers positioned in the grooves as the diffusion source doped layers.
13. The method of forming a semiconductor structure of claim 12, wherein the process of forming the doped material layer comprises an atomic layer deposition process or a chemical vapor deposition process;
and removing the doped material layers positioned on the top and the side wall of the grid structure, the side wall of the channel layer and the surface of the substrate by adopting a dry etching process.
14. The method of forming a semiconductor structure of claim 1, wherein the sacrificial layer is etched using a wet etching process for portions of the recess sides.
15. A semiconductor structure, comprising:
a substrate for forming a first type transistor;
the channel structure layer is positioned on the substrate and is arranged at intervals with the substrate, and the channel structure layer comprises one or more channel layers arranged at intervals;
a metal gate structure crossing the channel structure layer and covering a part of the top of the channel structure layer, wherein the metal gate structure also surrounds the channel layer, the metal gate structure between the channel layers and between the channel layer and the substrate is a first part, and the side wall of the first part is retracted relative to the side wall of the channel layer along the length direction of the channel layer;
an inversion doped region located in the channel layer;
the diffusion source doping layers are positioned on the side walls of the two sides of the first part along the length direction of the channel layer, doped ions with the second type of conduction type are doped in the diffusion source doping layers, the second type of conduction type is different from the first type of conduction type, and the diffusion source doping layers are used for diffusing the doped ions with the second type into the channel layer to form the inversion type doped region;
And the source-drain doped region is positioned at two sides of the metal gate structure and covers the channel layer and the diffusion source doped layer.
16. The semiconductor structure of claim 15, wherein the metal gate structure atop the channel structure layer is a second portion;
the side wall of the first part is flush with the side wall of the second part along the length direction of the channel layer, or the side wall of the first part protrudes out of the side wall of the second part.
17. The semiconductor structure of claim 15, wherein the sidewalls of the first portion are recessed from the sidewalls of the channel layer by 1nm to 4nm in a direction along the length of the channel layer.
18. The semiconductor structure of claim 15, wherein the first type transistor is an N-type MOS transistor, the diffusion source doped layer being doped with P-type dopant ions; or the first type transistor is a P-type MOS transistor, and N-type doping ions are doped in the diffusion source doping layer;
the material of the diffusion source doped layer comprises silicon oxide doped with doped ions of a second type of conductivity.
19. The semiconductor structure of claim 15, wherein a thickness of the diffusion source doping layer is less than a dimension of the sidewall of the first portion that is recessed relative to the sidewall of the channel layer along a direction of a length of the channel layer;
The semiconductor structure further includes: and the inner wall layer is positioned on the side wall of the diffusion source doping layer.
20. The semiconductor structure of claim 19, wherein a thickness of the diffusion source dopant layer along a length of the channel layer is one third to two thirds of a dimension of the sidewall of the first portion that is recessed relative to the sidewall of the channel layer.
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