CN108630543B - Semiconductor structure and forming method thereof - Google Patents
Semiconductor structure and forming method thereof Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 55
- 239000000758 substrate Substances 0.000 claims abstract description 81
- 238000005468 ion implantation Methods 0.000 claims abstract description 43
- 150000002500 ions Chemical class 0.000 claims description 39
- 239000000463 material Substances 0.000 claims description 20
- 238000000137 annealing Methods 0.000 claims description 14
- 238000005530 etching Methods 0.000 claims description 14
- 238000002347 injection Methods 0.000 claims description 13
- 239000007924 injection Substances 0.000 claims description 13
- 238000002513 implantation Methods 0.000 claims description 12
- 238000005137 deposition process Methods 0.000 claims description 11
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 8
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 8
- 229910052710 silicon Inorganic materials 0.000 claims description 7
- 239000010703 silicon Substances 0.000 claims description 7
- 229910052751 metal Inorganic materials 0.000 claims description 6
- 239000002184 metal Substances 0.000 claims description 6
- 125000006850 spacer group Chemical group 0.000 claims description 5
- 239000003989 dielectric material Substances 0.000 claims description 4
- NBVXSUQYWXRMNV-UHFFFAOYSA-N fluoromethane Chemical compound FC NBVXSUQYWXRMNV-UHFFFAOYSA-N 0.000 claims description 3
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 3
- 229910052721 tungsten Inorganic materials 0.000 claims description 3
- 239000010937 tungsten Substances 0.000 claims description 3
- 230000000694 effects Effects 0.000 description 21
- 238000002955 isolation Methods 0.000 description 15
- 230000009286 beneficial effect Effects 0.000 description 10
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 230000002829 reductive effect Effects 0.000 description 4
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- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 229910000449 hafnium oxide Inorganic materials 0.000 description 1
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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Abstract
A semiconductor structure and a method of forming the same, wherein the method comprises: providing a substrate, wherein a grid structure is arranged on the substrate, the grid structure comprises a grid layer and a grid side wall positioned on the grid layer, source and drain doped regions are arranged in the substrate at two sides of the grid structure, dielectric layers are arranged on the substrate and the source and drain doped regions, the dielectric layers cover the side wall of the grid structure, and the dielectric layers are exposed out of the top of the grid side wall; removing the grid side wall, and forming a side wall opening between the dielectric layer and the grid layer; and carrying out pocket region ion implantation on the substrate at the bottom of the side wall opening to form a pocket region. The method can reduce the difficulty of ion implantation of the pocket region, and the formed pocket region has better performance.
Description
Technical Field
The present invention relates to the field of semiconductor manufacturing, and more particularly, to a semiconductor structure and a method for forming the same.
Background
With the continuous improvement of the integration level of the semiconductor device, the characteristic size of the semiconductor device is gradually reduced, the channel length of the MOS transistor is also gradually reduced, and the thickness of the gate dielectric layer is also continuously reduced. Since the gate voltage is not continuously decreased (at least 1V at present), the electric field intensity received by the gate dielectric layer becomes large, Time Dependent Dielectric Breakdown (TDDB) also occurs more easily, and Hot Carrier Injection (HCI) is easily formed. In the prior art, the hot carrier injection effect is usually optimized by Light Doped Drain (LDD) ion implantation. However, lightly doped ion implantation tends to cause short channel effects.
In order to alleviate the short channel effect, in the prior art, after forming LDD source/drain regions, Pocket region (Pocket) implantation is performed on two sides of the LDD source/drain regions close to a channel region, where the type of impurity ions implanted in the Pocket region is opposite to the type of impurity ions implanted in the LDD region, so that depletion regions of the LDD source/drain regions close to two sides of the channel region are narrowed, and the short channel effect can be alleviated.
However, as the integration of semiconductor devices is further improved, the ion implantation of the pocket region becomes difficult, and the formed pocket region has poor performance.
Disclosure of Invention
The invention provides a semiconductor structure and a forming method thereof, which can improve the performance of the semiconductor structure.
To solve the above technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate, wherein a grid structure is arranged on the substrate, the grid structure comprises a grid layer and a grid side wall positioned on the side wall of the grid layer, source drain doped regions are arranged in the substrate at two sides of the grid structure, dielectric layers are arranged on the substrate and the source drain doped regions, the dielectric layers cover the side wall of the grid structure, and the dielectric layers are exposed out of the top of the grid side wall; removing the grid side wall, and forming a side wall opening between the dielectric layer and the grid layer; and carrying out pocket region ion implantation on the substrate at the bottom of the side wall opening to form a pocket region.
Optionally, the forming step of the source-drain doped region includes: forming openings in the substrate on two sides of the grid structure by adopting an etching process; forming an epitaxial layer in the opening by adopting a selective epitaxial deposition process; and doping P-type ions or N-type ions in the epitaxial layer to form the source drain doped region.
Optionally, the process parameters of the selective epitaxial deposition process include: the annealing temperature is 700-800 ℃, and the annealing time is 1-2 hours.
Optionally, the gate structure further includes: a gate dielectric layer; the gate layer is positioned on the gate dielectric layer; the grid side wall is also positioned on the side wall of the grid dielectric layer.
Optionally, the gate dielectric layer is made of: silicon oxide; the material of the gate layer comprises: silicon.
Optionally, the gate dielectric layer is made of: the high-K dielectric material has a K value range as follows: the K value is more than 3.9; the material of the gate layer comprises: a metal, the metal comprising: tungsten.
Optionally, the forming steps of the gate structure, the source-drain doped region and the dielectric layer include: forming a pseudo gate structure on the substrate, wherein the pseudo gate structure comprises a pseudo gate layer and a gate side wall positioned on the side wall of the pseudo gate layer; forming source and drain doped regions in the substrate on two sides of the pseudo gate structure; forming a dielectric layer on the substrate and the source-drain doped region, wherein the dielectric layer covers the side wall of the pseudo gate structure and is exposed out of the top of the gate side wall; after the dielectric layer is formed, removing the dummy gate layer to form a dummy gate opening; and forming a gate layer in the dummy gate opening.
Optionally, the material of the dummy gate layer includes: silicon.
Optionally, after the dielectric layer is formed and before the dummy gate opening is formed, removing the gate sidewall to form a sidewall opening; or after the grid structure is formed, removing the grid side wall to form a side wall opening.
Optionally, the pseudo gate structure further includes: a dummy gate dielectric layer; the dummy gate layer is positioned on the dummy gate dielectric layer; the grid side wall is also positioned on the side wall of the pseudo grid dielectric layer; the step of forming the dummy gate opening further comprises: and removing the dummy gate dielectric layer after removing the dummy gate layer.
Optionally, the material of the dummy gate dielectric layer includes: silicon oxide.
Optionally, after the gate structure is formed, the gate sidewall is removed to form the sidewall opening.
Optionally, the process for removing the gate sidewall includes: and (5) carrying out an anisotropic etching process.
Optionally, the process parameters of the anisotropic etching process include: the etching gas comprises CF4、CH3F and O2Wherein, CF4The flow rate of (A) is 5 to 100 standard ml/min, CH3The flow rate of F is 8 standard ml/min-50 standard ml/min, O2The flow rate of the gas is 10-100 standard ml/min, the radio frequency power is 50-300 w, the bias voltage is 30-100 v, and the pressure of the chamber is 10-2000 mTorr.
Optionally, the substrate comprises: the device comprises a substrate and a fin part positioned on the substrate; the gate structure spans across the fin.
Optionally, the source-drain doped region has doped ions therein; the process parameters of the pocket region ion implantation comprise: the conductivity type of the implanted ions is opposite to that of the doped ions in the source-drain doped region, the implantation energy is 2-30 kilo-electron volts, and the concentration of the implanted ions is 1.0e13Atomic number/square centimeter-1.0 e15Atomic number/square centimeter, the direction of implantation is perpendicular to the extending direction of the fin portion, and the included angle between the direction of implantation and the normal of the substrate is: 10 to 30 degrees.
Correspondingly, the invention also provides a semiconductor structure formed by adopting the method, which comprises the following steps: the semiconductor device comprises a substrate, wherein a grid structure is arranged on the substrate and comprises a grid layer, source and drain doped regions are arranged in the substrate on two sides of the grid structure, and dielectric layers are arranged on the substrate and the source and drain doped regions; and the side wall opening is positioned between the dielectric layer and the grid layer, and the pocket area is positioned in the substrate at the bottom of the side wall opening.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following beneficial effects:
in the method for forming the semiconductor structure provided by the technical scheme of the invention, after the source-drain doped region and the dielectric layer are formed, the side wall of the grid electrode is removed to form a side wall opening, and the side wall opening is used for carrying out pocket region ion implantation on a substrate at the bottom of the side wall opening to form a pocket region. Because the pocket region ion implantation is performed on the substrate at the bottom of the side wall opening and is formed after the source-drain doped region is formed, the high-temperature process for forming the source-drain doped region is difficult to drive ions in the subsequently formed pocket region to diffuse, so that the concentration of the pocket region ion implantation is easy to control, and the performance of the formed pocket region is good. The pocket region is beneficial to inhibiting short channel effect, thereby improving the performance of the semiconductor structure.
Further, in the process of forming the source-drain doped region, an epitaxial layer is formed in the opening by adopting a selective epitaxial deposition process, wherein the process parameters of the selective epitaxial deposition process comprise: the annealing temperature is 700-800 ℃, and the annealing time is 1-2 hours. The epitaxial layer forming process is performed before pocket region ion implantation is performed on the fin portion at the bottom of the side wall opening, so that the high-temperature process and the long-time annealing process for forming the epitaxial layer are difficult to drive ions in a subsequent pocket region to diffuse, the concentration of the pocket region ion implantation is easy to control, and the performance of the formed pocket region is good. The pocket region is beneficial to inhibiting short channel effect, thereby improving the performance of the semiconductor structure.
Further, the injection direction of the pocket region ion injection is perpendicular to the extending direction of the fin portion, and the gate layer crosses the fin portion, so that the injection direction is parallel to the extending direction of the gate layer, and when the pocket region ion injection is performed on the fin portion at the bottom of the side wall opening, the injected ions are not blocked by the side wall of the side wall opening, that is: and the fin part at the bottom of the side wall opening is not easy to generate a shadow effect when ion implantation is carried out on the pocket region. And the included angle between the implantation direction and the normal line of the substrate is as follows: the ion concentration in the pocket regions at the top and the side walls of the fin portion is uniform by 10-30 degrees, and the performance of the formed pocket regions is good. The pocket region is beneficial to inhibiting short channel effect, thereby improving the performance of the semiconductor structure.
Drawings
FIGS. 1-2 are schematic structural diagrams illustrating steps of a method for forming a semiconductor structure;
fig. 3 to 12 are schematic structural diagrams of steps of a method for forming a semiconductor structure according to an embodiment of the present invention.
Detailed Description
As described in the background, the ion implantation of the pocket region is difficult in the prior art, and the formed pocket region has poor performance.
Fig. 1 to 2 are schematic structural diagrams of steps of a method for forming a semiconductor structure.
Referring to fig. 1, a semiconductor substrate 100 is provided, the semiconductor substrate 100 having a fin 101 and an isolation layer 102 thereon, a top surface of the isolation layer 102 being lower than a top surface of the fin 101 and covering a portion of a sidewall of the fin 101; a gate structure 103 is formed across the fin 101.
Referring to fig. 2, a pocket region ion implantation is performed on the fin 101 at two sides of the gate structure 103.
After the ion implantation of the pocket region, the method further comprises: and forming a source drain doped region.
However, semiconductors prepared using the above method have poor performance due to:
in the above method, the fin 101 on both sides of the gate structure 103 is formed before the source-drain doped region is formed by performing pocket region ion implantation. The forming step of the source drain doped region comprises the following steps: forming openings in the fin parts 101 on two sides of the gate structure 103 by adopting an etching process; forming an epitaxial layer in the opening by adopting a selective epitaxial deposition process; and doping P-type ions or N-type ions in the epitaxial layer to form the source drain doped region. The process parameters of the selective epitaxial deposition process comprise: the annealing temperature is 700-800 ℃, and the annealing time is 1-2 hours. The epitaxial layer is formed after pocket region ion implantation is performed on the fin portions 101 on two sides of the gate structure 103, so that ions in the pocket region are driven to diffuse by an annealing process in the epitaxial layer forming process, the concentration of the pocket region ion implantation is difficult to control, the performance of the formed pocket region is poor, the effect of improving the short channel effect of the pocket region is poor, and the performance of the formed semiconductor structure is poor.
When pocket region ion implantation is performed on the fin portions 101 on two sides of the gate structure 103, the implantation direction of the pocket region ion implantation is along the extending direction perpendicular to the gate structure 103. The injection direction of the pocket region ion injection makes the injected ions blocked by the gate structure 103, and the shadow effect of the ion injection is easy to occur. Moreover, as the integration of semiconductor devices is continuously improved, the distance between adjacent gate structures 103 is continuously reduced, so that the aspect ratio of the trench formed by the adjacent gate structures 103 is larger, and the shadow effect is more serious. Namely: it becomes increasingly difficult to implant pocket regions into the fin 101 on both sides of the gate structure 103. The pocket region ion implantation is difficult to implant into the fin portions 101 on both sides of the gate structure 103, so that the performance of the formed pocket region is poor, the effect of the pocket region on improving the short channel effect is poor, and the performance of the formed semiconductor structure is poor.
To solve the above technical problem, the present invention provides a method for forming a semiconductor structure, including: providing a substrate, wherein a grid structure is arranged on the substrate, the grid structure comprises a grid layer and a grid side wall positioned on the side wall of the grid layer, source drain doped regions are arranged in the substrate at two sides of the grid structure, dielectric layers are arranged on the substrate and the source drain doped regions, the dielectric layers cover the side wall of the grid structure, and the dielectric layers are exposed out of the top of the grid side wall; removing the grid side wall, and forming a side wall opening between the dielectric layer and the grid layer; and carrying out pocket region ion implantation on the substrate at the bottom of the side wall opening to form a pocket region.
In the method, after the source-drain doped region and the dielectric layer are formed, the grid side wall is removed to form a side wall opening, and the side wall opening is used for carrying out pocket region ion implantation on a substrate at the bottom of the side wall opening to form a pocket region. Because the pocket region ion implantation is performed on the substrate at the bottom of the side wall opening and is formed after the source-drain doped region is formed, the high-temperature process for forming the source-drain doped region is difficult to drive ions in the subsequently formed pocket region to diffuse, so that the concentration of the pocket region ion implantation is easy to control, and the performance of the formed pocket region is good. The pocket region is beneficial to inhibiting short channel effect, thereby improving the performance of the semiconductor structure.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
The following description will take the gate process as an example to describe the formation method of the semiconductor structure of the present invention.
Fig. 3 to 12 are schematic structural diagrams of steps of a method for forming a semiconductor structure according to an embodiment of the present invention.
Referring to fig. 3, a substrate 200 is provided.
In this embodiment, the substrate 200 includes: a substrate 201 and a fin 202 on the substrate 201. In other embodiments, the substrate can also be a planar substrate.
The forming step of the substrate 200 includes: providing an initial substrate; the initial substrate is patterned to form a substrate 201 and a fin 202 on the substrate 201.
In this embodiment, the initial substrate is made of silicon. In other embodiments, the initial substrate may also be a semiconductor substrate such as a germanium substrate, a silicon-on-insulator or a germanium-on-insulator.
In this embodiment, the substrate 201 has an isolation structure 203 thereon.
The step of forming the isolation structure 203 comprises: forming an isolation material layer on the substrate 201 and the fin 202; flattening the isolation material layer by adopting a chemical mechanical polishing process; and etching to remove part of the isolation material layer to form an isolation structure 203. The isolation structures 203 cover portions of the sidewall surfaces of the fins 202, and the top surfaces of the isolation structures 203 are lower than the top surfaces of the fins 202.
The forming method of the isolation material layer comprises the following steps: chemical vapor deposition process.
The material of the isolation structure 203 includes: silicon oxide. In other embodiments, the material of the isolation structure may also be silicon oxynitride or silicon nitride.
The isolation structure 203 is used to achieve electrical isolation between different semiconductor devices.
Referring to fig. 4 and 5, fig. 5 is a schematic cross-sectional view taken along line a-a' of fig. 4, and a dummy gate structure is formed on the substrate 200, where the dummy gate structure includes a dummy gate layer 204 and a gate sidewall 205 located on the dummy gate layer 204.
The dummy gate structure further includes: a dummy gate dielectric layer (not shown) covering a portion of the sidewall and the top surface of the fin 202; the dummy gate layer 204 is positioned on the dummy gate dielectric layer; the gate spacers 205 are also located on the sidewalls of the dummy gate dielectric layer.
In this embodiment, the material of the dummy gate dielectric layer is silicon oxide. In other embodiments, the material of the dummy gate dielectric layer may also be silicon nitride or silicon oxynitride.
In this embodiment, the material of the dummy gate layer 204 is polysilicon.
In this embodiment, a mask layer (not shown) is disposed on the top surface of the dummy gate structure, the mask layer is made of silicon nitride, and the mask layer is used as a mask for forming the dummy gate layer 204 by etching.
The gate sidewall spacers 205 are used to define the positions where source and drain doped regions are to be formed subsequently.
Referring to fig. 6, source-drain doped regions 206 are formed in the substrate 200 at two sides of the dummy gate structure.
Fig. 6 is a cross-sectional view of fig. 5.
The forming steps of the source-drain doped region 206 include: forming openings in the fin portions 202 on two sides of the pseudo gate structure by adopting an etching process; forming an epitaxial layer in the opening by adopting a selective epitaxial deposition process; p-type ions or N-type ions are doped in the epitaxial layer to form the source/drain doped region 206.
The process parameters of the selective epitaxial deposition process comprise: the annealing temperature is 700-800 ℃, and the annealing time is 1-2 hours. The epitaxial layer formed by selecting the technological parameters of the selective epitaxial deposition process is good, and the performance of the semiconductor structure is improved.
Moreover, when the epitaxial layer is formed, pocket region ion implantation is not performed on the substrate at the bottom of the side wall opening and the substrate at the bottom of the side wall opening, so that the high-temperature process and the long-time annealing process for forming the epitaxial layer are difficult to drive ions in a subsequently formed pocket region to diffuse, the concentration of the ion implantation in the subsequently formed pocket region is easy to control, and the performance of the formed pocket region is good. The pocket region is beneficial to inhibiting short channel effect, thereby improving the performance of the semiconductor structure.
Referring to fig. 7, after the source-drain doped region 206 is formed, a dielectric layer 207 is formed on the substrate 200 and the source-drain doped region 206, the dielectric layer 207 covers the sidewall of the dummy gate structure, and the dielectric layer 207 exposes the top of the gate sidewall 205.
The forming step of the dielectric layer 207 includes: forming a dielectric film on the substrate 200, the source-drain doped region 206 and the top surface of the pseudo gate structure; and flattening the dielectric film, forming a dielectric layer 207 on the substrate 200 and the source-drain doped region 206, wherein the dielectric layer 207 covers the side wall of the pseudo gate structure, and the dielectric layer 207 exposes the top of the gate sidewall 205.
The dielectric film comprises the following materials: silicon oxide.
The forming method of the dielectric film comprises the following steps: a fluid chemical vapor deposition process.
In this embodiment, the process of planarizing the dielectric film is a chemical mechanical polishing process.
The dielectric layer 207 is used to electrically isolate the different devices of the semiconductor.
Referring to fig. 8, after the dielectric layer 207 is formed, the dummy gate layer 204 (shown in fig. 7) and the dummy gate dielectric layer (not shown) are removed to form a dummy gate opening 208.
In this embodiment, the step of forming the dummy gate opening 208 includes: removing the dummy gate layer 204; after removing the dummy gate layer 204, the dummy gate dielectric layer is removed.
The process for removing the dummy gate layer 204 includes: a dry etching process or a wet etching process.
The process for removing the pseudo gate dielectric layer comprises the following steps: a dry etching process or a wet etching process.
In the present embodiment, the bottom of the dummy gate opening 208 exposes the top surface of the fin 202. In other embodiments, the forming of the dummy gate opening includes: removing only the dummy gate layer; the bottom of the dummy gate opening is exposed out of the top surface of the dummy gate dielectric layer.
The dummy gate opening 208 is used for subsequent formation of a gate structure.
Referring to fig. 9, a gate structure 209 is formed in the dummy gate opening 208.
The gate structure 209 includes: forming a gate dielectric layer 210 on the sidewall and the bottom of the gate opening 208; after the gate dielectric layer 210 is formed, a gate layer 211 is formed on the gate dielectric layer 210.
In this embodiment, the gate dielectric layer 210 is made of a high-K dielectric material, and the K value range of the high-K dielectric material is: k is greater than 3.9, and the gate dielectric layer 210 is made of: and (3) hafnium oxide.
In this embodiment, the material of the gate layer 211 includes a metal, and the metal includes: tungsten.
After forming the gate dielectric layer 210 and before forming the gate electrode layer 211, a work function 212 is formed on the gate dielectric layer 210, and the work function 212 is used for reducing the threshold voltage.
Referring to fig. 10, after the gate structure 209 is formed, the gate sidewall spacers 205 are removed to form sidewall openings 213.
The process of removing the gate sidewall spacers 205 includes: the anisotropic etching process comprises the following process parameters: the etching gas comprises CF4、CH3F and O2Wherein, CF4The flow rate of (A) is 5 to 100 standard ml/min, CH3The flow rate of F is 8 standard ml/min-50 standard ml/min, O2The flow rate of the gas is 10-100 standard ml/min, the radio frequency power is 50-300 w, the bias voltage is 30-100 v, and the pressure of the chamber is 10-2000 mTorr.
In this example, the sidewall openings 213 are formed after the gate structure 209 is formed.
In this example, the reason why the sidewall opening 213 is selectively formed after the gate structure 209 is formed, but not selectively formed after the dielectric layer 207 is formed and before the dummy gate opening 208 is formed, is that: if the sidewall opening 213 is formed after the dielectric layer 207 is formed and before the dummy gate opening 208 is formed, in order to form the dummy gate opening 208 subsequently, when the dummy gate dielectric layer is removed, the dielectric layer 207 is easily damaged, so that different devices of the semiconductor cannot be effectively isolated, electric leakage between different devices is easy, and the performance of the semiconductor structure is not improved.
In other embodiments, removing the dummy gate structure comprises only: and removing the dummy gate layer. The side wall opening is formed after the dielectric layer is formed and before the pseudo gate opening is formed; or the side wall opening is formed after the gate structure is formed.
The sidewall openings 213 are used for performing pocket region ion implantation on the fin 202 at the bottom of the sidewall openings 213 in the following step.
Referring to fig. 11, a pocket region is formed by performing pocket region ion implantation on the fin 202 at the bottom of the sidewall opening 213.
Performing pocket region ion implantation on the fin portion 202 at the bottom of the sidewall opening 213, wherein the significance of performing the pocket region ion implantation after the source-drain doped region 206 and the dielectric layer 207 are formed is as follows: pocket region ion implantation is performed on the fin portion 202 at the bottom of the side wall opening 213, and the fin portion is formed after the source-drain doped region 206 is formed, so that the high-temperature process and the long-time annealing process for forming the source-drain doped region 206 are difficult to drive ions in the pocket region to diffuse, the concentration of the pocket region ion implantation is easy to control, and the performance of the formed pocket region is good. The pocket region is beneficial to inhibiting short channel effect, thereby improving the performance of the semiconductor structure.
The process parameters of the pocket region ion implantation comprise: the conductivity type of the implanted ions is opposite to that of the doped ions in the source-drain doped region 206, the implantation energy is 2-30 keV, and the concentration of the implanted ions is 1.0e13Atomic number/square centimeter-1.0 e15Atomic number per square centimeter, the implantation direction perpendicular to the extending direction of the fin portion 202, and the implantation direction and the normal of the substrate 201 form an included angle θ, the range of the included angle θ is: 10 to 30 degrees.
The implantation direction perpendicular to the extension direction of the fin 202 has the significance that: the injection direction of the pocket region ion implantation is perpendicular to the extending direction of the fin portion 202, and the gate layer 211 crosses the fin portion 202, so that the injection direction is parallel to the extending direction of the gate layer 211, so that when the pocket region ion implantation is performed on the fin portion 202 at the bottom of the sidewall opening 213, the injected ions are not blocked by the sidewall of the sidewall opening 213, that is: no shadow effect occurs when performing the pocket region ion implantation on the fin portion 202 at the bottom of the sidewall opening 213.
The significance of selecting the included angle theta is as follows: if the included angle θ is smaller than 10 degrees, the concentration of ions injected into the fin portion 202 at the bottom of the sidewall opening 213 is too high, so that the capacitance of the fin portion 202 is large, which is not beneficial to improving the performance of the semiconductor structure; if the included angle θ is greater than 30 degrees, the concentration of ions implanted into the fin portion 202 at the bottom of the sidewall opening 213 is too low, the formed pocket region has a weak effect on improving a short channel, and the performance of the formed semiconductor structure is poor. The implantation direction makes an angle with the normal of the substrate 201: the 10-30 degrees ensures that the ion concentration in the pocket regions at the top and the side walls of the fin portion 202 is uniform, the performance of the formed pocket region is good, and the pocket region is beneficial to inhibiting the short channel effect, so that the performance of the semiconductor structure is improved.
Referring to fig. 12, a first dielectric layer 214 is formed in the sidewall opening 213.
The step of forming the first dielectric layer 214 includes: forming a first dielectric film in the sidewall opening 213 and on the gate structure 209; the first dielectric film is planarized until the top surface of the gate layer 211 is exposed, forming a first dielectric layer 214.
The forming process of the first dielectric film comprises the following steps: a fluid chemical vapor deposition process.
The material of the first dielectric layer 214 includes: silicon oxide.
In summary, in this embodiment, after the source-drain doped region and the dielectric layer are formed, the gate sidewall is removed to form a sidewall opening, and the sidewall opening is used for performing pocket region ion implantation on the substrate at the bottom of the sidewall opening to form a pocket region. Because the pocket region ion implantation is performed on the substrate at the bottom of the side wall opening and is formed after the source-drain doped region is formed, the high-temperature process for forming the source-drain doped region is difficult to drive ions of the subsequently formed pocket region to diffuse, so that the concentration of the pocket region ion implantation is easy to control, and the performance of the formed pocket region is good. The pocket region is beneficial to inhibiting short channel effect, thereby improving the performance of the semiconductor structure.
Accordingly, an embodiment of the present invention further provides a semiconductor structure formed by the above method, with reference to fig. 11, including:
the semiconductor device comprises a substrate 200, wherein a gate structure 209 is arranged on the substrate 200, the gate structure 209 comprises a gate layer 211, source drain doped regions 206 are arranged in the substrate 200 at two sides of the gate structure 209, and dielectric layers 207 are arranged on the substrate 200 and the source drain doped regions 206; a sidewall opening 213 between the dielectric layer 207 and the gate layer 211, and a pocket region in the substrate at the bottom of the sidewall opening 213.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (14)
1. A method of forming a semiconductor structure, comprising:
providing a substrate, wherein a grid structure is arranged on the substrate, the grid structure comprises a grid layer and a grid side wall positioned on the side wall of the grid layer, source drain doped regions are arranged in the substrate at two sides of the grid structure, dielectric layers are arranged on the substrate and the source drain doped regions, the dielectric layers cover the side wall of the grid structure, and the dielectric layers are exposed out of the top of the grid side wall;
removing the grid side wall, and forming a side wall opening between the dielectric layer and the grid layer;
performing pocket region ion implantation on the substrate at the bottom of the side wall opening to form a pocket region;
the forming step of the source drain doped region comprises the following steps: forming openings in the substrate on two sides of the grid structure by adopting an etching process; forming an epitaxial layer in the opening by adopting a selective epitaxial deposition process; doping P-type ions or N-type ions in the epitaxial layer to form the source drain doping region;
the process parameters of the selective epitaxial deposition process comprise: the annealing temperature is 700-800 ℃, and the annealing time is 1-2 hours.
2. The method of forming a semiconductor structure of claim 1, wherein the gate structure further comprises: a gate dielectric layer; the gate layer is positioned on the gate dielectric layer; the grid side wall is also positioned on the side wall of the grid dielectric layer.
3. The method of claim 2, wherein the gate dielectric layer comprises: silicon oxide; the material of the gate layer comprises: silicon.
4. The method of claim 2, wherein the gate dielectric layer comprises: the high-K dielectric material has a K value range as follows: the K value is more than 3.9; the material of the gate layer comprises: a metal, the metal comprising: tungsten.
5. The method for forming the semiconductor structure according to claim 4, wherein the forming steps of the gate structure, the source-drain doped region and the dielectric layer comprise: forming a pseudo gate structure on the substrate, wherein the pseudo gate structure comprises a pseudo gate layer and a gate side wall positioned on the side wall of the pseudo gate layer; forming source and drain doped regions in the substrate on two sides of the pseudo gate structure; forming a dielectric layer on the substrate and the source-drain doped region, wherein the dielectric layer covers the side wall of the pseudo gate structure and is exposed out of the top of the gate side wall; after the dielectric layer is formed, removing the dummy gate layer to form a dummy gate opening; and forming a gate layer in the dummy gate opening.
6. The method of forming a semiconductor structure of claim 5, wherein the material of the dummy gate layer comprises: silicon.
7. The method for forming the semiconductor structure according to claim 5, wherein after the dielectric layer is formed and before the dummy gate opening is formed, the gate sidewall is removed to form a sidewall opening; or after the grid structure is formed, removing the grid side wall to form a side wall opening.
8. The method of forming a semiconductor structure of claim 5, wherein the dummy gate structure further comprises: a dummy gate dielectric layer; the dummy gate layer is positioned on the dummy gate dielectric layer; the grid side wall is also positioned on the side wall of the pseudo grid dielectric layer; the step of forming the dummy gate opening further comprises: and removing the dummy gate dielectric layer after removing the dummy gate layer.
9. The method for forming a semiconductor structure of claim 8, wherein the material of the dummy gate dielectric layer comprises: silicon oxide.
10. The method for forming a semiconductor structure according to claim 8, wherein the sidewall opening is formed by removing the gate sidewall after the gate structure is formed.
11. The method of claim 1, wherein the removing the gate sidewall spacers comprises: and (5) carrying out an anisotropic etching process.
12. The method of forming a semiconductor structure of claim 11, wherein the process parameters of the anisotropic etching process comprise: the etching gas comprises CF4、CH3F and O2Wherein, CF4The flow rate of (A) is 5 to 100 standard ml/min, CH3The flow rate of F is 8 standard ml/min-50 standard ml/min, O2The flow rate of the gas is 10-100 standard ml/min, the radio frequency power is 50-300 w, the bias voltage is 30-100 v, and the pressure of the chamber is 10-2000 mTorr.
13. The method of forming a semiconductor structure of claim 1, wherein the substrate comprises: the device comprises a substrate and a fin part positioned on the substrate; the gate structure spans across the fin.
14. The method for forming a semiconductor structure according to claim 13, wherein the source-drain doped region has doped ions therein; the process parameters of the pocket region ion implantation comprise: the conductivity type of the implanted ions is opposite to that of the doped ions in the source-drain doped region, the implantation energy is 2-30 kilo-electron volts, and the concentration of the implanted ions is 1.0e13Atomic number/square centimeter-1.0 e15The atomic number/square centimeter, the injection direction is vertical to the extending direction of the fin part, and the included angle between the injection direction and the normal line of the substrate is 10-30 degrees.
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| US6391728B1 (en) * | 2001-03-12 | 2002-05-21 | Advanced Micro Devices, Inc. | Method of forming a highly localized halo profile to prevent punch-through |
| CN103855004A (en) * | 2012-11-28 | 2014-06-11 | 中芯国际集成电路制造(上海)有限公司 | Transistor forming method |
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| CN103855004A (en) * | 2012-11-28 | 2014-06-11 | 中芯国际集成电路制造(上海)有限公司 | Transistor forming method |
| CN103943502A (en) * | 2013-01-22 | 2014-07-23 | 中芯国际集成电路制造(上海)有限公司 | Fin field effect transistor and forming method thereof |
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