CN108630543A - Semiconductor structure and forming method thereof - Google Patents
Semiconductor structure and forming method thereof Download PDFInfo
- Publication number
- CN108630543A CN108630543A CN201710160464.2A CN201710160464A CN108630543A CN 108630543 A CN108630543 A CN 108630543A CN 201710160464 A CN201710160464 A CN 201710160464A CN 108630543 A CN108630543 A CN 108630543A
- Authority
- CN
- China
- Prior art keywords
- grid
- layer
- dielectric layer
- substrate
- side wall
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000000034 method Methods 0.000 title claims abstract description 66
- 239000004065 semiconductor Substances 0.000 title claims abstract description 58
- 239000000758 substrate Substances 0.000 claims abstract description 82
- 150000002500 ions Chemical class 0.000 claims description 79
- 239000000463 material Substances 0.000 claims description 28
- 238000002347 injection Methods 0.000 claims description 22
- 239000007924 injection Substances 0.000 claims description 22
- 230000015572 biosynthetic process Effects 0.000 claims description 17
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 16
- 238000000137 annealing Methods 0.000 claims description 14
- 238000000151 deposition Methods 0.000 claims description 13
- 238000005530 etching Methods 0.000 claims description 9
- 239000000377 silicon dioxide Substances 0.000 claims description 8
- 229910052710 silicon Inorganic materials 0.000 claims description 7
- 239000010703 silicon Substances 0.000 claims description 7
- 239000003989 dielectric material Substances 0.000 claims description 6
- 229910052751 metal Inorganic materials 0.000 claims description 5
- 239000002184 metal Substances 0.000 claims description 5
- NBVXSUQYWXRMNV-UHFFFAOYSA-N fluoromethane Chemical compound FC NBVXSUQYWXRMNV-UHFFFAOYSA-N 0.000 claims description 3
- 238000002513 implantation Methods 0.000 claims description 3
- 229910052721 tungsten Inorganic materials 0.000 claims description 3
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 3
- 239000010937 tungsten Substances 0.000 claims description 3
- 230000000694 effects Effects 0.000 description 23
- 238000002955 isolation Methods 0.000 description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 239000011248 coating agent Substances 0.000 description 5
- 238000000576 coating method Methods 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 125000006850 spacer group Chemical group 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- 230000015556 catabolic process Effects 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 239000012530 fluid Substances 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- VIKNJXKGJWUCNN-XGXHKTLJSA-N norethisterone Chemical compound O=C1CC[C@@H]2[C@H]3CC[C@](C)([C@](CC4)(O)C#C)[C@@H]4[C@@H]3CCC2=C1 VIKNJXKGJWUCNN-XGXHKTLJSA-N 0.000 description 2
- 238000000926 separation method Methods 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 229910000449 hafnium oxide Inorganic materials 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
A kind of semiconductor structure and forming method thereof, wherein method includes：Substrate is provided, there is gate structure in the substrate, the gate structure includes grid layer and the grid curb wall on grid layer, there is source and drain doping area in the substrate of the gate structure both sides, there is dielectric layer in the substrate and source and drain doping area, the dielectric layer covers the side wall of the gate structure, and the dielectric layer exposes at the top of grid curb wall；The grid curb wall is removed, forms side wall opening between the dielectric layer and grid layer；Pocket region ion implanting is carried out to the substrate of the side wall open bottom and forms pocket region.The method can reduce the difficulty of pocket region ion implanting, and the pocket region better performances formed.
Description
Technical field
The present invention relates to field of semiconductor manufacture, more particularly, to a kind of semiconductor structure and forming method thereof.
Background technology
With the continuous improvement of semiconductor devices integrated level, the characteristic size of semiconductor devices is gradually reduced, MOS transistor
Channel length be also gradually reduced, the thickness of gate dielectric layer is also constantly reducing.Since grid voltage will not continue to reduce (at present
At least 1V) so that the electric field strength that the gate dielectric layer is subject to becomes larger, the dielectric breakdown (time with time correlation
Dependent dielectric breakdown, TDDB) it is also easier to occur, and be easy to form hot carrier injection effect
(Hot Carrier Injection, HCI).Generally use is lightly doped (Lightly Doped Drain, LDD) in the prior art
Ion implanting optimizes hot carrier injection effect.But ion implanting is lightly doped and easily causes short-channel effect.
It is in the prior art, close to the source/drain regions LDD after forming the source/drain regions LDD in order to alleviate short-channel effect
The both sides of channel region carry out pocket region (Pocket) injection again, and the type of the foreign ion of the pocket region injection is injected with LDD
Foreign ion type it is opposite so that depletion region of the source/drain regions LDD close to the both sides of channel region narrows, and can alleviate short
Channelling effect.
However, further increasing with semiconductor devices integrated level, the pocket region ion implanting becomes difficult, and shape
At pocket region performance it is poor.
Invention content
The technical problem to be solved by the present invention is to provide a kind of semiconductor structures and forming method thereof, can improve semiconductor junction
Structure performance.
In order to solve the above technical problems, the embodiment of the present invention provides a kind of forming method of semiconductor structure, including：It provides
Substrate has gate structure in the substrate, and the gate structure includes grid layer and the gate electrode side on grid layer side wall
Wall, gate structure both sides substrate is interior to have source and drain doping area, has dielectric layer in the substrate and source and drain doping area, described
Dielectric layer covers the side wall of the gate structure, and the dielectric layer exposes at the top of grid curb wall；The grid curb wall is removed,
Side wall opening is formed between the dielectric layer and grid layer；Pocket region ion note is carried out to the substrate of the side wall open bottom
Enter to form pocket region.
Optionally, the forming step in the source and drain doping area includes：Using etching technics in the gate structure both sides
Opening is formed in substrate；Epitaxial layer is formed using selective epitaxial depositing operation in the opening；It is mixed in the epitaxial layer
Miscellaneous p-type ion or N-type ion form the source and drain doping area.
Optionally, the technological parameter of the selective epitaxial depositing operation includes：Annealing temperature is 700 degrees Celsius~800
Degree Celsius, annealing time is 1 hour~2 hours.
Optionally, the gate structure further includes：Gate dielectric layer；The grid layer is located on the gate dielectric layer；Grid
Side wall is also located on the side wall of gate dielectric layer.
Optionally, the material of the gate dielectric layer includes：Silica；The material of the grid layer includes：Silicon.
Optionally, the material of the gate dielectric layer includes：High K dielectric material, the K values of the high K dielectric material are ranging from：
K values are more than 3.9；The material of the grid layer includes：Metal, the metal include：Tungsten.
Optionally, the forming step of the gate structure, source and drain doping area and dielectric layer includes：Shape on the substrate
At pseudo- grid structure, dummy gate structure includes dummy gate layer and the grid curb wall on the dummy gate layer side wall；Institute
It states and forms source and drain doping area in the substrate of pseudo- grid structure both sides；Dielectric layer is formed in the substrate and source and drain doping area, it is described
Dielectric layer covers the side wall of dummy gate structure, and the dielectric layer exposes at the top of grid curb wall；Formed the dielectric layer it
Afterwards, removal dummy gate layer forms pseudo- grid opening；Grid layer is formed in the pseudo- grid opening.
Optionally, the material of the dummy gate layer includes：Silicon.
Optionally, it after forming the dielectric layer, is formed before pseudo- grid opening, removes the grid curb wall and form side wall
Opening；Alternatively, after formation of the gate structure, removing the grid curb wall and forming side wall opening.
Optionally, dummy gate structure further includes：Pseudo- gate dielectric layer；The dummy gate layer is located at the pseudo- gate dielectric layer
On；The grid curb wall is also located on the side wall of pseudo- gate dielectric layer；The step of pseudo- grid are open is formed, further includes：Remove dummy grid
After layer, pseudo- gate dielectric layer is removed.
Optionally, the material of the pseudo- gate dielectric layer includes：Silica.
Optionally, after formation of the gate structure, removal grid curb wall forms the side wall opening.
Optionally, the technique for removing the grid curb wall includes：Anisotropic etch process.
Optionally, the technological parameter of the anisotropic etch process includes：Etching gas includes CF4、CH3F and O2,
In, CF4Flow be 5 standard milliliters/point~100 standard milliliters/point, CH3The flow of F be 8 standard milliliters/point~50 standard milli
Liter/min, O2Flow be 10 standard milliliters/point~100 standard milliliters/point, radio-frequency power is 50 watts~300 watts, bias voltage
It it is 30 volts~100 volts, chamber pressure is the millitorr of 10 millitorrs~2000.
Optionally, the substrate includes：Substrate and the fin on the substrate；The gate structure is across described
Fin.
Optionally, there are Doped ions in the source and drain doping area；The technological parameter of the pocket region ion implanting includes：
Inject the conduction type of Doped ions in conduction type and the source and drain doping area of ion on the contrary, Implantation Energy be 2 kiloelectron-volts~
30 kiloelectron-volts, inject a concentration of 1.0e of ion13Atomicity/square centimeter~1.0e15Atomicity/square centimeter, injection side
To the extending direction perpendicular to the fin, and the angle of the injection direction and substrate normal is：10 degree~30 degree.
Correspondingly, the present invention also provides a kind of a kind of semiconductor structures formed using the above method, including：Substrate, institute
Stating has gate structure in substrate, the gate structure includes grid layer, has source and drain in the substrate of the gate structure both sides
There is dielectric layer in doped region, the substrate and source and drain doping area；Side wall opening between the dielectric layer and grid layer,
Positioned at the intrabasement pocket region of side wall open bottom.
Compared with prior art, the technical solution of the embodiment of the present invention has the advantages that：
In the forming method for the semiconductor structure that technical solution of the present invention provides, the source and drain doping area and dielectric layer are formed
Later, it removes the grid curb wall and forms side wall opening, the side wall opening is for subsequently to the base of the side wall open bottom
Bottom carries out pocket region ion implanting and forms pocket region.Since the substrate to the side wall open bottom carries out pocket region ion implanting
The high-temperature technology for being formed after forming the source and drain doping area, therefore forming the source and drain doping area, which is difficult to drive, to be subsequently formed
Pocket region in ion spread so that the concentration of the pocket region ion implanting is easy to control, and is formed by pocket region
Better performances.The pocket region is conducive to inhibit short-channel effect, to improve the performance of semiconductor structure.
Further, during forming source and drain doping area, using selective epitaxial depositing operation shape in the opening
At epitaxial layer, the technological parameter of the selective epitaxial depositing operation includes：Annealing temperature is 700 degrees Celsius~800 degrees Celsius,
Annealing time is 1 hour~2 hours.The formation process of the epitaxial layer carries out pocket in the fin to the side wall open bottom
It is carried out before area's ion implanting, therefore the high-temperature technology of the formation epitaxial layer and the annealing process of long period are difficult to drive
Ion in follow-up pocket region is spread so that the concentration of the pocket region ion implanting is easy to control, and is formed by pocket
The better performances in area.The pocket region is conducive to inhibit short-channel effect, to improve the performance of semiconductor structure.
Further, the injection direction of the pocket region ion implanting is perpendicular to the extending direction of the fin, and grid layer
Across the fin, therefore, the injection direction is parallel with the extending direction of the grid layer so as to the side wall open bottom
When the fin in portion carries out pocket region ion implanting, the side wall that the injection ion will not be open by side wall stops, i.e.,：To the side
The fin of wall open bottom carries out being not susceptible to shadow effect when the ion implanting of pocket region.Also, injection direction and substrate normal
Angle be：10 degree~30 degree so that the ion concentration at the top of fin and in the pocket region of side wall is uniform, is formed by pocket region
Better performances.The pocket region is conducive to inhibit short-channel effect, to improve the performance of semiconductor structure.
Description of the drawings
Fig. 1 to Fig. 2 is a kind of structural schematic diagram of each step of the forming method of semiconductor structure；
Fig. 3 to Figure 12 is the structural schematic diagram of each step of one embodiment of forming method of semiconductor structure of the present invention.
Specific implementation mode
As described in background, pocket region ion implanting is difficult in the prior art, and the pocket region poor performance formed.
Fig. 1 to Fig. 2 is a kind of structural schematic diagram of each step of the forming method of semiconductor structure.
Referring to FIG. 1, providing semiconductor substrate 100, there is fin 101 and separation layer in the semiconductor substrate 100
102, the top surface of the separation layer 102 is less than the top surface of the fin 101, and covers the part of the fin 101
Side wall；It is developed across the gate structure 103 of the fin 101.
Referring to FIG. 2, the fin 101 to 103 both sides of the gate structure carries out pocket region ion implanting.
After the pocket region ion implanting, further include：Form source and drain doping area.
However, poor using semiconducting behavior prepared by the above method, reason is：
In the above method, pocket region ion implanting is carried out described in formation to the fin 101 of 103 both sides of the gate structure
It is formed before source and drain doping area.The forming step in the source and drain doping area includes：Using etching technics in the gate structure 103
Opening is formed in the fin 101 of both sides；Epitaxial layer is formed using selective epitaxial depositing operation in the opening；Described outer
Prolong doped p-type ion or N-type ion in layer, forms the source and drain doping area.The technique of the selective epitaxial depositing operation is joined
Number includes：Annealing temperature is 700 degrees Celsius~800 degrees Celsius, and annealing time is 1 hour~2 hours.The formation of the epitaxial layer
Technique to the fin 101 of 103 both sides of the gate structure formed after the ion implanting of pocket region, therefore the epitaxial layer
Forming process in annealing process the ion in the pocket region can be driven to spread so that the pocket region ion implanting
Concentration be difficult to control, the performance for being formed by pocket region is poor, and the effect that the pocket region improves short-channel effect is poor, institute
The semiconductor structure poor performance of formation.
When carrying out pocket region ion implanting to the fin 101 of 103 both sides of the gate structure, the pocket region ion implanting
Injection direction be along perpendicular to the gate structure 103 extending direction.The injection direction of the pocket region ion implanting makes
Ion must be injected easily to be stopped by gate structure 103, the shadow effect of ion implanting easily occurs.Also, with semiconductor devices collection
The spacing of the continuous improvement of Cheng Du, neighboring gate structures 103 constantly reduces so that the groove being made of neighboring gate structures 103
Depth-to-width ratio it is larger so that shadow effect is more serious.I.e.：Pocket region is carried out to the fin 101 of 103 both sides of the gate structure
Ion implanting becomes more and more difficult.The pocket region ion implanting is difficult to be injected into the fin of 103 both sides of the gate structure
In 101 so that the performance for being formed by pocket region is poor so that the pocket region improve short-channel effect effect compared with
Difference is formed by semiconductor structure poor performance.
In order to solve the above technical problems, the present invention provides a kind of forming method of semiconductor structure, including：Substrate is provided,
There is gate structure, the gate structure includes grid layer and the grid curb wall on grid layer side wall, institute in the substrate
Stating has source and drain doping area in the substrate of gate structure both sides, have dielectric layer, the medium in the substrate and source and drain doping area
Layer covers the side wall of the gate structure, and the dielectric layer exposes at the top of grid curb wall；The grid curb wall is removed, is being situated between
Side wall opening is formed between matter layer and grid layer；Pocket region ion implanting is carried out to the substrate of the side wall open bottom and forms mouth
Bag area.
It in the method, is formed after the source and drain doping area and dielectric layer, removes the grid curb wall formation side wall and open
Mouthful, the side wall opening forms pocket region for subsequently carrying out pocket region ion implanting to the substrate of the side wall open bottom.
Since the substrate progress pocket region ion implanting to the side wall open bottom is formed after forming the source and drain doping area, because
This high-temperature technology for forming the source and drain doping area is difficult to drive the ion in the pocket region being subsequently formed to spread so that institute
The concentration for stating pocket region ion implanting is easy to control, and is formed by the better performances of pocket region.The pocket region is conducive to inhibit
Short-channel effect, to improve the performance of semiconductor structure.
It is understandable to enable above-mentioned purpose, feature and the advantageous effect of the present invention to become apparent, below in conjunction with the accompanying drawings to this
The specific embodiment of invention is described in detail.
After below for grid technique, illustrate the forming method of semiconductor structure of the present invention.
Fig. 3 to Figure 12 is the structural schematic diagram of each step of one embodiment of forming method of semiconductor structure of the present invention.
Referring to FIG. 3, providing substrate 200.
In the present embodiment, the substrate 200 includes：Substrate 201 and the fin 202 on the substrate 201.At it
In its embodiment, the substrate can also be planar substrates.
The forming step of the substrate 200 includes：Initial substrate is provided；The graphical initial substrate, forms substrate 201
With the fin 202 on substrate 201.
In the present embodiment, the material of the initial substrate is silicon.In other embodiments, the initial substrate can also be
The semiconductor substrates such as germanium substrate, silicon-Germanium substrate, silicon-on-insulator or germanium on insulator.
In the present embodiment, there is isolation structure 203 on the substrate 201.
The forming step of the isolation structure 203 includes：Spacer material layer is formed on substrate 201 and fin 202；Using
Chemical machinery polishes technique and is planarized to the spacer material layer；Etching removal the part spacer material layer, formed every
From structure 203.The isolation structure 203 covers 202 partial sidewall surface of the fin, and the top of the isolation structure 203
Surface is less than the top surface of the fin 202.
The forming method of the spacer material layer includes：Chemical vapor deposition method.
The material of the isolation structure 203 includes：Silica.In other embodiments, the material of the isolation structure is also
Can be silicon oxynitride, silicon nitride.
The isolation structure 203 is for realizing the electrical isolation between different semiconductor devices.
It please refers to Fig.4 and Fig. 5, Fig. 5 is cross-sectional views of the Fig. 4 along A-A ' lines, formed in the substrate 200 pseudo-
Grid structure, dummy gate structure include dummy gate layer 204 and the grid curb wall 205 in the dummy gate layer 204.
Dummy gate structure further includes：Pseudo- gate dielectric layer (not shown), the puppet gate dielectric layer cover the fin
202 partial sidewalls and top surface；The dummy gate layer 204 is located on the pseudo- gate dielectric layer；The also position of the grid curb wall 205
In on the side wall of pseudo- gate dielectric layer.
In the present embodiment, the material of the pseudo- gate dielectric layer is silica.In other embodiments, the pseudo- gate medium
The material of layer can also be silicon nitride or silicon oxynitride.
In the present embodiment, the material of the dummy gate layer 204 is polysilicon.
In the present embodiment, the top surface of dummy gate structure has mask layer (not marked in figure), the mask layer
Material include silicon nitride, the mask layer forms the mask of the dummy gate layer 204 as etching.
The grid curb wall 205 is for defining the position for being subsequently formed source and drain doping area.
Referring to FIG. 6, forming source and drain doping area 206 in dummy gate structure both sides substrate 200.
It should be noted that Fig. 6 is consistent with the profile direction of Fig. 5.
The forming step in the source and drain doping area 206 includes：Fin using etching technics in the dummy gate structure both sides
Opening is formed in portion 202；Epitaxial layer is formed using selective epitaxial depositing operation in the opening；It is mixed in the epitaxial layer
Miscellaneous p-type ion or N-type ion form the source and drain doping area 206.
The technological parameter of the selective epitaxial depositing operation includes：Annealing temperature is 700 degrees Celsius~800 degrees Celsius,
Annealing time is 1 hour~2 hours.Select the epitaxial layer that the technological parameter of the selective epitaxial depositing operation is formed preferable,
Be conducive to improve the performance of semiconductor structure.
Moreover, when forming the epitaxial layer, side wall opening and the substrate progress pocket region ion note to side wall open bottom
Enter and do not carry out, therefore the high-temperature technology of the formation epitaxial layer and the annealing process of long period are difficult to drive and be subsequently formed
Pocket region in ion spread so that the concentration of follow-up pocket region ion implanting is easy to control, and is formed by pocket region
Better performances.The pocket region is conducive to inhibit short-channel effect, to improve the performance of semiconductor structure.
Referring to FIG. 7, being formed after the source and drain doping area 206, the shape in the substrate 200 and source and drain doping area 206
At dielectric layer 207, the dielectric layer 207 covers the side wall of the dummy gate structure, and the dielectric layer 207 exposes gate electrode side
The top of wall 205.
The forming step of the dielectric layer 207 includes：In the substrate 200, source and drain doping area 206 and pseudo- grid structure
Top surface formed deielectric-coating；The deielectric-coating is planarized, medium is formed in the substrate 200 and source and drain doping area 206
Layer 207, the dielectric layer 207 covers the side wall of dummy gate structure, and the dielectric layer 207 exposes grid curb wall 205
Top.
The material of the deielectric-coating includes：Silica.
The forming method of the deielectric-coating includes：Fluid chemistry gas-phase deposition.
In the present embodiment, the technique for planarizing the deielectric-coating is CMP process.
The dielectric layer 207 is for realizing the electric isolution between semiconductor different components.
Referring to FIG. 8, being formed after the dielectric layer 207, removal dummy gate layer 204 (as shown in Figure 7) and pseudo- gate medium
Layer (not shown) forms pseudo- grid opening 208.
In the present embodiment, the forming step of the pseudo- grid opening 208 includes：Remove dummy gate layer 204；Remove dummy grid
After layer 204, pseudo- gate dielectric layer is removed.
The technique for removing the dummy gate layer 204 includes：Dry etch process or wet-etching technology.
The technique of the pseudo- gate dielectric layer of removal includes：Dry etch process or wet-etching technology.
In the present embodiment, 208 bottom-exposeds of the pseudo- grid opening go out the top surface of the fin 202.In other realities
It applies in example, the forming step of the puppet grid opening includes：Only remove dummy gate layer；The bottom-exposed of the puppet grid opening goes out pseudo- grid
The top surface of dielectric layer.
The puppet grid opening 208 is for being subsequently formed gate structure.
Referring to FIG. 9, forming gate structure 209 in the pseudo- grid opening 208.
Gate structure 209 includes：Gate dielectric layer 210 is formed in the side wall of the gate openings 208 and bottom；Described in formation
After gate dielectric layer 210, grid layer 211 is formed on the gate dielectric layer 210.
In the present embodiment, the material of the gate dielectric layer 210 is high K dielectric material, the K values of the high K dielectric material
Range is：K is more than 3.9, and the material of the gate dielectric layer 210 includes：Hafnium oxide.
In the present embodiment, the material of the grid layer 211 includes metal, and the metal includes：Tungsten.
After forming gate dielectric layer 210, is formed before grid layer 211, work function is formed on the gate dielectric layer 210
212, the work function 212 is for reducing threshold voltage.
Referring to FIG. 10, being formed after gate structure 209, grid curb wall 205 is removed, forms side wall opening 213.
Removal grid curb wall 205 technique include：Anisotropic etch process, the technique of the anisotropic etch process
Parameter includes：Etching gas includes CF4、CH3F and O2, wherein CF4Flow be 5 standard milliliters/point~100 standard milliliters/
Point, CH3The flow of F be 8 standard milliliters/point~50 standard milliliters/point, O2Flow be 10 standard milliliters/point~100 standard milli
Liter/min, radio-frequency power is 50 watts~300 watts, and bias voltage is 30 volts~100 volts, and chamber pressure is the millitorr of 10 millitorrs~2000.
In this example, the side wall opening 213 is formed after forming gate structure 209.
In this example, 213 selection of side wall opening is formed after forming gate structure 209, without selecting
The reasons why being formed after dielectric layer 207, being formed before forming pseudo- grid opening 208 is：If the side wall opening 213 is forming Jie
It after matter layer 207, is formed before forming pseudo- grid opening 208, subsequently in order to form pseudo- grid opening 208, in the pseudo- gate dielectric layer of removal
When, the dielectric layer 207 is easy to happen damage so that semiconductor different components can not be effectively isolated, between different components
It is easy electric leakage, is unfavorable for improving the performance of semiconductor structure.
In other embodiments, removing pseudo- grid structure only includes：Remove dummy gate layer.The side wall opening is described in formation
After dielectric layer, formed before forming pseudo- grid opening；Alternatively, the side wall opening is formed after formation of the gate structure.
Fin 202 progress pocket region ion note of the side wall opening 213 for 213 bottoms that are subsequently open to the side wall
Enter.
1 is please referred to Fig.1, the progress pocket region ion implanting formation pocket of fin 202 for 213 bottoms that are open to the side wall
Area.
Pocket region ion implanting is carried out to the fin 202 of 213 bottoms of side wall opening, is forming the source and drain doping area
206 and dielectric layer 207 after carry out meaning be：Pocket region ion is carried out to the fin 202 of 213 bottoms of side wall opening
Injection is formed after forming the source and drain doping area 206 so that formed the source and drain doping area 206 high-temperature technology and
The annealing process of long period is difficult to drive the ion of pocket region to spread so that the concentration of the pocket region ion implanting is held
It is easy to control, it is formed by the better performances of pocket region.The pocket region is conducive to inhibit short-channel effect, to improve semiconductor
The performance of structure.
The technological parameter of the pocket region ion implanting includes：It injects in conduction type and the source and drain doping area 206 of ion
The conduction types of Doped ions injects a concentration of 1.0e of ion on the contrary, Implantation Energy is 2 kiloelectron-volts~30 kiloelectron-volts13
Atomicity/square centimeter~1.0e15Atomicity/square centimeter, injection direction perpendicular to the fin 202 extending direction, and
The injection direction is in θ angles with 201 normal of substrate, and the θ angles are ranging from：10 degree~30 degree.
Injection direction is perpendicular to the meaning of the extending direction of the fin 202：The note of the pocket region ion implanting
Enter extending direction of the direction perpendicular to the fin 202, and grid layer 211 is across the fin 202, therefore, the injection side
To parallel with the extending direction of the grid layer 211 so that carry out pocket region to the be open fin 202 of 213 bottoms of the side wall
When ion implanting, the injection ion will not be stopped by the side wall of side wall opening 213, i.e.,：To 213 bottoms of side wall opening
Be not in shadow effect when the progress pocket region ion implanting of fin 202.
The meaning of the θ angles is selected to be：If the θ angles are less than 10 degree, the fin for 213 bottoms that are open to the side wall
The ion concentration that portion 202 is injected is excessively high so that the capacitance of the fin 202 is larger, is unfavorable for improving the performance of semiconductor structure；
If the θ angles are more than 30 degree, the ion concentration injected to the fin 202 of 213 bottoms of side wall opening is too low, is formed by
Pocket region is weaker to improving short-channel effect, is formed by semiconductor structure poor performance.The folder of injection direction and 201 normal of substrate
Angle is：10 degree~30 degree so that the ion concentration in 202 top of fin and the pocket region of side wall is uniform, is formed by pocket region
Better performances, the pocket region be conducive to inhibit short-channel effect, to improve the performance of semiconductor structure.
2 are please referred to Fig.1, first medium layer 214 is formed in side wall opening 213.
The forming step of the first medium layer 214 includes：In side wall opening 213 and on gate structure 209
Form first medium film；The first medium film is planarized until exposing the top surface of grid layer 211, forms first medium
Layer 214.
The formation process of the first medium film includes：Fluid chemistry gas-phase deposition.
The material of the first medium layer 214 includes：Silica.
To sum up, in the present embodiment, it is formed after the source and drain doping area and dielectric layer, removes the grid curb wall and formed
Side wall is open, and the side wall opening forms mouth for subsequently carrying out pocket region ion implanting to the substrate of the side wall open bottom
Bag area.Since the substrate to the side wall open bottom carries out pocket region ion implanting shape after forming the source and drain doping area
At, therefore the high-temperature technology for forming the source and drain doping area is difficult to that the ion for the pocket region being subsequently formed is driven to spread, and makes
The concentration for obtaining the pocket region ion implanting is easy to control, and is formed by the better performances of pocket region.The pocket region is conducive to
Inhibit short-channel effect, to improve the performance of semiconductor structure.
Correspondingly, the embodiment of the present invention also provide it is a kind of semiconductor structure is formed by using the above method, please refer to figure
11, including：
Substrate 200, it includes grid layer 211, institute to have gate structure 209, the gate structure 209 in the substrate 200
Stating has source and drain doping area 206 in the substrate 200 of 209 both sides of gate structure, have in the substrate 200 and source and drain doping area 206
There is dielectric layer 207；Side wall opening 213 between the dielectric layer 207 and grid layer 211 is located at 213 bottoms of side wall opening
Intrabasement pocket region.
Although present disclosure is as above, present invention is not limited to this.Any those skilled in the art are not departing from this
It in the spirit and scope of invention, can make various changes or modifications, therefore protection scope of the present invention should be with claim institute
Subject to the range of restriction.
Claims (17)
1. a kind of forming method of semiconductor structure, which is characterized in that including：
Substrate is provided, there is gate structure, the gate structure to include grid layer and be located on grid layer side wall in the substrate
Grid curb wall, there is in the substrate of the gate structure both sides source and drain doping area, have in the substrate and source and drain doping area and be situated between
Matter layer, the dielectric layer covers the side wall of the gate structure, and the dielectric layer exposes at the top of grid curb wall；
The grid curb wall is removed, forms side wall opening between dielectric layer and grid layer；
Pocket region ion implanting is carried out to the substrate of the side wall open bottom and forms pocket region.
2. the forming method of semiconductor structure as described in claim 1, which is characterized in that the formation in the source and drain doping area walks
Suddenly include：Opening is formed in the substrate of the gate structure both sides using etching technics；Using selective epitaxial depositing operation
Epitaxial layer is formed in the opening；Doped p-type ion or N-type ion in the epitaxial layer, form the source and drain doping area.
3. the forming method of semiconductor structure as claimed in claim 2, which is characterized in that the selective epitaxial depositing operation
Technological parameter include：Annealing temperature is 700 degrees Celsius~800 degrees Celsius, and annealing time is 1 hour~2 hours.
4. the forming method of semiconductor structure as described in claim 1, which is characterized in that the gate structure further includes：Grid
Dielectric layer；The grid layer is located on the gate dielectric layer；Grid curb wall is also located on the side wall of gate dielectric layer.
5. the forming method of semiconductor structure as claimed in claim 4, which is characterized in that the material packet of the gate dielectric layer
It includes：Silica；The material of the grid layer includes：Silicon.
6. the forming method of semiconductor structure as claimed in claim 4, which is characterized in that the material packet of the gate dielectric layer
It includes：High K dielectric material, the K values of the high K dielectric material are ranging from：K values are more than 3.9；The material of the grid layer includes：Gold
Belong to, the metal includes：Tungsten.
7. the forming method of semiconductor structure as claimed in claim 6, which is characterized in that the gate structure, source and drain doping
The forming step of area and dielectric layer includes：Pseudo- grid structure is formed on the substrate, and dummy gate structure includes dummy gate layer
And the grid curb wall on the dummy gate layer side wall；Source and drain doping is formed in the substrate of dummy gate structure both sides
Area；Dielectric layer is formed in the substrate and source and drain doping area, the dielectric layer covers the side wall of dummy gate structure, and described
Dielectric layer exposes at the top of grid curb wall；It is formed after the dielectric layer, removal dummy gate layer forms pseudo- grid opening；In the puppet
Grid layer is formed in grid opening.
8. the forming method of semiconductor structure as claimed in claim 7, which is characterized in that the material packet of the dummy gate layer
It includes：Silicon.
9. the forming method of semiconductor structure as claimed in claim 7, which is characterized in that after forming the dielectric layer,
It is formed before pseudo- grid opening, removes the grid curb wall and form side wall opening；Alternatively, after formation of the gate structure, removing institute
It states grid curb wall and forms side wall opening.
10. the forming method of semiconductor structure as claimed in claim 7, which is characterized in that dummy gate structure further includes：It is pseudo-
Gate dielectric layer；The dummy gate layer is located on the pseudo- gate dielectric layer；The grid curb wall is also located at the side wall of pseudo- gate dielectric layer
On；The step of pseudo- grid are open is formed, further includes：After removing dummy gate layer, pseudo- gate dielectric layer is removed.
11. the forming method of semiconductor structure as claimed in claim 10, which is characterized in that the material of the puppet gate dielectric layer
Including：Silica.
12. the forming method of semiconductor structure as claimed in claim 10, which is characterized in that after formation of the gate structure,
Removal grid curb wall forms the side wall opening.
13. the forming method of semiconductor structure as described in claim 1, which is characterized in that remove the work of the grid curb wall
Skill includes：Anisotropic etch process.
14. the forming method of semiconductor structure as claimed in claim 13, which is characterized in that the anisotropic etch process
Technological parameter include：Etching gas includes CF4、CH3F and O2, wherein CF4Flow be 5 standard milliliters/point~100 standards
Ml/min, CH3The flow of F be 8 standard milliliters/point~50 standard milliliters/point, O2Flow be 10 standard milliliters/point~100 mark
Quasi- ml/min, radio-frequency power are 50 watts~300 watts, and bias voltage is 30 volts~100 volts, and chamber pressure is 10 millitorr~2000
Millitorr.
15. the forming method of semiconductor structure as described in claim 1, which is characterized in that the substrate includes：Substrate and
Fin on the substrate；The gate structure is across the fin.
16. the forming method of semiconductor structure as claimed in claim 15, which is characterized in that have in the source and drain doping area
Doped ions；The technological parameter of the pocket region ion implanting includes：The conduction type of injection ion is mixed with source and drain doping area
The conduction type of heteroion injects a concentration of 1.0e of ion on the contrary, Implantation Energy is 2 kiloelectron-volts~30 kiloelectron-volts13It is former
Subnumber/square centimeter~1.0e15Atomicity/square centimeter, injection direction is perpendicular to the extending direction of the fin, and the note
The angle for entering direction and substrate normal is 10 degree~30 degree.
17. a kind of being formed by semiconductor structure using such as any one of claim 1 to 16 method, which is characterized in that including：
Substrate has gate structure in the substrate, and the gate structure includes grid layer, the substrate of the gate structure both sides
It is interior that there is source and drain doping area, there is dielectric layer in the substrate and source and drain doping area；
Side wall opening between the dielectric layer and grid layer, is located at the intrabasement pocket region of side wall open bottom.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710160464.2A CN108630543B (en) | 2017-03-17 | 2017-03-17 | Semiconductor structure and forming method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710160464.2A CN108630543B (en) | 2017-03-17 | 2017-03-17 | Semiconductor structure and forming method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN108630543A true CN108630543A (en) | 2018-10-09 |
| CN108630543B CN108630543B (en) | 2022-02-15 |
Family
ID=63687823
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201710160464.2A Active CN108630543B (en) | 2017-03-17 | 2017-03-17 | Semiconductor structure and forming method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN108630543B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114446812A (en) * | 2020-11-06 | 2022-05-06 | 长鑫存储技术有限公司 | Test structure and manufacturing method thereof |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6391728B1 (en) * | 2001-03-12 | 2002-05-21 | Advanced Micro Devices, Inc. | Method of forming a highly localized halo profile to prevent punch-through |
| CN103855004A (en) * | 2012-11-28 | 2014-06-11 | 中芯国际集成电路制造(上海)有限公司 | Transistor forming method |
| CN103943502A (en) * | 2013-01-22 | 2014-07-23 | 中芯国际集成电路制造(上海)有限公司 | Fin field effect transistor and forming method thereof |
| CN104795331A (en) * | 2014-01-21 | 2015-07-22 | 中芯国际集成电路制造(上海)有限公司 | Transistor formation method |
-
2017
- 2017-03-17 CN CN201710160464.2A patent/CN108630543B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6391728B1 (en) * | 2001-03-12 | 2002-05-21 | Advanced Micro Devices, Inc. | Method of forming a highly localized halo profile to prevent punch-through |
| CN103855004A (en) * | 2012-11-28 | 2014-06-11 | 中芯国际集成电路制造(上海)有限公司 | Transistor forming method |
| CN103943502A (en) * | 2013-01-22 | 2014-07-23 | 中芯国际集成电路制造(上海)有限公司 | Fin field effect transistor and forming method thereof |
| CN104795331A (en) * | 2014-01-21 | 2015-07-22 | 中芯国际集成电路制造(上海)有限公司 | Transistor formation method |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114446812A (en) * | 2020-11-06 | 2022-05-06 | 长鑫存储技术有限公司 | Test structure and manufacturing method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN108630543B (en) | 2022-02-15 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN104022037B (en) | Fin formula field effect transistor and forming method thereof | |
| US7354839B2 (en) | Gate structure and a transistor having asymmetric spacer elements and methods of forming the same | |
| CN107958873B (en) | Fin type field effect transistor and forming method thereof | |
| US10971590B2 (en) | Transistor layout to reduce kink effect | |
| CN104752214B (en) | The forming method of fin field effect pipe | |
| CN107799591A (en) | Ldmos and forming method thereof | |
| US7419867B2 (en) | CMOS gate structure comprising predoped semiconductor gate material with improved uniformity of dopant distribution and method of forming the structure | |
| CN106486350B (en) | The forming method of semiconductor structure | |
| CN107919324B (en) | Method for forming semiconductor device | |
| CN103413763A (en) | Super junction transistor and forming method thereof | |
| CN112825327A (en) | Semiconductor structure and forming method thereof | |
| CN111180513A (en) | Semiconductor device and method of forming the same | |
| CN108666219A (en) | Semiconductor devices and forming method thereof | |
| CN106856170B (en) | The forming method of fin formula field effect transistor | |
| CN106449405B (en) | The forming method of semiconductor structure | |
| KR100840661B1 (en) | Semiconductor Device and Manufacturing Method Thereof | |
| CN102386226B (en) | Semiconductor structure and manufacturing method thereof | |
| CN104425520B (en) | Semiconductor devices and forming method | |
| CN104752216B (en) | The forming method of transistor | |
| CN106449404B (en) | Semiconductor structure and forming method thereof | |
| CN106935505A (en) | The forming method of fin formula field effect transistor | |
| CN106558493B (en) | Method for forming fin field effect transistor | |
| CN106328503B (en) | The forming method of semiconductor structure | |
| US11682725B2 (en) | Semiconductor device with isolation layer | |
| CN108630543A (en) | Semiconductor structure and forming method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |