CN103515209A - Fin field effect transistor and formation method thereof - Google Patents

Fin field effect transistor and formation method thereof Download PDF

Info

Publication number
CN103515209A
CN103515209A CN201210203757.1A CN201210203757A CN103515209A CN 103515209 A CN103515209 A CN 103515209A CN 201210203757 A CN201210203757 A CN 201210203757A CN 103515209 A CN103515209 A CN 103515209A
Authority
CN
China
Prior art keywords
fin
field effect
sub
fin field
epitaxial loayer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201210203757.1A
Other languages
Chinese (zh)
Other versions
CN103515209B (en
Inventor
三重野文健
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Semiconductor Manufacturing International Shanghai Corp
Original Assignee
Semiconductor Manufacturing International Shanghai Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Semiconductor Manufacturing International Shanghai Corp filed Critical Semiconductor Manufacturing International Shanghai Corp
Priority to CN201210203757.1A priority Critical patent/CN103515209B/en
Publication of CN103515209A publication Critical patent/CN103515209A/en
Application granted granted Critical
Publication of CN103515209B publication Critical patent/CN103515209B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/66818—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET the channel being thinned after patterning, e.g. sacrificial oxidation on fin
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823431—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

The invention provides a fin field effect transistor and a formation method thereof. The formation method of the fin field effect transistor comprises: providing a semiconductor substrate, the surface of which is covered with insulation layers, first sub-fin portions which run through the thickness of the insulation layers and are flush with the surfaces of the insulation layers, and epitaxial intrinsic layers which are arranged on the surfaces of the first sub-fin portions, wherein the first sub-fin portions are internally provided with doping ions, and the epitaxial intrinsic layers are not provided with doping ions; forming isolation layers on the surfaces of the epitaxial intrinsic layers, wherein each isolation layer is provided with an opening which defines a gate structure; trimming the epitaxial intrinsic layers in the openings and performing doping on the trimmed epitaxial intrinsic layers; forming epitaxial layers in the openings, wherein the epitaxial layers uniformly cover the tops and side walls of the doped epitaxial intrinsic layers; and forming gate structures which stretch across the tops and side walls of the epitaxial layers. A threshold voltage of the formed fin field effect transistor is low; a gate leakage current is small; and device performance is stable.

Description

Fin field effect pipe and forming method thereof
Technical field
The present invention relates to technical field of manufacturing semiconductors, relate in particular to a kind of fin field effect pipe and forming method thereof.
Background technology
Fin field effect pipe (Fin FET) is a kind of common multiple-grid device, and Fig. 1 shows the perspective view of a kind of fin field effect pipe of prior art.As shown in Figure 1, comprising: Semiconductor substrate 10, in described Semiconductor substrate 10, be formed with the fin 14 of protrusion, fin 14 is generally by obtaining after Semiconductor substrate 10 etchings; Dielectric layer 11, covers the part of the surface of described Semiconductor substrate 10 and the sidewall of fin 14; Grid structure 12, across on described fin 14, covers described fin 14 top and sidewall, and grid structure 12 comprises gate dielectric layer (not shown) and is positioned at the gate electrode (not shown) on gate dielectric layer.For Fin FET, the part that the sidewall of fin 14 top and both sides contacts with grid structure 12 all becomes channel region, has a plurality of grid, is conducive to increase drive current, improves device performance.
Yet along with further reducing of process node, the device performance of the fin formula field effect transistor of prior art existing problems.
More structures about fin formula field effect transistor and formation method please refer to the United States Patent (USP) that the patent No. is " US7868380B2 ".
Summary of the invention
The problem that the present invention solves is to provide fin field effect pipe that a kind of device performance is good and forming method thereof.
For addressing the above problem, embodiments of the invention provide a kind of formation method of fin field effect pipe, comprise: Semiconductor substrate is provided, described semiconductor substrate surface is coated with insulating barrier, the the first sub-fin that runs through described thickness of insulating layer and flush with described surface of insulating layer, be positioned at the extension intrinsic layer on described the first sub-fin surface, wherein, in described the first sub-fin, there is doping ion; On described extension intrinsic layer surface, form separator, described separator has the opening that defines grid structure; Described extension intrinsic layer in described opening is pruned, and the extension intrinsic layer after pruning is adulterated, form the second sub-fin; In described opening, form epitaxial loayer, top and the sidewall of the second sub-fin described in described epitaxial loayer uniform fold; In described opening, form across the top of described epitaxial loayer and the grid structure of sidewall.
Alternatively, in described epitaxial loayer, the ion concentration scope of doping is 0 atoms/cm 3-1E16atoms/cm 3.
Alternatively, the formation technique of described epitaxial loayer is selective epitaxial depositing operation.
Alternatively, the material of described epitaxial loayer is monocrystalline silicon, germanium, SiGe or III-V compounds of group.
Alternatively, when the material of described epitaxial loayer is monocrystalline silicon, the reacting gas that forms described epitaxial loayer employing is silicon source gas, HCl and H 2, reaction pressure is 0.1-1.0 holder, reaction temperature is 500 ℃-800 ℃.
Alternatively, the thickness of described epitaxial loayer is 5nm-25nm.
Alternatively, the width of described extension intrinsic layer is 20nm-100nm.
Alternatively, the width of the extension intrinsic layer after described pruning is 10nm-50nm.
Alternatively, the extension intrinsic layer after pruning is adulterated, the technique that forms the second sub-fin is molecular monolayer doping process.
Alternatively, the processing step of described molecular monolayer doping process comprises: the extension intrinsic layer of the hydrofluoric acid that adopts dilution after to described pruning cleans; After end to be cleaned, the solvent with high burning-point is doped in the extension intrinsic layer after described pruning, forms the second sub-fin; Adopt low temperature oxidation technology to form silicon oxide layer on described the second sub-fin surface; Adopt spike annealing technique to carry out annealing in process to described the second sub-fin.
Alternatively, the solvent of described high burning-point is triphenylphosphine solution.
Alternatively, the thickness of described silicon oxide layer is 15 nanometer-40 nanometers.
Alternatively, temperature during described spike annealing is 1000 degrees Celsius-1100 degrees Celsius.
Alternatively, in described the second sub-fin, the ion of doping comprises carbon ion or germanium ion.
Alternatively, the concentration range of described the second sub-fin doping ion is: 1E17atoms/cm 3-1E18atoms/cm 3.
Alternatively, in described the first sub-fin, the ion concentration scope of doping is: 1E18atoms/cm 3-1E19atoms/cm 3.
Alternatively, described Semiconductor substrate comprises first area and adjacent second area with it, and described first area is used to form N channel fin formula field effect transistor, and described second area is used to form P channel fin formula field effect transistor.
Accordingly, inventor also provides a kind of fin field effect pipe, comprising: Semiconductor substrate; Described semiconductor substrate surface is coated with insulating barrier; The the first sub-fin that runs through described thickness of insulating layer and flush with described surface of insulating layer; The extension intrinsic layer and the second sub-fin that are positioned at described the first sub-fin surface, the width of described the second sub-fin is less than the width of described the first sub-fin; The separator that is positioned at insulating barrier and extension intrinsic layer surface, described separator has the opening that runs through its thickness, and described opening exposes described the second sub-fin; Be positioned at the epitaxial loayer of described opening, top and the sidewall of described epitaxial loayer uniform fold the second sub-fin; Be positioned at described opening and across the top of described epitaxial loayer and the grid structure of sidewall.
Alternatively, in described epitaxial loayer, the concentration range of doping ion is 0atoms/cm 3-1E 16atoms/cm 3.
Alternatively, the material of described epitaxial loayer is monocrystalline silicon, germanium, SiGe or III-V compounds of group.
Alternatively, the thickness of described epitaxial loayer is 5nm-25nm.
Alternatively, the width of described the second sub-fin is 10nm-50nm.
Alternatively, in described the second sub-fin, the concentration range of doping ion is: 1E17atoms/cm 3-1E18atoms/cm 3.
Alternatively, the doping ion in described the second sub-fin comprises carbon ion or germanium ion.
Alternatively, in described the first sub-fin, the ion concentration scope of doping is: 1E18atoms/cm 3-1E19atoms/cm 3.
Compared with prior art, embodiments of the invention have the following advantages:
While forming fin field effect pipe, first form the first sub-fin and the plain extension intrinsic layer of doping, then the extension intrinsic layer in opening is pruned and adulterated, form the second sub-fin, then in opening, form the top of uniform fold the second sub-fin and the epitaxial loayer of sidewall, form technique simple, the fin field effect pipe forming the not only carrier mobility of channel region is high, and threshold voltage is low, grid leakage current is little, and device performance is stable.
Further, the width of the extension intrinsic layer after pruning is less, is 10nm-50nm.The extension intrinsic layer adulterating after described pruning, the technique adopting while forming the second sub-fin is molecular monolayer doping process, and the ion distribution in the second sub-fin of formation is even, and the threshold voltage of the fin field effect pipe of follow-up formation is lower.
Further, can at first area I and second area II, form N channel fin formula field effect transistor and P channel fin formula field effect transistor respectively, form technique simple, the performance of the CMOS fin field effect pipe of formation is good.
The fin of described fin field effect pipe is by the first sub-fin, be positioned at the second sub-fin on described the first sub-fin surface, jointly form with the top of the second sub-fin described in uniform fold and the epitaxial loayer of sidewall, owing to thering is doping ion in described the first sub-fin, improved the carrier mobility of fin field effect pipe channel region, and in the second sub-fin, there is doping ion, effectively reduce the threshold voltage of fin field effect pipe, and the existence due to epitaxial loayer, the grid leakage current that has effectively suppressed fin field effect pipe, the device performance of the fin field effect pipe of the embodiment of the present invention is stable.
Accompanying drawing explanation
Fig. 1 is the perspective view of the fin field effect pipe of prior art;
Fig. 2 is the schematic flow sheet of embodiment of the formation method of fin field effect pipe of the present invention;
Fig. 3-Figure 19 is the structural representation of formation method of the embodiment of fin field effect pipe of the present invention.
Embodiment
The device performance existing problems of the fin formula field effect transistor that as described in background, prior art forms.
Through research, inventor finds, the reason that affects the stability of fin field effect pipe has a plurality of, one of them reason is: prior art forms fin 14(as shown in Figure 1 at semiconductor substrate surface) after, while adulterating ion by the top surface of described fin 14 to fin 14 inside, the ion concentration at position, described fin 14 stage casing is the highest, and the ion concentration in fin 14 is reduced (doping tail) gradually to two ends by position, stage casing, also can inevitably there is more doping ion in described fin 14 tops, the fin field effect pipe that the fin 14 that adopts described top to have more doping ion forms, its grid leakage current increases, the unstable properties of fin field effect pipe.
Further, inventor finds, forms in the process of fin, can first form the first sub-fin, in described the first sub-fin, has doping ion, then forms plain extension intrinsic layer.The carrier mobility that had so both improved fin field effect pipe channel region, can not cause grid leakage current again, the stable performance of the fin field effect pipe of formation.
Further, inventor finds, if extension intrinsic layer is pruned, and to adulterating in the extension intrinsic layer after pruning, form the second sub-fin, on the second sub-fin surface, form epitaxial loayer, then form across the top of described epitaxial loayer and the grid structure of sidewall, the final fin field effect pipe forming not only can reach above-mentioned effect, and can reduce the threshold voltage of fin field effect pipe, further improves the performance of fin field effect pipe.
For above-mentioned purpose of the present invention, feature and advantage can be become apparent more, below in conjunction with accompanying drawing, the specific embodiment of the present invention is described in detail.
Please refer to Fig. 2, the formation method of the fin field effect pipe of the embodiment of the present invention, comprising:
Step S201, provides Semiconductor substrate, and described semiconductor substrate surface is coated with insulating barrier, the the first sub-fin that runs through described thickness of insulating layer and flush with described surface of insulating layer, be positioned at the extension intrinsic layer on described the first sub-fin surface, wherein, in described the first sub-fin, there is doping ion;
Step S203, forms separator on described extension intrinsic layer surface, and described separator has the opening that defines grid structure;
Step S205, prunes the described extension intrinsic layer in described opening, and the extension intrinsic layer after pruning is adulterated, and forms the second sub-fin;
Step S207 forms epitaxial loayer in described opening, top and the sidewall of the second sub-fin described in described epitaxial loayer uniform fold;
Step S209 forms across the top of described epitaxial loayer and the grid structure of sidewall in described opening.
Concrete, please refer to Fig. 3-Figure 13, Fig. 3-Figure 13 shows the cross-sectional view of forming process of the embodiment of fin field effect pipe of the present invention.
Please refer to Fig. 3, Semiconductor substrate 300 is provided, described Semiconductor substrate 300 surfaces have insulating barrier 301.
Described Semiconductor substrate 300 is used to subsequent technique that workbench is provided.Described Semiconductor substrate 300 is silicon substrate (Si) or silicon-on-insulator (SOI).In an embodiment of the present invention, described Semiconductor substrate 300 comprises first area I and adjacent second area II with it, and described first area I is used to form N channel fin formula field effect transistor, and described second area II is used to form P channel fin formula field effect transistor.The material of described Semiconductor substrate 300 is monocrystalline silicon.
Described insulating barrier 301 is for isolating adjacent fin.The material of described insulating barrier 301 is silica, silicon nitride, silicon oxynitride etc.The formation technique of described insulating barrier 301 is depositing operation, for example physical gas-phase deposition (PVD) or chemical vapor deposition method (CVD).In an embodiment of the present invention, the follow-up shallow trench isolation that is used to form of described insulating barrier 301 is from (STI), and the material of described insulating barrier 301 is silica, and the formation technique of described insulating barrier 301 is low-pressure chemical vapor deposition process (LPCVD).
It should be noted that, in embodiments of the invention, also comprise: form the dielectric layer 302 that is positioned at described Semiconductor substrate 300 surfaces, described dielectric layer 302 is for isolating the insulating barrier 301 of first area I and second area II.For the ease of follow-up removal insulating barrier 301, the material of described dielectric layer 302 is different from the material of described insulating barrier 301, and the speed of subsequent etching insulating barrier 301 is greater than the speed of etching dielectric layer 302.
Please refer to Fig. 4, form the groove 303 that runs through described insulating barrier 301 thickness, and at the sub-fin 305 of the interior formation first of described groove 303.
Described groove 303 runs through described insulating barrier 301 thickness, the follow-up window as forming fin.In an embodiment of the present invention, form after described groove 303, before formation the first sub-fin, also comprise: the insulating barrier 301 forming after groove 303 is carried out to planarization, for example isotropic etching technics (isotropic etching) or steam annealing technique (steam annealing), have an even surface insulating barrier 301.
Inventor finds, when ion is adulterated in the fin bottom forming, can improve the carrier mobility of fin field effect pipe channel region.Based on this, described the first sub-fin 305 has doping ion, for follow-up formation fin.When the ion concentration scope of described the first sub-fin 305 interior doping is: 1E18atoms/cm 3-1E19atoms/cm 3time, the carrier mobility of the fin field effect pipe channel region of formation is high.
The formation technique of described the first sub-fin 305 is selective epitaxial depositing operation, in order to save processing step and the ion that makes to adulterate is evenly distributed in the first sub-fin 305, the gas that described selective epitaxial depositing operation adopts comprises silicon source gas and doped source gas.Wherein, described silicon source gas is SiH 2cl 2or SiH 4, described doped source gas is C 3h 8, CH 4, AsH 3, PH 3or B 2h 6.In order to accelerate deposition rate, the gas that described selective epitaxial depositing operation adopts can also comprise hydrogen chloride and hydrogen.
In an embodiment of the present invention, the process parameters range of described selective epitaxial depositing operation is: depositing temperature is 650 ℃-750 ℃, the pressure of deposition chambers is 0.3 holder-1.0 holder, the quality of the first sub-fin 305 forming is good, the carrier mobility of the fin field effect pipe channel region of follow-up formation is high, the stable performance of the fin field effect pipe of formation.
It should be noted that, in an embodiment of the present invention, also comprise: described the first sub-fin 305 is heat-treated, so that the doping ion in the first sub-fin 305 further spreads evenly, make the fin field effect Guan channel region carrier mobility of follow-up formation high.Described process of thermal treatment parameter comprises: heat treatment temperature (anneal tempreature) is 600 ℃-1000 ℃, and heat treatment pressure (anneal pressure) is 1 atmospheric pressure, and heat treatment time (anneal time) is 1min-30min.
Please refer to Fig. 5, at the interior formation extension of described groove 301 intrinsic layer 307, described extension intrinsic layer 307 is positioned at described the first sub-fin 305 surfaces, removes the insulating barrier 301 of segment thickness, exposes described extension intrinsic layer 307 top and sidewall.
Described extension intrinsic layer 307, for follow-up pruning, doping, forms the second sub-fin.In described extension intrinsic layer 307, do not have doping ion, the width of described extension intrinsic layer 307 is identical with the width of described the first sub-fin 305, is 20nm-100nm.It forms technique is selective epitaxial depositing operation, and the reacting gas of described selective epitaxial depositing operation is SiH 2cl 2, HCl and H 2; Or SiH 4, HCl and H 2.In an embodiment of the present invention, the process parameters range of described selective epitaxial depositing operation is: depositing temperature is 650 ℃-750 ℃, and the pressure of deposition chambers is 0.3 holder-1.0 holder.
The insulating barrier 301 of removing segment thickness, is beneficial to the sub-fin of follow-up formation second, epitaxial loayer and grid structure.The technique of removing insulating barrier 301 employings of segment thickness is etching technics, for example anisotropic dry method or wet etching.Remove after the insulating barrier 301 of segment thickness, remaining insulating barrier 301 surfaces higher than described the first sub-fin 305 tops or with described the first sub-fin 305 flush.In an embodiment of the present invention, remove after the insulating barrier 301 of segment thickness, the remaining insulating barrier of described first area I and second area II 301 surfaces flush with described the first sub-fin 305 tops.
It should be noted that, in other embodiments of the invention, can also adopt additive method to form to there is the first sub-fin 305 of doping ion and not have the extension intrinsic layer 307 of the ion that adulterates, for example, first in the interior doping of Semiconductor substrate 300, then described in etching, Semiconductor substrate 300 forms the first sub-fin 305 with doping ion, then forms the extension intrinsic layer 307 without doping ion that is positioned at described the first sub-fin 305 surfaces.Detailed process does not repeat them here.
Incorporated by reference to reference to figure 6 and Fig. 7, the plan structure schematic diagram that Fig. 7 is Fig. 6, is isolated for ease of understanding, dotting in Fig. 7 the extension intrinsic layer 307 that layer 311 and dummy gate structure 309 cover.Formation is across the dummy gate structure 309 of described extension intrinsic layer 307 tops and sidewall, and is positioned at the separator 311 on described insulating barrier 301 surfaces, described separator 311 surfaces and described dummy gate structure 309 flush.
Described dummy gate structure 309 is for defining position, the size and shape of grid structure.The formation step of described dummy gate structure 309 comprises: form the pseudo-gate dielectric layer (not shown) that covers described extension intrinsic layer 307 tops and sidewall; Form the pseudo-gate electrode layer (not shown) that covers described pseudo-gate dielectric layer surface.Wherein, the material of described pseudo-gate dielectric layer is silica, and the material of described pseudo-gate electrode layer is polysilicon.
In an embodiment of the present invention, described dummy gate structure 309 comprises the first dummy gate structure 3091 that is positioned at described first area I, and is positioned at the second dummy gate structure 3092 of described second area II.
After forming dummy gate structure 309, also comprise form be positioned at described insulating barrier 301 surfaces and with the separator 311 of described dummy gate structure 309 flush.Described separator 311 is avoided damaging for the fin beyond follow-up grill-protected electrode structure, and at the grid structure of follow-up isolation adjacent fins formula field effect transistor.The formation technique of described separator 311 is depositing operation, for example physics or chemical vapor deposition method.For ease of follow-up removal dummy gate structure, the material of described separator 311 is different from the material of dummy gate structure.In an embodiment of the present invention, the material of described separator 311 is silica.
In an embodiment of the present invention, due to described extension intrinsic layer 307 tops and dielectric layer 302 flush, dummy gate structure 309 is across described extension intrinsic layer 307 top and sidewall, therefore described dummy gate structure 309 surfaces are higher than dielectric layer 302 surfaces, separator 311 and dummy gate structure 309 flush again, therefore, the surface of described dielectric layer 302 is formed with separator 311.
Incorporated by reference to reference to figure 8 and Fig. 9, the plan structure schematic diagram that Fig. 9 is Fig. 8.Remove the first dummy gate structure, form the first opening 313.
Described the first opening 313 defines the grid structure of first area I, and is beneficial to the follow-up extension intrinsic layer 307 to described first area I and prunes and adulterate.The formation technique of described the first opening 313 is etching technics, and the technique that forms the first opening 313 due to etching the first dummy gate structure is well known to those skilled in the art, does not repeat them here.
Incorporated by reference to reference to Figure 10 and Figure 11, the plan structure schematic diagram that Figure 11 is Figure 10.Prune to the described extension intrinsic layer 307(in described the first opening 313 as shown in Figure 7), and the extension intrinsic layer after pruning is adulterated, form the second sub-fin 307a.
Inventor finds, prior art is by shown in described fin 14(Fig. 1) top surface while adulterating ion to fin 14 inside, also can inevitably there is more doping ion in described fin 14 tops, thereby cause fin field effect pipe to produce grid leakage current, affected the performance of fin field effect pipe.Yet when only the first sub-fin 305 being adulterated, and during to the doping of described extension intrinsic layer, although phenomenon of gate leakage has obtained inhibition, the threshold voltage of the fin field effect pipe forming raises, the performance of fin field effect pipe improves comparatively limited.
After further research, inventor finds, can prune described extension intrinsic layer 307, then doping forms the second sub-fin 307a, then on the second sub-fin 307a surface, form epitaxial loayer, to reach suppressor grid leakage current and to reduce the object of fin field effect pipe threshold voltage, improve the performance of fin field effect pipe.
In the embodiment of the present invention, first the described extension intrinsic layer 307 in the first opening 313 is pruned, pruning the technique that described extension intrinsic layer 307 adopts is etching technics, for example dry method or wet etching, the width W of the described extension intrinsic layer 307 after pruning 1for 10nm-50nm.The width W of extension intrinsic layer 307 after described pruning 1when scope is 10nm-50nm, the second sub-fin 307a that the extension intrinsic layer 307 after described pruning is adulterated and formed, the final fin field effect pipe forming can obtain low threshold voltage, the width W of extension intrinsic layer 307 after described pruning 1while exceeding above-mentioned scope, the width W of the second sub-fin 307a that follow-up doping forms 1also exceed above-mentioned scope, or be unfavorable for forming the fin field effect pipe that volume is little, or the threshold voltage of fin field effect pipe is higher.
For improving the threshold voltage of fin field effect pipe, also need the extension intrinsic layer 307 after described pruning to adulterate and form the second sub-fin 307a, in described the second sub-fin 307a, the ion of doping comprises carbon ion or germanium ion.Through research, find, the concentration range of the ion that adulterates in the second sub-fin 307a is: 1E17atoms/cm 3-1E18atoms/cm 3time, the fin field effect pipe of formation can obtain lower threshold voltage, the stable performance of fin field effect pipe.In an embodiment of the present invention, first area I is used to form N channel fin formula field effect transistor, and in described first area I, the ion of doping comprises carbon ion.
Width W due to described extension intrinsic layer 307 after pruning 1less, when avoiding adulterating by ion doping to the region beyond the described extension intrinsic layer 307 after described pruning, or the skewness of doping ion in the second sub-fin 307a that avoids forming.In embodiments of the invention, the technique that extension intrinsic layer 307 after pruning is adulterated is molecular monolayer doping process (Molecular Monolayer Doping Technique), described molecular monolayer doping process is minimum to the infringement on extension intrinsic layer 307 surfaces after pruning, the quality of the second sub-fin 307a forming is good, and ion can not be doped to the region beyond the described extension intrinsic layer 307 after pruning, ion distribution in the second sub-fin 307a forming is even, is particularly suitable for the extension intrinsic layer 307a that in the present embodiment, depth-width ratio is large.
The processing step of described molecular monolayer doping process comprises: the extension intrinsic layer 307 of the hydrofluoric acid that adopts dilution after to described pruning cleans, and removes the oxide film (be mainly and the oxidation of airborne oxygen contact nature forms) on extension intrinsic layer 307 surfaces after described pruning; After end to be cleaned, the solvent (for example triphenylphosphine (Triphenylphosphine) solution) with high burning-point is doped in the extension intrinsic layer 307 after described pruning, forms the second sub-fin 307a; Adopt low temperature oxidation technology to form silicon oxide layer on described the second sub-fin 307a surface; Adopt spike annealing (spike anneal) technique to carry out annealing in process to described the second sub-fin 307a.Wherein, the thickness of the described silicon oxide layer of formation is 15 nanometer-40 nanometers, and temperature during described spike annealing is 1000 degrees Celsius-1100 degrees Celsius.Especially when forming the silicon oxide layer that thickness is 20nm, when the temperature of spike annealing is 1050 degrees Celsius, the ion distribution in the second sub-fin 307a is even, and the threshold voltage of the fin field effect pipe of follow-up formation is low.
It should be noted that, in an embodiment of the present invention, described width refers to the size that is parallel to described Semiconductor substrate 300 surface direction.
Incorporated by reference to reference to Figure 12 and Figure 13, the plan structure schematic diagram that Figure 13 is Figure 12.At interior formation the first epitaxial loayer 315 of described the first opening 313, top and the sidewall of the second sub-fin 307a described in described the first epitaxial loayer 315 uniform folds.
Inventor finds, the ion concentration when the grid structure contact position of fin and fin field effect pipe is greater than 1E16atoms/cm 3time, easily produce grid leakage current, and be less than or equal to 1E16atoms/cm when the ion concentration of the grid structure contact position of fin and fin field effect pipe 3or the grid structure contact position of fin and fin field effect pipe do not exist doping during ion, the grid leakage current of fin field effect pipe is little.
Described the first epitaxial loayer 315 is for suppressing the grid leakage current of the fin field effect pipe of first area I.The material of described the first epitaxial loayer 315 is monocrystalline silicon, germanium, SiGe or III-V compounds of group.The ion concentration scope of described the first epitaxial loayer 315 interior doping is 0atoms/cm 3-1E16atoms/cm 3, grid leakage current that can more effective inhibition fin field effect pipe.In an embodiment of the present invention, the material of described the first epitaxial loayer 315 is monocrystalline silicon, in described the first epitaxial loayer 315, does not have doping ion, and the ion concentration of doping is 0atoms/cm 3.
It should be noted that, in other embodiments of the invention, described the first epitaxial loayer 315 is interior can also have doping ion, as long as the concentration of described doping ion is less than 1E16atoms/cm 3can suppressor grid leakage current.
For making the follow-up place contacting with grid structure of fin all not produce grid leakage current, top and the sidewall of the second sub-fin 307a described in described the first epitaxial loayer 315 uniform folds.The formation technique of described the first epitaxial loayer 315 is depositing operation, for example chemical vapor deposition method.In an embodiment of the present invention, for saving processing step, and making the first epitaxial loayer 315 of formation at the thickness homogeneous of the second sub-fin 307a top and sidewall, the formation technique of described the first epitaxial loayer 315 is selective epitaxial depositing operation (Selective Epitaxy Deposition).In an embodiment of the present invention, owing to adopting selective epitaxial depositing operation, silicon atom is only deposited on top and the sidewall of the second sub-fin 307a, and can not be formed on insulating barrier 301 and separator 311 surfaces, has saved processing step.
In an embodiment of the present invention, during the first epitaxial loayer 315 that to form material be monocrystalline silicon, the reacting gas of employing is silicon source gas, HCl and H 2, reaction pressure is 0.1-1.0 holder, reaction temperature is 500 ℃-800 ℃.
The thickness of described the first epitaxial loayer 315 is relevant with the thickness of the extension intrinsic layer 307 pruning away, in an embodiment of the present invention, for effective suppressor grid leakage current, and make the volume of the fin field effect pipe that forms little, the thickness of described the first epitaxial loayer 315 is identical with the thickness of the extension intrinsic layer 307 pruning away, and is 5nm-25nm.
Incorporated by reference to reference to Figure 14 and Figure 15, the plan structure schematic diagram that Figure 15 is Figure 14.First grid structure 317 in the interior formation of described the first opening 313 across described the first epitaxial loayer 315 top and sidewall.
The formation step of described first grid structure 317 comprises: the first high-K gate dielectric layer (not shown) in the interior formation of described the first opening 313 across described the first epitaxial loayer 315 top and sidewall; Form the first metal gate electrode layer (not shown) that covers described the first high-K gate dielectric layer.The performance of the described fin field effect pipe that comprises high-K gate dielectric layer and metal gate electrode layer is more superior.
Incorporated by reference to reference to Figure 16 and Figure 17, the plan structure schematic diagram that Figure 17 is Figure 16.The second dummy gate structure of removing second area II, forms the second opening 319.
Described the second opening 319 exposes the bottom of insulating barrier 301, defines the grid structure of second area II, and prunes and adulterate for the follow-up extension intrinsic layer 307 to described second area II.The formation technique of described the second opening 319 is etching technics, and the technique that forms the second opening 319 due to etching the second dummy gate structure is well known to those skilled in the art, does not repeat them here.
Incorporated by reference to reference to Figure 18 and Figure 19, the plan structure schematic diagram that Figure 19 is Figure 18.Shown in described second opening 319(Figure 11) in extension intrinsic layer 307(Figure 11 shown in) prune, and the extension intrinsic layer 307 after pruning is adulterated, form the second sub-fin 307b; Then in the second opening 319, form the top of the sub-fin 307b of uniform fold second and the second epitaxial loayer 321 of sidewall; The second grid structure 323 across described the second epitaxial loayer 321 top and sidewall in the interior formation of described the second opening 319 again.
Because second area II in embodiments of the invention is used to form P channel fin formula field effect transistor, it is slightly different that Yu first area I forms N channel fin formula field effect transistor, in the second sub-fin 307b of second area II, the ion of doping comprises germanium ion, to form the P channel fin formula field effect transistor that carrier mobility is high.
The width W of the extension intrinsic layer 307 of described second area II after pruning 2for 10nm-50nm, the concentration range of its inner doping ion is 1E17atoms/cm 3-1E18atoms/cm 3, the thickness of the second epitaxial loayer 321 is 5nm-25nm, and the ion concentration scope of its inner doping is 0atoms/cm 3-1E16atoms/cm 3time, the threshold voltage of the follow-up P channel fin formula field effect transistor forming at second area II is low, has effectively suppressed grid leakage current, and device performance is stable.
The formation step of described second grid structure 323 is identical with the formation step of first grid structure 317, comprising: the second high-K gate dielectric layer (not shown) in the interior formation of described the first opening 319 across described the second epitaxial loayer 321 top and sidewall; Form the second metal gate electrode layer (not shown) that covers described the second high-K gate dielectric layer.The performance of the described fin field effect pipe that comprises the second high-K gate dielectric layer and the second metal gate electrode layer is more superior.
It should be noted that, prune the described extension intrinsic layer 307(of second area II as shown in figure 11), the described extension intrinsic layer 307 of the described second area II after pruning is adulterated, form the second sub-fin 307b, and form the second epitaxial loayer 321 formation Method and process and aforementioned in the I of first area to the first sub-fin 307(as shown in Figure 7) prune, adulterate, form the first sub-fin 307a identical with the formation Method and process that forms the first epitaxial loayer 315, do not repeat them here.
After above-mentioned steps completes, the completing of the fin field effect pipe of the embodiment of the present invention.The threshold voltage Di， channel region carrier mobility of the fin field effect pipe forming is high, and grid leakage current is little, and device performance is stable.
Accordingly, please continue combination with reference to Figure 18 and Figure 19, inventor also provides a kind of fin field effect pipe, comprising: Semiconductor substrate 300; Described Semiconductor substrate 300 surface coverage have insulating barrier 301; Run through described insulating barrier 301 thickness and with the first sub-fin 305 of described insulating barrier 301 flush; The extension intrinsic layer 307 and the second sub-fin that are positioned at described the first sub-fin 305 surfaces, the width of described the second sub-fin is less than the width of described the first sub-fin 305; Be positioned at the separator 311 on insulating barrier 301 and extension intrinsic layer 307 surfaces, described separator 311 has the opening (not shown) that runs through its thickness, and described opening exposes described the second sub-fin; Be positioned at the epitaxial loayer of described opening, top and the sidewall of described epitaxial loayer uniform fold the second sub-fin; Be positioned at described opening and across the top of described epitaxial loayer and the grid structure of sidewall.
Wherein, described Semiconductor substrate 300 is used to subsequent technique that workbench is provided.Described Semiconductor substrate 300 is silicon substrate (Si) or silicon-on-insulator (SOI).In an embodiment of the present invention, described Semiconductor substrate 300 comprises first area I and adjacent second area II with it, and described first area I is used to form N channel fin formula field effect transistor, and described second area II is used to form P channel fin formula field effect transistor.
Described insulating barrier 301 is for isolating adjacent fin.The material of described insulating barrier 301 is silica, silicon nitride, silicon oxynitride etc.In an embodiment of the present invention, described insulating barrier 301 is as shallow trench isolation from (STI), and the material of described insulating barrier 301 is silica.
In embodiments of the invention, also comprise: be positioned at the dielectric layer 302 on described Semiconductor substrate 300 surfaces, described dielectric layer 302 is for isolating the described insulating barrier 301 of first area I and second area II.The material of described dielectric layer 302 is different from the material of insulating barrier 301.
Described the first sub-fin 305 and the second sub-fin and epitaxial loayer form the fin of fin field effect pipe jointly.The ion concentration scope of described the first sub-fin 305 interior doping is: 1E18atoms/cm 3-1E19atoms/cm 3, the carrier mobility of the fin field effect pipe channel region of formation is high.
Described extension intrinsic layer 307 is for forming the second sub-fin 307a of first area I and the second sub-fin 307b of second area II after pruning, adulterating.In described extension intrinsic layer 307, do not there is doping ion, and its width is identical with the width of described the first sub-fin 305.
Described the second sub-fin is for reducing fin field effect pipe threshold voltage.In an embodiment of the present invention, described the second sub-fin obtains after by extension intrinsic layer 307 etchings, comprises the second sub-fin 307a that is positioned at described first area I and the second sub-fin 307b that is positioned at described second area II.
Described separator 311 is avoided damaging for the fin beyond follow-up grill-protected electrode structure, and at the grid structure of follow-up isolation adjacent fins formula field effect transistor.The material of described separator 311 is different from the material of dummy gate structure (not shown).In an embodiment of the present invention, the material of described separator 311 is silica.
Opening in described separator 311 defines size, shape and the position of grid structure.The width W of the second sub-fin in described opening 1for 10nm-50nm, the fin field effect pipe of formation can obtain low threshold voltage.In described the second sub-fin, the concentration range of doping ion is: 1E17atoms/cm 3-1E18atoms/cm 3time, fin field effect pipe can obtain lower threshold voltage, the stable performance of fin field effect pipe.
It should be noted that, because first area I is used to form N channel fin formula field effect transistor, second area II is used to form P channel fin formula field effect transistor, in the second sub-fin 307a of described first area I, the ion of doping comprises carbon ion, and in the second sub-fin 307b of described second area II, the ion of doping comprises germanium ion.
Top and the sidewall of described epitaxial loayer uniform fold the second sub-fin, its thickness is 5nm-25nm, for suppressing the grid leakage current of fin field effect pipe.The material of described epitaxial loayer is monocrystalline silicon, germanium, SiGe or III-V compounds of group, and in described epitaxial loayer, the ion concentration scope of doping is 0atoms/cm 3-1E16atoms/cm 3time, the grid leakage current of fin field effect pipe is little.In an embodiment of the present invention, owing to thering is Liang Ge region, described epitaxial loayer comprises the first epitaxial loayer 315 that is positioned at first area I and the second epitaxial loayer 321 that is positioned at second area II, is respectively used to suppress the grid leakage current of N channel fin formula field effect transistor or P channel fin formula field effect transistor.
Described grid structure is used to form the grid of fin field effect pipe.Described grid structure comprises across the top of described epitaxial loayer and the high-K gate dielectric layer of sidewall, covers the metal gate electrode layer of described high-K gate dielectric layer.In an embodiment of the present invention, described grid structure comprises the first grid structure 317 across described the first epitaxial loayer 315, with the second grid structure 323 across described the second epitaxial loayer 321, be respectively used to form the grid of N channel fin formula field effect transistor or P channel fin formula field effect transistor.
In embodiments of the invention, the first sub-fin, be positioned at the second sub-fin on described the first sub-fin surface, with the top of the second sub-fin described in uniform fold and the epitaxial loayer of sidewall, jointly formed the fin of fin field effect pipe, in described the first sub-fin, there is doping ion, improved the carrier mobility of fin field effect pipe channel region, and in the second sub-fin, there is doping ion, effectively reduce the threshold voltage of fin field effect pipe, and the existence due to epitaxial loayer, the grid leakage current that has effectively suppressed fin field effect pipe, the device performance of the fin field effect pipe of the embodiment of the present invention is stable.
To sum up, while forming fin field effect pipe, first form the first sub-fin and the plain extension intrinsic layer of doping, then the extension intrinsic layer in opening is pruned and adulterated, form the second sub-fin, in opening, form again the top of uniform fold the second sub-fin and the epitaxial loayer of sidewall, formation technique is simple, and the fin field effect pipe of the formation not only carrier mobility of channel region is high, and threshold voltage is low, grid leakage current is little, and device performance is stable.
Further, the width of the extension intrinsic layer after pruning is less, is 10nm-50nm.The extension intrinsic layer adulterating after described pruning, the technique adopting while forming the second sub-fin is molecular monolayer doping process, and the ion distribution in the second sub-fin of formation is even, and the threshold voltage of the fin field effect pipe of follow-up formation is lower.
Further, can at first area I and second area II, form N channel fin formula field effect transistor and P channel fin formula field effect transistor respectively, form technique simple, the performance of the CMOS fin field effect pipe of formation is good.
The fin of described fin field effect pipe is by the first sub-fin, be positioned at the second sub-fin on described the first sub-fin surface, jointly form with the top of the second sub-fin described in uniform fold and the epitaxial loayer of sidewall, owing to thering is doping ion in described the first sub-fin, improved the carrier mobility of fin field effect pipe channel region, and in the second sub-fin, there is doping ion, effectively reduce the threshold voltage of fin field effect pipe, and the existence due to epitaxial loayer, the grid leakage current that has effectively suppressed fin field effect pipe, the device performance of the fin field effect pipe of the embodiment of the present invention is stable.
Although the present invention with preferred embodiment openly as above; but it is not for limiting the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; can utilize method and the technology contents of above-mentioned announcement to make possible change and modification to technical solution of the present invention; therefore; every content that does not depart from technical solution of the present invention; any simple modification, equivalent variations and the modification above embodiment done according to technical spirit of the present invention, all belong to the protection range of technical solution of the present invention.

Claims (25)

1. a formation method for fin field effect pipe, is characterized in that, comprising:
Semiconductor substrate is provided, described semiconductor substrate surface is coated with insulating barrier, and the first sub-fin that runs through described thickness of insulating layer and flush with described surface of insulating layer is positioned at the extension intrinsic layer on described the first sub-fin surface, wherein, in described the first sub-fin, there is doping ion;
On described extension intrinsic layer surface, form separator, described separator has the opening that defines grid structure;
Described extension intrinsic layer in described opening is pruned, and the extension intrinsic layer after pruning is adulterated, form the second sub-fin;
In described opening, form epitaxial loayer, top and the sidewall of the second sub-fin described in described epitaxial loayer uniform fold;
In described opening, form across the top of described epitaxial loayer and the grid structure of sidewall.
2. the formation method of fin field effect pipe as claimed in claim 1, is characterized in that, in described epitaxial loayer, the ion concentration scope of doping is 0atoms/cm 3-1E16atoms/cm 3.
3. the formation method of fin field effect pipe as claimed in claim 1, is characterized in that, the formation technique of described epitaxial loayer is selective epitaxial depositing operation.
4. the formation method of fin field effect pipe as claimed in claim 1, is characterized in that, the material of described epitaxial loayer is monocrystalline silicon, germanium, SiGe or III-V compounds of group.
5. the formation method of fin field effect pipe as claimed in claim 1, is characterized in that, when the material of described epitaxial loayer is monocrystalline silicon, the reacting gas that forms described epitaxial loayer employing is silicon source gas, HCl and H 2, reaction pressure is 0.1-1.0 holder, reaction temperature is 500 ℃-800 ℃.
6. the formation method of fin field effect pipe as claimed in claim 1, is characterized in that, the thickness of described epitaxial loayer is 5nm-25nm.
7. the formation method of fin field effect pipe as claimed in claim 1, is characterized in that, the width of described extension intrinsic layer is 20nm-100nm.
8. the formation method of fin field effect pipe as claimed in claim 1, is characterized in that, the width of the extension intrinsic layer after described pruning is 10nm-50nm.
9. the formation method of fin field effect pipe as claimed in claim 1, is characterized in that, the extension intrinsic layer after pruning is adulterated, and the technique that forms the second sub-fin is molecular monolayer doping process.
10. the formation method of fin field effect pipe as claimed in claim 9, is characterized in that, the processing step of described molecular monolayer doping process comprises: the extension intrinsic layer of the hydrofluoric acid that adopts dilution after to described pruning cleans; After end to be cleaned, the solvent with high burning-point is doped in the extension intrinsic layer after described pruning, forms the second sub-fin; Adopt low temperature oxidation technology to form silicon oxide layer on described the second sub-fin surface; Adopt spike annealing technique to carry out annealing in process to described the second sub-fin.
The formation method of 11. fin field effect pipes as claimed in claim 10, is characterized in that, the solvent of described high burning-point is triphenylphosphine solution.
The formation method of 12. fin field effect pipes as claimed in claim 10, is characterized in that, the thickness of described silicon oxide layer is 15 nanometer-40 nanometers.
The formation method of 13. fin field effect pipes as claimed in claim 10, is characterized in that, temperature during described spike annealing is 1000 degrees Celsius-1100 degrees Celsius.
The formation method of 14. fin field effect pipes as claimed in claim 1, is characterized in that, in described the second sub-fin, the ion of doping comprises carbon ion or germanium ion.
The formation method of 15. fin field effect pipes as claimed in claim 1, is characterized in that, in described the second sub-fin, the concentration range of doping ion is: 1E17atoms/cm 3-1E18atoms/cm 3.
The formation method of 16. fin field effect pipes as claimed in claim 1, is characterized in that, in described the first sub-fin, the ion concentration scope of doping is: 1E18atoms/cm 3-1E19atoms/cm 3.
The formation method of 17. fin field effect pipes as claimed in claim 1, it is characterized in that, described Semiconductor substrate comprises first area and adjacent second area with it, and described first area is used to form N channel fin formula field effect transistor, and described second area is used to form P channel fin formula field effect transistor.
18. 1 kinds of fin field effect pipes, is characterized in that, comprising:
Semiconductor substrate;
Described semiconductor substrate surface is coated with insulating barrier;
The the first sub-fin that runs through described thickness of insulating layer and flush with described surface of insulating layer;
The extension intrinsic layer and the second sub-fin that are positioned at described the first sub-fin surface, the width of described the second sub-fin is less than the width of described the first sub-fin;
The separator that is positioned at insulating barrier and extension intrinsic layer surface, described separator has the opening that runs through its thickness, and described opening exposes described the second sub-fin;
Be positioned at the epitaxial loayer of described opening, top and the sidewall of described epitaxial loayer uniform fold the second sub-fin;
Be positioned at described opening and across the top of described epitaxial loayer and the grid structure of sidewall.
19. fin field effect pipes as claimed in claim 18, is characterized in that, in described epitaxial loayer, the concentration of doping ion is 0atoms/cm 3-1E16atoms/cm 3.
20. fin field effect pipes as claimed in claim 18, is characterized in that, the material of described epitaxial loayer is monocrystalline silicon, germanium, SiGe or III-V compounds of group.
21. fin field effect pipes as claimed in claim 18, is characterized in that, the thickness of described epitaxial loayer is 5nm-25nm.
22. fin field effect pipes as claimed in claim 18, is characterized in that, the width of described the second sub-fin is 10nm-50nm.
23. fin field effect pipes as claimed in claim 18, is characterized in that, in described the second sub-fin, the concentration range of doping ion is: 1E17atoms/cm 3-1E18atoms/cm 3.
24. fin field effect pipes as claimed in claim 18, is characterized in that, the doping ion in described the second sub-fin comprises carbon ion or germanium ion.
25. fin field effect pipes as claimed in claim 18, is characterized in that, in described the first sub-fin, the ion concentration scope of doping is: 1E18atoms/cm 3-1E19atoms/cm 3.
CN201210203757.1A 2012-06-19 2012-06-19 Fin field effect pipe and forming method thereof Active CN103515209B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201210203757.1A CN103515209B (en) 2012-06-19 2012-06-19 Fin field effect pipe and forming method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201210203757.1A CN103515209B (en) 2012-06-19 2012-06-19 Fin field effect pipe and forming method thereof

Publications (2)

Publication Number Publication Date
CN103515209A true CN103515209A (en) 2014-01-15
CN103515209B CN103515209B (en) 2017-07-14

Family

ID=49897742

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201210203757.1A Active CN103515209B (en) 2012-06-19 2012-06-19 Fin field effect pipe and forming method thereof

Country Status (1)

Country Link
CN (1) CN103515209B (en)

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106252228A (en) * 2015-06-11 2016-12-21 中国科学院微电子研究所 A kind of compound fin, semiconductor device and forming method thereof
CN107112359A (en) * 2014-12-23 2017-08-29 英特尔公司 Thin channel area on wide sub- fin
CN107293492A (en) * 2016-04-11 2017-10-24 三星电子株式会社 Semiconductor devices and its manufacture method
CN108470770A (en) * 2018-03-21 2018-08-31 上海华力集成电路制造有限公司 Fin transistor and its manufacturing method
CN109075078A (en) * 2016-03-30 2018-12-21 英特尔公司 The geometry of transistor based on fin adjusts
CN109872971A (en) * 2017-12-04 2019-06-11 中芯国际集成电路制造(上海)有限公司 Semiconductor structure and forming method thereof
CN111463173A (en) * 2019-01-18 2020-07-28 中芯国际集成电路制造(上海)有限公司 Semiconductor structure and forming method thereof
CN112786704A (en) * 2020-12-31 2021-05-11 泉芯集成电路制造(济南)有限公司 Variable capacitance diode in fin field effect transistor process and manufacturing method thereof
CN112802898A (en) * 2020-12-31 2021-05-14 泉芯集成电路制造(济南)有限公司 Fin type field effect transistor and manufacturing method thereof

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1581431A (en) * 2003-08-14 2005-02-16 三星电子株式会社 Multi-structure silicon fin and its making method
US20060157687A1 (en) * 2005-01-18 2006-07-20 Doyle Brian S Non-planar MOS structure with a strained channel region
US20070176245A1 (en) * 2004-02-05 2007-08-02 Samsung Electronics Co., Ltd. Fin fet and method of fabricating same
CN101490821A (en) * 2006-07-14 2009-07-22 美光科技公司 Subresolution silicon features and methods for forming the same
CN102468235A (en) * 2010-11-02 2012-05-23 台湾积体电路制造股份有限公司 Fin-like field effect transistor (finfet) device and method of manufacturing same

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1581431A (en) * 2003-08-14 2005-02-16 三星电子株式会社 Multi-structure silicon fin and its making method
US20070176245A1 (en) * 2004-02-05 2007-08-02 Samsung Electronics Co., Ltd. Fin fet and method of fabricating same
US20060157687A1 (en) * 2005-01-18 2006-07-20 Doyle Brian S Non-planar MOS structure with a strained channel region
CN101490821A (en) * 2006-07-14 2009-07-22 美光科技公司 Subresolution silicon features and methods for forming the same
CN102468235A (en) * 2010-11-02 2012-05-23 台湾积体电路制造股份有限公司 Fin-like field effect transistor (finfet) device and method of manufacturing same

Cited By (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107112359A (en) * 2014-12-23 2017-08-29 英特尔公司 Thin channel area on wide sub- fin
CN107112359B (en) * 2014-12-23 2022-08-09 英特尔公司 Thin channel region on wide sub-fin
EP3238267A4 (en) * 2014-12-23 2018-09-05 Intel Corporation Thin channel region on wide subfin
CN106252228A (en) * 2015-06-11 2016-12-21 中国科学院微电子研究所 A kind of compound fin, semiconductor device and forming method thereof
CN106252228B (en) * 2015-06-11 2019-11-08 中国科学院微电子研究所 A kind of forming method of compound fin
CN109075078A (en) * 2016-03-30 2018-12-21 英特尔公司 The geometry of transistor based on fin adjusts
CN107293492A (en) * 2016-04-11 2017-10-24 三星电子株式会社 Semiconductor devices and its manufacture method
CN107293492B (en) * 2016-04-11 2021-10-29 三星电子株式会社 Method for manufacturing semiconductor device
CN109872971B (en) * 2017-12-04 2020-12-22 中芯国际集成电路制造(上海)有限公司 Semiconductor structure and forming method thereof
CN109872971A (en) * 2017-12-04 2019-06-11 中芯国际集成电路制造(上海)有限公司 Semiconductor structure and forming method thereof
CN108470770A (en) * 2018-03-21 2018-08-31 上海华力集成电路制造有限公司 Fin transistor and its manufacturing method
CN111463173A (en) * 2019-01-18 2020-07-28 中芯国际集成电路制造(上海)有限公司 Semiconductor structure and forming method thereof
CN112786704A (en) * 2020-12-31 2021-05-11 泉芯集成电路制造(济南)有限公司 Variable capacitance diode in fin field effect transistor process and manufacturing method thereof
CN112802898A (en) * 2020-12-31 2021-05-14 泉芯集成电路制造(济南)有限公司 Fin type field effect transistor and manufacturing method thereof
CN112786704B (en) * 2020-12-31 2023-04-07 泉芯集成电路制造(济南)有限公司 Variable capacitance diode in fin field effect transistor process and manufacturing method thereof

Also Published As

Publication number Publication date
CN103515209B (en) 2017-07-14

Similar Documents

Publication Publication Date Title
CN103515209A (en) Fin field effect transistor and formation method thereof
US20150091057A1 (en) Semiconductor structure and device and methods of forming same using selective epitaxial process
CN103426765B (en) The forming method of semiconductor device, the forming method of fin field effect pipe
CN104752214B (en) The forming method of fin field effect pipe
CN103187439B (en) Semiconductor structure and forming method thereof, CMOS and forming method thereof
CN103426755A (en) Semiconductor component and forming method thereof
US20080224212A1 (en) Semiconductor device and method for fabricating the same
CN106558614A (en) Semiconductor structure and forming method thereof
JP2023533725A (en) Selective silicon etching for gate-all-around transistors
CN103367253B (en) Fin type field effect transistor forming method
CN104934324A (en) Semiconductor device and manufacturing method thereof
CN102969345A (en) Fin field-effect tube with T-shaped fin portion and forming method of fin field-effect tube
CN103296068B (en) Cmos and forming method thereof
US20220123123A1 (en) Formation of gate all around device
CN103123899B (en) FinFET manufacture method
CN106960789A (en) Semiconductor devices and the method for improving performance of semiconductor device
CN103377898B (en) The formation method of semiconductor device, the formation method of fin field effect pipe
CN104282562A (en) Fin field effect transistor and forming method thereof
JP2023536856A (en) Conformal oxidation for gate-all-around nanosheet input/output devices
CN103632945A (en) Formation method for fin-type field effect transistor
CN103383961A (en) Finfet structure and manufacturing method thereof
CN108122761A (en) Semiconductor structure and forming method thereof
CN103531471B (en) A kind of MOSFET and preparation method thereof
CN103000688A (en) Finned-type field-effect transistor structure and finned-type field-effect transistor forming method
CN103165509B (en) Preparation method of silicon-on-quasi-insulator field-effect transistor

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant