CN103515209B - Fin field effect pipe and forming method thereof - Google Patents
Fin field effect pipe and forming method thereof Download PDFInfo
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- CN103515209B CN103515209B CN201210203757.1A CN201210203757A CN103515209B CN 103515209 B CN103515209 B CN 103515209B CN 201210203757 A CN201210203757 A CN 201210203757A CN 103515209 B CN103515209 B CN 103515209B
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- 230000004888 barrier function Effects 0.000 claims abstract description 45
- 238000009966 trimming Methods 0.000 claims abstract description 40
- 239000000758 substrate Substances 0.000 claims abstract description 37
- 239000004065 semiconductor Substances 0.000 claims abstract description 35
- 238000000926 separation method Methods 0.000 claims abstract description 26
- 239000010410 layer Substances 0.000 claims description 250
- 230000008569 process Effects 0.000 claims description 30
- 239000000463 material Substances 0.000 claims description 27
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 23
- 238000000151 deposition Methods 0.000 claims description 22
- 239000007789 gas Substances 0.000 claims description 14
- -1 carbon ion Chemical class 0.000 claims description 13
- 229910052732 germanium Inorganic materials 0.000 claims description 13
- 238000000137 annealing Methods 0.000 claims description 11
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims description 11
- 239000002356 single layer Substances 0.000 claims description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 9
- 229910052710 silicon Inorganic materials 0.000 claims description 9
- 239000010703 silicon Substances 0.000 claims description 8
- RIOQSEWOXXDEQQ-UHFFFAOYSA-N triphenylphosphine Chemical compound C1=CC=CC=C1P(C=1C=CC=CC=1)C1=CC=CC=C1 RIOQSEWOXXDEQQ-UHFFFAOYSA-N 0.000 claims description 8
- 229910052799 carbon Inorganic materials 0.000 claims description 7
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 7
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- 229910052814 silicon oxide Inorganic materials 0.000 claims description 7
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 claims description 6
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- 229910003818 SiH2Cl2 Inorganic materials 0.000 description 2
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 2
- 238000009826 distribution Methods 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 239000001257 hydrogen Substances 0.000 description 2
- 229910052739 hydrogen Inorganic materials 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- 229910052757 nitrogen Inorganic materials 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
- H01L29/66818—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET the channel being thinned after patterning, e.g. sacrificial oxidation on fin
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823431—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
A kind of fin field effect pipe and forming method thereof, wherein the forming method of fin field effect pipe of the present invention, including：Semiconductor substrate is provided, the semiconductor substrate surface is covered with insulating barrier, the first sub- fin flushed through thickness of insulating layer and with surface of insulating layer, positioned at the extension intrinsic layer of the first sub- fin portion surface, wherein, have in the first sub- fin and do not have Doped ions in Doped ions, extension intrinsic layer；Separation layer is formed on extension intrinsic layer surface, separation layer has the opening for defining grid structure；The split intraoral extension intrinsic layer is trimmed, and the extension intrinsic layer after trimming is doped；Epitaxial layer, extension intrinsic layer top and side wall after the doping of epitaxial layer uniform fold are formed in the opening；The top of epitaxial layer and the grid structure of side wall are developed across in the opening.The threshold voltage of the fin field effect pipe of formation is low, and grid leakage current is small, and device performance is stable.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, more particularly to a kind of fin field effect pipe and forming method thereof.
Background technology
Fin field effect pipe（Fin FET）It is a kind of common multi-gate device, Fig. 1 shows a kind of fin of prior art
The dimensional structure diagram of FET.As shown in figure 1, including：It is formed with Semiconductor substrate 10, the Semiconductor substrate 10
The fin 14 of protrusion, fin 14 after being etched to Semiconductor substrate 10 generally by obtaining；Dielectric layer 11, covering is described partly to be led
The surface of body substrate 10 and a part for the side wall of fin 14；Grid structure 12, across on the fin 14, covering is described
The top of fin 14 and side wall, grid structure 12 include gate dielectric layer（Not shown in figure）With the gate electrode on gate dielectric layer
（Not shown in figure）.For Fin FET, the part that the top of fin 14 and the side wall of both sides are in contact with grid structure 12 is all
As channel region, i.e., with multiple grid, be conducive to increasing driving current, improve device performance.
However as the further reduction of process node, the device performance of the fin formula field effect transistor of prior art is present
Problem.
More structures and forming method on fin formula field effect transistor refer to Patent No. " US7868380B2 "
United States Patent (USP).
The content of the invention
The problem of present invention is solved is to provide good fin field effect pipe of a kind of device performance and forming method thereof.
To solve the above problems, The embodiment provides a kind of forming method of fin field effect pipe, including：Carry
For Semiconductor substrate, the semiconductor substrate surface covered with insulating barrier, through the thickness of insulating layer and with the insulating barrier
The first sub- fin that surface is flushed, positioned at the extension intrinsic layer of the described first sub- fin portion surface, wherein, in the first sub- fin
With Doped ions；In the intrinsic layer surface formation separation layer of the extension, the separation layer, which has, defines opening for grid structure
Mouthful；The extension intrinsic layer in the opening is trimmed, and the extension intrinsic layer after trimming is doped, the is formed
Two sub- fins；Epitaxial layer is formed in the opening, the top of the second sub- fin and side wall described in the epitaxial layer uniform fold；
The top of the epitaxial layer and the grid structure of side wall are developed across in the opening.
Alternatively, the ion concentration range of doping is 0 atoms/cm in the epitaxial layer3-1E16atoms/cm3。
Alternatively, the formation process of the epitaxial layer is selective epitaxial depositing operation.
Alternatively, the material of the epitaxial layer is monocrystalline silicon, germanium, SiGe or III-V.
Alternatively, when the material of the epitaxial layer is monocrystalline silicon, the reacting gas that the formation epitaxial layer is used is silicon
Source gas, HCl and H2, reaction pressure is 0.1-1.0 supports, and reaction temperature is 500 DEG C -800 DEG C.
Alternatively, the thickness of the epitaxial layer is 5nm-25nm.
Alternatively, the width of the extension intrinsic layer is 20nm-100nm.
Alternatively, the width of the extension intrinsic layer after the trimming is 10nm-50nm.
Alternatively, the extension intrinsic layer after trimming is doped, the technique for forming the second sub- fin is mixed for molecular monolayer
General labourer's skill.
Alternatively, the processing step of the molecular monolayer doping process includes：Using the hydrofluoric acid of dilution to the trimming
Extension intrinsic layer afterwards is cleaned；After end to be cleaned, the solvent with high-flash is doped into the extension after the trimming
In intrinsic layer, the second sub- fin is formed；Using low temperature oxidation technology in the described second sub- fin portion surface formation silicon oxide layer；Using
Spike annealing process makes annealing treatment to the described second sub- fin.
Alternatively, the solvent of the high-flash is triphenylphosphine solution.
Alternatively, the thickness of the silicon oxide layer is 15 nanometers -40 nanometers.
Alternatively, the temperature during spike annealing is 1000 degrees Celsius -1100 degrees Celsius.
Alternatively, the ion of doping includes carbon ion or germanium ion in the described second sub- fin.
Alternatively, the concentration range of the described second sub- fin Doped ions is：1E17atoms/cm3-1E18atoms/cm3。
Alternatively, the ion concentration range of doping is in the described first sub- fin：1E18atoms/cm3-1E19atoms/
cm3。
Alternatively, the Semiconductor substrate includes first area and second area adjacent thereto, and the first area is used
In forming N-channel fin field effect pipe, the second area is used to form P-channel fin field effect pipe.
Accordingly, inventor additionally provides a kind of fin field effect pipe, including：Semiconductor substrate；The Semiconductor substrate
Surface is covered with insulating barrier；The the first sub- fin flushed through the thickness of insulating layer and with the surface of insulating layer；Positioned at institute
The extension intrinsic layer and the second sub- fin of the first sub- fin portion surface are stated, the width of the second sub- fin is less than the described first sub- fin
The width in portion；Positioned at insulating barrier and the separation layer of the intrinsic layer surface of extension, the separation layer has the opening through its thickness, institute
State opening and expose the described second sub- fin；Epitaxial layer in the opening, the sub- fin of the epitaxial layer uniform fold second
The top in portion and side wall；In the opening and across the top of the epitaxial layer and the grid structure of side wall.
Alternatively, the concentration range of Doped ions is 0atoms/cm in the epitaxial layer3-1E 16atoms/cm3。
Alternatively, the material of the epitaxial layer is monocrystalline silicon, germanium, SiGe or III-V.
Alternatively, the thickness of the epitaxial layer is 5nm-25nm.
Alternatively, the width of the described second sub- fin is 10nm-50nm.
Alternatively, the concentration range of Doped ions is in the described second sub- fin：1E17atoms/cm3-1E18atoms/
cm3。
Alternatively, the Doped ions in the described second sub- fin include carbon ion or germanium ion.
Alternatively, the ion concentration range of doping is in the described first sub- fin：1E18atoms/cm3-1E19atoms/
cm3。
Compared with prior art, embodiments of the invention have advantages below：
When forming fin field effect pipe, the first sub- fin for being initially formed doping and the extension intrinsic layer undoped, then
Split intraoral extension intrinsic layer is trimmed and adulterated, and forms the second sub- fin, then the formation uniform fold second in opening
The top of sub- fin and the epitaxial layer of side wall, formation process are simple, the carrier of the fin field effect pipe of formation not only channel region
Mobility is high, and threshold voltage is low, and grid leakage current is small, and device performance is stable.
Further, the width of the extension intrinsic layer after trimming is smaller, is 10nm-50nm.Adulterate outer after the trimming
Prolong intrinsic layer, form the technique used during the second sub- fin for molecular monolayer doping process, in the second sub- fin of formation from
Son is evenly distributed, and the threshold voltage for the fin field effect pipe being subsequently formed is lower.
Further, can be respectively in first area I and second area II formation N-channel fin field effect pipes and P ditches
Road fin field effect pipe, formation process is simple, and the performance of the CMOS fin field effect pipes of formation is good.
The fin of the fin field effect pipe is by the first sub- fin, positioned at the second sub- fin of the described first sub- fin portion surface
The top of second sub- fin described in portion and uniform fold and the epitaxial layer of side wall are collectively formed, due in the described first sub- fin
With Doped ions, improve the carrier mobility of fin field effect pipe channel region, and have in the second sub- fin doping from
Son, effectively reduces the threshold voltage of fin field effect pipe, and due to the presence of epitaxial layer, effectively inhibit fin field effect
The grid leakage current of pipe, the device performance of the fin field effect pipe of the embodiment of the present invention is stable.
Brief description of the drawings
Fig. 1 is the dimensional structure diagram of the fin field effect pipe of prior art；
Fig. 2 is the schematic flow sheet of the embodiment of the forming method of fin field effect pipe of the present invention；
Fig. 3-Figure 19 is the structural representation of the forming method of the embodiment of fin field effect pipe of the present invention.
Embodiment
As described in background, there is problem in the device performance of the fin formula field effect transistor of prior art formation.
By research, inventor find, influence fin field effect pipe stability the reason for have multiple, one of them
Reason is：Prior art is in semiconductor substrate surface formation fin 14（As shown in Figure 1）Afterwards, by the top surface of the fin 14
When being doped ion inside to fin 14, the ion concentration highest at the stage casing position of the fin 14, and in fin 14
Ion concentration is gradually reduced from stage casing position to two ends（doping tail）, the top of fin 14 also can inevitably be deposited
In more Doped ions, there is the fin field effect pipe of the formation of fin 14 of more Doped ions, its grid using the top
Pole leakage current increase, the unstable properties of fin field effect pipe.
Further, inventor has found, during forming fin, can be initially formed the first sub- fin, first son
There are Doped ions in fin, the extension intrinsic layer undoped is then formed.Fin field effect pipe channel region was so both improved
Carrier mobility, grid leakage current will not be caused again, the performance of the fin field effect pipe of formation is stable.
Further, inventor has found, if extension intrinsic layer is trimmed, and in the extension intrinsic layer after trimming
It is doped, forms the second sub- fin, in the second sub- fin portion surface formation epitaxial layer, is then developed across the top of the epitaxial layer
Portion and the grid structure of side wall, the fin field effect pipe ultimately formed can not only reach the effect above, and can also reduce
The threshold voltage of fin field effect pipe, further improves the performance of fin field effect pipe.
To enable the above objects, features and advantages of the present invention more obvious understandable, below in conjunction with the accompanying drawings to the present invention
Embodiment be described in detail.
It refer to Fig. 2, the forming method of the fin field effect pipe of the embodiment of the present invention, including：
Step S201 is there is provided Semiconductor substrate, and the semiconductor substrate surface is covered with insulating barrier, through the insulating barrier
Thickness and the first sub- fin flushed with the surface of insulating layer, positioned at the extension intrinsic layer of the described first sub- fin portion surface, its
In, there are Doped ions in the first sub- fin；
Step S203, in the intrinsic layer surface formation separation layer of the extension, the separation layer, which has, defines grid structure
Opening；
Step S205, is trimmed to the extension intrinsic layer in the opening, and to the extension intrinsic layer after trimming
It is doped, forms the second sub- fin；
Step S207, forms epitaxial layer in the opening, the top of the second sub- fin described in the epitaxial layer uniform fold
Portion and side wall；
Step S209, is developed across the top of the epitaxial layer and the grid structure of side wall in the opening.
Specifically, refer to Fig. 3-Figure 13, Fig. 3-Figure 13 shows the formation of the embodiment of fin field effect pipe of the present invention
The cross-sectional view of process.
Fig. 3 be refer to there is provided Semiconductor substrate 300, the surface of Semiconductor substrate 300 has insulating barrier 301.
The Semiconductor substrate 300 is used to provide workbench for subsequent technique.The Semiconductor substrate 300 is silicon substrate
（Si）Or silicon-on-insulator（SOI）.In an embodiment of the present invention, the Semiconductor substrate 300 includes first area I and therewith
Adjacent second area II, the first area I is used for shape for forming N-channel fin field effect pipe, the second area II
Into P-channel fin field effect pipe.The material of the Semiconductor substrate 300 is monocrystalline silicon.
The insulating barrier 301 is used to isolate adjacent fin.The material of the insulating barrier 301 is silica, silicon nitride, nitrogen
Silica etc..The formation process of the insulating barrier 301 is depositing operation, such as physical gas-phase deposition（PVD）Or chemical gas
Phase depositing operation（CVD）.In an embodiment of the present invention, the insulating barrier 301 is subsequently used for forming shallow trench isolation（STI）,
The material of the insulating barrier 301 is silica, and the formation process of the insulating barrier 301 is low-pressure chemical vapor deposition process
（LPCVD）.
It should be noted that in embodiments of the invention, also including：Formed positioned at the surface of Semiconductor substrate 300
Dielectric layer 302, the dielectric layer 302 is used for the insulating barrier 301 for isolating first area I and second area II.For the ease of follow-up
Insulating barrier 301 is removed, the material of the dielectric layer 302 is different from the material of the insulating barrier 301, and subsequent etching insulating barrier
301 speed is more than the speed of etch media layer 302.
It refer to Fig. 4, form the groove 303 through the thickness of insulating barrier 301, and form in the groove 303 the
One sub- fin 305.
The groove 303 runs through the thickness of insulating barrier 301, is subsequently used as being formed the window of fin.In the reality of the present invention
Apply in example, formed after the groove 303, before the first sub- fin is formed, also included：To forming the insulating barrier after groove 303
301 carry out planarization process, such as isotropic etching technics（isotropic etching）Or steam annealing technique
（steam annealing）So that the surface of insulating barrier 301 is flat.
Inventor has found, when the fin bottom Doped ions of formation, can improve the load of fin field effect pipe channel region
Flow transport factor.Based on this, the first sub- fin 305 has Doped ions, for subsequently constituting fin.When the described first son
The ion concentration range of doping is in fin 305：1E18atoms/cm3-1E19atoms/cm3When, the fin field effect pipe of formation
The carrier mobility of channel region is high.
The formation process of the first sub- fin 305 is selective epitaxial depositing operation, in order to save processing step and make
Obtain Doped ions to be evenly distributed in the first sub- fin 305, the gas that the selective epitaxial depositing operation is used includes silicon source
Gas and doped source gas.Wherein, the silicon source gas is SiH2Cl2Or SiH4, the doped source gas is C3H8、CH4、
AsH3、PH3Or B2H6.In order to accelerate sedimentation rate, the gas that the selective epitaxial depositing operation is used can also include chlorination
Hydrogen and hydrogen.
In an embodiment of the present invention, the process parameters range of the selective epitaxial depositing operation is：Depositing temperature is
650 DEG C -750 DEG C, the pressure of deposition chambers is the support of 0.3 support -1.0, and the quality of the first sub- fin 305 of formation is good, is subsequently formed
Fin field effect pipe channel region carrier mobility it is high, the performance of the fin field effect pipe of formation is stable.
It should be noted that in an embodiment of the present invention, also including：Described first sub- fin 305 is heat-treated,
So that further diffusion is uniform for the Doped ions in the first sub- fin 305, make the channel region of fin field effect pipe being subsequently formed
Carrier mobility is high.The process of thermal treatment parameter includes：Heat treatment temperature（anneal tempreature）For 600
DEG C -1000 DEG C, it is heat-treated pressure（anneal pressure）For 1 atmospheric pressure, heat treatment time（anneal time）For
1min-30min。
Fig. 5 is refer to, extension intrinsic layer 307 is formed in the groove 301, the extension intrinsic layer 307 is located at described
The first sub- surface of fin 305, removes the insulating barrier 301 of segment thickness, exposes the top and side of the extension intrinsic layer 307
Wall.
The extension intrinsic layer 307 is used to subsequently trim, adulterated, and forms the second sub- fin.In the extension intrinsic layer 307
Without Doped ions, the width of the extension intrinsic layer 307 is identical with the width of the described first sub- fin 305, is 20nm-
100nm.Its formation process is selective epitaxial depositing operation, and the reacting gas of the selective epitaxial depositing operation is
SiH2Cl2, HCl and H2；Or SiH4, HCl and H2.In an embodiment of the present invention, the work of the selective epitaxial depositing operation
Skill parameter area is：Depositing temperature is 650 DEG C -750 DEG C, and the pressure of deposition chambers is the support of 0.3 support -1.0.
The insulating barrier 301 of segment thickness is removed, in favor of being subsequently formed the second sub- fin, epitaxial layer and grid structure.Remove
The technique that the insulating barrier 301 of segment thickness is used is etching technics, such as anisotropic dry or wet etch.Remove part
After the insulating barrier 301 of thickness, the remaining surface of insulating barrier 301 higher than the top of the described first sub- fin 305 or with the described first son
The surface of fin 305 is flushed.In an embodiment of the present invention, remove segment thickness insulating barrier 301 after, the first area I and
The remaining surfaces of insulating barrier 301 of second area II are flushed with the described first sub- top of fin 305.
It should be noted that in other embodiments of the invention, can also adopt be formed by other methods with doping from
The the first sub- fin 305 and the extension intrinsic layer 307 without Doped ions of son, for example, being mixed first in Semiconductor substrate 300
It is miscellaneous, the first sub- fin 305 of the formation of Semiconductor substrate 300 with Doped ions is then etched, is then formed described in being located at
The extension intrinsic layer 307 without Doped ions on the first sub- surface of fin 305.Detailed process will not be repeated here.
Incorporated by reference to being Fig. 6 overlooking the structure diagram with reference to Fig. 6 and Fig. 7, Fig. 7, for ease of understanding, dotted line table is used in Fig. 7
Show and be isolated the extension intrinsic layer 307 that layer 311 and dummy gate structure 309 are covered.It is developed across the top of extension intrinsic layer 307
With the dummy gate structure 309 of side wall, and the separation layer 311 positioned at the surface of insulating barrier 301, the surface of separation layer 311 with
The surface of dummy gate structure 309 is flushed.
The dummy gate structure 309 is used for position, the size and shape for defining grid structure.The dummy gate structure
309 forming step includes：Form the pseudo- gate dielectric layer of the covering top of extension intrinsic layer 307 and side wall（It is not shown）；Shape
Into the pseudo- gate electrode layer for covering the pseudo- gate dielectric layer surface（It is not shown）.Wherein, the material of the pseudo- gate dielectric layer is oxidation
Silicon, the material of the pseudo- gate electrode layer is polysilicon.
In an embodiment of the present invention, the dummy gate structure 309 includes the first dummy grid positioned at the first area I
Structure 3091, and positioned at the second dummy gate structure 3092 of the second area II.
Formed dummy gate structure 309 after, also including formed positioned at the surface of insulating barrier 301 and with the dummy grid
The separation layer 311 that the surface of structure 309 is flushed.The separation layer 311 is used to subsequently protect the fin beyond grid structure from damaging
It is bad, and in the grid structure for subsequently isolating adjacent fin FET.The formation process of the separation layer 311 is depositing operation,
Such as physically or chemically gas-phase deposition.Dummy gate structure is removed for ease of follow-up, the material of the separation layer 311 is different from
The material of dummy gate structure.In an embodiment of the present invention, the material of the separation layer 311 is silica.
In an embodiment of the present invention, because the top of extension intrinsic layer 307 is flushed with the surface of dielectric layer 302, pseudo- grid
Pole structure 309 is across the top of the extension intrinsic layer 307 and side wall, therefore the surface of the dummy gate structure 309 is higher than medium
302 surface of layer, and separation layer 311 flushes with the surface of dummy gate structure 309, therefore, the surface of the dielectric layer 302 be formed with every
Absciss layer 311.
Incorporated by reference to the overlooking the structure diagram for referring to Fig. 8 and Fig. 9, Fig. 9 are Fig. 8.Remove the first dummy gate structure, form the
One opening 313.
First opening 313 defines first area I grid structure, and beneficial to follow-up to the first area I's
Extension intrinsic layer 307 is trimmed and adulterated.The formation process of first opening 313 is etching technics, due to etching first
The technique of the opening 313 of dummy gate structure formation first has been well known to those skilled in the art, and will not be repeated here.
Incorporated by reference to the overlooking the structure diagram for referring to Figure 10 and Figure 11, Figure 11 are Figure 10.To in the described first opening 313
The extension intrinsic layer 307（As shown in Figure 7）Trimmed, and the extension intrinsic layer after trimming is doped, form second
Sub- fin 307a.
Inventor has found that prior art is by the fin 14（Shown in Fig. 1）Top surface mixed to inside fin 14
During heteroion, the top of fin 14 also can inevitably have more Doped ions, so as to cause fin field effect pipe
Grid leakage current is produced, the performance of fin field effect pipe is have impact on.However, only the first sub- fin 305 ought be doped, without
When being adulterated to the extension intrinsic layer, although phenomenon of gate leakage is suppressed, but the threshold of the fin field effect pipe formed
Threshold voltage is raised, and the performance of fin field effect pipe improves relatively limited.
After further research, inventor has found, the extension intrinsic layer 307 can be trimmed, shape of then adulterating
Into the second sub- fin 307a, epitaxial layer then is formed on the second sub- fin 307a surfaces, to reach suppressor grid leakage current and drop
The purpose of low fin field effect pipe threshold voltage, improves the performance of fin field effect pipe.
In the embodiment of the present invention, the extension intrinsic layer 307 in the first opening 313 is trimmed first, institute is trimmed
Technique that extension intrinsic layer 307 uses is stated for etching technics, such as dry or wet etch, the extension intrinsic layer after trimming
307 width W1For 10nm-50nm.The width W of extension intrinsic layer 307 after the trimming1When scope is 10nm-50nm, to institute
State the extension intrinsic layer 307 after trimming and be doped the sub- fin 307a of to be formed second, the fin field effect pipe ultimately formed can
To obtain low threshold voltage, the width W of extension intrinsic layer 307 after the trimming1During beyond above range, shape of subsequently adulterating
Into the second sub- fin 307a width W1Also above range is exceeded, otherwise it is unfavorable for being formed the fin field effect pipe of small volume,
The threshold voltage of fin field effect pipe is higher.
To improve the threshold voltage of fin field effect pipe, in addition it is also necessary to which the extension intrinsic layer 307 after the trimming is mixed
The ion of doping includes carbon ion or germanium ion in miscellaneous formation the second sub- fin 307a, the second sub- fin 307a.By grinding
Discovery is studied carefully, when the concentration range of Doped ions in the second sub- fin 307a is：1E17atoms/cm3-1E18atoms/cm3When, shape
Into fin field effect pipe can obtain relatively low threshold voltage, the performance of fin field effect pipe is stable.In the implementation of the present invention
In example, the ion that first area I is used to be formed doping in N-channel fin field effect pipe, the first area I includes carbon ion.
Due to the width W of the extension intrinsic layer 307 after trimming1It is smaller, to avoid ion doping during doping described in
Point of Doped ions in the region beyond the extension intrinsic layer 307 after trimming, or the second sub- fin 307a avoided the formation of
Cloth is uneven.In embodiments of the invention, the technique being doped to the extension intrinsic layer 307 after trimming is adulterated for molecular monolayer
Technique（Molecular Monolayer Doping Technique）, the molecular monolayer doping process is to the extension after trimming
The infringement on the surface of intrinsic layer 307 is minimum, and the second sub- fin 307a of formation quality is good, and ion will not be doped to after trimming
Ion distribution in region beyond the extension intrinsic layer 307, the second sub- fin 307a of formation is uniform, is particularly suitable for this
The big extension intrinsic layer 307a of depth-width ratio in embodiment.
The processing step of the molecular monolayer doping process includes：Using the hydrofluoric acid of dilution to the extension after the trimming
Intrinsic layer 307 is cleaned, and removes the oxide film on the surface of extension intrinsic layer 307 after the trimming（Predominantly with air
Oxygen contact nature aoxidize to be formed）；After end to be cleaned, by the solvent with high-flash（Such as triphenylphosphine
（Triphenylphosphine）Solution）It is doped into the extension intrinsic layer 307 after the trimming, forms the second sub- fin
307a；Silicon oxide layer is formed on the described second sub- fin 307a surfaces using low temperature oxidation technology；Using spike annealing（spike
anneal）Technique fin 307a to described second makes annealing treatment.Wherein, the thickness of the silicon oxide layer of formation is 15
- 40 nanometers of nanometer, the temperature during spike annealing is 1000 degrees Celsius -1100 degrees Celsius.It is 20nm especially when forming thickness
Silicon oxide layer, when the temperature of spike annealing is 1050 degrees Celsius, the ion distribution in the second sub- fin 307a is uniform, follow-up shape
Into fin field effect pipe threshold voltage it is low.
It should be noted that in an embodiment of the present invention, the width is referred to parallel to the Semiconductor substrate 300
The size of surface direction.
Incorporated by reference to the overlooking the structure diagram for referring to Figure 12 and Figure 13, Figure 13 are Figure 12.The shape in the described first opening 313
Into the first epitaxial layer 315, the second sub- fin 307a top and side wall described in the uniform fold of the first epitaxial layer 315.
Inventor has found, when fin and the ion concentration of the grid structure contact position of fin field effect pipe are more than
1E16atoms/cm3When, easily produce grid leakage current, and when fin and the grid structure contact position of fin field effect pipe from
Sub- concentration is less than or equal to 1E16atoms/cm3Or Doped ions are not present in the grid structure contact position of fin and fin field effect pipe
When, the grid leakage current of fin field effect pipe is small.
First epitaxial layer 315 is used for the grid leakage current for suppressing first area I fin field effect pipe.Described first
The material of epitaxial layer 315 is monocrystalline silicon, germanium, SiGe or III-V.The ion of doping in first epitaxial layer 315
Concentration range is 0atoms/cm3-1E16atoms/cm3, can more effectively suppress the grid leakage current of fin field effect pipe.At this
In the embodiment of invention, the material of first epitaxial layer 315 is without doping in monocrystalline silicon, first epitaxial layer 315
Ion, that is, the ion concentration adulterated is 0atoms/cm3。
It should be noted that in other embodiments of the invention, can also have doping in first epitaxial layer 315
Ion, as long as the concentration of the Doped ions is less than 1E16atoms/cm3Can suppressor grid leakage current.
To make the place that fin subsequently contacts with grid structure not produce grid leakage current, first epitaxial layer 315
Second sub- fin 307a top and side wall described in uniform fold.The formation process of first epitaxial layer 315 is depositing operation,
Such as chemical vapor deposition method.In an embodiment of the present invention, to save processing step, and the first epitaxial layer to be formed is made
315 thickness with side wall at the top of the second sub- fin 307a is homogeneous, and the formation process of first epitaxial layer 315 is outer for selectivity
Prolong depositing operation（Selective Epitaxy Deposition）.In an embodiment of the present invention, due to outer using selectivity
Prolong depositing operation, silicon atom is only deposited at the second sub- fin 307a top and side wall, without formed insulating barrier 301 and every
The surface of absciss layer 311, saves processing step.
In an embodiment of the present invention, formed material be monocrystalline silicon the first epitaxial layer 315 when, the reacting gas used for
Silicon source gas, HCl and H2, reaction pressure is 0.1-1.0 supports, and reaction temperature is 500 DEG C -800 DEG C.
The thickness of extension intrinsic layer 307 of the thickness of first epitaxial layer 315 with trimming is relevant, in the reality of the present invention
Apply in example, be effective suppressor grid leakage current, and make the small volume of fin field effect pipe to be formed, first epitaxial layer
The thickness of extension intrinsic layer 307 of 315 thickness with trimming is identical, is 5nm-25nm.
Incorporated by reference to the overlooking the structure diagram for referring to Figure 14 and Figure 15, Figure 15 are Figure 14.The shape in the described first opening 313
Into the top across first epitaxial layer 315 and the first grid structure 317 of side wall.
The forming step of the first grid structure 317 includes：Described first is developed across in the described first opening 313
The top of epitaxial layer 315 and the first high-K gate dielectric layer of side wall（It is not shown）；Form covering first high-K gate dielectric layer
First metal gate electrode layer（It is not shown）.The property of the fin field effect pipe including high-K gate dielectric layer and metal gate electrode layer
Can be more superior.
Incorporated by reference to the overlooking the structure diagram for referring to Figure 16 and Figure 17, Figure 17 are Figure 16.Remove the second of second area II
Dummy gate structure, forms the second opening 319.
Second opening 319 exposes the bottom of insulating barrier 301, defines second area II grid structure, is used in combination
In subsequently the extension intrinsic layer 307 of the second area II is trimmed and adulterated.The formation process of second opening 319
For etching technics, by the technique of the second dummy gate structure of etching the second opening 319 of formation is ripe for those skilled in the art
Know, will not be repeated here.
Incorporated by reference to the overlooking the structure diagram for referring to Figure 18 and Figure 19, Figure 19 are Figure 18.To the described second opening 319（Figure
Shown in 11）Interior extension intrinsic layer 307（Shown in Figure 11）Trimmed, and the extension intrinsic layer 307 after trimming be doped,
Form the second sub- fin 307b；Then in the second opening 319, the sub- fin 307b of uniform fold second top and side wall is formed
The second epitaxial layer 321；Top and the side wall of second epitaxial layer 321 are developed across in the described second opening 319 again
Second grid structure 323.
Because second area II is used to form P-channel fin field effect pipe in embodiments of the invention, and in first area I
N-channel fin field effect pipe is formed to be slightly different, in second area II the second sub- fin 307b the ion of doping include germanium from
Son, the P-channel fin field effect pipe high to form carrier mobility.
The width W of the extension intrinsic layer 307 of second area II after trimming2Adulterated for 10nm-50nm, inside it from
The concentration range of son is 1E17atoms/cm3-1E18atoms/cm3, the thickness of the second epitaxial layer 321 is 5nm-25nm, and in it
The ion concentration range of portion's doping is 0atoms/cm3-1E16atoms/cm3When, subsequently in the P-channel fin of second area II formation
The threshold voltage of formula FET is low, effectively inhibits grid leakage current, and device performance is stable.
The forming step of the second grid structure 323 is identical with the forming step of first grid structure 317, including：
Second high-K gate dielectric layer at the top and side wall of second epitaxial layer 321 is developed across in first opening 319（Do not scheme
Show）；Form the second metal gate electrode layer of covering second high-K gate dielectric layer（It is not shown）.It is described to be situated between including the second high K grid
The performance of the fin field effect pipe of matter layer and the second metal gate electrode layer is more superior.
It should be noted that the trimming second area II extension intrinsic layer 307（As shown in figure 11）, to trimming after
The extension intrinsic layer 307 of the second area II is doped, and forms the second sub- fin 307b, and form the second extension
Layer 321 forming method and technique with it is foregoing in the I of first area to the first sub- fin 307（As shown in Figure 7）Trimmed, mixed
Miscellaneous, it is identical with technique with the forming method for forming the first epitaxial layer 315 to form the first sub- fin 307a, will not be repeated here.
After above-mentioned steps are completed, the fin field effect pipe of the embodiment of the present invention completes.The fin effect of formation
Should pipe threshold voltage it is low, channel region carrier mobility is high, and grid leakage current is small, and device performance is stable.
Accordingly, continuing with combining with reference to Figure 18 and Figure 19, inventor additionally provides a kind of fin field effect pipe, including：
Semiconductor substrate 300；The surface of Semiconductor substrate 300 is covered with insulating barrier 301；Through the thickness of insulating barrier 301 and with
The first sub- fin 305 that the surface of insulating barrier 301 is flushed；Extension intrinsic layer 307 positioned at the described first sub- surface of fin 305
With the second sub- fin, the width of the second sub- fin is less than the width of the described first sub- fin 305；Positioned at the He of insulating barrier 301
The separation layer 311 on the surface of extension intrinsic layer 307, the separation layer 311 has the opening through its thickness（It is not shown）, it is described to open
Mouth exposes the described second sub- fin；Epitaxial layer in the opening, the sub- fin of the epitaxial layer uniform fold second
Top and side wall；In the opening and across the top of the epitaxial layer and the grid structure of side wall.
Wherein, the Semiconductor substrate 300 is used to provide workbench for subsequent technique.The Semiconductor substrate 300 is
Silicon substrate（Si）Or silicon-on-insulator（SOI）.In an embodiment of the present invention, the Semiconductor substrate 300 includes first area I
With second area II, the first area I adjacent thereto for forming N-channel fin field effect pipe, the second area II
For forming P-channel fin field effect pipe.
The insulating barrier 301 is used to isolate adjacent fin.The material of the insulating barrier 301 is silica, silicon nitride, nitrogen
Silica etc..In an embodiment of the present invention, the insulating barrier 301 is isolated as shallow trench（STI）, the insulating barrier 301
Material is silica.
In embodiments of the invention, also include：Dielectric layer 302 positioned at the surface of Semiconductor substrate 300, the medium
Layer 302 is used for the insulating barrier 301 for isolating first area I and second area II.The material of the dielectric layer 302 is different from exhausted
The material of edge layer 301.
The first sub- fin 305 and second sub- fin and epitaxial layer collectively form the fin of fin field effect pipe.It is described
The ion concentration range of doping is in first sub- fin 305：1E18atoms/cm3-1E19atoms/cm3, the fin effect of formation
Should pipe channel region carrier mobility it is high.
Second sub- fin 307a and secondth area of the extension intrinsic layer 307 for forming first area I after trimming, adulterating
Domain II the second sub- fin 307b.Do not have Doped ions, and its width and the described first sub- fin in the extension intrinsic layer 307
The width in portion 305 is identical.
The second sub- fin is used to reduce fin field effect pipe threshold voltage.In an embodiment of the present invention, described
Two sub- fins are obtained after being etched by extension intrinsic layer 307, including the second sub- fin 307a positioned at the first area I and are located at
The second sub- fin 307b of the second area II.
The separation layer 311 is used to subsequently protect the fin beyond grid structure against damages, and is subsequently isolating adjacent
The grid structure of fin field effect pipe.The material of the separation layer 311 is different from dummy gate structure（It is not shown）Material.At this
In the embodiment of invention, the material of the separation layer 311 is silica.
Opening in the separation layer 311 defines the size, shape and position of grid structure.Second son in the opening
The width W of fin1For 10nm-50nm, the fin field effect pipe of formation can obtain low threshold voltage.The second sub- fin
The concentration range of interior Doped ions is：1E17atoms/cm3-1E18atoms/cm3When, fin field effect pipe can obtain relatively low
Threshold voltage, the performance of fin field effect pipe is stable.
It should be noted that because first area I is used to form N-channel fin field effect pipe, second area II is used for shape
Into P-channel fin field effect pipe, the ion of doping includes carbon ion in the second sub- fin 307a of the first area I, described
The ion of doping includes germanium ion in second area II the second sub- fin 307b.
The top of the sub- fin of the epitaxial layer uniform fold second and side wall, its thickness are 5nm-25nm, for suppressing fin
The grid leakage current of formula FET.The material of the epitaxial layer is monocrystalline silicon, germanium, SiGe or III-V, described outer
The ion concentration range for prolonging doping in layer is 0atoms/cm3-1E16atoms/cm3When, the grid leakage current of fin field effect pipe
It is small.In an embodiment of the present invention, because with two regions, the epitaxial layer includes the first extension positioned at first area I
Layer 315 and the second epitaxial layer 321 positioned at second area II, are respectively used to suppress N-channel fin field effect pipe or P-channel fin
The grid leakage current of FET.
The grid structure is used for the grid for forming fin field effect pipe.The grid structure is included across the epitaxial layer
Top and side wall high-K gate dielectric layer, cover the metal gate electrode layer of the high-K gate dielectric layer.In embodiments of the invention
In, the grid structure includes the first grid structure 317 across first epitaxial layer 315, and across second extension
The second grid structure 323 of layer 321, is for respectively forming the grid of N-channel fin field effect pipe or P-channel fin field effect pipe
Pole.
In embodiments of the invention, the first sub- fin, the second sub- fin positioned at the described first sub- fin portion surface and uniform
The top of the described second sub- fin and the epitaxial layer of side wall are covered, the fin of fin field effect pipe, described first is together constituted
There are Doped ions in sub- fin, the carrier mobility of fin field effect pipe channel region is improved, and have in the second sub- fin
There are Doped ions, effectively reduce the threshold voltage of fin field effect pipe, and due to the presence of epitaxial layer, effectively inhibit fin
The grid leakage current of formula FET, the device performance of the fin field effect pipe of the embodiment of the present invention is stable.
To sum up, when forming fin field effect pipe, the first sub- fin for being initially formed doping and the extension intrinsic layer undoped,
Then split intraoral extension intrinsic layer is trimmed and adulterated, and forms the second sub- fin, then form in opening uniform fold
The top of second sub- fin and the epitaxial layer of side wall, formation process are simple, the load of the fin field effect pipe of formation not only channel region
Flow transport factor high, and threshold voltage is low, and grid leakage current is small, and device performance is stable.
Further, the width of the extension intrinsic layer after trimming is smaller, is 10nm-50nm.Adulterate outer after the trimming
Prolong intrinsic layer, form the technique used during the second sub- fin for molecular monolayer doping process, in the second sub- fin of formation from
Son is evenly distributed, and the threshold voltage for the fin field effect pipe being subsequently formed is lower.
Further, can be respectively in first area I and second area II formation N-channel fin field effect pipes and P ditches
Road fin field effect pipe, formation process is simple, and the performance of the CMOS fin field effect pipes of formation is good.
The fin of the fin field effect pipe is by the first sub- fin, positioned at the second sub- fin of the described first sub- fin portion surface
The top of second sub- fin described in portion and uniform fold and the epitaxial layer of side wall are collectively formed, due in the described first sub- fin
With Doped ions, improve the carrier mobility of fin field effect pipe channel region, and have in the second sub- fin doping from
Son, effectively reduces the threshold voltage of fin field effect pipe, and due to the presence of epitaxial layer, effectively inhibit fin field effect
The grid leakage current of pipe, the device performance of the fin field effect pipe of the embodiment of the present invention is stable.
Although the present invention is disclosed as above with preferred embodiment, it is not for limiting the present invention, any this area
Technical staff without departing from the spirit and scope of the present invention, may be by the methods and techniques content of the disclosure above to this hair
Bright technical scheme makes possible variation and modification, therefore, every content without departing from technical solution of the present invention, according to the present invention
Any simple modification, equivalent variation and modification for being made to above example of technical spirit, belong to technical solution of the present invention
Protection domain.
Claims (21)
1. a kind of forming method of fin field effect pipe, it is characterised in that including：
There is provided Semiconductor substrate, the semiconductor substrate surface covered with insulating barrier, through the thickness of insulating layer and with it is described
The first sub- fin that surface of insulating layer is flushed, positioned at the extension intrinsic layer of the described first sub- fin portion surface, wherein, first son
There are Doped ions, the ion concentration range of the interior doping of the first sub- fin is in fin：1E18atoms/cm3-
1E19atoms/cm3；
In the intrinsic layer surface formation separation layer of the extension, the separation layer has the opening for defining grid structure；
The extension intrinsic layer in the opening is trimmed, and the extension intrinsic layer after trimming is doped, is formed
The concentration range of Doped ions is in second sub- fin, the second sub- fin：1E17atoms/cm3-1E18atoms/cm3；
Epitaxial layer is formed in the opening, the top of the second sub- fin and side wall described in the epitaxial layer uniform fold；It is described
The thickness of extension intrinsic layer of the thickness of epitaxial layer with trimming is identical；
The top of the epitaxial layer and the grid structure of side wall are developed across in the opening；
The grid structure includes the high-K gate dielectric layer across the top of the epitaxial layer and side wall, covers the high-K gate dielectric
The metal gate electrode layer of layer.
2. the forming method of fin field effect pipe as claimed in claim 1, it is characterised in that in the epitaxial layer doping from
Sub- concentration range is 0atoms/cm3-1E16atoms/cm3。
3. the forming method of fin field effect pipe as claimed in claim 1, it is characterised in that the formation process of the epitaxial layer
For selective epitaxial depositing operation.
4. the forming method of fin field effect pipe as claimed in claim 1, it is characterised in that the material of the epitaxial layer is single
Crystal silicon, germanium, SiGe or III-V.
5. the forming method of fin field effect pipe as claimed in claim 1, it is characterised in that when the material of the epitaxial layer is
During monocrystalline silicon, the reacting gas that the formation epitaxial layer is used is silicon source gas, HCl and H2, reaction pressure is 0.1-1.0 supports,
Reaction temperature is 500 DEG C -800 DEG C.
6. the forming method of fin field effect pipe as claimed in claim 1, it is characterised in that the thickness of the epitaxial layer is
5nm-25nm。
7. the forming method of fin field effect pipe as claimed in claim 1, it is characterised in that the width of the extension intrinsic layer
For 20nm-100nm.
8. the forming method of fin field effect pipe as claimed in claim 1, it is characterised in that the extension after the trimming is intrinsic
The width of layer is 10nm-50nm.
9. the forming method of fin field effect pipe as claimed in claim 1, it is characterised in that to the extension intrinsic layer after trimming
It is doped, the technique for forming the second sub- fin is molecular monolayer doping process.
10. the forming method of fin field effect pipe as claimed in claim 9, it is characterised in that the molecular monolayer doping work
The processing step of skill includes：The extension intrinsic layer after the trimming is cleaned using the hydrofluoric acid of dilution；It is to be cleaned to terminate
Afterwards, the solvent with high-flash is doped into the extension intrinsic layer after the trimming, forms the second sub- fin；Using cryogenic oxygen
Chemical industry skill is in the described second sub- fin portion surface formation silicon oxide layer；The described second sub- fin is moved back using spike annealing process
Fire processing.
11. the forming method of fin field effect pipe as claimed in claim 10, it is characterised in that the solvent of the high-flash is
Triphenylphosphine solution.
12. the forming method of fin field effect pipe as claimed in claim 10, it is characterised in that the thickness of the silicon oxide layer
For 15 nanometers -40 nanometers.
13. the forming method of fin field effect pipe as claimed in claim 10, it is characterised in that the temperature during spike annealing
Spend for 1000 degrees Celsius -1100 degrees Celsius.
14. the forming method of fin field effect pipe as claimed in claim 1, it is characterised in that mixed in the second sub- fin
Miscellaneous ion includes carbon ion or germanium ion.
15. the forming method of fin field effect pipe as claimed in claim 1, it is characterised in that the Semiconductor substrate includes
First area and second area adjacent thereto, the first area are used to form N-channel fin field effect pipe, secondth area
Domain is used to form P-channel fin field effect pipe.
16. a kind of fin field effect pipe, it is characterised in that including：
Semiconductor substrate；
The semiconductor substrate surface is covered with insulating barrier；
Adulterated in the first sub- fin flushed through the thickness of insulating layer and with the surface of insulating layer, the first sub- fin
Ion concentration range be：1E18atoms/cm3-1E19atoms/cm3；
Positioned at the extension intrinsic layer and the second sub- fin of the described first sub- fin portion surface, the width of the second sub- fin is less than institute
The concentration range for stating Doped ions in the width of the first sub- fin, the second sub- fin is：1E17atoms/cm3-
1E18atoms/cm3；
Positioned at insulating barrier and the separation layer of the intrinsic layer surface of extension, the separation layer has the opening through its thickness, described to open
Mouth exposes the described second sub- fin；
Epitaxial layer in the opening, the top of the sub- fin of the epitaxial layer uniform fold second and side wall；The extension
The thickness of extension intrinsic layer of the thickness of layer with trimming is identical；
In the opening and across the top of the epitaxial layer and the grid structure of side wall；
The grid structure includes the high-K gate dielectric layer across the top of the epitaxial layer and side wall, covers the high-K gate dielectric
The metal gate electrode layer of layer.
17. fin field effect pipe as claimed in claim 16, it is characterised in that the concentration of Doped ions is in the epitaxial layer
0atoms/cm3-1E16atoms/cm3。
18. fin field effect pipe as claimed in claim 16, it is characterised in that the material of the epitaxial layer be monocrystalline silicon, germanium,
SiGe or III-V.
19. fin field effect pipe as claimed in claim 16, it is characterised in that the thickness of the epitaxial layer is 5nm-25nm.
20. fin field effect pipe as claimed in claim 16, it is characterised in that the width of the second sub- fin is 10nm-
50nm。
21. fin field effect pipe as claimed in claim 16, it is characterised in that the Doped ions bag in the second sub- fin
Include carbon ion or germanium ion.
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Families Citing this family (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2016105404A1 (en) * | 2014-12-23 | 2016-06-30 | Intel Corporation | Thin channel region on wide subfin |
| CN106252228B (en) * | 2015-06-11 | 2019-11-08 | 中国科学院微电子研究所 | A kind of forming method of compound fin |
| DE112016006696T5 (en) * | 2016-03-30 | 2018-12-20 | Intel Corporation | Geometry tuning of a fin-based transistor |
| US9953883B2 (en) * | 2016-04-11 | 2018-04-24 | Samsung Electronics Co., Ltd. | Semiconductor device including a field effect transistor and method for manufacturing the same |
| CN109872971B (en) * | 2017-12-04 | 2020-12-22 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| CN108470770A (en) * | 2018-03-21 | 2018-08-31 | 上海华力集成电路制造有限公司 | Fin transistor and its manufacturing method |
| CN111463173B (en) * | 2019-01-18 | 2023-04-28 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| CN112802898B (en) * | 2020-12-31 | 2023-05-23 | 泉芯集成电路制造(济南)有限公司 | Fin type field effect transistor and manufacturing method thereof |
| CN112786704B (en) * | 2020-12-31 | 2023-04-07 | 泉芯集成电路制造(济南)有限公司 | Variable capacitance diode in fin field effect transistor process and manufacturing method thereof |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1581431A (en) * | 2003-08-14 | 2005-02-16 | 三星电子株式会社 | Multi-structure silicon fin and its making method |
| US20070176245A1 (en) * | 2004-02-05 | 2007-08-02 | Samsung Electronics Co., Ltd. | Fin fet and method of fabricating same |
| CN101490821A (en) * | 2006-07-14 | 2009-07-22 | 美光科技公司 | Subresolution silicon features and methods for forming the same |
| CN102468235A (en) * | 2010-11-02 | 2012-05-23 | 台湾积体电路制造股份有限公司 | Fin-like field effect transistor (finfet) device and method of manufacturing same |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7193279B2 (en) * | 2005-01-18 | 2007-03-20 | Intel Corporation | Non-planar MOS structure with a strained channel region |
-
2012
- 2012-06-19 CN CN201210203757.1A patent/CN103515209B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1581431A (en) * | 2003-08-14 | 2005-02-16 | 三星电子株式会社 | Multi-structure silicon fin and its making method |
| US20070176245A1 (en) * | 2004-02-05 | 2007-08-02 | Samsung Electronics Co., Ltd. | Fin fet and method of fabricating same |
| CN101490821A (en) * | 2006-07-14 | 2009-07-22 | 美光科技公司 | Subresolution silicon features and methods for forming the same |
| CN102468235A (en) * | 2010-11-02 | 2012-05-23 | 台湾积体电路制造股份有限公司 | Fin-like field effect transistor (finfet) device and method of manufacturing same |
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