CN103839814B - The forming method of fin formula field effect transistor - Google Patents
The forming method of fin formula field effect transistor Download PDFInfo
- Publication number
- CN103839814B CN103839814B CN201210477241.6A CN201210477241A CN103839814B CN 103839814 B CN103839814 B CN 103839814B CN 201210477241 A CN201210477241 A CN 201210477241A CN 103839814 B CN103839814 B CN 103839814B
- Authority
- CN
- China
- Prior art keywords
- fin
- channel region
- field effect
- forming method
- grid
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000000034 method Methods 0.000 title claims abstract description 66
- 230000005669 field effect Effects 0.000 title claims abstract description 31
- 239000000758 substrate Substances 0.000 claims abstract description 42
- 239000004065 semiconductor Substances 0.000 claims abstract description 40
- 239000000463 material Substances 0.000 claims description 42
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 24
- 229910052710 silicon Inorganic materials 0.000 claims description 24
- 239000010703 silicon Substances 0.000 claims description 24
- 230000015572 biosynthetic process Effects 0.000 claims description 16
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 15
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 14
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 14
- 229920005591 polysilicon Polymers 0.000 claims description 14
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 14
- 238000005530 etching Methods 0.000 claims description 13
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims description 11
- 229910052582 BN Inorganic materials 0.000 claims description 10
- PZNSFCLAULLKQX-UHFFFAOYSA-N Boron nitride Chemical compound N#B PZNSFCLAULLKQX-UHFFFAOYSA-N 0.000 claims description 10
- 229910003481 amorphous carbon Inorganic materials 0.000 claims description 10
- 230000008569 process Effects 0.000 claims description 10
- 239000004576 sand Substances 0.000 claims description 10
- 238000001312 dry etching Methods 0.000 claims description 9
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 9
- 229910003978 SiClx Inorganic materials 0.000 claims description 6
- 239000002184 metal Substances 0.000 claims description 6
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 5
- 238000001039 wet etching Methods 0.000 claims description 5
- 238000012545 processing Methods 0.000 claims description 3
- OBOXTJCIIVUZEN-UHFFFAOYSA-N [C].[O] Chemical compound [C].[O] OBOXTJCIIVUZEN-UHFFFAOYSA-N 0.000 claims 3
- 239000010410 layer Substances 0.000 description 137
- 238000000151 deposition Methods 0.000 description 5
- 238000010586 diagram Methods 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 5
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 5
- 238000005229 chemical vapour deposition Methods 0.000 description 4
- 230000008021 deposition Effects 0.000 description 3
- 229910052732 germanium Inorganic materials 0.000 description 3
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 3
- 239000012212 insulator Substances 0.000 description 3
- 230000009467 reduction Effects 0.000 description 3
- 239000002356 single layer Substances 0.000 description 3
- 230000004888 barrier function Effects 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 239000000969 carrier Substances 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 239000003989 dielectric material Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(IV) oxide Inorganic materials O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- MRELNEQAGSRDBK-UHFFFAOYSA-N lanthanum oxide Inorganic materials [O-2].[O-2].[O-2].[La+3].[La+3] MRELNEQAGSRDBK-UHFFFAOYSA-N 0.000 description 2
- DOTMOQHOJINYBL-UHFFFAOYSA-N molecular nitrogen;molecular oxygen Chemical compound N#N.O=O DOTMOQHOJINYBL-UHFFFAOYSA-N 0.000 description 2
- KTUFCUMIWABKDW-UHFFFAOYSA-N oxo(oxolanthaniooxy)lanthanum Chemical compound O=[La]O[La]=O KTUFCUMIWABKDW-UHFFFAOYSA-N 0.000 description 2
- 125000006850 spacer group Chemical group 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 230000003628 erosive effect Effects 0.000 description 1
- 238000002353 field-effect transistor method Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000005012 migration Effects 0.000 description 1
- 238000013508 migration Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
A kind of forming method of fin formula field effect transistor, including: Semiconductor substrate is provided；Hard mask layer is formed at semiconductor substrate surface；With described hard mask layer as mask, etch semiconductor substrates, form fin；Pseudo-grid, dummy gate span and cover fin the first channel region and the hard mask layer at top thereof is formed at semiconductor substrate surface；Source electrode and the dielectric layer of drain electrode covering fin is formed in pseudo-grid both sides；Remove pseudo-grid, expose the first channel region and the hard mask layer at top thereof of fin；Etch described first channel region so that it is width reduces, and forms the second channel region；It is developed across and covers the grid of the second channel region.The forming method of described fin formula field effect transistor, it is possible to reduce the resistance of source and drain, improves the driving electric current of transistor.
Description
Technical field
The present invention relates to technical field of semiconductors, particularly to the formation side of a kind of fin formula field effect transistor
Method.
Background technology
Along with the development of semiconductor process technique, process node is gradually reduced, rear grid (gate-last)
Technique is widely applied, and to obtain preferable threshold voltage, improves device performance.But work as device
Characteristic size (CD, Critical Dimension) when declining further, even if grid technique system after Cai Yonging
The field effect transistor made the most cannot meet the demand to device performance, and multi-gate device has acquired widely
Pay close attention to.
Fin formula field effect transistor (Fin FET) is a kind of common multi-gate device, and Fig. 1 shows existing skill
The fin of a kind of fin formula field effect transistor of art and the perspective view of grid structure.Such as Fig. 1 institute
Show, including: Semiconductor substrate 10, described Semiconductor substrate 10 is formed the fin 14 of protrusion；Medium
Layer 11, covers the surface of described Semiconductor substrate 10 and a part for the sidewall of fin 14；Grid structure
12, on described fin 14 and cover top and the sidewall of described fin 14, grid structure 12 includes grid
Dielectric layer (not shown) and the gate electrode (not shown) being positioned on gate dielectric layer.With grid
The top of the fin 14 that structure 12 contacts and the sidewall constituting channel district of both sides, therefore, Fin FET has
Having multiple grid, this is conducive to increasing large-drive-current, improves device performance.
But being as the reduction of fin size, the source and drain areas area at fin two ends reduces the most accordingly, causes
The contact resistance of source electrode and drain electrode increases, and causes driving electric current to decline, thus affects the performance of device.?
In formation technology, being formed after fin transistor can be in the gate lateral wall of transistor and source electrode and drain electrode
Sidewall forms side wall.A kind of method of existing reduction source electrode and drain resistance is, removes source electrode and drain electrode
The side wall of both sides, then forms silicon epitaxial layers to source electrode and drain surface and improves the area of source and drain areas,
Thus reduce source and drain resistance.But, this method, on the one hand, can remove not thorough due to bottom side wall,
Source electrode and the formation of drain surface epitaxial layer can be hindered, on the other hand, removing source electrode and the sidewall that drains
Side wall also can get rid of the part side wall of gate lateral wall simultaneously, causes on source electrode, drain and gate surface together
Time formed epitaxial layer, when the epitaxial layer on source electrode, drain and gate reaches certain thickness, source can be caused
The bridging of epitaxial layer between pole, drain and gate, causes short circuit between source electrode, drain and gate.
More structures about fin formula field effect transistor and forming method refer to Patent No.
The United States Patent (USP) of " US7868380B2 ".
Summary of the invention
The problem that the present invention solves is to provide the forming method of fin formula field effect transistor, and described fin field is imitated
Answer the forming method of transistor, the resistance of source electrode and drain electrode can be reduced, improve the driving electric current of transistor.
For solving the problems referred to above, the invention provides the forming method of a kind of fin formula field effect transistor, bag
Include: Semiconductor substrate is provided；Hard mask layer is formed at semiconductor substrate surface；With described hard mask layer it is
Mask, etch semiconductor substrates, form fin；Pseudo-grid, dummy gate is formed at semiconductor substrate surface
First channel region of span and cover fin and the hard mask layer at top thereof, described first channel region position
In the middle part of fin, described first channel region both sides are source electrode and the drain electrode of fin；In pseudo-grid both sides shape
Becoming to cover source electrode and the dielectric layer of drain electrode of fin, described dielectric layer surface flushes with pseudo-grid surface；Remove
Pseudo-grid, expose the first channel region and the hard mask layer at top thereof of fin；Etch described first raceway groove
The both sides in region so that it is width reduces, and forms the second channel region；It is developed across and covers the second raceway groove
The grid in region.
Preferably, the method for described formation fin includes: after forming hard mask layer, firmly cover described
The both sides of film layer form the first side wall, using the side wall of described hard mask layer and both sides thereof as mask, etching
Semiconductor substrate, forms fin.
Preferably, the material of described first side wall be silicon nitride, amorphous carbon, boron nitride, silicon oxynitride,
Fire sand or siloxicon.
Preferably, the bottom width of described first side wall is more than 2nm.
Preferably, the method for described formation the second channel region is: removes described first side wall, then adopts
The both sides of described first channel region are etched so that it is width reduces by wet processing or dry etch process,
Described dry etch process, with hard mask layer as mask, carries out vertical etch.
Preferably, the method for described formation fin includes: with described hard mask layer as mask, and etching is described
After Semiconductor substrate forms pretreatment fin, then in described pretreatment fin both sides grown epitaxial layer, shape
Become fin.
Preferably, described epitaxial layer is single or multiple lift structure.
Preferably, the material of described epitaxial layer is silicon, SiGe or carborundum.
Preferably, the method for described formation the second channel region is: use wet etching or dry etching work
Skill etches the both sides of described first channel region so that it is width reduces, the plasma of described dry etching
Direction in horizontal plane, the sidewall of the most described first channel region.
Preferably, the thickness of described hard mask layer is more than 10nm.
Preferably, the width of described fin is more than 30nm.
Preferably, the width of described second channel region is more than 10nm.
Preferably, the material of described hard mask layer be silicon nitride, amorphous carbon, boron nitride, silicon oxynitride,
Fire sand or siloxicon.
Preferably, the material of dummy gate is polysilicon.
Preferably, the material of described dielectric layer includes silicon oxide, silicon nitride or silicon oxynitride.
Preferably, also include: being formed after the second channel region, at described dielectric layer towards second
The sidewall surfaces of channel region forms the second side wall.
Preferably, the material of described second side wall be silicon nitride, amorphous carbon, boron nitride, silicon oxynitride,
Fire sand or siloxicon.
Preferably, described grid is high-K metal gate or polysilicon gate.
Compared with prior art, the invention have the advantages that
Technical scheme, is formed after fin at semiconductor substrate surface, by the of fin
One channel region forms pseudo-grid, after pseudo-grid both sides form the medium of source electrode and the drain electrode covering fin,
Remove pseudo-grid, expose the first channel region of fin, by etching the width of thinning first channel region,
Form the second channel region.Ultimately form source and drain width big, the fin that channel region width is little.The present invention
The technical scheme fin bigger by being initially formed width after, the channel region of fin is carried out thinning
Source and drain is protected so that the size of source and drain keeps not by the dielectric layer of covering source electrode and drain electrode simultaneously
Become, so while obtaining the width of the channel region needed, improve the size of source electrode and drain electrode,
Effectively reduce transistor source and the resistance of drain electrode, improve the driving electric current of transistor.
Further, by pretreatment fin both sides grown epitaxial layer, thus obtain the fin that width is bigger
Portion.Described epitaxial layer can be the silicon of monolayer, SiGe or carborundum, it is possible to have multiple structure,
The material of each layer adjacent monolayer is different.Described epitaxial layer can produce stress effect to channel region,
Improve the mobility of raceway groove carriers.If the epitaxial layer formed is silicon germanide layer, it is favorably improved ditch
The tensile stress in region, road, in raising raceway groove, the mobility of electronics, is favorably improved the performance of NMOS；Outward
Prolonging layer is the compressive stress that silicon carbide layer is then favorably improved channel region, the mobility in hole in raising raceway groove,
It is favorably improved the performance of PMOS.Epitaxial layer can be adjusted for different types of MOS transistor
Structure and material, it is thus achieved that suitably stress.Described technical scheme, while reducing source and drain resistance, also
The carrier mobility of transistor can be improved.
Accompanying drawing explanation
Fig. 1 is the schematic diagram of existing fin transistor；
Fig. 2 to Figure 16 is the schematic diagram forming fin formula field effect transistor in the first embodiment of the present invention；
Figure 17 to Figure 26 is the schematic diagram forming fin formula field effect transistor in the second embodiment of the present invention.
Detailed description of the invention
As described in the background art, existing fin formula field effect transistor, along with the reduction of fin size,
The source and drain areas area at fin two ends reduces the most accordingly, causes the contact resistance of source and drain to increase, and drives electric current
Can decline, thus affect the performance of device.In prior art, typically forming fin formula field effect transistor
Afterwards, source and drain is carried out epitaxial growth and improves the size of source and drain areas, and this method exists deposition quality
Problem the highest, easily short circuit between source and drain and grid.
For solving the problems referred to above, the present invention proposes a kind of method forming fin formula field effect transistor, first
Form larger-size fin, then the width of the channel region of fin is carried out thinning, obtain less chi
Obtain the source and drain areas of large-size while very little channel region, thus reduce the resistance of source electrode and drain electrode.
Understandable, below in conjunction with the accompanying drawings for enabling the above-mentioned purpose of the present invention, feature and advantage to become apparent from
The detailed description of the invention of the present invention is described in detail.Described embodiment be only the present invention can
A part for embodiment rather than they are whole.When describing the embodiment of the present invention in detail, for purposes of illustration only,
Schematic diagram can be disobeyed general ratio and be made partial enlargement, and described schematic diagram is example, and it should not at this
Limit the scope of the invention.Additionally, the three of length, width and the degree of depth should be comprised in actual fabrication
Dimension space size.According to described embodiment, those of ordinary skill in the art is without creative work
Under premise, obtainable other embodiments all, broadly fall into protection scope of the present invention.Therefore the present invention
Do not limited by following public being embodied as.
First embodiment
Refer to Fig. 2, it is provided that Semiconductor substrate 110.
The material of described Semiconductor substrate 110 includes the semi-conducting materials such as silicon, germanium, SiGe, GaAs,
Can be body material can also be composite construction such as silicon-on-insulator or germanium on insulator.The technology of this area
Personnel can select described Semiconductor substrate 110 according to the semiconductor device formed in Semiconductor substrate 110
Type, the type of the most described Semiconductor substrate should not limit the scope of the invention.
In the present embodiment, the material of the Semiconductor substrate 110 used is silicon-on-insulator, serves as a contrast including silicon
Bottom 100, intermediate silicon oxide layer 101 and monocrystal silicon top layer 102.
Refer to Fig. 3, form hardmask material 200 on Semiconductor substrate 110 surface.
Concrete, deposit one layer firmly by chemical vapor deposition method on described Semiconductor substrate 110 surface
Mask layer.The material of described hardmask material is silicon nitride, amorphous carbon, boron nitride, nitrogen oxygen
Other suitable materials such as SiClx, fire sand or siloxicon.
Refer to Fig. 4, form hard mask layer 201 at semiconductor substrate surface.
Concrete, etch described hardmask material 200(and refer to Fig. 3), form hard mask layer 201,
The thickness of described hard mask layer 201 is more than 10nm.
Refer to Fig. 5, form the first side wall 202 in described hard mask layer 201 both sides.
Concrete, the material of described first side wall 202 is silicon nitride, amorphous carbon, boron nitride, nitrogen oxygen
Other suitable materials such as SiClx, fire sand or siloxicon.The formation side of described first side wall 202
Method is: use chemical vapor deposition method, formation covering semiconductor substrate surface and hard mask layer surface
First spacer material layer；Utilize plasma etch process, the first spacer material layer described in vertical etch,
Until exposing hard mask layer 201 top surface and semiconductor substrate surface, in hard mask layer 201 both sides
Form the first side wall 202.The bottom width of described first side wall is more than 2nm.Described first side wall with firmly cover
The bottom overall width of film layer is more than 30nm.In other embodiments of the invention, it is also possible to be formed without described
First side wall, only forms hard mask layer, and makes the width of hard mask layer more than 30nm.
Refer to Fig. 6, using the first side wall 202 of described hard mask layer 201 and both sides thereof as mask, carve
Erosion Semiconductor substrate, forms fin 300.
Concrete, in the present embodiment, use the monocrystal silicon top layer of dry etch process etch semiconductor substrates
102(refer to Fig. 5), form fin 300, the width of the fin 300 of described formation is more than 30nm.
In other embodiments of the invention, if being formed without the first side wall 202, then directly with hard mask layer 201
For mask, etch semiconductor substrates, form the width fin more than 30nm.
Refer to Fig. 7, be developed across and cover the first channel region and the hard mask layer at top thereof of fin
201 and the first pseudo-grid 400 of side wall 202.
Concrete, the material of dummy gate 400 is polysilicon.First channel region of described fin is positioned at
The middle part of fin.Described form pseudo-grid technique be: substrate surface formed one layer cover fin and
Its top hard mask layer and the polysilicon layer of side wall, and planarized；Again in polysilicon layer surface shape
Become cover described first channel region mask layer, with described mask layer for mask etching polysilicon layer after,
Expose source electrode and the drain region at fin two ends, and the hard mask layer at source electrode and top, drain region and
Side wall.In other embodiments of the invention, if employing body silicon or other materials are as Semiconductor substrate,
After forming fin, before forming pseudo-grid, form a layer insulating at substrate surface, as follow-up shape
Insulating barrier between the grid and the substrate that become.
Refer to Fig. 8, form source electrode and the dielectric layer 401 of drain electrode covering fin in pseudo-grid 400 both sides.
Concrete, the material of described dielectric layer is silicon nitride or silicon oxynitride.Form described dielectric layer 401
Method be: utilize chemical vapor deposition method, at pseudo-grid both sides deposits dielectric materials, cover described fin
After the source electrode in portion and drain electrode, planarized, formed dielectric layer 401, the height of described dielectric layer 401
Flush with the height of pseudo-grid 400.Described dielectric layer 401 covers source electrode and the drain electrode of fin, makes source and drain exist
Being protected in subsequent technique, size will not change.
Refer to Fig. 9, remove pseudo-grid 400(and refer to Fig. 8), expose fin the first channel region and
The hard mask layer at its top and the first side wall.
Concrete, the described technique removing pseudo-grid is wet etching or dry etching.
Refer to Figure 10, for the top view of the Fig. 9 after the pseudo-grid of removal.
Described channel region (not shown) is positioned at the unlapped zone line of dielectric layer 401, by the first side
Wall 202 and hard mask layer 201 are covered.
Refer to Figure 11, after removing pseudo-grid, along the generalized section in AA ' direction.
Wherein the first channel region 301 of fin is positioned on silicon oxide layer 101, by hard mask layer 201
Cover with the first side wall 202.
Refer to Figure 12, etch described first channel region 301(and refer to Figure 11) so that it is width reduces,
Form the second channel region 302.
Concrete, in the present embodiment, etch described first channel region 301, form the second channel region
The method of 302 is wet-etching technology.Dry etching work can also be used in other embodiments of the invention
Skill, the plasma direction of described dry etching, in horizontal plane, is perpendicular to the sidewall of described channel region.
The width of the second channel region 302 of described formation is more than 10nm.
In other embodiments of the invention, it is also possible to first remove described first side wall 202, expose first
The part that channel region is not covered by hard mask layer 201, then using hard mask layer 201 as mask, use
First channel region described in dry etch process vertical etch, forms the second channel region 302.In the present invention
Other embodiments in, it is also possible to be formed without the first side wall being formed after hard mask layer 201, such
In the case of, wet processing or dry etch process can be used to etch described first channel region, described dry
The plasma direction of method etching, in horizontal plane, is perpendicular to the sidewall of described channel region.
Refer to Figure 13, remove the first side wall 202(and refer to Figure 12).
Refer to Figure 14, refer to Figure 12 for removing the first side wall 202() after top view.
Described second channel region 302(refer to Figure 13) top only has hard mask layer 201.
Refer to Figure 15, dielectric layer 401 towards fin the second channel region sidewall surfaces formed second
Side wall 402.
Concrete, the material of described second side wall be silicon nitride, amorphous carbon, boron nitride, silicon oxynitride,
Other suitable materials such as fire sand or siloxicon.
Described second side wall can make up during performing etching the first channel region for media of both sides
The damage that layer 401 is caused, keeps the smooth of surface, improves the deposition quality of the grid being subsequently formed.
Refer to Figure 16, be developed across and cover the grid 500 of the second channel region.
Concrete, in the present embodiment, described grid 500 is high-k/metal gate, and forming method is: first
Depositing one layer of high-k dielectric layer, described high K medium can be HfO2、La2O3, HfSiON or HfAlO2Deng
High-g value.Again at described high-K dielectric layer forming metal layer on surface, planarize afterwards.At its of the present invention
In his embodiment, described grid 500 can also be polysilicon gate.In other embodiments of the invention,
Described hard mask layer 201(can also be refer to Figure 15) remove after form grid 500 again.
In the present embodiment, before forming grid, source electrode and drain region are carried out plasma injection.
In the present embodiment, after the fin by the bigger width of formation, utilize dielectric layer that source and drain areas is entered
Row covering protection, then the first channel region of fin is performed etching, its width thinning, form source and drain chi
Very little greatly, the fin that channel region size is little.In the case of meeting channel region size, improve source and drain
Size, thus reduce source and drain resistance, improve the driving electric current of transistor.Further, described transistor
Source and drain is protected by dielectric layer, will not and the later stage formed grid between formed short circuit.
Second embodiment
The present embodiment additionally provides the another kind of method forming fin formula field effect transistor.
Refer to Figure 17, use the method identical with first embodiment, form hard mask layer at substrate surface
After 201, etch semiconductor substrates forms pretreatment fin 500.
Refer to Figure 18, at the sidewall growth epitaxial layer 501 of described pretreatment fin, described pretreatment fin
The epitaxial layer 501 of portion 500 and both sides thereof forms fin 510.
Concrete, in the present embodiment, the material of described epitaxial layer 501 is silicon.Other realities in the present invention
Executing in example, the material of described epitaxial layer 501 can also is that SiGe or carborundum.Described epitaxial layer 501
Can be the silicon of monolayer, SiGe or silicon carbide structure, it is also possible to formed many by the material that multilamellar is different
Rotating fields, such as, first at described one layer of SiGe of pretreatment fin sidewall growth, then at described SiGe
Superficial growth silicon carbide layer.Form silicon germanide layer and be favorably improved the tensile stress of channel region, improve raceway groove
The mobility of interior electronics, it is adaptable to NMOS；And silicon carbide layer is favorably improved the compressive stress of channel region,
The mobility in hole in raising raceway groove, it is adaptable to PMOS.In specific embodiment, can be for inhomogeneity
The MOS of type, adjusts the structure and material of epitaxial layer, it is thus achieved that suitably stress.The width of described fin 510
Degree is more than 30nm.
Refer to Figure 19, be developed across and cover the first channel region of fin 510 and firmly covering of top thereof
The pseudo-grid 600 of film layer 201.
Concrete, the material of dummy gate 600 is polysilicon.First channel region of described fin is positioned at
The middle part of fin.Described form pseudo-grid technique be: substrate surface formed one layer cover fin and
Its top hard mask layer and the polysilicon layer of side wall, and planarized；Again in polysilicon layer surface shape
Become cover described first channel region mask layer, with described mask layer for mask etching polysilicon layer after,
Expose source electrode and the drain region at fin two ends, and the hard mask layer at top and side wall.In the present invention
Other embodiments in, if use body silicon or other materials as Semiconductor substrate, formed fin it
After, before forming pseudo-grid, form a layer insulating at substrate surface, as the grid being subsequently formed and lining
Insulating barrier at the end.
Refer to Figure 20, form source electrode and the dielectric layer 601 of drain electrode covering fin in pseudo-grid 600 both sides.
Concrete, the material of described dielectric layer includes silicon oxide, silicon nitride or silicon oxynitride.Formed described
The method of dielectric layer 601 is: utilize chemical vapor deposition method, at pseudo-grid both sides deposits dielectric materials,
After covering source electrode and the drain electrode of described fin, planarized, formed dielectric layer, described dielectric layer
Height flushes with pseudo-grid height.Described dielectric layer covers source electrode and the drain electrode of fin, makes source and drain in follow-up work
Being protected in skill, size will not change.
Refer to Figure 21, remove pseudo-grid 600(and refer to Figure 20), expose the first channel region of fin
And the hard mask layer at top.
Refer to Figure 22, for removing the top view after pseudo-grid 600.
Refer to Figure 23, for Figure 22 sectional view on BB ' direction, described first channel region 502 is wide
Degree is more than hard mask layer 201 width.Described first channel region is positioned at the middle part of fin, not by dielectric layer
601(refer to Figure 22) region that covers, including epitaxial layer and the pretreatment fin of part of part.
Refer to Figure 24, etch described first channel region 502(and refer to Figure 23) so that it is width reduces,
Form the second channel region 503.
Concrete, in the present embodiment, described etching the first channel region 502, form the second channel region
The method of 503 is wet-etching technology.Dry etching work can also be used in other embodiments of the invention
Skill, the plasma direction of described dry etching, in horizontal plane, is perpendicular to the sidewall of described channel region.
The width of the second channel region 503 of described formation is more than 10nm.In other embodiments of the invention,
The first channel region described in dry etch process vertical etch can be used using hard mask layer 201 as mask
Territory, forms the second channel region 503.The width of described second channel region 503 is more than 10nm.
Refer to Figure 25, dielectric layer 601 towards fin the second channel region sidewall surfaces formed second
Side wall 602.
Concrete, the material of described second side wall be silicon nitride, amorphous carbon, boron nitride, silicon oxynitride,
Other suitable materials such as fire sand or siloxicon.
Described second side wall can make up during performing etching the first channel region for media of both sides
The damage that layer 601 is caused, keeps the smooth of surface, improves the deposition quality of the grid being subsequently formed.
Refer to Figure 26, be developed across and cover the grid 700 of the second channel region.
Concrete, in the present embodiment, described grid 700 is high-k/metal gate, and forming method is: first
Depositing one layer of high-k dielectric layer, described high K medium can be HfO2、La2O3, HfSiON or HfAlO2Deng
High-g value.Again at described high-K dielectric layer forming metal layer on surface, planarize afterwards.At its of the present invention
In his embodiment, described grid 700 can also be polysilicon gate.In other embodiments of the invention,
Described hard mask layer 201(can also be refer to Figure 25) forming grid 700 afterwards.
In the present embodiment, before forming grid, source electrode and drain region are carried out plasma injection.
In the present embodiment, it is initially formed pretreatment fin, then grows extension in the both sides of described pretreatment fin
Layer forms the fin of bigger width.Utilize dielectric layer that source and drain areas is carried out covering protection, then to fin
First channel region performs etching, its width thinning, forms source and drain size big, and channel region size is little
Fin.In the case of meeting channel region size, improve the size of source and drain, thus reduce source and drain electricity
Resistance, improves the driving electric current of transistor.Further, the source and drain of described transistor is protected by dielectric layer, will not
And form short circuit between the grid of later stage formation.Further, described epitaxial layer can be the germanium of single or multiple lift
The material such as SiClx, carborundum, produces stress effect to channel region, improves the migration of raceway groove carriers
Rate.Such as, forming described epitaxial layer is silicon germanide layer, is favorably improved the tensile stress of channel region, carries
The mobility of electronics in high raceway groove, is favorably improved the performance of NMOS；Epitaxial layer is that silicon carbide layer then has
Helping improve the compressive stress of channel region, in raising raceway groove, the mobility in hole, is favorably improved PMOS
Performance.The structure and material of epitaxial layer for different types of MOS transistor, can be adjusted, it is thus achieved that
Suitably stress.
Above by the explanation of embodiment, professional and technical personnel in the field should be able to be made to be more fully understood that the present invention,
And can reproduce and use the present invention.Those skilled in the art can according to principle specifically described herein
To above-described embodiment as various changes and modifications to be without departing from the spirit and scope of the present invention
Obviously.Therefore, the present invention should not be construed as being limited to above-described embodiment shown in this article, its
Protection domain should be defined by appending claims.
Claims (15)
1. the forming method of a fin formula field effect transistor, it is characterised in that including:
Semiconductor substrate is provided；
Hard mask layer is formed at semiconductor substrate surface；
Being formed after hard mask layer, form the first side wall in the both sides of described hard mask layer, with described firmly
The side wall of mask layer and both sides thereof, as mask, etch semiconductor substrates, forms fin；Or with described
Hard mask layer is mask, after etching described Semiconductor substrate formation pretreatment fin, then at described pre-place
Reason fin both sides grown epitaxial layer, forms fin；
Pseudo-grid, the first channel region of dummy gate span and cover fin is formed at semiconductor substrate surface
And the hard mask layer at top, described first channel region is positioned at the middle part of fin, described first channel region
Both sides, territory are source electrode and the drain electrode of fin；
Form source electrode and the dielectric layer of drain electrode covering fin in pseudo-grid both sides, described dielectric layer surface is with pseudo-
Grid surface flushes；
Remove pseudo-grid, expose the first channel region and the hard mask layer at top thereof of fin；
Etch the both sides of described first channel region so that it is width reduces, and forms the second channel region, institute
The width stating the second channel region is identical with the width of hard mask layer；
It is developed across and covers the grid of the second channel region；
Described forming method also includes: being formed after the second channel region, described dielectric layer towards
The sidewall surfaces of the second channel region forms the second side wall.
The forming method of fin formula field effect transistor the most according to claim 1, it is characterised in that described
The material of the first side wall is silicon nitride, amorphous carbon, boron nitride, silicon oxynitride, fire sand or oxygen carbon
SiClx.
The forming method of fin formula field effect transistor the most according to claim 1, it is characterised in that described
The bottom width of the first side wall is more than 2nm.
The forming method of fin formula field effect transistor the most according to claim 1, it is characterised in that described
The method carving formation the second channel region is: removes described first side wall, then uses wet processing or dry
Method etching technics etches the both sides of described first channel region so that it is width reduces, described dry etching work
Skill, with hard mask layer as mask, carries out vertical etch.
The forming method of fin formula field effect transistor the most according to claim 1, it is characterised in that described
Epitaxial layer is single or multiple lift structure.
The forming method of fin formula field effect transistor the most according to claim 1, it is characterised in that described
The material of epitaxial layer is silicon, SiGe or carborundum.
The forming method of fin formula field effect transistor the most according to claim 1, it is characterised in that formed
The method of the second channel region is: use wet etching or dry etch process to etch described first channel region
The both sides in territory so that it is width reduces, the most described first raceway groove in plasma direction of described dry etching
The sidewall in region.
The forming method of fin formula field effect transistor the most according to claim 1, it is characterised in that described
The thickness of hard mask layer is more than 10nm.
The forming method of fin formula field effect transistor the most according to claim 1, it is characterised in that described
The width of fin is more than 30nm.
The forming method of fin formula field effect transistor the most according to claim 1, it is characterised in that described
The width of the second channel region is more than 10nm.
The forming method of 11. fin formula field effect transistors according to claim 1, it is characterised in that described
The material of hard mask layer is silicon nitride, amorphous carbon, boron nitride, silicon oxynitride, fire sand or oxygen carbon
SiClx.
The forming method of 12. fin formula field effect transistors according to claim 1, it is characterised in that described
The material of pseudo-grid is polysilicon.
The forming method of 13. fin formula field effect transistors according to claim 1, it is characterised in that described
The material of dielectric layer includes silicon oxide, silicon nitride or silicon oxynitride.
The forming method of 14. fin formula field effect transistors according to claim 1, it is characterised in that described
The material of the second side wall is silicon nitride, amorphous carbon, boron nitride, silicon oxynitride, fire sand or oxygen carbon
SiClx.
The forming method of 15. fin formula field effect transistors according to claim 1, it is characterised in that described
Grid is high-K metal gate or polysilicon gate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210477241.6A CN103839814B (en) | 2012-11-21 | 2012-11-21 | The forming method of fin formula field effect transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210477241.6A CN103839814B (en) | 2012-11-21 | 2012-11-21 | The forming method of fin formula field effect transistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103839814A CN103839814A (en) | 2014-06-04 |
| CN103839814B true CN103839814B (en) | 2016-12-21 |
Family
ID=50803201
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201210477241.6A Active CN103839814B (en) | 2012-11-21 | 2012-11-21 | The forming method of fin formula field effect transistor |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103839814B (en) |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110277316B (en) * | 2018-03-13 | 2023-06-02 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| CN109003902B (en) * | 2018-08-01 | 2021-07-27 | 中国科学院微电子研究所 | Semiconductor structure and preparation method thereof |
| CN117038460A (en) * | 2019-01-21 | 2023-11-10 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| CN111509045B (en) * | 2019-01-31 | 2023-09-15 | 中芯国际集成电路制造(上海)有限公司 | Fin field effect transistor and forming method thereof |
| CN114127949A (en) * | 2021-02-07 | 2022-03-01 | 深圳市汇顶科技股份有限公司 | Field effect transistor and method for manufacturing the same |
| CN112864239B (en) * | 2021-03-17 | 2022-04-26 | 长江存储科技有限责任公司 | Field effect transistor and preparation method thereof |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6762483B1 (en) * | 2003-01-23 | 2004-07-13 | Advanced Micro Devices, Inc. | Narrow fin FinFET |
| US6764884B1 (en) * | 2003-04-03 | 2004-07-20 | Advanced Micro Devices, Inc. | Method for forming a gate in a FinFET device and thinning a fin in a channel region of the FinFET device |
| US7045401B2 (en) * | 2003-06-23 | 2006-05-16 | Sharp Laboratories Of America, Inc. | Strained silicon finFET device |
| US6812119B1 (en) * | 2003-07-08 | 2004-11-02 | Advanced Micro Devices, Inc. | Narrow fins by oxidation in double-gate finfet |
| US7087471B2 (en) * | 2004-03-15 | 2006-08-08 | International Business Machines Corporation | Locally thinned fins |
| CN101315892A (en) * | 2007-05-29 | 2008-12-03 | 南亚科技股份有限公司 | Method for manufacturing self-alignement fin-shaped fieldistor device |
-
2012
- 2012-11-21 CN CN201210477241.6A patent/CN103839814B/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| CN103839814A (en) | 2014-06-04 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US10510853B2 (en) | FinFET with two fins on STI | |
| US10991795B2 (en) | Semiconductor device and manufacturing method thereof | |
| US9153657B2 (en) | Semiconductor devices comprising a fin | |
| KR100634372B1 (en) | Semiconductor devices and methods for forming the same | |
| CN103839814B (en) | The forming method of fin formula field effect transistor | |
| US9202920B1 (en) | Methods for forming vertical and sharp junctions in finFET structures | |
| TWI642181B (en) | Iii-v gate all around semiconductor device and method for manufaturing the same | |
| US9461150B2 (en) | Method for fabricating semiconductor device with fin-shaped structure | |
| US11038039B2 (en) | Method of forming a semiconductor device | |
| KR20140112354A (en) | Ditches near semiconductor fins and methods for forming the same | |
| CN104124172B (en) | Fin formula field effect transistor and forming method thereof | |
| US10411118B2 (en) | Semiconductor structures and fabrication methods thereof | |
| CN106531803A (en) | Enhanced volume control by recess profile control | |
| CN105336624B (en) | The manufacturing method of fin formula field effect transistor and its false grid | |
| CN108133955B (en) | NMOS transistor structure and forming method thereof | |
| CN103123899B (en) | FinFET manufacture method | |
| CN103730367B (en) | Semiconductor device manufacturing method | |
| TWI626694B (en) | Methods of forming strained channel regions on finfet devices by performing a heating process on a heat-expandable material | |
| CN103426757B (en) | The formation method of Ω shape fin formula field effect transistor | |
| CN106784005A (en) | A kind of fin formula field effect transistor of improvement and preparation method thereof | |
| CN103000505B (en) | The formation method of multi-gate device | |
| CN102956701B (en) | Structure and forming method of fin type field-effect tube | |
| KR20060005041A (en) | Method for manufacturing a finfet | |
| CN115692461A (en) | Semiconductor structure and forming method thereof | |
| CN116978947A (en) | Semiconductor structure and forming method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |