CN103839814A - Method for forming fin field effect transistor - Google Patents
Method for forming fin field effect transistor Download PDFInfo
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- CN103839814A CN103839814A CN201210477241.6A CN201210477241A CN103839814A CN 103839814 A CN103839814 A CN 103839814A CN 201210477241 A CN201210477241 A CN 201210477241A CN 103839814 A CN103839814 A CN 103839814A
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- 238000000034 method Methods 0.000 title claims abstract description 77
- 230000005669 field effect Effects 0.000 title claims abstract description 36
- 239000000758 substrate Substances 0.000 claims abstract description 45
- 239000004065 semiconductor Substances 0.000 claims abstract description 41
- 238000005530 etching Methods 0.000 claims abstract description 36
- 230000015572 biosynthetic process Effects 0.000 claims description 49
- 239000000463 material Substances 0.000 claims description 47
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 25
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- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 17
- 230000008569 process Effects 0.000 claims description 17
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 14
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 14
- 229920005591 polysilicon Polymers 0.000 claims description 14
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 14
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims description 12
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- 238000001312 dry etching Methods 0.000 claims description 6
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- 238000001039 wet etching Methods 0.000 claims description 5
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
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Abstract
A method for forming a fin field effect transistor comprises the following steps: providing a semiconductor substrate; forming a hard mask layer on the surface of the semiconductor substrate; etching the semiconductor substrate by using the hard mask layer as a mask to form a fin part; forming a dummy gate on the surface of the semiconductor substrate, wherein the dummy gate is across and covers a first channel region of the fin part and the hard mask layer at the top of the first channel region; forming a dielectric layer covering the source and the drain of the fin part on the two sides of the dummy gate; removing the dummy gate to expose the first channel region of the fin part and the hard mask layer at the top of the first channel region; etching the first channel region to reduce the width thereof to form a second channel region; and forming a gate which is across and covers the second channel region. The method for forming a fin field effect transistor can reduce the resistances of the source and the drain and improve the driving current of a transistor.
Description
Technical field
The present invention relates to technical field of semiconductors, particularly a kind of formation method of fin formula field effect transistor.
Background technology
Along with the development of semiconductor process techniques, process node reduces gradually, and rear grid (gate-last) technique is widely applied, and to obtain desirable threshold voltage, improves device performance.But in the time that the characteristic size (CD, Critical Dimension) of device further declines, even if the field effect transistor that after adopting, grid technique is made also cannot meet the demand to device performance, multiple-grid device has acquired widely and has paid close attention to.
Fin formula field effect transistor (Fin FET) is a kind of common multiple-grid device, and Fig. 1 shows a kind of fin of fin formula field effect transistor and the perspective view of grid structure of prior art.As shown in Figure 1, comprising: Semiconductor substrate 10, is formed with the fin 14 of protrusion in described Semiconductor substrate 10; Dielectric layer 11, covers the part of the surface of described Semiconductor substrate 10 and the sidewall of fin 14; Grid structure 12, across on described fin 14 and cover top and the sidewall of described fin 14, grid structure 12 comprises gate dielectric layer (not shown) and is positioned at the gate electrode (not shown) on gate dielectric layer.The sidewall constituting channel district of the top of the fin 14 contacting with grid structure 12 and both sides, therefore, Fin FET has multiple grid, and this is conducive to increase drive current, improves device performance.
But along with reducing of fin size, also corresponding reducing of the source and drain areas area at fin two ends, causes the contact resistance of source electrode and drain electrode to increase, and causes drive current to decline, thereby affects the performance of device.In formation technology, form fin transistor and can form side wall at the sidewall of transistorized gate lateral wall and source electrode and drain electrode afterwards.A kind of method of existing reduction source electrode and drain resistance is that the side wall of removal source electrode and drain electrode both sides, then improves the area of source and drain areas to source electrode and drain surface formation silicon epitaxial layers, thereby reduce source ohmic leakage.But, this method, on the one hand, can be because bottom side wall is removed not thorough, can hinder the formation of source electrode and drain surface epitaxial loayer, on the other hand, also can get rid of the part side wall of gate lateral wall simultaneously at the side wall of removing source electrode and drain electrode sidewall, cause forming epitaxial loayer on source electrode, drain and gate surface simultaneously, in the time that the epitaxial loayer on source electrode, drain and gate reaches certain thickness, can cause the bridging of epitaxial loayer between source electrode, drain and gate, cause short circuit between source electrode, drain and gate.
More structures about fin formula field effect transistor and formation method please refer to the United States Patent (USP) that the patent No. is " US7868380B2 ".
Summary of the invention
The problem that the present invention solves is to provide the formation method of fin formula field effect transistor, and the formation method of described fin formula field effect transistor can reduce the resistance of source electrode and drain electrode, improves transistorized drive current.
For addressing the above problem, the invention provides a kind of formation method of fin formula field effect transistor, comprising: Semiconductor substrate is provided; Form hard mask layer at semiconductor substrate surface; Taking described hard mask layer as mask, etching semiconductor substrate, forms fin; Form pseudo-grid at semiconductor substrate surface, described pseudo-grid across and cover the first channel region of fin and the hard mask layer at top thereof, described the first channel region is positioned at the middle part of fin, source electrode and drain electrode that described the first channel region both sides are fin; Form in pseudo-grid both sides and cover the source electrode of fin and the dielectric layer of drain electrode, described dielectric layer surface and pseudo-grid flush; Remove pseudo-grid, expose the first channel region of fin and the hard mask layer at top thereof; The both sides of the first channel region described in etching, reduce its width, form the second channel region; Form across and cover the grid of the second channel region.
Preferably, the method for described formation fin comprises: forming after hard mask layer, form the first side wall in the both sides of described hard mask layer, using the side wall of described hard mask layer and both sides thereof as mask, etching semiconductor substrate, forms fin.
Preferably, the material of described the first side wall is silicon nitride, amorphous carbon, boron nitride, silicon oxynitride, fire sand or siloxicon.
Preferably, the bottom width of described the first side wall is greater than 2nm.
Preferably, the method of described formation the second channel region is: remove described the first side wall, then adopt the both sides of the first channel region described in wet processing or dry etch process etching, its width is reduced, described dry etch process, taking hard mask layer as mask, is carried out vertical etching.
Preferably, the method for described formation fin comprises: taking described hard mask layer as mask, after Semiconductor substrate forms preliminary treatment fin described in etching, then at described preliminary treatment fin both sides grown epitaxial layer, form fin.
Preferably, described epitaxial loayer is single or multiple lift structure.
Preferably, the material of described epitaxial loayer is silicon, SiGe or carborundum.
Preferably, the method of described formation the second channel region is: the both sides of the first channel region described in employing wet etching or dry etch process etching, its width is reduced, the plasma direction of described dry etching in horizontal plane, the sidewall of vertical described the first channel region.
Preferably, the thickness of described hard mask layer is greater than 10nm.
Preferably, the width of described fin is greater than 30nm.
Preferably, the width of described the second channel region is greater than 10nm.
Preferably, the material of described hard mask layer is silicon nitride, amorphous carbon, boron nitride, silicon oxynitride, fire sand or siloxicon.
Preferably, the material of described pseudo-grid is polysilicon.
Preferably, the material of described dielectric layer comprises silica, silicon nitride or silicon oxynitride.
Preferably, also comprise: after forming the second channel region, form the second side wall in the sidewall surfaces towards the second channel region of described dielectric layer.
Preferably, the material of described the second side wall is silicon nitride, amorphous carbon, boron nitride, silicon oxynitride, fire sand or siloxicon.
Preferably, described grid is high-K metal grid or polysilicon gate.
Compared with prior art, the present invention has the following advantages:
Technical scheme of the present invention, after semiconductor substrate surface forms fin, form pseudo-grid by the first channel region at fin, after pseudo-grid both sides form the covering source electrode of fin and the medium of drain electrode, remove pseudo-grid, expose the first channel region of fin, by the width of etching attenuate the first channel region, form the second channel region.It is large that width is leaked in final formation source, the fin that channel region width is little.Technical scheme of the present invention is by after first forming the fin that width is larger; thereby by the dielectric layer that covers source electrode and drain electrode, source leakage is protected the size that leak in source is remained unchanged when the channel region of fin is carried out to attenuate; so in obtaining the width of the channel region needing; improve the size of source electrode and drain electrode; the resistance that effectively reduces transistor source and drain electrode, improves transistorized drive current.
Further, by preliminary treatment fin both sides grown epitaxial layer, thereby obtain the larger fin of width.Described epitaxial loayer can be silicon, SiGe or the carborundum of individual layer, also can have sandwich construction, and the material of each layer of adjacent monolayer is different.Described epitaxial loayer can produce effect of stress to channel region, improves the mobility of charge carrier in raceway groove.If the epitaxial loayer forming is silicon germanide layer, contribute to improve the tensile stress of channel region, improve the mobility of electronics in raceway groove, contribute to improve the performance of NMOS; Epitaxial loayer is the compression that silicon carbide layer contributes to improve channel region, improves the mobility in hole in raceway groove, contributes to improve the performance of PMOS.Can, for dissimilar MOS transistor, adjust the structure and material of epitaxial loayer, obtain suitable stress.Described technical scheme, in reducing source ohmic leakage, can also improve transistorized carrier mobility.
Brief description of the drawings
Fig. 1 is the schematic diagram of existing fin transistor;
Fig. 2 to Figure 16 is the schematic diagram that forms fin formula field effect transistor in the first embodiment of the present invention;
Figure 17 to Figure 26 is the schematic diagram that forms fin formula field effect transistor in the second embodiment of the present invention.
Embodiment
As described in the background art, existing fin formula field effect transistor, along with reducing of fin size, also corresponding reducing of the source and drain areas area at fin two ends, causes the contact resistance that leak in source to increase, and drive current can decline, thereby affects the performance of device.In prior art, generally forming after fin formula field effect transistor, source is leaked to the size of carrying out epitaxial growth and improve source and drain areas, and this method exists that deposition quality is not high, the easily problem of short circuit is leaked between grid in source.
For addressing the above problem, the present invention proposes a kind of method that forms fin formula field effect transistor, first form larger-size fin, the width of the channel region to fin carries out attenuate again, in the channel region that obtains reduced size, obtain the source and drain areas of large-size, thereby reduce the resistance of source electrode and drain electrode.
For above-mentioned purpose of the present invention, feature and advantage can more be become apparent, below in conjunction with accompanying drawing, the specific embodiment of the present invention is described in detail.Described embodiment is only a part for embodiment of the present invention, instead of they are whole.Describing in detail when the embodiment of the present invention, for ease of explanation, schematic diagram can be disobeyed general ratio and be done local amplification, and described schematic diagram is example, and it should not limit the scope of the invention at this.In addition in actual fabrication, should comprise, the three-dimensional space of length, width and the degree of depth.According to described embodiment, those of ordinary skill in the art is obtainable all other execution modes under the prerequisite without creative work, all belong to protection scope of the present invention.Therefore the present invention is not subject to the restriction of following public concrete enforcement.
The first embodiment
Please refer to Fig. 2, Semiconductor substrate 110 is provided.
The material of described Semiconductor substrate 110 comprises the semi-conducting materials such as silicon, germanium, SiGe, GaAs, can be that body material can be also that composite construction is as silicon-on-insulator or germanium on insulator.Those skilled in the art can select according to the semiconductor device forming in Semiconductor substrate 110 type of described Semiconductor substrate 110, and therefore the type of described Semiconductor substrate should not limit the scope of the invention.
In the present embodiment, the material of the Semiconductor substrate 110 adopting is silicon-on-insulator, comprises layer-of-substrate silicon 100, intermediate oxidation silicon layer 101 and monocrystalline silicon top layer 102.
Please refer to Fig. 3, form hard mask material layer 200 on Semiconductor substrate 110 surfaces.
Concrete, by chemical vapor deposition method at described Semiconductor substrate 110 surface deposition one deck hard mask material layers.The material of described hard mask material layer is other suitable materials such as silicon nitride, amorphous carbon, boron nitride, silicon oxynitride, fire sand or siloxicon.
Please refer to Fig. 4, form hard mask layer 201 at semiconductor substrate surface.
Concrete, hard mask material layer 200(please refer to Fig. 3 described in etching), form hard mask layer 201, the thickness of described hard mask layer 201 is greater than 10nm.
Please refer to Fig. 5, form the first side wall 202 in described hard mask layer 201 both sides.
Concrete, the material of described the first side wall 202 is other suitable materials such as silicon nitride, amorphous carbon, boron nitride, silicon oxynitride, fire sand or siloxicon.The formation method of described the first side wall 202 is: adopt chemical vapor deposition method, form the first spacer material layer that covers semiconductor substrate surface and hard mask layer surface; Utilize plasma etch process, vertically the first spacer material layer described in etching, until expose hard mask layer 201 top surfaces and semiconductor substrate surface, forms the first side wall 202 in hard mask layer 201 both sides.The bottom width of described the first side wall is greater than 2nm.The bottom overall width of described the first side wall and hard mask layer is greater than 30nm.In other embodiments of the invention, also can not form described the first side wall, only form hard mask layer, and make the width of hard mask layer be greater than 30nm.
Please refer to Fig. 6, using the first side wall 202 of described hard mask layer 201 and both sides thereof as mask, etching semiconductor substrate, forms fin 300.
Concrete, in the present embodiment, adopt the monocrystalline silicon top layer 102(of dry etch process etching semiconductor substrate to please refer to Fig. 5), form fin 300, the width of the fin 300 of described formation is greater than 30nm.In other embodiments of the invention, if do not form the first side wall 202, directly taking hard mask layer 201 as mask, etching semiconductor substrate, forms the fin that width is greater than 30nm.
Please refer to Fig. 7, form across and cover the pseudo-grid 400 of the first channel region of fin and the hard mask layer 201 at top and the first side wall 202.
Concrete, the material of described pseudo-grid 400 is polysilicon.The first channel region of described fin is positioned at the middle part of fin.The technique of the pseudo-grid of described formation is: form the polysilicon layer of one deck covering fin and top hard mask layer and side wall at substrate surface, and by its planarization; Form on polysilicon layer surface the mask layer that covers described the first channel region again, after mask etching polysilicon layer, expose source electrode and the drain region at fin two ends taking described mask layer, and hard mask layer and the side wall at source electrode and top, drain region.In other embodiments of the invention, if adopt body silicon or other materials as Semiconductor substrate, after forming fin, before forming pseudo-grid, form a layer insulating at substrate surface, as the insulating barrier between grid and the substrate of follow-up formation.
Please refer to Fig. 8, form and cover the source electrode of fin and the dielectric layer of drain electrode 401 in pseudo-grid 400 both sides.
Concrete, the material of described dielectric layer is silicon nitride or silicon oxynitride.The method that forms described dielectric layer 401 is: utilize chemical vapor deposition method, at pseudo-grid both sides deposition medium material, after covering the source electrode and drain electrode of described fin, by its planarization, form dielectric layer 401, the height of described dielectric layer 401 flushes with the height of pseudo-grid 400.Described dielectric layer 401 covers source electrode and the drain electrode of fin, source is leaked and in subsequent technique, be protected, and size can not change.
Please refer to Fig. 9, remove pseudo-grid 400(and please refer to Fig. 8), expose the first channel region of fin and the hard mask layer at top and the first side wall.
Concrete, the technique of the pseudo-grid of described removal is wet etching or dry etching.
Please refer to Figure 10, for removing the vertical view of the Fig. 9 after pseudo-grid.
Described channel region (not shown) is positioned at the unlapped zone line of dielectric layer 401, is covered by the first side wall 202 and hard mask layer 201.
Please refer to Figure 11, for removing after pseudo-grid, along the generalized section of AA ' direction.
Wherein the first channel region 301 of fin is positioned on silicon oxide layer 101, is covered by hard mask layer 201 and the first side wall 202.
Please refer to Figure 12, the first channel region 301(please refer to Figure 11 described in etching), its width is reduced, form the second channel region 302.
Concrete, in the present embodiment, the first channel region 301 described in etching, the method that forms the second channel region 302 is wet-etching technology.Also can adopt in other embodiments of the invention dry etch process, the plasma direction of described dry etching is in horizontal plane, perpendicular to the sidewall of described channel region.The width of the second channel region 302 of described formation is greater than 10nm.
In other embodiments of the invention, also can first remove described the first side wall 202, expose the part that the first channel region is not covered by hard mask layer 201, again using hard mask layer 201 as mask, the first channel region described in the vertical etching of employing dry etch process, forms the second channel region 302.In other embodiments of the invention, can after forming hard mask layer 201, not form the first side wall yet, in such situation, can adopt the first channel region described in wet processing or dry etch process etching, the plasma direction of described dry etching is in horizontal plane, perpendicular to the sidewall of described channel region.
Please refer to Figure 13, remove the first side wall 202(and please refer to Figure 12).
Please refer to Figure 14, please refer to Figure 12 for removing the first side wall 202() vertical view afterwards.
Described the second channel region 302(please refer to Figure 13) top only has hard mask layer 201.
Please refer to Figure 15, form the second side wall 402 at dielectric layer 401 towards the sidewall surfaces of fin the second channel region.
Concrete, the material of described the second side wall is other suitable materials such as silicon nitride, amorphous carbon, boron nitride, silicon oxynitride, fire sand or siloxicon.
Described the second side wall can make up the damage causing for media of both sides layer 401 in the first channel region is carried out to etching process, keeps the smooth of surface, improves the deposition quality of the grid of follow-up formation.
Please refer to Figure 16, form across and cover the grid 500 of the second channel region.
Concrete, in the present embodiment, described grid 500 is high-k/metal gate, formation method is: first deposit one deck high K medium layer, described high K medium can be HfO
2, La
2o
3, HfSiON or HfAlO
2contour k material.Again in described high K dielectric layer forming metal layer on surface, planarization afterwards.In other embodiments of the invention, described grid 500 can be also polysilicon gate.In other embodiments of the invention, also described hard mask layer 201(can be please refer to Figure 15) form again grid 500 after removing.
In the present embodiment, form grid and before source electrode and drain region are carried out to plasma injection.
In the present embodiment, after forming the fin of larger width, utilize dielectric layer to carry out covering protection to source and drain areas, then the first channel region of fin is carried out to etching, its width of attenuate, formation source leakage size is large, the fin that channel region size is little.In the situation that meeting channel region size, improve the size that leak in source, thereby reduced source ohmic leakage, improve transistorized drive current.And described transistorized source is leaked and is protected by dielectric layer, not can and the grid that forms of later stage between form short circuit.
The second embodiment
The present embodiment also provides the method for another kind of formation fin formula field effect transistor.
Please refer to Figure 17, adopt the method identical with the first embodiment, after substrate surface forms hard mask layer 201, etching semiconductor substrate forms preliminary treatment fin 500.
Please refer to Figure 18, at the sidewall grown epitaxial layer 501 of described preliminary treatment fin, the epitaxial loayer 501 of described preliminary treatment fin 500 and both sides thereof forms fin 510.
Concrete, in the present embodiment, the material of described epitaxial loayer 501 is silicon.In other embodiments of the invention, the material of described epitaxial loayer 501 can also be SiGe or carborundum.Silicon, SiGe or silicon carbide structure that described epitaxial loayer 501 can be individual layer, the sandwich construction that also can be formed by the different material of multilayer, for example, first at described preliminary treatment fin sidewall growth one deck SiGe, then at described SiGe superficial growth silicon carbide layer.Form the tensile stress that silicon germanide layer contributes to improve channel region, improve the mobility of electronics in raceway groove, be applicable to NMOS; And silicon carbide layer contributes to improve the compression of channel region, improve the mobility in hole in raceway groove, be applicable to PMOS.In specific embodiment, can, for dissimilar MOS, adjust the structure and material of epitaxial loayer, obtain suitable stress.The width of described fin 510 is greater than 30nm.
Please refer to Figure 19, form across and cover the pseudo-grid 600 of the first channel region of fin 510 and the hard mask layer 201 at top thereof.
Concrete, the material of described pseudo-grid 600 is polysilicon.The first channel region of described fin is positioned at the middle part of fin.The technique of the pseudo-grid of described formation is: form the polysilicon layer of one deck covering fin and top hard mask layer and side wall at substrate surface, and by its planarization; Form on polysilicon layer surface the mask layer that covers described the first channel region again, after mask etching polysilicon layer, expose source electrode and the drain region at fin two ends taking described mask layer, and the hard mask layer at top and side wall.In other embodiments of the invention, if adopt body silicon or other materials as Semiconductor substrate, after forming fin, before forming pseudo-grid, form a layer insulating at substrate surface, as the insulating barrier between grid and the substrate of follow-up formation.
Please refer to Figure 20, form and cover the source electrode of fin and the dielectric layer of drain electrode 601 in pseudo-grid 600 both sides.
Concrete, the material of described dielectric layer comprises silica, silicon nitride or silicon oxynitride.The method that forms described dielectric layer 601 is: utilize chemical vapor deposition method, at pseudo-grid both sides deposition medium material, after covering the source electrode and drain electrode of described fin, by its planarization, form dielectric layer, the height of described dielectric layer flushes with pseudo-grid height.Described dielectric layer covers source electrode and the drain electrode of fin, source is leaked and in subsequent technique, be protected, and size can not change.
Please refer to Figure 21, remove pseudo-grid 600(and please refer to Figure 20), expose the first channel region of fin and the hard mask layer at top thereof.
Please refer to Figure 22, for removing pseudo-grid 600 vertical view afterwards.
Please refer to Figure 23, is the cutaway view of Figure 22 in BB ' direction, and described the first channel region 502 width are greater than hard mask layer 201 width.Described the first channel region is positioned at the middle part of fin, not please refer to Figure 22 by dielectric layer 601() cover region, comprise part epitaxial loayer and part preliminary treatment fin.
Please refer to Figure 24, the first channel region 502(please refer to Figure 23 described in etching), its width is reduced, form the second channel region 503.
Concrete, in the present embodiment, described etching the first channel region 502, the method that forms the second channel region 503 is wet-etching technology.Also can adopt in other embodiments of the invention dry etch process, the plasma direction of described dry etching is in horizontal plane, perpendicular to the sidewall of described channel region.The width of the second channel region 503 of described formation is greater than 10nm.In other embodiments of the invention, can be using hard mask layer 201 as mask, adopt the first channel region described in the vertical etching of dry etch process, form the second channel region 503.The width of described the second channel region 503 is greater than 10nm.
Please refer to Figure 25, form the second side wall 602 at dielectric layer 601 towards the sidewall surfaces of fin the second channel region.
Concrete, the material of described the second side wall is other suitable materials such as silicon nitride, amorphous carbon, boron nitride, silicon oxynitride, fire sand or siloxicon.
Described the second side wall can make up the damage causing for media of both sides layer 601 in the first channel region is carried out to etching process, keeps the smooth of surface, improves the deposition quality of the grid of follow-up formation.
Please refer to Figure 26, form across and cover the grid 700 of the second channel region.
Concrete, in the present embodiment, described grid 700 is high-k/metal gate, formation method is: first deposit one deck high K medium layer, described high K medium can be HfO
2, La
2o
3, HfSiON or HfAlO
2contour k material.Again in described high K dielectric layer forming metal layer on surface, planarization afterwards.In other embodiments of the invention, described grid 700 can be also polysilicon gate.In other embodiments of the invention, also described hard mask layer 201(can be please refer to Figure 25) forming grid 700 afterwards.
In the present embodiment, form grid and before source electrode and drain region are carried out to plasma injection.
In the present embodiment, first form preliminary treatment fin, then form the fin of larger width at the both sides of described preliminary treatment fin grown epitaxial layer.Utilize dielectric layer to carry out covering protection to source and drain areas, then the first channel region of fin is carried out to etching, its width of attenuate, formation source leakage size is large, the fin that channel region size is little.In the situation that meeting channel region size, improve the size that leak in source, thereby reduced source ohmic leakage, improve transistorized drive current.And described transistorized source is leaked and is protected by dielectric layer, not can and the grid that forms of later stage between form short circuit.And described epitaxial loayer can be the material such as SiGe, carborundum of single or multiple lift, channel region is produced to effect of stress, improve the mobility of charge carrier in raceway groove.For example, forming described epitaxial loayer is silicon germanide layer, contributes to improve the tensile stress of channel region, improves the mobility of electronics in raceway groove, contributes to improve the performance of NMOS; Epitaxial loayer is the compression that silicon carbide layer contributes to improve channel region, improves the mobility in hole in raceway groove, contributes to improve the performance of PMOS.Can, for dissimilar MOS transistor, adjust the structure and material of epitaxial loayer, obtain suitable stress.
Above-mentioned by the explanation of embodiment, should be able to make professional and technical personnel in the field understand better the present invention, and can reproduce and use the present invention.Those skilled in the art can do not depart from the spirit and scope of the invention in the situation that to above-described embodiment do various changes according to described principle herein and amendment is apparent.Therefore, the present invention should not be understood to be limited to above-described embodiment shown in this article, and its protection range should be defined by appending claims.
Claims (18)
1. a formation method for fin formula field effect transistor, is characterized in that, comprising:
Semiconductor substrate is provided;
Form hard mask layer at semiconductor substrate surface;
Taking described hard mask layer as mask, etching semiconductor substrate, forms fin;
Form pseudo-grid at semiconductor substrate surface, described pseudo-grid across and cover the first channel region of fin and the hard mask layer at top thereof, described the first channel region is positioned at the middle part of fin, source electrode and drain electrode that described the first channel region both sides are fin;
Form in pseudo-grid both sides and cover the source electrode of fin and the dielectric layer of drain electrode, described dielectric layer surface and pseudo-grid flush;
Remove pseudo-grid, expose the first channel region of fin and the hard mask layer at top thereof;
The both sides of the first channel region described in etching, reduce its width, form the second channel region;
Form across and cover the grid of the second channel region.
2. the formation method of fin formula field effect transistor according to claim 1, it is characterized in that, the method of described formation fin comprises: after forming hard mask layer, form the first side wall in the both sides of described hard mask layer, using the side wall of described hard mask layer and both sides thereof as mask, etching semiconductor substrate, forms fin.
3. the formation method of fin formula field effect transistor according to claim 2, is characterized in that, the material of described the first side wall is silicon nitride, amorphous carbon, boron nitride, silicon oxynitride, fire sand or siloxicon.
4. the formation method of fin formula field effect transistor according to claim 2, is characterized in that, the bottom width of described the first side wall is greater than 2nm.
5. the formation method of fin formula field effect transistor according to claim 2, it is characterized in that, the method that forms the second channel region described quarter is: remove described the first side wall, then adopt the both sides of the first channel region described in wet processing or dry etch process etching, its width is reduced, described dry etch process, taking hard mask layer as mask, is carried out vertical etching.
6. the formation method of fin formula field effect transistor according to claim 1, it is characterized in that, the method of described formation fin comprises: taking described hard mask layer as mask, after described in etching, Semiconductor substrate forms preliminary treatment fin, at described preliminary treatment fin both sides grown epitaxial layer, form fin again.
7. the formation method of fin formula field effect transistor according to claim 6, is characterized in that, described epitaxial loayer is single or multiple lift structure.
8. the formation method of fin formula field effect transistor according to claim 6, is characterized in that, the material of described epitaxial loayer is silicon, SiGe or carborundum.
9. according to the formation method of the fin formula field effect transistor described in claim 1,2 or 6, it is characterized in that, the method that forms the second channel region is: the both sides of the first channel region described in employing wet etching or dry etch process etching, its width is reduced, the sidewall of vertical described first channel region of plasma direction of described dry etching.
10. the formation method of fin formula field effect transistor according to claim 1, is characterized in that, the thickness of described hard mask layer is greater than 10nm.
11. according to the formation method of the fin formula field effect transistor described in claim 1,2 or 6, it is characterized in that, the width of described fin is greater than 30nm.
12. according to the formation method of the fin formula field effect transistor described in claim 1,2 or 6, it is characterized in that, the width of described the second channel region is greater than 10nm.
The formation method of 13. fin formula field effect transistors according to claim 1, is characterized in that, the material of described hard mask layer is silicon nitride, amorphous carbon, boron nitride, silicon oxynitride, fire sand or siloxicon.
The formation method of 14. fin formula field effect transistors according to claim 1, is characterized in that, the material of described pseudo-grid is polysilicon.
The formation method of 15. fin formula field effect transistors according to claim 1, is characterized in that, the material of described dielectric layer comprises silica, silicon nitride or silicon oxynitride.
16. according to the formation method of the fin formula field effect transistor described in claim 1,2 or 6, it is characterized in that, also comprises: after forming the second channel region, form the second side wall in the sidewall surfaces towards the second channel region of described dielectric layer.
The formation method of 17. fin formula field effect transistors according to claim 16, is characterized in that, the material of described the second side wall is silicon nitride, amorphous carbon, boron nitride, silicon oxynitride, fire sand or siloxicon.
The formation method of 18. fin formula field effect transistors according to claim 1, is characterized in that, described grid is high-K metal grid or polysilicon gate.
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109003902A (en) * | 2018-08-01 | 2018-12-14 | 中国科学院微电子研究所 | A kind of semiconductor structure and preparation method thereof |
| CN110277316A (en) * | 2018-03-13 | 2019-09-24 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| CN111463276A (en) * | 2019-01-21 | 2020-07-28 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| CN111509045A (en) * | 2019-01-31 | 2020-08-07 | 中芯国际集成电路制造(上海)有限公司 | Fin field effect transistor and forming method thereof |
| CN112864239A (en) * | 2021-03-17 | 2021-05-28 | 长江存储科技有限责任公司 | Field effect transistor and preparation method thereof |
| CN114127949A (en) * | 2021-02-07 | 2022-03-01 | 深圳市汇顶科技股份有限公司 | Field effect transistor and method for manufacturing the same |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040197975A1 (en) * | 2003-01-23 | 2004-10-07 | Zoran Krivokapic | Narrow fin finfet |
| US6812119B1 (en) * | 2003-07-08 | 2004-11-02 | Advanced Micro Devices, Inc. | Narrow fins by oxidation in double-gate finfet |
| CN1674239A (en) * | 2004-03-15 | 2005-09-28 | 国际商业机器公司 | Field effect transistor and producing method thereof |
| CN1771589A (en) * | 2003-04-03 | 2006-05-10 | 先进微装置公司 | Method for forming a gate in a FinFET device and thinning a fin in a channel region of the FinFET device |
| US7045401B2 (en) * | 2003-06-23 | 2006-05-16 | Sharp Laboratories Of America, Inc. | Strained silicon finFET device |
| CN101315892A (en) * | 2007-05-29 | 2008-12-03 | 南亚科技股份有限公司 | Method for manufacturing self-alignement fin-shaped fieldistor device |
-
2012
- 2012-11-21 CN CN201210477241.6A patent/CN103839814B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040197975A1 (en) * | 2003-01-23 | 2004-10-07 | Zoran Krivokapic | Narrow fin finfet |
| CN1771589A (en) * | 2003-04-03 | 2006-05-10 | 先进微装置公司 | Method for forming a gate in a FinFET device and thinning a fin in a channel region of the FinFET device |
| US7045401B2 (en) * | 2003-06-23 | 2006-05-16 | Sharp Laboratories Of America, Inc. | Strained silicon finFET device |
| US6812119B1 (en) * | 2003-07-08 | 2004-11-02 | Advanced Micro Devices, Inc. | Narrow fins by oxidation in double-gate finfet |
| CN1674239A (en) * | 2004-03-15 | 2005-09-28 | 国际商业机器公司 | Field effect transistor and producing method thereof |
| CN101315892A (en) * | 2007-05-29 | 2008-12-03 | 南亚科技股份有限公司 | Method for manufacturing self-alignement fin-shaped fieldistor device |
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110277316A (en) * | 2018-03-13 | 2019-09-24 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| CN110277316B (en) * | 2018-03-13 | 2023-06-02 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| CN109003902A (en) * | 2018-08-01 | 2018-12-14 | 中国科学院微电子研究所 | A kind of semiconductor structure and preparation method thereof |
| CN109003902B (en) * | 2018-08-01 | 2021-07-27 | 中国科学院微电子研究所 | Semiconductor structure and preparation method thereof |
| CN111463276A (en) * | 2019-01-21 | 2020-07-28 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| CN111463276B (en) * | 2019-01-21 | 2023-09-19 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| CN111509045A (en) * | 2019-01-31 | 2020-08-07 | 中芯国际集成电路制造(上海)有限公司 | Fin field effect transistor and forming method thereof |
| CN111509045B (en) * | 2019-01-31 | 2023-09-15 | 中芯国际集成电路制造(上海)有限公司 | Fin field effect transistor and forming method thereof |
| CN114127949A (en) * | 2021-02-07 | 2022-03-01 | 深圳市汇顶科技股份有限公司 | Field effect transistor and method for manufacturing the same |
| CN112864239A (en) * | 2021-03-17 | 2021-05-28 | 长江存储科技有限责任公司 | Field effect transistor and preparation method thereof |
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