CN111509045B - Fin field effect transistor and forming method thereof - Google Patents
Fin field effect transistor and forming method thereof Download PDFInfo
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- CN111509045B CN111509045B CN201910099831.1A CN201910099831A CN111509045B CN 111509045 B CN111509045 B CN 111509045B CN 201910099831 A CN201910099831 A CN 201910099831A CN 111509045 B CN111509045 B CN 111509045B
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- 238000000034 method Methods 0.000 title claims abstract description 44
- 230000005669 field effect Effects 0.000 title claims abstract description 20
- 239000004065 semiconductor Substances 0.000 claims abstract description 64
- 239000000758 substrate Substances 0.000 claims abstract description 45
- 238000005530 etching Methods 0.000 claims abstract description 34
- 239000010410 layer Substances 0.000 claims description 121
- 239000000463 material Substances 0.000 claims description 31
- 239000011241 protective layer Substances 0.000 claims description 30
- 239000012212 insulator Substances 0.000 description 8
- 230000017525 heat dissipation Effects 0.000 description 6
- 230000000694 effects Effects 0.000 description 5
- 239000002184 metal Substances 0.000 description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 229920005591 polysilicon Polymers 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 238000010438 heat treatment Methods 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 238000000231 atomic layer deposition Methods 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 230000014509 gene expression Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 238000005019 vapor deposition process Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
- H01L29/66803—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with a step of doping the vertical sidewall, e.g. using tilted or multi-angled implants
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
- H01L23/3677—Wire-like or pin-like cooling fins or heat sinks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
- H01L29/0688—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions characterised by the particular shape of a junction between semiconductor regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
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- Thin Film Transistor (AREA)
Abstract
The invention also discloses a forming method of the fin field effect transistor, which comprises the following steps: providing a semiconductor substrate comprising a first region and a second region, wherein a fin part is formed on the semiconductor substrate; forming a first protection layer on the side wall of the fin part; etching the first protection layer on the side wall of the fin part of the second region to enable the thickness dimension of the first protection layer remained on the side wall of the fin part of the second region to be smaller than that of the first protection layer on the side wall of the fin part of the first region; forming a dielectric layer between adjacent fin parts, and exposing part of the side walls of the fin parts or part of the first protection layers of the side walls of the fin parts; and etching part of the side wall of the exposed fin part or removing the exposed first protection layer until the part of the side wall of the fin part of the second region is exposed, wherein the width dimension of the top of the fin part of the first region is l 1 The width dimension of the top of the second region fin is l 2 ，l 1 ＞l 2 . The unequal width sizes of the tops of the fin parts can effectively dissipate heat in time, and the performance of the device is improved.
Description
Technical Field
The present disclosure relates to semiconductor manufacturing, and more particularly, to a fin field effect transistor and a method for forming the same.
Background
With the continued decrease in semiconductor device size, semiconductor device cells have evolved from conventional CMOS devices to the field of fin field effect transistor (FinFET) technology. The technology nodes are at 14nm and even smaller, thus also presenting other problems. For example, when the device is operated, the device generates heat due to movement of carriers, and as the width of the fin is smaller, the generated heat is difficult to dissipate, which becomes Self-heating Effect. Heat cannot be dissipated in time, the driving current of the device is reduced due to the increase of the temperature, and the whole leakage current of the device is increased, so that the performance of the semiconductor device is affected.
Therefore, there is a need in the art for a method of forming a fin field effect transistor and a corresponding device that can effectively dissipate heat.
Disclosure of Invention
The embodiment of the invention provides a fin field effect transistor and a forming method thereof, wherein the width dimensions of the tops of fin parts in different areas are unequal, so that heat dissipation is effectively accelerated, and the performance of a semiconductor device is improved.
The invention discloses a fin field effect transistor, comprising: the semiconductor substrate comprises a first region and a second region, a fin portion is formed above the semiconductor substrate, the width dimension of the bottom of the fin portion is larger than or equal to the width dimension of the top of the fin portion, and the width dimension of the top of the fin portion of the first region is l 1 The width dimension of the top of the second region fin is l 2 ，l 1 ＞l 2 The method comprises the steps of carrying out a first treatment on the surface of the The protective layer is formed on the side wall of part of the fin part; and the dielectric layer is arranged between the adjacent fin parts.
According to one aspect of the invention, Δl=l 1 -l 2 ，0.1≤Δl:l 1 ≤0.3。
According to one aspect of the invention, the first region fin has a height dimension h 1 The height dimension of the second region fin is h 2 ，h 1 ＜h 2 。
According to one aspect of the invention, the thickness dimension of the protective layer of the first region fin sidewall is greater than the thickness dimension of the protective layer of the second region fin sidewall.
Correspondingly, the invention also discloses a forming method of the fin field effect transistor, which comprises the following steps: providing a semiconductor substrate comprising a first region and a second region, wherein a fin part is formed on the semiconductor substrate; forming a first protection layer on the side wall of the fin part; etching the first protection layer on the side wall of the fin part of the second region to enable the thickness dimension of the first protection layer remained on the side wall of the fin part of the second region to be smaller than that of the first protection layer on the side wall of the fin part of the first region; forming a dielectric layer between adjacent fin parts, and exposing part of the side walls of the fin parts or part of the first protection layers of the side walls of the fin parts; and etching part of the side wall of the exposed fin part or removing the exposed first protection layer until the part of the side wall of the fin part of the second region is exposed, wherein the width dimension of the top of the fin part of the first region is l 1 The width dimension of the top of the second region fin is l 2 ，l 1 ＞l 2 The width dimension of the bottom of the fin is greater than or equal to the width dimension of the top of the fin.
According to one aspect of the invention, Δl=l 1 -l 2 ，0.1≤Δl:l 1 ≤0.3。
According to one aspect of the present invention, the etching the first protection layer of the second region fin sidewall includes: forming an intermediate material layer covering the first region fin portion; and etching the first protection layer on the side wall of the fin part of the second region by taking the intermediate material layer as a mask.
According to one aspect of the invention, after the first protection layer of the second region fin side wall is etched, the second region fin side wall is exposed.
According to one aspect of the present invention, after etching the first protection layer on the side wall of the fin portion of the second region, before forming the dielectric layer between adjacent fin portions, the method further comprises: removing the intermediate material layer; and forming a second protection layer, wherein the second protection layer is arranged on the surface of the first protection layer or on the side wall of the exposed second region fin part.
According to one aspect of the invention, the process step of exposing a portion of the fin sidewall or a portion of the first protection layer of the fin sidewall comprises: forming a dielectric layer covering the fin part; removing part of the dielectric layer to expose part of the second protective layer; and removing the exposed second protective layer.
According to one aspect of the present invention, after etching the first protection layer on the side wall of the fin portion of the second region with the intermediate material layer as a mask, the method further includes: and continuing to etch part of the semiconductor substrate under the fin part of the second region, so that the height dimension of the fin part of the first region is smaller than that of the fin part of the second region.
Compared with the prior art, the technical scheme of the invention has the following advantages:
the width dimension of the top of the first region fin in the fin field effect transistor of the invention is l 1 The width dimension of the top of the second region fin is l 2 ，l 1 ＞l 2 . The width dimensions of the fin parts at the tops of different areas are unequal, devices in different areas can timely dissipate heat generated during respective work, the self-heating effect is effectively avoided, the electric leakage of the devices is reduced, and the semiconductors are improvedPerformance of the bulk device.
Further, the height dimension of the fin portion of the first region is h 1 The height dimension of the second region fin is h 2 ，h 1 ＜h 2 . That is, the thicknesses of the semiconductor substrates at the bottoms of the fin parts in different areas are different, and heat generated by the device can be dissipated through the semiconductor substrates, so that the heat dissipation can be further promoted through the difference of the thicknesses of the semiconductor substrates.
Correspondingly, in the method for forming the fin field effect transistor disclosed by the invention, part of the side wall of the exposed fin part is etched or the exposed first protection layer is removed until the part of the side wall of the fin part of the second region is exposed, and the width dimension of the top of the fin part of the first region is l 1 The width dimension of the top of the second region fin is l 2 ，l 1 ＞l 2 . The width dimensions formed at the tops of the fin parts in different areas are unequal, devices in different areas can timely dissipate heat generated during respective work, the self-heating effect is effectively avoided, the electric leakage of the devices is reduced, and the performance of the semiconductor device is improved.
Further, after etching the first protection layer on the side wall of the fin portion of the second region by using the intermediate material layer as a mask, the method further comprises: and continuing to etch part of the semiconductor substrate under the fin part of the second region, so that the height dimension of the fin part of the first region is smaller than that of the fin part of the second region. The thicknesses of the semiconductor substrates at the bottoms of the fin parts in different areas are different, and heat generated by the device can be dissipated through the semiconductor substrates, so that the heat dissipation can be further promoted through the difference of the thicknesses of the semiconductor substrates.
Drawings
Fig. 1-5 c are schematic structural diagrams of a finfet formation process according to an embodiment of the invention.
Detailed Description
As described above, the conventional fin field effect transistor has a problem of poor heat dissipation.
It was found that the cause of the above problems is: the width dimensions of the tops of the fin parts of different working areas are consistent, and heat generated after the device works can not be effectively dissipated.
In order to solve the problem, the invention provides the fin field effect transistor, the width dimensions of the tops of the fin parts in different areas are different, heat generated after the device works can be effectively dissipated in time, the leakage current of the device is prevented from increasing, and the performance of the semiconductor device is improved.
Various exemplary embodiments of the present invention will now be described in detail with reference to the accompanying drawings. It should be understood that the relative arrangement of parts and steps, numerical expressions and numerical values set forth in these embodiments should not be construed as limiting the scope of the present invention unless it is specifically stated otherwise.
Furthermore, it should be understood that the dimensions of the various elements shown in the figures are not necessarily drawn to actual scale, e.g., the thickness or width of some layers may be exaggerated relative to other layers for ease of description.
The following description of the exemplary embodiment(s) is merely illustrative, and is in no way intended to limit the invention, its application, or uses.
Techniques, methods, and apparatus known to one of ordinary skill in the relevant art may not be discussed in detail, but where applicable, should be considered part of the present specification.
It should be noted that like reference numerals and letters refer to like items in the following figures, and thus once an item is defined or illustrated in one figure, no further discussion thereof will be necessary in the description of the subsequent figures.
Referring to fig. 1, a fin portion 110 is formed on a semiconductor substrate 100, and a first protection layer 120 is formed on a sidewall of the fin portion 110.
The semiconductor substrate 100 serves as a basis for subsequent processing. In the embodiment of the present invention, the material of the semiconductor substrate 100 is at least one of the following materials: polysilicon, silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-germanium-on-insulator (S-SiGeOI), silicon-germanium-on-insulator (SiGeOI), and the like. In an embodiment of the present invention, the material of the semiconductor substrate 100 is polysilicon. And other structures may be included in the semiconductor substrate 100, such as: the structures such as metal plugs, metal connection layers, dielectric layers, and the like, or other semiconductor devices including the structures, are not particularly limited herein. The semiconductor substrate 100 includes a first region i and a second region ii, which are subsequently formed into a PMOS region and an NMOS region or an NMOS region and a PMOS region, respectively, without being particularly limited thereto.
The fin 110 is formed by etching the semiconductor substrate 100. The material of the fin upper portion for subsequent formation of a channel layer (not shown) includes one or more of Si, siC, gaN, inGaP, inP, gaAs. In the embodiment of the invention, the fin portion includes a first region i fin portion and a second region ii fin portion, as shown in fig. 1.
The first protection layer 120 is formed to protect the structure of the fin 110 from being damaged by subsequent processes, affecting the size and structural integrity of the fin 110. Meanwhile, after the first protection layer 120 is formed, the dimensions of the fin 110 (which will be described in detail below) can be locally changed by performing a subsequent process by adjusting the thickness of the first protection layer 120, so as to achieve a desired effect.
The material of the first protective layer 120 is a dielectric material conventional in semiconductor processing, such as SiO x 、SiN x SiON, etc., as long as the fin 110 can be protected. Specifically, in the embodiment of the present invention, the material of the first protection layer 120 is SiO 2 。
In the embodiment of the present invention, the first protection layer 120 is directly formed on the sidewall of the fin 110. In other embodiments of the present invention, the first protection layer 120 covering the sidewalls of the fin 110, the top surface and the surface of the semiconductor substrate 100 may be formed first, and then a portion of the first protection layer 120 is removed, so that only the first protection layer 120 formed on the sidewalls of the fin 110 remains. Here, no particular limitation is imposed.
The process of forming the first protective layer 120 is a conventional semiconductor process, such as: spin coating process, atomic layer deposition process, vapor deposition process (PVD, CVD), etc., and are not particularly limited herein.
Referring to fig. 2 a-2 b, an intermediate material layer 130 is formed overlying the first region i fin.
The intermediate material layer 130 is formed for subsequent etching or only partially etching of the first protection layer 120 of the second region ii fin sidewall surface.
After forming the intermediate material layer 130, the method further includes etching the first protection layer 120 on the fin sidewall of the second region ii with the intermediate material layer 130 as a mask.
After etching the first protection layer 120 on the fin side wall of the second area ii, the thickness dimension of the fin side wall of the second area ii is not equal to that of the first protection layer 120 on the fin side wall of the first area i, and the width dimension of the tops of the two remaining fin portions is not equal after the subsequent specific process is implemented. Specifically, in the embodiment of the present invention, after etching a portion of the first protection layer 120 on the fin sidewall of the second region ii with the intermediate material layer 130 as a mask, a portion of the first protection layer 120 remains. At this time, the thickness of the first protection layer 120 on the fin sidewall of the second region ii is smaller than the thickness of the first protection layer 120 on the fin sidewall of the first region i.
In another embodiment of the present invention, as shown in fig. 2b, the first protection layer 120 on the fin sidewall of the second region ii is completely etched away by using the intermediate material layer 130 as a mask, so as to expose the fin sidewall of the second region ii. That is, the thickness of the first protection layer 120 on the fin sidewall of the second region ii is 0, which is still smaller than the thickness of the first protection layer 120 on the fin sidewall of the first region i.
In other embodiments of the present invention, etching of portions of the second region ii fin may be continued after exposing sidewalls of the second region ii fin. There is no particular limitation herein.
Referring to fig. 3, a portion of second region ii of semiconductor substrate 100 under the fin of second region ii is etched.
Etching the portion of the semiconductor substrate 100 under the second region II fin enables the height dimensions of the first region I fin and the second region II fin to be unequal, i.e., h 1 ≠h 2 . When the semiconductor substrate 100 at the bottom of the fin 110 is thicker, heat dissipation can be accelerated. At the same time, h 1 ≠h 2 The thicknesses of the semiconductor substrates 100 at the bottoms of the fins 110 in different regions are different, and the thickness dimensions are mutually intersectedThe error rule can further promote the device to dissipate heat generated during operation, and improve the performance of the device. Specifically, in the embodiment of the present invention, h 1 ＜h 2 。
After etching the portion of the semiconductor substrate 100 under the fin portion of the second region ii, a portion of the sidewall exposed under the fin portion of the second region ii is not covered by the first protection layer 120, so that the first protection layer 120 may be formed to cover the portion of the sidewall of the fin portion 110. In other embodiments of the present invention, the subsequent process may be directly performed without forming the first protection layer 120. Here, no particular limitation is imposed.
In other embodiments of the present invention, the second region ii of the portion of the semiconductor substrate 100 under the fin portion of the second region ii may not be etched, i.e., the height dimensions of the fin portions of the first region i and the second region ii may be kept equal all the time. There is no particular limitation herein.
Referring to fig. 4 a-4 b, the intermediate material layer 130 is removed and a second passivation layer 140 is formed.
Fig. 4a is a schematic diagram of a structure of an embodiment of the present invention after etching a second region of the semiconductor substrate 100, and fig. 4b is a schematic diagram of a structure of another embodiment of the present invention without etching the second region of the semiconductor substrate 100.
The removal of the intermediate material layer 130 facilitates subsequent processing. In an embodiment of the present invention, after removing the intermediate material layer 130, forming the second protection layer 140 is further included.
Since the end point of the etching process is difficult to control, it is difficult to control the width dimension of the remaining fin portion 110 or the thickness dimension of the remaining first protection layer 120, so that forming the second protection layer 140 can be used to adjust the dimension of the remaining structure, ensuring the accuracy of the dimension of the subsequent structure.
The second protection layer 140 is formed on the surface of the first protection layer 120 on the side wall of the fin 110 (as shown in fig. 4 a) or also on the side wall of the exposed second region ii fin (as shown in fig. 4 b).
The materials of the second protective layer 140 and the first protective layer 120 may be the same or different, and are not particularly limited herein. In the embodiment of the present invention, the second protection layer 140 and the first protection layer 120 are made of the same material. The forming process may or may not be identical to that of the first protective layer 120, and is not limited thereto.
In other embodiments of the present invention, the second protection layer 140 may not be formed, and is not particularly limited herein.
Referring to fig. 5 a-5 c, a dielectric layer 150 is formed between adjacent fins 110, and the first protection layer 120 is etched.
The dielectric layer 150 is formed so that the local positions of the fins 110 in different regions have different width dimensions.
In the embodiment of the present invention, after the dielectric layer 150 is formed, part of the side wall of the fin portion 110 or part of the first protection layer 120 of the side wall of the fin portion 110 needs to be exposed, so that a subsequent etching process is conveniently performed, and the effect that the width dimensions of the top of the fin portion 110 in different regions are unequal is achieved.
Since the second protection layer 140 is formed in the embodiment of the present invention, the process steps of exposing a portion of the sidewall of the fin 110 or a portion of the first protection layer 120 of the sidewall of the fin 110 include: the dielectric layer 150 covering the fin 110 is formed first, a portion of the dielectric layer 150 is removed to expose a top portion of the fin 110, a portion of the dielectric layer 150 is etched to expose a portion of the second protection layer 140, and finally the exposed second protection layer 140 is removed to expose a portion of the sidewalls of the fin 110 or a portion of the first protection layer 120 of the sidewalls of the fin 110.
The following process further includes: and etching to remove the exposed first protection layer 120 or etching part of the side wall of the second region II fin portion 110 until the side wall of the first region I fin portion is exposed.
As described above, the second region ii fin sidewall is exposed prior to the first region i fin sidewall being exposed because the thickness of the first protective layer 120 remaining on the first region i fin sidewall and the second region ii fin sidewall are not equal. Therefore, during the process of exposing the side wall of the first region I fin portion by continuing the etching process, the second region II fin portion is further etched, and the top width dimension l of the remaining first region I fin portion is finally obtained 1 Is larger than the top width dimension l of the fin part of the second region II 2 。
In the embodiment of the inventionIn Δl=l 1 -l 2 ，0.1≤Δl:l 1 Less than or equal to 0.3. Specifically, in the embodiment of the invention, deltal:l 1 ＝0.2。
As described above, in other embodiments of the present invention, the second protection layer may not be formed, that is, the dielectric layer 150 may be formed directly between the fins 110 after removing the intermediate material layer 130 on the basis of fig. 2 b. Then, the top of the fin 110 is exposed, and then a portion of the dielectric layer 150 is etched, so that a portion of the sidewall of the fin 110 or a portion of the first protection layer 120 of the sidewall of the fin 110 is directly exposed, and then the exposed first protection layer 120 or a portion of the sidewall of the fin 110 in the second region ii is etched to remove until the sidewall of the fin in the first region i is exposed, as shown in fig. 5 b. Fin top width dimension l of the final remaining first region I 1 Is larger than the top width dimension l of the fin part of the second region II 2 。
In other embodiments of the present invention, after the sidewalls of the first region i fin portion are exposed, the etching process may be further performed, and simultaneously, the exposed sidewalls of the first region i fin portion and the exposed sidewalls of the second region ii fin portion may be further etched, which is not particularly limited herein, so long as the condition that the width dimensions of the top of the first region i fin portion and the width dimensions of the top of the second region ii fin portion are not equal is finally satisfied. As in one embodiment of the invention, the width dimension of the bottom of the fin 110 may be greater than or equal to the width dimension of the top thereof. As shown in fig. 5c, the fin 110 has a bottom width dimension that is greater than a top width dimension thereof.
The functions of the semiconductor devices in different areas are different, so that the heat generated by the devices in different areas during operation is also different, the width sizes of the tops of the fin parts in the first area I and the fin parts in the second area II are unequal, the heat generated by the devices in different areas during subsequent operation can be dissipated through the fin parts 110 below the working areas in time, and the performance of the devices is improved. Meanwhile, for one region, the width dimension of the bottom of the fin portion 110 is larger than the width dimension of the top of the corresponding fin portion 110, so that heat dissipation can be further promoted, and the performance of the semiconductor device is further improved.
In the forming process of the fin field effect transistor, the width of the top of each region fin is equal, so that heat generated after the device works cannot be dissipated in time, the temperature of the device is increased, the whole driving current of the device is reduced, and the device is easy to generate a leakage phenomenon. The forming process of the embodiment of the invention can timely dissipate heat and improve the performance of the device.
In summary, the invention discloses a method for forming a fin field effect transistor, wherein the width dimensions of the tops of fin parts in different areas are unequal, so that heat generated during the operation of a semiconductor device is effectively promoted to be dissipated, and the performance of the semiconductor device is improved.
Accordingly, referring to fig. 5 a-5 c, the embodiment of the present invention further provides a fin field effect transistor, including: the semiconductor substrate 100, the fin 110 located above the semiconductor substrate 100, the protection layer of a portion of the fin sidewall, and the dielectric layer 150.
The semiconductor substrate 100 serves as a basis for subsequent processing. In the embodiment of the present invention, the material of the semiconductor substrate 100 is at least one of the following materials: polysilicon, silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-germanium-on-insulator (S-SiGeOI), silicon-germanium-on-insulator (SiGeOI), and the like. In an embodiment of the present invention, the material of the semiconductor substrate 100 is polysilicon. And other structures may be included in the semiconductor substrate 100, such as: the structures such as metal plugs, metal connection layers, dielectric layers, and the like, or other semiconductor devices including the structures, are not particularly limited herein. The semiconductor substrate 100 includes a first region i and a second region ii, which are respectively PMOS and NMOS regions or NMOS and PMOS regions, and are not particularly limited herein.
The fin 110 is formed by etching the semiconductor substrate 100. The material of the fin upper portion as a channel layer (not shown) includes one or more of Si, siC, gaN, inGaP, inP, gaAs. In an embodiment of the present invention, the fin comprises a first region i fin and a second region ii fin, as shown in fig. 5 a.
In an embodiment of the present invention, the width dimension of the top of the first region I fin is l 1 Second region II FinThe width dimension of the top of the part is l 2 ，l 1 ＞l 2 . The width dimensions of the fin parts at the tops of different areas are different, so that devices in different subsequent areas can timely emit heat generated during working, and the performance of the semiconductor device is improved.
In an embodiment of the invention, Δl=l 1 -l 2 ，0.1≤Δl:l 1 Less than or equal to 0.3. Specifically, in the embodiment of the present invention, Δl=0.2.
It should be noted that, in the embodiment of the present invention, the width dimension of the bottom of the fin 110 is greater than or equal to the width dimension of the top of the fin 110. As in one embodiment of the invention, the width dimension of the bottom of the fin 110 is greater than the width dimension of the top of the fin 110, as shown in fig. 5 c.
In the embodiment of the invention, the height dimension of the first region I fin portion is h 1 The height dimension of the second region II fin part is h 2 ，h 1 ≠h 2 . Generally, heat generated during operation of the device is dissipated through the fin below, so that when the fin 110 is low, heat can be dissipated from below the fin and from the semiconductor substrate 100 in time. In addition, the heat productivity of the devices in different regions is different, so in the embodiment of the invention, the thickness dimension of the semiconductor substrate 100 under the fin portion 110 in different regions shows an alternating rule, which further promotes the dissipation of heat and further improves the performance of the semiconductor device.
It is obvious that, in other embodiments of the present invention, the height dimension of the first region i fin may be equal to the height dimension of the second region ii fin, as shown in fig. 5b, so long as the condition that the width dimensions of the tops of the different region fins 110 are not equal is satisfied, and the present invention is not limited specifically.
In the process of forming the transistor, the protection layer is used to protect the fin 110 from being damaged or lost, and the protection layer is disposed on a sidewall of a portion of the fin 110. In the embodiment of the invention, the thickness dimension of the protective layer on the side wall of the fin portion in the first region I is larger than the thickness dimension of the protective layer on the side wall of the fin portion in the second region II. As shown in fig. 5a, the protective layers include a first protective layer 120 and a second protective layer 140.
As shown in fig. 5b, the protective layer may include only the first protective layer 120. The second region II fin side wall is not provided with a protective layer, and the condition that the thickness dimension of the protective layer of the first region I fin side wall is larger than that of the protective layer of the second region II fin side wall is still met.
A dielectric layer 150 is formed between adjacent fins 110.
In summary, the embodiment of the invention provides a fin field effect transistor, the width dimensions of the tops of the fin parts in different areas are unequal, so that heat generated by the operation of a device can be dissipated in time, and the performance of a semiconductor device is improved.
The present invention has been described in detail so far. In order to avoid obscuring the concepts of the invention, some details known in the art have not been described. How to implement the solutions disclosed herein will be fully apparent to those skilled in the art from the above description.
While certain specific embodiments of the invention have been described in detail by way of example, it will be appreciated by those skilled in the art that the above examples are for illustration only and are not intended to limit the scope of the invention. It will be appreciated by those skilled in the art that modifications may be made to the above embodiments without departing from the scope and spirit of the invention. The scope of the invention is defined by the appended claims.
Claims (11)
1. A method for forming a fin field effect transistor, comprising:
providing a semiconductor substrate comprising a first region and a second region, wherein a fin part is formed on the semiconductor substrate;
forming a first protection layer on the side wall of the fin part;
etching the first protection layer on the side wall of the fin part of the second region, so that the thickness dimension of the first protection layer remained on the side wall of the fin part of the second region is smaller than that of the first protection layer on the side wall of the fin part of the first region;
forming a dielectric layer between adjacent fin parts, and exposing part of the side wall of the fin part or part of the first protection layer of the side wall of the fin part; and
etching part of the side wall of the exposed fin portion or removing the exposed first protection layer until part of the side wall of the fin portion of the second region is exposed, wherein the width dimension of the top of the fin portion of the first region is l 1 The width dimension of the top of the fin portion of the second region is l 2 ，l 1 ＞l 2 And the width dimension of the bottom of the fin part is larger than or equal to the width dimension of the top of the fin part.
2. The method of forming a finfet in claim 1, wherein Δl = l 1 -l 2 ，0.1≤Δl:l 1 ≤0.3。
3. The method of claim 1, wherein etching the first protective layer of the second region fin sidewall comprises:
forming an intermediate material layer covering the first region fin portion; and
and etching the first protection layer on the side wall of the fin part of the second region by taking the intermediate material layer as a mask.
4. The method of claim 3, wherein the second region fin sidewall is exposed after etching the first protective layer of the second region fin sidewall.
5. The method of claim 4, further comprising, after etching the first protective layer on the second fin sidewall, before forming a dielectric layer between adjacent fins: removing the intermediate material layer; and
and forming a second protection layer, wherein the second protection layer is arranged on the surface of the first protection layer or the exposed side wall of the fin part of the second region.
6. The method of claim 5, wherein exposing a portion of the fin sidewall or a portion of the first protective layer of the fin sidewall comprises:
forming a dielectric layer covering the fin part;
removing a portion of the dielectric layer to expose a portion of the second protective layer; and
and removing the exposed second protective layer.
7. The method of claim 3, wherein etching the first protection layer on the second fin sidewall using the intermediate material layer as a mask, further comprises: and continuing to etch part of the semiconductor substrate below the second region fin portion, so that the height dimension of the first region fin portion is smaller than that of the second region fin portion.
8. A finfet formed according to any one of claims 1-7, comprising:
the semiconductor substrate comprises a first region and a second region, a fin portion is formed above the semiconductor substrate, the width dimension of the bottom of the fin portion is larger than or equal to the width dimension of the top of the fin portion, and the width dimension of the top of the fin portion of the first region is l 1 The width dimension of the top of the fin portion of the second region is l 2 ，l 1 ＞l 2 ；
The protective layer is formed on part of the side wall of the fin part; and
and the dielectric layers are arranged between the adjacent fin parts.
9. The finfet in claim 8, wherein Δl=l 1 -l 2 ，
0.1≤Δl:l 1 ≤0.3。
10. According to claim 8The fin field effect transistor is characterized in that the height dimension of the first region fin portion is h 1 The height dimension of the second region fin portion is h 2 ，h 1 ＜h 2 。
11. The fin field effect transistor of claim 8, wherein a thickness dimension of the protective layer of the first region fin sidewall is greater than a thickness dimension of the protective layer of the second region fin sidewall.
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103839814A (en) * | 2012-11-21 | 2014-06-04 | 中芯国际集成电路制造(上海)有限公司 | Method for forming fin field effect transistor |
| CN104795332A (en) * | 2014-01-21 | 2015-07-22 | 中芯国际集成电路制造(上海)有限公司 | Fin-type field effect transistor forming method |
| CN105826187A (en) * | 2015-01-06 | 2016-08-03 | 中芯国际集成电路制造(上海)有限公司 | FinFET (Fin Field Effect Transistor) and formation method thereof |
| CN106952816A (en) * | 2016-01-06 | 2017-07-14 | 中芯国际集成电路制造(上海)有限公司 | The forming method of fin transistor |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103839814A (en) * | 2012-11-21 | 2014-06-04 | 中芯国际集成电路制造(上海)有限公司 | Method for forming fin field effect transistor |
| CN104795332A (en) * | 2014-01-21 | 2015-07-22 | 中芯国际集成电路制造(上海)有限公司 | Fin-type field effect transistor forming method |
| CN105826187A (en) * | 2015-01-06 | 2016-08-03 | 中芯国际集成电路制造(上海)有限公司 | FinFET (Fin Field Effect Transistor) and formation method thereof |
| CN106952816A (en) * | 2016-01-06 | 2017-07-14 | 中芯国际集成电路制造(上海)有限公司 | The forming method of fin transistor |
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