CN111509045A - Fin field effect transistor and forming method thereof - Google Patents
Fin field effect transistor and forming method thereof Download PDFInfo
- Publication number
- CN111509045A CN111509045A CN201910099831.1A CN201910099831A CN111509045A CN 111509045 A CN111509045 A CN 111509045A CN 201910099831 A CN201910099831 A CN 201910099831A CN 111509045 A CN111509045 A CN 111509045A
- Authority
- CN
- China
- Prior art keywords
- fin
- region
- protective layer
- layer
- area
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000000034 method Methods 0.000 title claims abstract description 47
- 230000005669 field effect Effects 0.000 title claims abstract description 17
- 239000010410 layer Substances 0.000 claims abstract description 95
- 239000004065 semiconductor Substances 0.000 claims abstract description 64
- 239000011241 protective layer Substances 0.000 claims abstract description 63
- 239000000758 substrate Substances 0.000 claims abstract description 45
- 238000005530 etching Methods 0.000 claims abstract description 29
- 239000000463 material Substances 0.000 claims description 31
- 230000000694 effects Effects 0.000 claims description 7
- 230000008569 process Effects 0.000 description 24
- 238000002161 passivation Methods 0.000 description 13
- 230000017525 heat dissipation Effects 0.000 description 5
- 229910052732 germanium Inorganic materials 0.000 description 4
- 238000010438 heat treatment Methods 0.000 description 4
- 239000012212 insulator Substances 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 229920005591 polysilicon Polymers 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 229910004205 SiNX Inorganic materials 0.000 description 1
- 238000000231 atomic layer deposition Methods 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 230000014509 gene expression Effects 0.000 description 1
- 230000020169 heat generation Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
- 238000005019 vapor deposition process Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
- H01L29/66803—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with a step of doping the vertical sidewall, e.g. using tilted or multi-angled implants
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
- H01L23/3677—Wire-like or pin-like cooling fins or heat sinks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
- H01L29/0688—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions characterised by the particular shape of a junction between semiconductor regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
Abstract
The invention also discloses a method for forming the fin field effect transistor, which comprises the following steps: providing a semiconductor substrate comprising a first area and a second area, wherein a fin part is formed on the semiconductor substrate; forming a first protective layer on the side wall of the fin portion; etching the first protective layer on the side wall of the fin portion of the second area, so that the thickness dimension of the remaining first protective layer on the side wall of the fin portion of the second area is smaller than that of the first protective layer on the side wall of the fin portion of the first area; forming a dielectric layer between adjacent fin portions, and exposing partial side walls of the fin portions or partial first protective layers on the side walls of the fin portions; and etching part of the side wall of the exposed fin part or removing the exposed first protective layer until part of the side wall of the fin part in the second area is exposed, wherein the width dimension of the top of the fin part in the first area is l1The width of the top of the fin portion in the second region is l2，l1＞l2. Unequal width sizes of the tops of the fin parts can effectively and timely dissipate heat, and performance of the device is improved.
Description
Technical Field
The invention relates to the field of semiconductor manufacturing, in particular to a fin field effect transistor and a forming method thereof.
Background
As semiconductor device dimensions continue to decrease, semiconductor device cells have evolved from conventional CMOS devices to the field of fin field effect transistors (finfets). The technology node is at 14nm and even smaller, thus also presenting other problems. For example, when the device is in operation, the device generates heat due to the movement of carriers, and the generated heat is difficult to dissipate as the width dimension of the fin portion is smaller, which becomes a Self-heating Effect (Self-heating Effect). The heat cannot be dissipated in time, the drive current of the device is reduced due to the rise of the temperature, the leakage current of the whole device is increased, and the performance of the semiconductor device is influenced.
Therefore, there is a need in the art for a method of forming a finfet device that can efficiently dissipate heat and a corresponding device.
Disclosure of Invention
The embodiment of the invention provides a fin field effect transistor and a forming method thereof, wherein the width sizes of the tops of fins in different regions are unequal, so that the heat dissipation is effectively accelerated, and the performance of a semiconductor device is improved.
The invention discloses a fin field effect transistor, comprising: the semiconductor substrate comprises a first area and a second area, a fin portion is formed above the semiconductor substrate, the width dimension of the bottom of the fin portion is larger than or equal to the width dimension of the top of the fin portion, and the width dimension of the top of the fin portion of the first area is l1The width of the top of the fin portion in the second region is l2，l1＞l2(ii) a A protective layer formed on the sidewall of the fin portion; and the dielectric layer is arranged between the adjacent fin parts.
According to one aspect of the invention, Δ l ═ l1-l2，0.1≤Δl:l1≤0.3。
According to one aspect of the present invention, the first region fin has a height dimension h1The height dimension of the fin portion of the second region is h2，h1＜h2。
According to an aspect of the invention, a thickness dimension of the protection layer on the sidewalls of the first region of fins is larger than a thickness dimension of the protection layer on the sidewalls of the second region of fins.
Correspondingly, the invention also discloses a method for forming the fin field effect transistor, which comprises the following steps: providing a semiconductor substrate comprising a first area and a second area, wherein a fin part is formed on the semiconductor substrate; forming a first protective layer on the side wall of the fin portion; etching the first protective layer on the side wall of the fin portion of the second region to enable the thickness dimension of the remaining first protective layer on the side wall of the fin portion of the second region to be smaller than that of the first protective layer on the side wall of the fin portion of the first region; forming a dielectric layer between adjacent fin portions, and exposing partial side walls of the fin portions or partial first protective layers on the side walls of the fin portions; and etching part of the side wall of the exposed fin part or removing the exposed first protective layer until part of the side wall of the fin part in the second area is exposed, wherein the width dimension of the top of the fin part in the first area is l1The width of the top of the fin portion in the second region is l2，l1＞l2The width dimension of the bottom of the fin portion is larger than or equal to the width dimension of the top of the fin portion.
According to one aspect of the invention, Δ l ═ l1-l2，0.1≤Δl:l1≤0.3。
According to one aspect of the invention, the process of etching the first protective layer on the sidewall of the fin portion in the second region comprises the following steps: forming an intermediate material layer covering the first region fin portion; and etching the first protective layer on the side wall of the fin part in the second area by taking the intermediate material layer as a mask.
According to one aspect of the invention, after etching the first protective layer on the sidewalls of the second region of fins, the sidewalls of the second region of fins are exposed.
According to an aspect of the present invention, after etching the first protective layer on the sidewall of the fin portion in the second region, before forming a dielectric layer between adjacent fin portions, the method further includes: removing the intermediate material layer; and forming a second protective layer, wherein the second protective layer is arranged on the surface of the first protective layer or the exposed side wall of the fin part of the second area.
According to one aspect of the present invention, the step of exposing a portion of the sidewalls of the fin or a portion of the first protection layer on the sidewalls of the fin comprises: forming a dielectric layer covering the fin part; removing part of the dielectric layer to expose part of the second protective layer; and removing the exposed second protective layer.
According to an aspect of the invention, after etching the first protection layer on the sidewall of the fin in the second region by using the intermediate material layer as a mask, the method further includes: and continuing to etch part of the semiconductor substrate below part of the second region of the fin part, so that the height dimension of the first region of the fin part is smaller than that of the second region of the fin part.
Compared with the prior art, the technical scheme of the invention has the following advantages:
the width dimension of the top of the fin part of the first region in the fin type field effect transistor is l1The width of the top of the fin portion in the second region is l2，l1＞l2. The width sizes of the tops of the fin parts in different areas are unequal, and devices in different areas can dissipate heat generated during respective working in time, so that the self-heating effect is effectively avoided, the electric leakage of the devices is reduced, and the performance of the semiconductor device is improved.
Furthermore, the height dimension of the fin part in the first region is h1The height dimension of the second region fin portion is h2，h1＜h2. Namely, the thicknesses of the semiconductor substrates at the bottoms of the fins in different regions are different, and the heat generated by the device can be dissipated through the semiconductor substrates, and the heat dissipation can be further promoted by the difference of the thicknesses of the semiconductor substrates.
Correspondingly, in the method for forming the fin field effect transistor, the exposed partial side wall of the fin portion is etched or the exposed first protective layer is removed until the partial side wall of the fin portion in the second area is exposed, and the width dimension of the top of the fin portion in the first area is l1The width of the top of the fin portion in the second region is l2，l1＞l2. The width sizes formed at the tops of the fin parts in different regions are unequal, and devices in different regions can dissipate heat generated during respective working in time, so that the self-heating effect is effectively avoided, the electric leakage of the devices is reduced, and the performance of the semiconductor device is improved.
Furthermore, after the intermediate material layer is used as a mask to etch the first protective layer on the sidewall of the fin portion in the second region, the method further comprises the following steps: and continuing to etch part of the semiconductor substrate below part of the second region fin part, so that the height dimension of the first region fin part is smaller than that of the second region fin part. The thickness of the semiconductor substrate at the bottom of the fin part in different areas is different, and heat generated by the device can be dissipated through the semiconductor substrate, and the heat dissipation can be further promoted by the difference of the thickness of the semiconductor substrate.
Drawings
Fig. 1-5 c are schematic structural diagrams illustrating a finfet formation process according to an embodiment of the invention.
Detailed Description
As described above, the conventional finfet has a problem of poor heat dissipation.
The research finds that the reasons causing the problems are as follows: the width sizes of the tops of the fin parts in different working areas are consistent, and heat generated after the device works cannot be effectively dissipated.
In order to solve the problem, the invention provides a fin field effect transistor, the width sizes of the tops of fins in different regions are different, heat generated after the device works can be effectively dissipated in time, the increase of leakage current of the device is avoided, and the performance of a semiconductor device is improved.
Various exemplary embodiments of the present invention will now be described in detail with reference to the accompanying drawings. It should be understood that the relative arrangement of parts and steps, numerical expressions, and numerical values set forth in these embodiments should not be construed as limiting the scope of the present invention unless it is specifically stated otherwise.
Further, it should be understood that the dimensions of the various elements shown in the figures are not necessarily drawn to scale, for ease of description, and that the thickness or width of some layers may be exaggerated relative to other layers, for example.
The following description of the exemplary embodiment(s) is merely illustrative and is not intended to limit the invention, its application, or uses in any way.
Techniques, methods, and apparatus known to those of ordinary skill in the relevant art may not be discussed in detail, but are intended to be part of the specification as applicable.
It should be noted that like reference numerals and letters refer to like items in the following figures, and thus, once an item is defined or illustrated in one figure, further discussion thereof will not be required in the subsequent description of the figures.
Referring to fig. 1, a fin 110 is formed on a semiconductor substrate 100, and a first protection layer 120 is formed on sidewalls of the fin 110.
The semiconductor substrate 100 serves as a base for subsequent processes. In the embodiment of the present invention, the material of the semiconductor substrate 100 is at least one of the following materials: polysilicon, silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-on-insulator-germanium (S-SiGeOI), silicon-on-insulator-germanium (SiGeOI), and the like. In the embodiment of the present invention, the material of the semiconductor substrate 100 is polysilicon. And other structures may be included in the semiconductor substrate 100, such as: the structures of metal plugs, metal connection layers, dielectric layers, etc., or other semiconductor devices including these structures, are not limited in this respect. The semiconductor substrate 100 includes a first region i and a second region ii, which are subsequently formed with a PMOS region and an NMOS region or an NMOS region and a PMOS region, respectively, and are not particularly limited herein.
The fin 110 is formed by etching the semiconductor substrate 100. The material of the upper portion of the fin for subsequently forming a channel layer (not shown) includes one or more of Si, SiC, GaN, InGaP, InP, and GaAs. In an embodiment of the present invention, the fin portion includes a first region Ifin portion and a second region IIfin portion, as shown in FIG. 1.
The first protection layer 120 is formed to protect the structure of the fin 110 from being damaged by a subsequent process, which may affect the size and structural integrity of the fin 110. Meanwhile, after the first protection layer 120 is formed, the subsequent processes may be performed to locally change the size of the fin 110 (described in detail below) by adjusting the thickness of the first protection layer 120, so as to achieve the desired effect.
The material of the first protection layer 120 is a dielectric material conventional in semiconductor process, such as SiOx、 SiNxSiON, etc., as long as it can function to protect the fin 110. Specifically, in the embodiment of the present invention, the material of the first passivation layer 120 is SiO2。
In the embodiment of the invention, the first protection layer 120 is directly formed on the sidewall of the fin 110. In other embodiments of the present invention, the first protection layer 120 covering the sidewalls, the top surface and the surface of the semiconductor substrate 100 of the fin 110 may be formed first, and then a portion of the first protection layer 120 is removed, so that only the first protection layer 120 formed on the sidewalls of the fin 110 remains. Here, it is not particularly limited.
The process of forming the first protection layer 120 is a conventional semiconductor process, such as: a spin coating process, an atomic layer deposition process, a vapor deposition process (PVD, CVD), etc., and herein, are not particularly limited.
Referring to fig. 2 a-2 b, an intermediate material layer 130 is formed overlying the first region ipfin.
The intermediate material layer 130 is formed for subsequent etching of only or only a portion of the first protective layer 120 on the second region iifin sidewall surface.
After the intermediate material layer 130 is formed, the method further includes etching the first protective layer 120 on the sidewalls of the second region ii fin portion by using the intermediate material layer 130 as a mask.
After the first protective layer 120 on the sidewall of the second region ii fin portion is etched, the thickness of the first protective layer 120 on the sidewall of the second region ii fin portion is not equal to the thickness of the first protective layer 120 on the sidewall of the first region i fin portion, and the width of the tops of the two remaining fin portions is not equal after the subsequent specific process is performed. Specifically, in the embodiment of the invention, after the intermediate material layer 130 is used as a mask and a portion of the first protection layer 120 on the sidewall of the fin portion ii in the second region is etched, a portion of the first protection layer 120 still remains. At this time, the thickness of the first passivation layer 120 on the sidewalls of the second region ii fins is smaller than the thickness of the first passivation layer 120 on the sidewalls of the first region i fins.
In another embodiment of the present invention, as shown in fig. 2b, the intermediate material layer 130 is used as a mask to etch and remove all the first passivation layer 120 on the sidewalls of the second region of the iifin, thereby exposing the sidewalls of the second region of the iifin. That is, the thickness of the first passivation layer 120 on the sidewalls of the second region ii fins is 0, which is still smaller than the thickness of the first passivation layer 120 on the sidewalls of the first region i fins.
In other embodiments of the present invention, after the sidewalls of the second region iifin portion are exposed, a portion of the second region iifin portion may be further etched. And are not particularly limited herein.
Referring to fig. 3, a portion of the second region ii of the semiconductor substrate 100 under the fin portion of the second region ii is etched.
Etching the part of the semiconductor substrate 100 below the second region IIfin portion can enable the height sizes of the first region IIfin portion and the second region IIfin portion to be unequal, namely h1≠h2. When the semiconductor substrate 100 is thicker at the bottom of the fin 110, heat dissipation can be accelerated. At the same time, h1≠h2The thicknesses of the semiconductor substrate 100 at the bottoms of the fin portions 110 in different regions are different, and the thickness dimensions are in a mutually staggered rule, so that the heat generated during operation can be further dissipated by the device, and the performance of the device is improved. Specifically, in the embodiment of the present invention, h1＜h2。
After etching a portion of the semiconductor substrate 100 under the second region iifin, the exposed sidewall of the lower portion of the second region iifin is not covered by the first protection layer 120, so that the first protection layer 120 may be formed to cover the sidewall of the portion of the fin 110. In other embodiments of the present invention, the subsequent process may be performed without forming the first protection layer 120. Here, no particular limitation is imposed.
In other embodiments of the present invention, the second region ii of the portion of the semiconductor substrate 100 below the second region ii fin may not be etched, that is, the height dimensions of the first region i fin and the second region ii fin are always kept equal. And are not particularly limited herein.
Referring to fig. 4 a-4 b, the intermediate material layer 130 is removed, and a second passivation layer 140 is formed.
Fig. 4a is a schematic structural diagram of the semiconductor substrate 100 after the second region is etched according to the embodiment of the present invention, and fig. 4b is a schematic structural diagram of the semiconductor substrate 100 without etching the second region according to another embodiment of the present invention.
The removal of the intermediate material layer 130 facilitates subsequent processing. In an embodiment of the present invention, after removing the intermediate material layer 130, forming a second protection layer 140 is further included.
Since the end point of the etching process is difficult to control, it is difficult to control the width of the remaining fin 110 or the thickness of the remaining first protection layer 120, so that the formation of the second protection layer 140 can be used to adjust the size of the remaining structure, thereby ensuring the accuracy of the size of the subsequent structure.
The second passivation layer 140 is formed on the sidewalls of the fins 110 and the surface of the first passivation layer 120 (as shown in fig. 4 a) or on the sidewalls of the exposed second region iifins (as shown in fig. 4 b).
The materials of the second protective layer 140 and the first protective layer 120 may be the same or different, and are not particularly limited herein. In the embodiment of the present invention, the second protective layer 140 and the first protective layer 120 are made of the same material. The formation process may or may not be the same as that of the first protective layer 120, and is not limited herein.
In other embodiments of the present invention, the second protection layer 140 may not be formed, and is not particularly limited herein.
Referring to fig. 5 a-5 c, a dielectric layer 150 is formed between adjacent fins 110 and the first passivation layer 120 is etched.
The dielectric layer 150 is formed to have different width dimensions at different local locations of the fin 110.
In the implementation of the present invention, after the dielectric layer 150 is formed, a portion of the sidewall of the fin 110 or a portion of the first protection layer 120 on the sidewall of the fin 110 needs to be exposed, so as to perform a subsequent etching process, thereby achieving the effect of unequal top width dimensions of the fins 110 in different regions.
Since the second protection layer 140 is formed in the embodiment of the invention, the process steps of exposing a portion of the sidewall of the fin 110 or a portion of the first protection layer 120 on the sidewall of the fin 110 include: the dielectric layer 150 covering the fin 110 is formed, a portion of the dielectric layer 150 is removed to expose the top of the fin 110, a portion of the dielectric layer 150 is etched to expose a portion of the second protection layer 140, and finally the exposed second protection layer 140 is removed to expose a portion of the sidewall of the fin 110 or a portion of the first protection layer 120 on the sidewall of the fin 110.
The following process further comprises: the exposed sidewalls of the first passivation layer 120 are removed or a portion of the second set of IIfin portions 110 is etched until the sidewalls of the first set of IIfin portions are exposed.
As mentioned above, since the remaining first passivation layer 120 has unequal thickness on the sidewalls of the first region and the second region, the sidewalls of the second region and the second region are exposed before the sidewalls of the first region and the second region are exposed. Therefore, in the process of continuing to perform the etching process to expose the side wall of the first region I fin portion, the second region II fin portion is further etched, and finally the width dimension l of the top of the remaining first region I fin portion1Is larger than the width dimension l of the top of the second region II fin part2。
In an embodiment of the present invention, Δ l ═ l1-l2，0.1≤Δl:l1Less than or equal to 0.3. Specifically, in the present example,. DELTA.l: l1＝0.2。
As mentioned above, in other embodiments of the present invention, the second passivation layer may not be formed, i.e., the dielectric layer 150 may be formed directly between the fins 110 after removing the intermediate material layer 130 on the basis of fig. 2 b. Similarly, the top of the fin 110 is exposed, then a portion of the dielectric layer 150 is etched to directly expose a portion of the sidewall of the fin 110 or a portion of the first protective layer 120 on the sidewall of the fin 110, and then the exposed first protective layer 120 is etched away or a portion of the sidewall of the second region iifin 110 is etched until the sidewall of the first region iifin is exposed, as shown in fig. 5 b. Final remaining first region I fin top width dimension l1Is larger than the width dimension l of the top of the second region II fin part2。
It should be noted that, in other embodiments of the present invention, after the sidewalls of the first region i fin portion are exposed, the etching process may be further performed, and at the same time, the exposed sidewalls of the first region i fin portion and the exposed sidewalls of the second region ii fin portion are further etched, where the etching process is not specifically limited, and finally, the condition that the width dimensions of the top of the first region i fin portion and the top of the second region ii fin portion are not equal is satisfied. As in one embodiment of the present invention, the width dimension of the bottom of the fin 110 may be greater than or equal to the width dimension of the top thereof. As shown in fig. 5c, the width of the fin 110 is greater at the bottom than at the top.
The functions of semiconductor devices in different regions are different, so that the heat generated by the devices in different regions during working is also different, and the width sizes of the tops of the first fin part in the first region and the second fin part in the second region are different, so that the heat generated by the devices in different regions during subsequent working can be dissipated through the fin part 110 below the working region, and the performance of the devices is improved. Meanwhile, for one region, the width dimension of the bottom of the fin portion 110 is larger than the width dimension of the top of the corresponding fin portion 110, so that the dissipation of generated heat can be further promoted, and the performance of the semiconductor device is further improved.
In a fin field effect transistor forming process, the width size of the top of a fin part in each region is equal, so that heat generated after a device works cannot be dissipated timely, the temperature of the device is increased, the driving current of the whole device is reduced, and the device is easy to leak electricity. The forming process of the embodiment of the invention can dissipate heat in time and improve the performance of the device.
In summary, the present invention discloses a method for forming a fin field effect transistor, wherein the widths of the tops of the fins in different regions are not equal, so as to effectively promote dissipation of heat generated during operation of the device and improve the performance of the semiconductor device.
Accordingly, with continued reference to fig. 5 a-5 c, an embodiment of the present invention further provides a finfet, including: the semiconductor device includes a semiconductor substrate 100, a fin 110 located above the semiconductor substrate 100, a protective layer on a sidewall of a portion of the fin, and a dielectric layer 150.
The semiconductor substrate 100 serves as a base for subsequent processes. In the embodiment of the present invention, the material of the semiconductor substrate 100 is at least one of the following materials: polysilicon, silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-on-insulator-germanium (S-SiGeOI), silicon-on-insulator-germanium (SiGeOI), and the like. In the embodiment of the present invention, the material of the semiconductor substrate 100 is polysilicon. And other structures may be included in the semiconductor substrate 100, such as: the structures of metal plugs, metal connection layers, dielectric layers, etc., or other semiconductor devices including these structures, are not limited in this respect. The semiconductor substrate 100 includes a first region i and a second region ii, which are a PMOS region and an NMOS region or an NMOS region and a PMOS region, respectively, and are not particularly limited herein.
The fin 110 is formed by etching the semiconductor substrate 100. The material of the upper part of the fin as a channel layer (not shown) comprises one or more of Si, SiC, GaN, InGaP, InP and GaAs. In an embodiment of the present invention, the fin portion includes a first region Ifin portion and a second region IIfin portion, as shown in FIG. 5 a.
In one embodiment of the present invention, the top of the first region I fin has a width dimension of l1The width of the top of the second region II fin portion is l2，l1＞l2. The width sizes of the tops of the fin parts in different areas are different, so that heat generated during working can be timely dissipated by devices in different subsequent areas, and the performance of the semiconductor device is improved.
In an embodiment of the present invention, Δ l ═ l1-l2，0.1≤Δl:l1Less than or equal to 0.3. Specifically, in the present embodiment, Δ l is 0.2.
It should be noted that, in the embodiment of the present invention, the width dimension of the bottom of the fin 110 is greater than or equal to the width dimension of the top of the fin 110. As in one embodiment of the present invention, the width dimension at the bottom of the fin 110 is greater than the width dimension at the top of the fin 110, as shown in fig. 5 c.
In the embodiment of the invention, the height dimension of the first region I fin part is h1The height dimension of the second region II fin part is h2，h1≠h2. In general, the heat generated during device operation is dissipated and conducted through the lower fin portion, so that when the fin portion 110 is low in height, the heat can be conducted awayAnd in time from under the fins and from the semiconductor substrate 100. Moreover, the heat generation amount of the devices in different regions is different, so in the embodiment of the present invention, the thickness dimensions of the semiconductor substrate 100 below the fins 110 in different regions exhibit an alternating rule, which further promotes the dissipation of heat and further improves the performance of the semiconductor device.
Obviously, in other embodiments of the present invention, the height of the first region i fins may be equal to the height of the second region ii fins, as shown in fig. 5b, as long as the condition that the widths of the tops of the fins 110 in different regions are not equal is satisfied, which is not limited herein.
In the process of forming the transistor, the protection layer is used to protect the fin 110 from being damaged or lost, and the protection layer is disposed on the sidewalls of some of the fins 110. In an embodiment of the invention, a thickness dimension of the protective layer on the sidewall of the first region I fin portion is larger than a thickness dimension of the protective layer on the sidewall of the second region II fin portion. As shown in fig. 5a, the protective layer includes a first protective layer 120 and a second protective layer 140.
As shown in fig. 5b, the protective layer may include only the first protective layer 120. And no protective layer is formed on the side wall of the II fin parts of the second area, and the condition that the thickness dimension of the protective layer on the side wall of the I fin part of the first area is larger than that of the protective layer on the side wall of the II fin part of the second area is still met.
A dielectric layer 150 is formed between adjacent fins 110.
In summary, embodiments of the present invention provide a fin field effect transistor, where widths of tops of fins in different regions are not equal, so that heat generated by device operation can be dissipated in time, and performance of a semiconductor device is improved.
Thus far, the present invention has been described in detail. Some details well known in the art have not been described in order to avoid obscuring the concepts of the present invention. It will be fully apparent to those skilled in the art from the foregoing description how to practice the presently disclosed embodiments.
Although some specific embodiments of the present invention have been described in detail by way of illustration, it should be understood by those skilled in the art that the above illustration is only for the purpose of illustration and is not intended to limit the scope of the invention. It will be appreciated by those skilled in the art that modifications may be made to the above embodiments without departing from the scope and spirit of the invention. The scope of the invention is defined by the appended claims.
Claims (11)
1. A fin field effect transistor, comprising:
the semiconductor substrate comprises a first area and a second area, a fin portion is formed above the semiconductor substrate, the width dimension of the bottom of the fin portion is larger than or equal to the width dimension of the top of the fin portion, and the width dimension of the top of the fin portion in the first area is l1The width dimension of the top of the fin part of the second region is l2，l1＞l2；
A protective layer formed on a portion of the fin sidewall; and
and the dielectric layers are arranged between the adjacent fin parts.
2. The finfet of claim 1, wherein Δ l ═ l1-l2，0.1≤Δl:l1≤0.3。
3. The fin-field effect transistor of claim 1, wherein the first-region fin has a height dimension h1The height dimension of the fin part in the second region is h2，h1＜h2。
4. The fin-type field effect transistor of claim 1, wherein a thickness dimension of the protective layer of the first-region fin sidewalls is greater than a thickness dimension of the protective layer of the second-region fin sidewalls.
5. A method for forming a fin field effect transistor (FinFET), comprising:
providing a semiconductor substrate comprising a first area and a second area, wherein a fin part is formed on the semiconductor substrate;
forming a first protective layer on the side wall of the fin part;
etching the first protection layer on the side wall of the second region fin portion to enable the thickness dimension of the first protection layer remaining on the side wall of the second region fin portion to be smaller than that of the first protection layer on the side wall of the first region fin portion;
forming a dielectric layer between the adjacent fin parts, and exposing partial side walls of the fin parts or partial first protective layers on the side walls of the fin parts; and
etching part of exposed side walls of the fin portion or removing the exposed first protective layer until part of side walls of the fin portion in the second area are exposed, wherein the width of the top of the fin portion in the first area is l1The width dimension of the top of the fin part of the second region is l2，l1＞l2And the width size of the bottom of the fin part is larger than or equal to the width size of the top of the fin part.
6. The method of claim 5, wherein Δ l ═ l is defined by1-l2，0.1≤Δl:l1≤0.3。
7. The method of claim 5, wherein the step of etching the first protective layer on the second region fin sidewalls comprises:
forming an intermediate material layer covering the first region fin part; and
and etching the first protective layer on the side wall of the fin part in the second area by taking the intermediate material layer as a mask.
8. The method of claim 7, wherein the second region fin sidewalls are exposed after etching the first protective layer of the second region fin sidewalls.
9. The method of claim 8, wherein after etching the first protective layer on the sidewalls of the second region fins and before forming a dielectric layer between adjacent fins, further comprising:
removing the intermediate material layer; and
and forming a second protective layer which is arranged on the surface of the first protective layer or the exposed side wall of the second region fin part.
10. The method of claim 9, wherein the exposing the fin sidewall or the first protective layer comprises:
forming a dielectric layer covering the fin part;
removing part of the dielectric layer to expose part of the second protective layer; and
and removing the exposed second protective layer.
11. The method of claim 7, wherein etching the first protective layer on the second region fin sidewall using the intermediate material layer as a mask further comprises: and continuously etching part of the semiconductor substrate below part of the second region of the fin part to enable the height dimension of the first region of the fin part to be smaller than that of the second region of the fin part.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910099831.1A CN111509045B (en) | 2019-01-31 | 2019-01-31 | Fin field effect transistor and forming method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910099831.1A CN111509045B (en) | 2019-01-31 | 2019-01-31 | Fin field effect transistor and forming method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN111509045A true CN111509045A (en) | 2020-08-07 |
| CN111509045B CN111509045B (en) | 2023-09-15 |
Family
ID=71875669
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201910099831.1A Active CN111509045B (en) | 2019-01-31 | 2019-01-31 | Fin field effect transistor and forming method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN111509045B (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103839814A (en) * | 2012-11-21 | 2014-06-04 | 中芯国际集成电路制造(上海)有限公司 | Method for forming fin field effect transistor |
| CN104795332A (en) * | 2014-01-21 | 2015-07-22 | 中芯国际集成电路制造(上海)有限公司 | Fin-type field effect transistor forming method |
| CN105826187A (en) * | 2015-01-06 | 2016-08-03 | 中芯国际集成电路制造(上海)有限公司 | FinFET (Fin Field Effect Transistor) and formation method thereof |
| CN106952816A (en) * | 2016-01-06 | 2017-07-14 | 中芯国际集成电路制造(上海)有限公司 | The forming method of fin transistor |
-
2019
- 2019-01-31 CN CN201910099831.1A patent/CN111509045B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103839814A (en) * | 2012-11-21 | 2014-06-04 | 中芯国际集成电路制造(上海)有限公司 | Method for forming fin field effect transistor |
| CN104795332A (en) * | 2014-01-21 | 2015-07-22 | 中芯国际集成电路制造(上海)有限公司 | Fin-type field effect transistor forming method |
| CN105826187A (en) * | 2015-01-06 | 2016-08-03 | 中芯国际集成电路制造(上海)有限公司 | FinFET (Fin Field Effect Transistor) and formation method thereof |
| CN106952816A (en) * | 2016-01-06 | 2017-07-14 | 中芯国际集成电路制造(上海)有限公司 | The forming method of fin transistor |
Also Published As
| Publication number | Publication date |
|---|---|
| CN111509045B (en) | 2023-09-15 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US9548305B2 (en) | Semiconductor devices and methods of manufacture thereof | |
| US8609480B2 (en) | Methods of forming isolation structures on FinFET semiconductor devices | |
| US10312377B2 (en) | Localized fin width scaling using a hydrogen anneal | |
| US8703557B1 (en) | Methods of removing dummy fin structures when forming finFET devices | |
| US8766363B2 (en) | Method and structure for forming a localized SOI finFET | |
| US8835262B2 (en) | Methods of forming bulk FinFET devices by performing a recessing process on liner materials to define different fin heights and FinFET devices with such recessed liner materials | |
| CN107452679B (en) | Semiconductor device and method for manufacturing the same | |
| CN105826193A (en) | Formation method of semiconductor device | |
| US10714469B2 (en) | Electrostatic discharge protection structure | |
| US10483395B2 (en) | Method for fabricating semiconductor device | |
| US20160086952A1 (en) | Preventing epi damage for cap nitride strip scheme in a fin-shaped field effect transistor (finfet) device | |
| US10043675B2 (en) | Semiconductor device and method for fabricating the same | |
| US11049969B2 (en) | Semiconductor device and fabrication method thereof | |
| US20180061832A1 (en) | Methods, apparatus and system for sti recess control for highly scaled finfet devices | |
| CN111509045B (en) | Fin field effect transistor and forming method thereof | |
| US20180114730A1 (en) | Spacer integration scheme for nfet and pfet devices | |
| KR102087198B1 (en) | Etching using chamber with top plate formed of non-oxygen containing material | |
| CN112687622A (en) | Single diffusion region cutting structure of fin field effect transistor and forming method thereof | |
| US11329144B2 (en) | Semiconductor structure and fabrication method thereof | |
| CN111599755A (en) | Method for forming semiconductor device | |
| CN111446286A (en) | Semiconductor structure and forming method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |