CN106960789A - Semiconductor devices and the method for improving performance of semiconductor device - Google Patents
Semiconductor devices and the method for improving performance of semiconductor device Download PDFInfo
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- CN106960789A CN106960789A CN201610011819.7A CN201610011819A CN106960789A CN 106960789 A CN106960789 A CN 106960789A CN 201610011819 A CN201610011819 A CN 201610011819A CN 106960789 A CN106960789 A CN 106960789A
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66492—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a pocket or a lightly doped drain selectively formed at the side of the gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823814—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823821—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
- H01L29/7848—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
A kind of semiconductor devices and the method for improving performance of semiconductor device, wherein improving the method for performance of semiconductor device includes：Substrate is provided, the substrate surface is formed with grid structure；Etching forms first and is open positioned at the substrate of the first thickness of the grid structure both sides；The first side wall is formed on the first opening sidewalls surface；The first open bottom exposed along first side wall etches downwards the substrate for removing second thickness, is less than the width dimensions of the first opening in the width dimensions of the described first opening the second opening formed below, and second opening；Remove first side wall；The stressor layers of filling full first opening and the second opening are formed, and lightly doped district is formed in the stressor layers of the described first opening.The present invention improves the performance of the lightly doped district formed while raising stressor layers put on the stress of channel region, it is to avoid lightly doped district is etched and by injection lattice damage, and then improves the performance of the semiconductor devices of formation.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, more particularly to a kind of semiconductor devices and improvement half
The method of conductor device performance.
Background technology
With continuing to develop for semiconductor technology, carrier mobility enhancing technology obtains extensive research
And application, the driving current of MOS device can be increased by improving the carrier mobility of channel region, improve device
The performance of part.
In existing semiconductor device fabrication process, because stress can change the energy gap and carrier of silicon materials
Mobility, therefore the performance of MOS transistor is improved as more and more conventional means by stress.Tool
Body, by suitable control stress, carrier (electronics in nmos pass transistor, PMOS can be improved
Hole in transistor) mobility, and then driving current is improved, MOS transistor is greatly enhanced with this
Performance.
At present, using embedded germanium silicon (Embedded SiGe) technology, that is, needing to form source region and leakage
The region in area is initially formed germanium silicon material, and source region and the drain region to form PMOS transistor are then doped again；
Form the germanium silicon material and be to introduce the compression of lattice mismatch formation between silicon and germanium silicon (SiGe),
To improve the performance of PMOS transistor.Using embedded carbon silicon (Embedded SiC) technology, that is, needing
The region for forming source region and drain region is initially formed carbon silicon materials, then is doped to form nmos pass transistor again
Source region and drain region；Forming the carbon silicon materials is formed to introduce lattice mismatch between silicon and carbon silicon
Tension, to improve the performance of nmos pass transistor.
The introducing of embedded germanium silicon technology or embedded carbon silicon technology can improve semiconductor to a certain extent
The carrier mobility of device, but find in actual applications, the electric property of semiconductor devices still has
Wait to improve.
The content of the invention
The problem of present invention is solved is to provide a kind of semiconductor devices and improves the side of performance of semiconductor device
Method, while semiconductor devices carrier mobility is improved, improves the quality of the lightly doped district formed,
So as to improve the electric property of the semiconductor devices of formation.
To solve the above problems, the present invention provides a kind of method of improvement performance of semiconductor device, including：
Substrate is provided, the substrate surface is formed with grid structure；Etching positioned at the grid structure both sides the
The substrate of one thickness, forms first and is open；The first side wall is formed on the first opening sidewalls surface；Edge
The first open bottom that first side wall exposes etches downwards the substrate for removing second thickness, described
First opening the second opening formed below, and the width dimensions of second opening are less than the first width being open
Spend size；Remove first side wall；The stressor layers of filling full first opening and the second opening are formed,
And form lightly doped district in the stressor layers of the described first opening.
Optionally, the width dimensions of first side wall are 4~8 nanometers；It is described first opening depth be
1~4 nanometer；The depth of second opening is 15~30 nanometers.
Optionally, the material of first side wall is silicon nitride, silica, silicon oxynitride, carbon nitrogen oxidation
Silicon or boron nitride.
Optionally, doped with Doped ions in the stressor layers, the Doped ions are N-type ion or P
Type ion, and the Doped ions concentration being located in the stressor layers of the second opening is more than answering positioned at the first opening
Doped ions concentration in power layer.
Optionally, the stressor layers are formed using epitaxy technique, and it is in situ during stressor layers are formed
Doped ions described in auto-dope.
Optionally, the material of the stressor layers is SiGeB, and former during the stressor layers are formed
Position auto-dope B ions, wherein, the B ion concentrations in the first opening, which are less than, to be located in the second opening
B ion concentrations.
Optionally, the material of the stressor layers is SiCP, and in situ during the stressor layers are formed
Auto-dope P ion, wherein, the P ion concentration in the first opening is less than the P being located in the second opening
Ion concentration.
The present invention also provides a kind of semiconductor devices, including：Substrate, the substrate surface is formed with grid
Structure；Positioned at intrabasement first opening of the first thickness of grid structure both sides；Opened positioned at described first
Mouthful lower section and the second opening mutually run through with the first opening, the width dimensions of second opening are less than the
One A/F size；Filling full described first is open and the second stressor layers being open, and described first opens
Lightly doped district is formed with the stressor layers of mouth.
Compared with prior art, technical scheme has advantages below：
The present invention is provided in a kind of technical scheme for the method for improving performance of semiconductor device, and etching is located at grid
The substrate of the first thickness of pole structure both sides, forms first and is open；In the first opening sidewalls surface shape
Into the first side wall；The first open bottom exposed along first side wall etches downwards removal second thickness
Substrate, described first opening it is formed below second opening, and it is described second opening width dimensions it is small
In the width dimensions of the first opening；Remove first side wall；Form full first opening of filling and the
The stressor layers of two openings, and form lightly doped district in the stressor layers of the described first opening.The present invention is in shape
Into forming lightly doped district during stressor layers so that the lightly doped district of formation keeps complete performance, and
The lightly doped district of formation and the distance of channel region are near, so that lightly doped district can play stronger electricity
Effect, improves the electric property of the semiconductor devices formed.Simultaneously as first opening with channel region it
Between it is closer to the distance so that stressor layers act on channel region stress enhancing, so as to improve formation
The carrier mobility of semiconductor devices.
Further, the stressor layers are formed using epitaxy technique, and it is in situ during stressor layers are formed
Doped ions described in auto-dope, and form heavily doped region in the stressor layers of the described second opening.So that shape
Technique into heavily doped region will not have undesirable effect to lightly doped district, it is to avoid lightly doped district is injected
Lattice damage, so as to further improve the performance of the lightly doped district of formation, and then further improves semiconductor
The performance of device.
The present invention also provides a kind of structural behaviour superior semiconductor devices, the substrate in grid structure both sides
It is interior to form the first opening and the second opening mutually run through, and the second opening is located at the first opening lower section, the
Two A/F sizes are less than the first A/F size；Also include, full first opening of filling and the
Lightly doped district is formed with the stressor layers of two openings, and the stressor layers of first opening.Open due to first
Mouthful width dimensions it is bigger than the width dimensions of the second opening, first opening and the distance of channel region are near,
So that the stress that stressor layers put on channel region is more notable, and then improve the load of semiconductor devices
Transport factor is flowed, improves the performance of semiconductor devices.
Brief description of the drawings
The cross-section structure for the semiconductor devices forming process that Fig. 1 to Figure 15 provides for one embodiment of the invention shows
It is intended to；
The section knot for the semiconductor devices forming process that Figure 16 to Figure 20 provides for another embodiment of the present invention
Structure schematic diagram.
Embodiment
It can be seen from background technology, the electric property of the semiconductor devices of prior art formation still has much room for improvement.
In order to introduce embedded germanium silicon or embedded carbon silicon technology, it is necessary to first in the base of grid structure both sides
Groove is formed in bottom, germanium silicon material or carbon silicon materials are then filled in groove, generally formed groove it
Before, lightly doped district is formed in the substrate of the grid structure both sides, the lightly doped district is suitable to improve heat
Carrier effect and short-channel effect.However, the substrate in etching grid structure both sides forms groove
In technical process, the lightly doped district positioned at grid structure both sides can be removed by part or all of etching, be caused
Electricity that lightly doped district is played effect variation will not even play electricity effect, in turn result in partly leading of being formed
The electric property of body device is poor.
To solve the above problems, the present invention provides a kind of method of improvement performance of semiconductor device, including：
Substrate is provided, the substrate surface is formed with grid structure；Etching positioned at the grid structure both sides the
The substrate of one thickness, forms first and is open；The first side wall is formed on the first opening sidewalls surface；Edge
The first open bottom that first side wall exposes etches downwards the substrate for removing second thickness, described
First opening the second opening formed below, and the width dimensions of second opening are less than the first width being open
Spend size；Remove first side wall；The stressor layers of filling full first opening and the second opening are formed,
And form lightly doped district in the stressor layers of the described first opening.The present invention is during stressor layers are formed
Lightly doped district is formed, and the lightly doped district and the distance of channel region that are formed are near, so that lightly doped district energy
It is enough to play stronger electricity effect, improve the electric property of the semiconductor devices formed.
It is understandable to enable the above objects, features and advantages of the present invention to become apparent, below in conjunction with the accompanying drawings
The specific embodiment of the present invention is described in detail.
The cross-section structure for the semiconductor devices forming process that Fig. 1 to Figure 15 provides for one embodiment of the invention shows
It is intended to.
With reference to Fig. 1, there is provided substrate.
So that the semiconductor devices of formation is cmos device as an example, the substrate includes first area I and the
Two region II, the first area I are NMOS area or PMOS area, and the second area II is
NMOS area or PMOS area, the first area I are different with second area II area type.
In the present embodiment, the first area I is PMOS area, and the second area II is NMOS area.
In other embodiments, the first area is NMOS area, and second area is PMOS area.
In its another embodiment, the substrate can also only include PMOS area or NMOS area, corresponding shape
Into semiconductor devices be PMOS or NMOS tube.
In the present embodiment, so that the semiconductor devices of formation is fin field effect pipe as an example, the substrate includes：
Substrate 101 and the fin 102 positioned at the surface of substrate 101.
In another embodiment, the semiconductor devices is planar transistor, and the substrate is planar substrates,
The planar substrates are silicon substrate, germanium substrate, silicon-Germanium substrate or silicon carbide substrates, silicon-on-insulator substrate
Or germanium substrate on insulator, glass substrate or III-V substrate (such as gallium nitride substrate or arsenic
Gallium substrate etc.), grid structure is formed at the plane.
The material of the substrate 101 is silicon, germanium, SiGe, carborundum, GaAs or gallium indium, institute
It can also be the silicon substrate on insulator or the germanium substrate on insulator to state substrate 101；The fin 102
Material include silicon, germanium, SiGe, carborundum, GaAs or gallium indium.It is described in the present embodiment
Substrate 101 is silicon substrate, and the material of the fin 102 is silicon.
In the present embodiment, forming the substrate 101, the processing step of fin 102 includes：Initial lining is provided
Bottom；Patterned hard mask layer is formed in the initial substrate surface；Carved by mask of the hard mask layer
The initial substrate after the initial substrate, etching is lost as substrate 101, the projection positioned at the surface of substrate 101
It is used as fin 102.
The substrate also includes, and the separation layer 103 positioned at the surface of substrate 101, the separation layer 103 is covered
The partial sidewall surface of fin 102, and the top of the separation layer 103 is less than the top of fin 102.It is described every
Absciss layer 103 plays a part of being electrically isolated adjacent fin 102, and the material of the separation layer 103 is insulation material
Material, for example, silica, silicon nitride, silicon oxynitride or carbon silicon oxynitride.In the present embodiment, it is described every
The material of absciss layer 103 is silica.
With reference to Fig. 2, in substrate surface formation grid structure.
In the present embodiment, in first area I substrate surfaces formation first grid structure 110, described
Second area II substrate surfaces formation second grid structure 120.Specifically, the first grid structure 110
Positioned at the surface of first area I parts separation layer 103, and across first area I fins 102, is also covered
The atop part surface of one region I fins 102 and sidewall surfaces；The second grid structure 120 is located at second
The surface of region II parts separation layer 103, and across second area II fins 102, also cover second area
The atop part surface of II fins 102 and sidewall surfaces.
In one embodiment, the first grid structure 110 is pseudo- grid structure (dummy gate),
Extended meeting removes the described first pseudo- grid structure 110 afterwards, then in the position where the first grid structure 110
The first actual gate structure of semiconductor devices is re-formed, the first grid structure 110 is individual layer knot
Structure or laminated construction, the first grid structure 110 include pseudo- gate layer, or the first grid structure
110 include pseudo- oxide layer and the pseudo- gate layer positioned at pseudo- oxidation layer surface, wherein, the material of pseudo- gate layer is many
Crystal silicon or amorphous carbon, the material of the pseudo- oxide layer is silica or silicon oxynitride.
In another embodiment, the first grid structure 110 can also be the actual grid of semiconductor devices
Pole structure, the first grid structure 110 includes gate dielectric layer and the grid electricity positioned at gate dielectric layer surface
Pole layer, wherein, the material of gate dielectric layer is silica or high-k gate dielectric material, the gate electrode layer
Material be polysilicon or metal material, the metal material include Ti, Ta, TiN, TaN, TiAl, TiAlN,
One or more in Cu, Al, W, Ag or Au.
The second grid structure 120 also can be pseudo- grid structure, or be the actual grid of semiconductor devices
Pole structure.
So that the first grid structure 110 and second grid structure 120 are actual gate structure as an example,
Forming the processing step of the first grid structure 110 and second grid structure includes：In the separation layer
103 surfaces form gate dielectric film, and the gate dielectric film covers the top table of fin 102 across fin 102
Face and sidewall surfaces；Gate electrode film is formed on the gate dielectric film surface；In gate electrode film surface shape
Into mask layer 104, the mask layer 104 defines first grid structure 110 to be formed and second grid
The figure of structure 120；It is mask with the mask layer 104, the graphical gate electrode film and grid are situated between
Plasma membrane, forms first grid structure 110, described second on the surface of first area I separation layers 103
The surface of region II separation layers 103 forms second grid structure 120.
In the present embodiment, retain and be located at the top surface of first grid structure 110 and second grid structure 120
The mask layer 104 of top surface so that the mask layer 104 mutually tackles the first grid during subsequent technique
Pole structure 110 and the top of second grid structure 120 play a protective role.The material of the mask layer 104
Expect for silicon nitride, silicon oxynitride, carborundum or boron nitride, in the present embodiment, not to the mask layer 104
Material limited.
Also include step：In the sidewall surfaces of first grid structure 110 and second grid structure 120
Sidewall surfaces the second side wall 105 of formation.Second side wall 105 can either play protection first grid structure
The effect of 110 sidewall surfaces and the sidewall surfaces of second grid structure 120, additionally it is possible to make be subsequently formed
There is a certain distance between one lightly doped district and the sidewall surfaces of first grid structure 110, make to be subsequently formed
The second lightly doped district and the sidewall surfaces of second grid structure 120 between have a certain distance.
The material of second side wall 105 is silica, silicon nitride or silicon oxynitride；Second side wall
105 be single layer structure or laminated construction.In the present embodiment, the material of second side wall 105 is silicon nitride；
Forming the method for second side wall 105 includes：In the surface of separation layer 103, first grid structure
110 surfaces and the surface of second grid structure 120 deposit the second side wall film；Returned using without mask etching technique
The second side wall film is etched, until the top of first grid structure 110 and second grid structure 120 are pushed up
The second side wall film in portion is etched removal, and the second side wall film on the surface of part separation layer 103 is etched
Remove, remaining second side wall film is used as the second side wall 105.It should be noted that in other embodiments, also
The processing step to form the second side wall can be omitted.
It is the schematic diagram on the basis of Fig. 2 with reference to Fig. 3 and Fig. 4, Fig. 3, wherein, Fig. 3 is and fin
The parallel cross-sectional view of 102 bearing of trends, Fig. 4 be and the bearing of trend of first area I fins 102
Vertical cross-sectional view, etching is located at the substrate of the first thickness of the grid structure both sides,
The first opening 106 is formed in the substrate.
In the present embodiment, the first opening 106 is formed in the substrate of the both sides of first grid structure 110,
The first opening 106 of the first area I is located in first area I fin 102, also described second
The first opening 106, the first opening of the second area II are formed in the substrate of the both sides of grid structure 120
106 are located in second area II fin 102.
Using dry etch process, etching is positioned at the both sides of first grid structure 110 and positioned at second grid
The substrate of the both sides of structure 120, forms first opening 106.
Specifically, forming the first mask layer 121 on the surface of separation layer 103 and the surface of fin 102；
It is mask with first mask layer 121, etching removes first positioned at the both sides of first grid structure 110
The fin 102 of thickness, forms the first opening 106, while also carving in the first area I fins 102
Etching off removes the fin 102 of the first thickness positioned at the both sides of second grid structure 102, in the second area II
The first opening 106 is formed in fin 102.
In the present embodiment, retain first mask layer 121 after first opening 106 is formed, make
Obtain during the first stressor layers are subsequently formed, the first mask layer 121 positioned at the surface of fin 102 can
It is blocked in the growth that the surface of fin 102 carries out the first stressor layers.
First mask layer 121 is silicon nitride, boron nitride, carbonitride of silicium, titanium nitride or tantalum nitride.
Extended meeting forms the first lightly doped district in first area I the first opening 106 afterwards, in second area
The second lightly doped district is formed in II the first opening 106.Therefore, it is described first opening 106 depth with
The depth of the depth of first lightly doped district to be formed and the second lightly doped district to be formed is identical.
In the present embodiment, the depth of first opening 106 is 1~4 nanometer.It should be noted that Fig. 4
In it is shown in phantom be the fin 102 before the first opening 106 is formed tip position and sidewall surfaces.
It is the schematic diagram on the basis of Fig. 3 with reference to Fig. 5 and Fig. 6, Fig. 5, Fig. 6 is on the basis of Fig. 4
Schematic diagram, in the described first 106 bottoms of opening and sidewall surfaces, the surface of first grid structure 110, the
The surface of two grid structure 120 and substrate surface the first side wall film 107 of formation.
In the present embodiment, the first side wall film 107 be covered in the bottom of the first opening 106 and sidewall surfaces,
The surface of first grid structure 110, the surface of second grid structure 120, the surface of fin 102 and separation layer
103 surfaces.Because the first mask layer 121 being previously formed is not removed, therefore the first side wall film 107
It is also located at the surface of the first mask layer 121.
Using chemical vapor deposition method, physical gas-phase deposition and atom layer deposition process formation institute
State the first side wall film 107.In order to improve covering for the first side wall film 107 at the bottom corners of the first opening 106
Lid ability so that the first side wall being subsequently formed is good to the spreadability at the first 106 bottom corners of opening,
In the present embodiment, the first side wall film 107 is formed using atom layer deposition process.
The material of the first side wall film 107 is boron nitride, silica, silicon nitride, silicon oxynitride, carbon
Silica or carbon silicon oxynitride.In the present embodiment, the material of the first side wall film 107 is silicon nitride.
Unsuitable excessively thin, the width for the first side wall being otherwise subsequently formed of the thickness of the first side wall film 107
It is undersized so that the difference of the width dimensions of the first opening 106 and the second opening being subsequently formed is too small；
The thickness of the first side wall film 107 also should not blocked up, the width for the first side wall film being otherwise subsequently formed
It is oversized, and the first side wall film 107 formed is easily full by the filling of the first opening 106, causes to etch shape
Into.
Therefore, in the present embodiment, the thickness of the first side wall film 107 is 4~8 nanometers.
Unless otherwise instructed, the cross-sectional view subsequently provided is the schematic diagram on the basis of Fig. 3.
With reference to Fig. 7, the first graph layer 108 of the covering first area I the first side wall film 107 is formed.
The process of fin 102 of the first side wall film 107, second area II in subsequent etching second area II
In, first graph layer 108 plays protection first area I the first side wall film 107 and first area
The effect of I fin 102, and avoid the material in the second stressor layers of superficial growth of first area I fins 102
Material.
In the present embodiment, the material of first graph layer 108 is photoresist, forms first figure
The processing step of layer 108 includes：The first initial graphics layer is formed on the surface of the first side wall film 107；
Processing and development treatment are exposed to first initial graphics layer, removed positioned at second area II's
First initial graphics layer, forms first graph layer 106.
It should be noted that the present invention does not limit the material of the first graph layer 108, in other embodiments,
The material of first graph layer can also be hard mask material.
With reference to Fig. 8, using the first side wall film 107 that second area II is etched without mask etching technique, until
106 section bottom surfaces of the openings of second area II first are exposed, first in the second area II opens
Mouth 106 sidewall surfaces the first side wall 117 of formation.
During etching second area II the first side wall film 107, first graph layer 108 pair the
One region I the first side wall film 107 plays a protective role.
Described is dry etching without mask etching technique, the material of first side wall 117 is silicon nitride,
Silica, silicon oxynitride, carbon silicon oxynitride or boron nitride.
In the present embodiment, the material of first side wall 117 is silicon nitride, first side wall 117
Width dimensions are 4~8 nanometers.
After the first side wall 117 is formed, also have in the sidewall surfaces of second area II fins 102
The remaining material of first side wall film 107.
With reference to Fig. 9, the first 106 bottoms of opening exposed along the first side wall 117 of the second area II
Etching removes the substrate of second thickness downwards, formed below in the first opening 106 of the second area II
Second opening 109.
Specifically, the first 106 bottoms of opening exposed along the first side wall 117 of the second area II
Etching removes the fin 102 of second thickness downwards, below the first opening 106 of the second area II
The second opening 109 is formed, first opening 106 mutually runs through with the second opening 109.
What the width dimensions and the first opening 106 of second opening 109 were exposed by the first side wall 117
Width dimensions are consistent, therefore width of the width dimensions less than the first opening 106 of second opening 109
Size.
In the present embodiment, the depth of first opening 106 is 1~4 nanometer；Second opening 109
Depth be 15~30 nanometers.
The fin for the second thickness for being located at the lower section of the first opening 106 is etched using anisotropic etch process
102.In a specific embodiment, the anisotropic etching be reactive ion etching, the reaction from
The technological parameter of sub- etching technics is：Reacting gas includes CF4、SF6And Ar, CF4Flow is 50sccm
To 100sccm, SF6Flow be 10sccm to 100sccm, Ar flows be 100sccm to 300sccm,
Source power is 50 watts to 1000 watts, and bias power is 50 watts to 250 watts, and chamber pressure is 50 millitorrs
To 200 millitorrs, chamber temp is 20 degree to 90 degree.
With reference to Figure 10, the first side wall 117 (referring to Fig. 9) of the second area II is removed.
Using wet-etching technology, etching removes the first side wall 117 of the second area II.The present embodiment
In, the material of first side wall 117 is silicon nitride, and etching removes second area II the first side wall 117
Etch liquids be phosphoric acid solution, wherein, phosphoric acid quality percentage is 65% to 85%, and solution temperature is
120 degrees Celsius to 200 degrees Celsius.
With reference to Figure 11, formed the full second area II of filling the first 106 (referring to Figure 10) of opening and
Second stressor layers 142 of the second 109 (referring to Figure 10) of opening, and the second of the described first opening 106
The second lightly doped district (not indicating) is formed in stressor layers 142.
The material of second stressor layers 142 is SiGe, SiB, SiGeB, SiC, SiP or SiCP.Institute
State in the second stressor layers 142 doped with Doped ions, the Doped ions are N-type ion or p-type ion,
Wherein, N-type ion is P, As or Sb, and p-type ion is B, Ga or In, and positioned at the second opening
Doped ions concentration in 109 the second stressor layers 142 is more than the second stressor layers for being located at the first opening 106
Doped ions concentration in 142.
In the present embodiment, second stressor layers 142 are formed using epitaxy technique, and forming the second stress
Doped ions described in auto-dope in situ during layer 142, so as to form the mistake of the second stressor layers 142
Cheng Zhong, forms the second lightly doped district and the second heavily doped region, wherein, the second lightly doped district is located at first
In second stressor layers 142 of opening 106, the second heavily doped region is located at the second stress of the second opening 109
In layer 142, the second stressor layers with different Doped ions concentration are obtained by changing Doped ions concentration
142.For example, during the second stressor layers 142 are formed, change is passed through Doped ions source in reaction chamber
The flow of material, to change the Doped ions concentration in the second stressor layers 142.
In the present embodiment, second area II is NMOS area, and the material of the second stressor layers 142 is SiCP,
Second stressor layers 142 provide action of pulling stress for the channel region of NMOS area, so as to improve NMOS
Regional carrier mobility.The auto-dope P ion in situ during second stressor layers 142 are formed,
Wherein, the P ion concentration in the first opening 106 is less than the P ion being located in the second opening 109
Concentration.In the present embodiment, P ion concentration is 1E17 in the second stressor layers 142 of the first opening 106
atom/cm3To 1E20atom/cm3；P ion is dense in the second stressor layers 142 of the second opening 109
Spend for 1E20atom/cm3To 5E23atom/cm3。
In one embodiment, point on the direction of the first opening 106, be located at along the second opening 109
P ion concentration is first incremented by and successively decreased afterwards in second stressor layers 142 of the second opening 109, or, positioned at the
P ion concentration is identical in second stressor layers 142 of two openings 109, or, positioned at the second opening 109
The second stressor layers 142 in P ion increasing concen-trations.
In the present embodiment, second lightly doped district is formed while the second stressor layers 142 are formed, is kept away
The technique for exempting to be formed the second stressor layers 142 has undesirable effect to the second lightly doped district so that the of formation
Two lightly doped districts have better quality, and the electricity effect that the second lightly doped district is played is improved.Also,
The present embodiment carries out auto-dope in situ during the second stressor layers 142 are formed and forms the second heavily doped region,
Avoid and to form the ion implantation technology of the second heavily doped region implant damage is caused to the second lightly doped district.Together
When, because the width dimensions of the first opening 106 are bigger than the width dimensions of the second opening 109, described first
Opening 106 and the distance of second area II channel regions are near, so that the second stressor layers 142 put on ditch
The stress in road area is more notable, and then improves the carrier mobility of the device of second area II formation.
Then, first graph layer 108 is removed.In the present embodiment, the material of first graph layer 108
Expect for photoresist, using cineration technics or wet method degumming process, remove first graph layer 108.
With reference to Figure 12, the covering second grid structure 120, the second stressor layers 142 and second are formed
The second graph layer 118 of region II substrate surfaces.
The description of material and effect about second graph layer 118 refers to foregoing first graph layer 208
Description, will not be repeated here.In the present embodiment, the material of the second graph layer 118 is photoresist.
With reference to Figure 13, using (the reference of the first side wall film 107 that first area I is etched without mask etching technique
Figure 12), until 106 section bottom surfaces of the openings of first area I first are exposed, in the first area
I first opening 106 sidewall surfaces the first side wall 117 of formation；Then, along the of the first area I
Etching removes the substrates of second thickness to the first opening 106 that one side wall 117 exposes downwards, described the
One region I second opening 109 formed below of the first opening 106.
The material of first side wall 117 be silicon nitride, silica, silicon oxynitride, carbon silicon oxynitride or
Boron nitride.The width dimensions of first side wall 117 are 4~8 nanometers.
The description of the first side wall 117 and the second opening 109 about formation first area I refers to foregoing
Second area II the first side wall 117 and the description of the second opening 109 is formed, be will not be repeated here.
With reference to Figure 14, the first side wall 117 (referring to Figure 13) of the first area I is removed；Form filling
First 106 (referring to Figure 13) of opening of the full first area and the second 109 (referring to Figure 13) of opening
The first stressor layers 141, and form first in the first stressor layers 141 of the described first opening 106 and gently mix
Miscellaneous area.
Using wet-etching technology, etching removes the first side wall 117 of the first area I.
The material of first stressor layers 141 is SiGe, SiB, SiGeB, SiC, SiP or SiCP.Institute
State in the first stressor layers 141 doped with Doped ions, the Doped ions are N-type ion or p-type ion,
Wherein, N-type ion is P, As or Sb, and p-type ion is B, Ga or In, and positioned at the second opening
Doped ions concentration in 109 the first stressor layers 141 is more than the first stressor layers for being located at the first opening 106
Doped ions concentration in 141.
In the present embodiment, first stressor layers 141 are formed using epitaxy technique, and forming the first stress
Doped ions described in auto-dope in situ during layer 141, so as to form the mistake of the first stressor layers 141
Cheng Zhong, forms the first lightly doped district and the first heavily doped region, wherein, the first lightly doped district is located at first
In first stressor layers 141 of opening 106, the first heavily doped region is located at the first stress of the second opening 109
In layer 141, the first stressor layers with different Doped ions concentration are obtained by changing Doped ions concentration
141.For example, during the first stressor layers 141 are formed, change is passed through Doped ions source in reaction chamber
The flow of material, to change the Doped ions concentration in the first stressor layers 141.
In the present embodiment, first area I is PMOS area, and the material of the first stressor layers 141 is SiGeB,
First stressor layers 141 provide action of compressive stress for the channel region of PMOS area, so as to improve PMOS
Regional carrier mobility.The auto-dope B ions in situ during first stressor layers 141 are formed,
Wherein, the B ions that the B ion concentrations positioned at the first opening 106 are less than in the second opening 109 are dense
Degree.In the present embodiment, B ion concentrations are 1E17 in the first stressor layers 141 of the first opening 106
atom/cm3To 1E20atom/cm3；B ions are dense in the first stressor layers 141 of the second opening 109
Spend for 1E20atom/cm3To 5E23atom/cm3.In one embodiment, along second opening 109
On the direction for pointing to the first opening 106, the B ions in the first stressor layers 141 of the second opening 109
Concentration is first incremented by and successively decreased afterwards, or, B ions are dense in the first stressor layers 141 of the second opening 109
Degree is identical, or, B ion concentrations are incremented by the first stressor layers 109 of the second opening 109.
In the present embodiment, first lightly doped district is formed while the first stressor layers 141 are formed, is kept away
The technique for exempting to be formed the first stressor layers 141 has undesirable effect to the first lightly doped district so that the of formation
One lightly doped district has better quality, and the electricity effect that the first lightly doped district is played is improved.Also,
The present embodiment carries out auto-dope in situ during the first stressor layers 141 are formed and forms the first heavily doped region,
Avoid and to form the ion implantation technology of the first heavily doped region implant damage is caused to the first lightly doped district.Together
When, because the width dimensions of the first opening 106 are bigger than the width dimensions of the second opening 109, described first
Opening 106 and the distance of first area I channel regions are near, so that the first stressor layers 141 put on raceway groove
The stressor layers effect in area significantly, and then improves the carrier mobility of the device of first area I formation.
With reference to Figure 15,118 (referring to Figure 14) of the second graph layer are removed.
In the present embodiment, the material of the second graph layer 118 is photoresist, is removed photoresist using wet method or ash
Chemical industry skill, removes the second graph layer 118；Also remove first mask layer 121.
Follow-up processing step also includes：The 3rd side wall is formed on the gate structure sidewall surface；Then,
The stressor layers are carried out with ion implanting, the ion implanting is suitable to the sheet resistance of reduction stressor layers.Tool
Body, in the sidewall surfaces of first grid structure 110 the 3rd side wall of formation, the 3rd side wall covering
Part the first lightly doped district surface, so as to avoid ion implantation technology from entering the first lightly doped district surface
Row doping, the 3rd side wall also the second lightly doped district of covering part surface, so as to avoid ion implanting work
Skill is doped to the second lightly doped district surface；Then, on the surface of first grid structure 110
And the surface of the first stressor layers 141 forms the 3rd graph layer, the 3rd graph layer exposes the second stress
142 surface of layer and second grid structure 120；Second ion implanting is carried out to second stressor layers 142,
In the present embodiment, the second area II is NMOS area, the injection ion of second ion implanting
For N-type ion；Remove the 3rd graph layer；On the surface of second grid structure 120 and second
The surface of stressor layers 142 forms the 4th graph layer, and the 4th graph layer exposes the table of the first stressor layers 141
Face and the surface of first grid structure 110；First ion implanting is carried out to first stressor layers 141,
In the present embodiment, the first area I is PMOS area, the injection ion of first ion implanting
For p-type ion.
In the present embodiment, the first side wall of the first area and the first side wall of second area are successively suitable
Sequence formation, in other embodiments, the first side wall of the first area and the first side of second area
Wall can also be described in detail for what is formed simultaneously below with reference to accompanying drawing.Fig. 5,16 to Figure 20 are
The cross-sectional view for the semiconductor devices forming process that another embodiment of the present invention is provided.
With reference to Fig. 5 and Figure 16 is referred to, in the described first 106 bottoms of opening and sidewall surfaces, first grid
The surface of structure 110 and the surface of second grid structure 120 form the first side wall film 107；Carved using without mask
Etching technique etches the first side wall film 107, until the lower surface of the first opening 106 is exposed, described
First area I first opening 106 sidewall surfaces the first side wall 217 of formation, while in the second area
II first opening 106 sidewall surfaces the second side wall 217 of formation.
In the present embodiment, without in mask etching technique, the shape of the first side wall film 107 is being etched with along with
Into the first side wall 217 positioned at first area I and second area II.
With reference to Figure 17, the covering first grid structure 110, first area I the first opening 106 are formed
And the first graph layer 208 of first area I the first side wall 217；Along the first of the second area II
The first 106 bottoms of opening that side wall 217 exposes etch downwards the substrate for removing second thickness, described
Second area II second opening 209 formed below of the first opening 106.
Description about the first graph layer 208, second opening 209 refers to the respective description of previous embodiment,
It will not be repeated here.
With reference to Figure 18, the first side wall 217 (referring to Figure 17) of the second area II is removed；Formation is filled out
Second stressor layers 242 of the first opening 106 and the second opening 209 full of the second area II, and
The second lightly doped district is formed in the second stressor layers 242 of the described first opening 106.
Description about the second stressor layers 242 refers to the respective description of previous embodiment, no longer goes to live in the household of one's in-laws on getting married herein
State.
In the present embodiment, second lightly doped district is formed while the second stressor layers 242 are formed, is kept away
The technique for exempting to be formed the second stressor layers 242 has undesirable effect to the second lightly doped district so that the of formation
Two lightly doped districts have better quality, and the electricity effect that the second lightly doped district is played is improved.Also,
The present embodiment carries out auto-dope in situ during the second stressor layers 242 are formed and forms the second heavily doped region,
Avoid and to form the ion implantation technology of the second heavily doped region implant damage is caused to the second lightly doped district.Together
When, because the width dimensions of the first opening 106 are bigger than the width dimensions of the second opening 209, described first
Opening 106 and the distance of second area II channel regions are near, so that the second stressor layers 242 put on ditch
The stress in road area is more notable, and then improves the carrier mobility of the device of second area II formation.
Then, first graph layer 208 is removed.
With reference to Figure 19, the covering second grid structure 120, the second stressor layers 242 and second are formed
The second graph layer 218 of region II substrate surfaces；Then, along the first side wall 217 of the first area I
The first 106 bottoms of opening exposed etch downwards the substrate for removing second thickness, in the first area I
First opening 106 it is formed below second opening 209.
With reference to Figure 20, the first side wall 217 (referring to Figure 19) of the first area I is removed；Form filling
The full first area I the first 106 (referring to Figure 19) of opening and the second 209 (referring to Figure 19) of opening
The first stressor layers 241, and form first in the first stressor layers 241 of the described first opening 106 and gently mix
Miscellaneous area.
The material of first stressor layers 241 is SiGe, SiB, SiGeB, SiC, SiP or SiCP.Institute
State in the first stressor layers 241 doped with Doped ions, the Doped ions are N-type ion or p-type ion,
Wherein, N-type ion is P, As or Sb, and p-type ion is B, Ga or In, and positioned at the second opening
Doped ions concentration in 209 the first stressor layers 241 is more than the first stressor layers for being located at the first opening 106
Doped ions concentration in 241.
In the present embodiment, first stressor layers 241 are formed using epitaxy technique, and forming the first stress
Doped ions described in auto-dope in situ during layer 241, so as to form the mistake of the first stressor layers 241
Cheng Zhong, forms the first lightly doped district and the first heavily doped region, wherein, the first lightly doped district is located at first
In first stressor layers 241 of opening 106, the first heavily doped region is located at the first stress of the second opening 209
In layer 241, the first stressor layers with different Doped ions concentration are obtained by changing Doped ions concentration
241.For example, during the first stressor layers 241 are formed, change is passed through Doped ions source in reaction chamber
The flow of material, to change the Doped ions concentration in the first stressor layers 241.
Detailed description about the first stressor layers 241 refers to the respective description of previous embodiment, herein not
Repeat again.
In the present embodiment, first lightly doped district is formed while the first stressor layers 241 are formed, is kept away
The technique for exempting to be formed the first stressor layers 241 has undesirable effect to the first lightly doped district so that the of formation
One lightly doped district has better quality, and the electricity effect that the first lightly doped district is played is improved.Also,
The present embodiment carries out auto-dope in situ during the first stressor layers 241 are formed and forms the first heavily doped region,
Avoid and to form the ion implantation technology of the first heavily doped region implant damage is caused to the first lightly doped district.Together
When, because the width dimensions of the first opening 106 are bigger than the width dimensions of the second opening 209, described first
Opening 106 and the distance of first area I channel regions are near, so that the first stressor layers 241 put on raceway groove
The stressor layers effect in area significantly, and then improves the carrier mobility of the device of first area I formation.
After first stressor layers 241 are formed, 218 (referring to Figure 19) of the second graph layer are removed.
Follow-up processing step also includes：The 3rd side wall is formed on the gate structure sidewall surface；Then,
The stressor layers are carried out with ion implanting, the ion implanting is suitable to the sheet resistance of reduction stressor layers.Please
With reference to the corresponding description of previous embodiment, it will not be repeated here.
The explanation needed, the present embodiment so that the semiconductor devices that is formed is cmos device as an example,
In other embodiment, the semiconductor devices of formation can also be nmos device or PMOS device.
The present invention also provides a kind of semiconductor devices, with reference to Figure 20, including：
Substrate, the substrate surface is formed with grid structure；First thickness positioned at grid structure both sides
Intrabasement first opening；Second mutually run through below the described first opening and with the first opening opens
Mouthful, the width dimensions of second opening are less than the first A/F size；Full first opening of filling
Lightly doped district is formed with the stressor layers of the second opening, and the stressor layers of first opening.
So that the semiconductor devices of offer is cmos device as an example, it is described in detail below with reference to accompanying drawing.
In the present embodiment, the substrate includes first area I and second area II, the first area I are
PMOS area or NMOS area, the second area II be PMOS area or NMOS area,
And the first area I is different with second area II area type；The grid structure includes being located at the
The first grid structure 110 of one region I substrate surfaces and second positioned at second area II substrate surfaces
Grid structure 120, wherein, it is formed with the first area I substrates of the both sides of first grid structure 110
Shape in first opening and the second opening, the second area II substrates of the both sides of second grid structure 120
Into have the first opening and second opening；The stressor layers include the first stressor layers positioned at first area I
141 and the second stressor layers 142 positioned at second area II；The lightly doped district includes being located at first area
I the first lightly doped district and the second lightly doped district positioned at second area II.
In the present embodiment, the substrate includes：Substrate 101, the discrete fin positioned at the surface of substrate 101
102 and the separation layer 103 positioned at the surface of substrate 101 and the partial sidewall surface of fin 102, wherein,
The grid structure is across fin 102, and the atop part and sidewall surfaces of covering fin 102, and described the
One opening and the second opening are in the fin 102 of grid structure both sides.
The difference of the width dimensions of first opening and the width dimensions of the second opening is 4~8 nanometers；It is described
The depth of first opening is 1~4 nanometer；The depth of second opening is 15~30 nanometers.The stress
Doped with Doped ions in layer, the Doped ions are N-type ion or p-type ion, and are opened positioned at second
It is dense that Doped ions concentration in the stressor layers of mouth is more than the Doped ions being located in the stressor layers of the first opening
Degree.
In the present embodiment, the material of the first stressor layers 241 is SiGeB, and positioned at the first of the first opening
B ion concentrations in stressor layers 241 are less than the B ions being located in the first stressor layers 241 of the second opening
Concentration.The material of second stressor layers 242 is SiCP, and positioned at the second stressor layers 242 of the first opening
Interior P ion concentration is less than the P ion concentration being located in the second stressor layers 242 of the second opening.
Because the width dimensions of the first opening are bigger than the width dimensions of the second opening, first opening and the
The distance of one region I or second area II channel regions is near, so that the first stressor layers 241 or second should
The stress that power layer 242 puts on channel region is more notable, and then the carrier of raising semiconductor devices is moved
Shifting rate, improves the electric property of semiconductor devices.
Although present disclosure is as above, the present invention is not limited to this.Any those skilled in the art,
Without departing from the spirit and scope of the present invention, it can make various changes or modifications, therefore the guarantor of the present invention
Shield scope should be defined by claim limited range.
Claims (20)
1. a kind of method of improvement performance of semiconductor device, including:
Substrate is provided, the substrate surface is formed with grid structure；
Etching forms first and is open positioned at the substrate of the first thickness of the grid structure both sides；
The first side wall is formed on the first opening sidewalls surface；
The first open bottom exposed along first side wall etches downwards the substrate for removing second thickness,
It is open in the described first opening formed below second, and the width dimensions of second opening are opened less than first
The width dimensions of mouth；
Remove first side wall；
Form the stressor layers of completely described first opening of filling and the second opening, and answering in the described first opening
Lightly doped district is formed in power layer.
2. the method as described in claim 1, it is characterised in that the width dimensions of first side wall are 4~8
Nanometer；The depth of first opening is 1~4 nanometer；The depth of second opening is received for 15~30
Rice.
3. the method as described in claim 1, it is characterised in that the material of first side wall be silicon nitride,
Silica, silicon oxynitride, carbon silicon oxynitride or boron nitride.
4. the method as described in claim 1, it is characterised in that form the processing step bag of first side wall
Include：In first open bottom and sidewall surfaces the first side wall film of formation, the first side wall film is also
Positioned at grid structure surface and substrate surface；First side wall is etched using without mask etching technique
Film, until exposing the first opening portion lower surface, forms and is located at the first opening sidewalls surface
The first side wall.
5. the method as described in claim 1, it is characterised in that use wet-etching technology, etching removes institute
State the first side wall.
6. the method as described in claim 1, it is characterised in that doped with Doped ions in the stressor layers,
The Doped ions are N-type ion or p-type ion, and the doping being located in the stressor layers of the second opening
Ion concentration is more than the Doped ions concentration being located in the stressor layers of the first opening.
7. method as claimed in claim 6, it is characterised in that the stressor layers are formed using epitaxy technique,
And during stressor layers are formed Doped ions described in auto-dope in situ, and in the described second opening
Heavily doped region is formed in stressor layers.
8. method as claimed in claim 6, it is characterised in that the material of the stressor layers is SiGeB, and
The auto-dope B ions in situ during the stressor layers are formed, wherein, in the first opening
B ion concentrations are less than the B ion concentrations being located in the second opening.
9. method as claimed in claim 6, it is characterised in that the material of the stressor layers is SiCP, and
Auto-dope P ion in situ during the stressor layers is formed, wherein, the P in the first opening
Ion concentration is less than the P ion concentration being located in the second opening.
10. the method as described in claim 1, it is characterised in that the substrate includes first area and the secondth area
Domain, the first area is PMOS area or NMOS area, and the second area is PMOS
Region or NMOS area, and the first area is different with the area type of second area；The grid
Pole structure is included positioned at the first grid structure of first area substrate surface and positioned at second area substrate
The second grid structure on surface, wherein, shape in the first area substrate of the first grid structure both sides
Into having the first opening and the second opening, shape in the second area substrate of the second grid structure both sides
Into have the first opening and second opening；First side wall includes the first side wall positioned at first area
And positioned at the second side wall of second area；The stressor layers include the first stress positioned at first area
Layer and positioned at the second stressor layers of second area；The lightly doped district includes the positioned at first area
One lightly doped district and the second lightly doped district positioned at second area.
11. method as claimed in claim 10, it is characterised in that form the processing step bag of first opening
Include：Etching is located at second positioned at the substrate of the first thickness of first grid structure both sides while also etching
The substrate of the first thickness of grid structure both sides, in the substrate of the first area and second area
Substrate in formed first be open.
12. method as claimed in claim 10, it is characterised in that etch the first side using without mask etching technique
Wall film, forms first side wall, and the first side wall of first area and second area to be formed simultaneously,
Or sequencing formation.
13. method as claimed in claim 10, it is characterised in that form second opening and stressor layers
Processing step includes：First open bottom and sidewall surfaces, first grid body structure surface and
Second grid body structure surface the first side wall film of formation；Form the first side wall film of the covering first area
The first graph layer；Then, using the first side wall film that second area is etched without mask etching technique,
The first side wall is formed on the first opening sidewalls surface of the second area；Along the of the second area
The first open bottom that one side wall exposes etches downwards the substrate for removing second thickness, described second
First opening, second opening formed below in region；Remove the first side wall of the second area；Formed
First opening of the full second area of filling and the second stressor layers of the second opening, and described first
The second lightly doped district is formed in second stressor layers of opening；Remove first graph layer；Form covering
The second graph layer of the second grid structure, the second stressor layers and second area substrate surface；Connect
, using the first side wall film that first area is etched without mask etching technique, in the first area
First opening sidewalls surface forms the first side wall；Exposed along the first side wall of the first area
One Open Side Down etching remove second thickness substrate, the first area first opening under it is square
Into the second opening；Remove the first side wall of the first area；Form the full first area of filling
First stressor layers of the first opening and the second opening, and the shape in the first stressor layers of the described first opening
Into the first lightly doped district；Remove the second graph layer.
14. method as claimed in claim 10, it is characterised in that form second opening and stressor layers
Processing step includes：First open bottom and sidewall surfaces, first grid body structure surface and
Second grid body structure surface the first side wall film of formation；First side is etched using without mask etching technique
Wall film, until the first open bottom surface is exposed, the first opening sidewalls table in the first area
Face forms the first side wall, while forming the second side wall on the first opening sidewalls surface of the second area；
Form the covering first grid structure, the first opening of first area and the first side of first area
First graph layer of wall；Then, the first open bottom exposed along the first side wall of the second area
Portion etches downwards the substrate for removing second thickness, in the first opening formed below the of the second area
Two openings；Remove the first side wall of the second area；Form the first of the full second area of filling
Second stressor layers of opening and the second opening, and form the in the second stressor layers of the described first opening
Two lightly doped districts；Remove first graph layer；The formation covering second grid structure, second answer
The second graph layer of power layer and second area substrate surface；Then, along the of the first area
The first open bottom that one side wall exposes etches downwards the substrate for removing second thickness, described first
First opening, second opening formed below in region；Remove the first side wall of the first area；Formed
First opening of the full first area of filling and the first stressor layers of the second opening, and described first
The first lightly doped district is formed in first stressor layers of opening；Remove the second graph layer.
15. the method as described in claim 1, it is characterised in that the substrate includes：Substrate, positioned at substrate
The discrete fin on surface and the separation layer positioned at substrate surface and fin partial sidewall surface,
Wherein, the grid structure is across fin, and covers the atop part and sidewall surfaces of fin, described
First opening and the second opening are in the fin of grid structure both sides.
16. the method as described in claim 1, it is characterised in that after the stressor layers are formed, described
Gate structure sidewall surface forms the 3rd side wall；It is described to stress layer surface formation ion implanting
Ion implanting is suitable to reduce stressor layers surface contacted resistance.
17. a kind of semiconductor devices, it is characterised in that including：
Substrate, the substrate surface is formed with grid structure；
Positioned at intrabasement first opening of the first thickness of grid structure both sides；
Positioned at the described first opening lower section and the second opening mutually run through that is open with first, described second opens
The width dimensions of mouth are less than the first A/F size；
The stressor layers of filling full first opening and the second opening, and in the stressor layers of first opening
It is formed with lightly doped district.
18. semiconductor devices as claimed in claim 17, it is characterised in that the width dimensions of first opening
And the difference of the width dimensions of the second opening is 4~8 nanometers；The depth of first opening is 1~4 nanometer；
The depth of second opening is 15~30 nanometers.
19. semiconductor devices as claimed in claim 17, it is characterised in that doped with doping in the stressor layers
Ion, the Doped ions are N-type ion or p-type ion, and in the stressor layers of the second opening
Doped ions concentration be more than be located at first opening stressor layers in Doped ions concentration.
20. semiconductor devices as claimed in claim 17, it is characterised in that the substrate includes：Substrate, position
In substrate surface discrete fin and positioned at substrate surface and fin partial sidewall surface every
Absciss layer, wherein, the grid structure is across fin, and the atop part and sidewall surfaces of covering fin,
First opening and the second opening are in the fin of grid structure both sides.
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| CN109980003A (en) * | 2017-12-27 | 2019-07-05 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor devices and forming method thereof |
| CN114446812A (en) * | 2020-11-06 | 2022-05-06 | 长鑫存储技术有限公司 | Test structure and manufacturing method thereof |
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