CN106960789B - Semiconductor device and method for improving performance of semiconductor device - Google Patents
Semiconductor device and method for improving performance of semiconductor device Download PDFInfo
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- CN106960789B CN106960789B CN201610011819.7A CN201610011819A CN106960789B CN 106960789 B CN106960789 B CN 106960789B CN 201610011819 A CN201610011819 A CN 201610011819A CN 106960789 B CN106960789 B CN 106960789B
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66492—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a pocket or a lightly doped drain selectively formed at the side of the gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823814—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823821—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
- H01L29/7848—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain
Abstract
A semiconductor device and a method of improving performance of a semiconductor device, wherein the method of improving performance of a semiconductor device comprises: providing a substrate, wherein a grid structure is formed on the surface of the substrate; etching the substrate with the first thickness positioned at two sides of the grid structure to form a first opening; forming a first side wall on the surface of the side wall of the first opening; etching downwards along the bottom of the first opening exposed by the first side wall to remove the substrate with the second thickness, forming a second opening below the first opening, wherein the width dimension of the second opening is smaller than that of the first opening; removing the first side wall; and forming a stress layer filling the first opening and the second opening, and forming a lightly doped region in the stress layer of the first opening. The invention improves the stress action of the stress layer applied to the channel region, simultaneously improves the performance of the formed lightly doped region, avoids the lightly doped region from being etched and damaged by injected crystal lattices, and further improves the performance of the formed semiconductor device.
Description
Technical Field
The invention relates to the technical field of semiconductor manufacturing, in particular to a semiconductor device and a method for improving the performance of the semiconductor device.
Background
With the continuous development of semiconductor technology, the carrier mobility enhancement technology has been widely researched and applied, and improving the carrier mobility of a channel region can increase the driving current of an MOS device and improve the performance of the device.
In the existing semiconductor device manufacturing process, since the energy gap and carrier mobility of the silicon material can be changed by the stress, it is becoming a more and more common means to improve the performance of the MOS transistor by the stress. Specifically, by appropriately controlling the stress, the mobility of carriers (electrons in NMOS transistors, holes in PMOS transistors) can be increased, thereby increasing the driving current, thereby greatly improving the performance of MOS transistors.
At present, an Embedded germanium-silicon (Embedded SiGe) technology is adopted, i.e., a germanium-silicon material is formed in a region where a source region and a drain region need to be formed, and then doping is performed to form the source region and the drain region of a PMOS transistor; the silicon germanium material is formed to introduce compressive stress created by lattice mismatch between silicon and silicon germanium (SiGe) to improve the performance of the PMOS transistor. Adopting an Embedded carbon silicon (Embedded SiC) technology, namely forming a carbon silicon material in a region where a source region and a drain region need to be formed, and then doping to form the source region and the drain region of the NMOS transistor; the carbon-silicon material is formed to introduce a tensile stress resulting from lattice mismatch between silicon and carbon-silicon to improve the performance of the NMOS transistor.
The introduction of the embedded sige technology or the embedded carbo-si technology can improve the carrier mobility of the semiconductor device to some extent, but in practical applications, it is found that the electrical performance of the semiconductor device still needs to be improved.
Disclosure of Invention
The invention solves the problem of providing a semiconductor device and a method for improving the performance of the semiconductor device, which improves the carrier mobility of the semiconductor device and simultaneously improves the quality of a formed lightly doped region so as to improve the electrical performance of the formed semiconductor device.
To solve the above problems, the present invention provides a method for improving the performance of a semiconductor device, comprising: providing a substrate, wherein a grid structure is formed on the surface of the substrate; etching the substrate with the first thickness positioned at two sides of the grid structure to form a first opening; forming a first side wall on the surface of the side wall of the first opening; etching downwards along the bottom of the first opening exposed by the first side wall to remove the substrate with the second thickness, forming a second opening below the first opening, wherein the width dimension of the second opening is smaller than that of the first opening; removing the first side wall; and forming a stress layer filling the first opening and the second opening, and forming a lightly doped region in the stress layer of the first opening.
Optionally, the width of the first side wall is 4-8 nm; the depth of the first opening is 1-4 nanometers; the depth of the second opening is 15-30 nanometers.
Optionally, the first side wall is made of silicon nitride, silicon oxide, silicon oxynitride, silicon oxycarbonitride or boron nitride.
Optionally, the stress layer is doped with doped ions, the doped ions are N-type ions or P-type ions, and the concentration of the doped ions in the stress layer of the second opening is greater than that of the doped ions in the stress layer of the first opening.
Optionally, an epitaxial process is used to form the stress layer, and the dopant ions are in-situ self-doped in the process of forming the stress layer.
Optionally, the stress layer is made of SiGeB, and B ions are in-situ self-doped in the process of forming the stress layer, wherein the concentration of the B ions in the first opening is less than that in the second opening.
Optionally, the stress layer is made of SiCP, and P ions are self-doped in situ in the process of forming the stress layer, wherein the concentration of the P ions in the first opening is less than the concentration of the P ions in the second opening.
The present invention also provides a semiconductor device comprising: the device comprises a substrate, wherein a grid structure is formed on the surface of the substrate; the first opening is positioned in the substrate with the first thickness at two sides of the grid structure; the second opening is positioned below the first opening and mutually penetrates through the first opening, and the width dimension of the second opening is smaller than that of the first opening; and filling the stress layer of the first opening and the second opening, wherein a lightly doped region is formed in the stress layer of the first opening.
Compared with the prior art, the technical scheme of the invention has the following advantages:
in the technical scheme of the method for improving the performance of the semiconductor device, a substrate with a first thickness positioned at two sides of a grid structure is etched to form a first opening; forming a first side wall on the surface of the side wall of the first opening; etching downwards along the bottom of the first opening exposed by the first side wall to remove the substrate with the second thickness, forming a second opening below the first opening, wherein the width dimension of the second opening is smaller than that of the first opening; removing the first side wall; and forming a stress layer filling the first opening and the second opening, and forming a lightly doped region in the stress layer of the first opening. According to the invention, the lightly doped region is formed in the stress layer forming process, so that the formed lightly doped region keeps complete performance, and the formed lightly doped region is close to the channel region, so that the lightly doped region can play a stronger electrical role, and the electrical performance of the formed semiconductor device is improved. Meanwhile, the distance between the first opening and the channel region is short, so that the stress action of the stress layer on the channel region is enhanced, and the carrier mobility of the formed semiconductor device is improved.
Further, the stress layer is formed by adopting an epitaxial process, the doping ions are self-doped in situ in the process of forming the stress layer, and a heavily doped region is formed in the stress layer of the second opening. The process for forming the heavily doped region can not cause adverse effect on the lightly doped region, and the damage of the injected crystal lattice to the lightly doped region is avoided, so that the performance of the formed lightly doped region is further improved, and the performance of a semiconductor device is further improved.
The invention also provides a semiconductor device with excellent structural performance, wherein a first opening and a second opening which are mutually penetrated are formed in the substrate at two sides of the grid structure, the second opening is positioned below the first opening, and the width dimension of the second opening is smaller than that of the first opening; the stress layer filling the first opening and the second opening is further included, and a lightly doped region is formed in the stress layer of the first opening. Because the width dimension of the first opening is larger than that of the second opening, and the first opening is close to the channel region, the stress action applied to the channel region by the stress layer is more obvious, the carrier mobility of the semiconductor device is improved, and the performance of the semiconductor device is improved.
Drawings
Fig. 1 to 15 are schematic cross-sectional views illustrating a semiconductor device forming process according to an embodiment of the present invention;
fig. 16 to 20 are schematic cross-sectional views illustrating a semiconductor device forming process according to another embodiment of the present invention.
Detailed Description
As is known from the background art, the electrical performance of the semiconductor devices formed by the prior art still needs to be improved.
In order to introduce the embedded sige or embedded gsi technology, it is necessary to form a recess in the substrate on both sides of the gate structure first, and then fill the recess with sige material or gsi material. However, in the process of etching the substrate on the two sides of the gate structure to form the groove, the lightly doped regions on the two sides of the gate structure are partially or completely etched and removed, so that the electrical function of the lightly doped regions is deteriorated or even the lightly doped regions cannot play an electrical function, and further the electrical performance of the formed semiconductor device is poor.
To solve the above problems, the present invention provides a method for improving the performance of a semiconductor device, comprising: providing a substrate, wherein a grid structure is formed on the surface of the substrate; etching the substrate with the first thickness positioned at two sides of the grid structure to form a first opening; forming a first side wall on the surface of the side wall of the first opening; etching downwards along the bottom of the first opening exposed by the first side wall to remove the substrate with the second thickness, forming a second opening below the first opening, wherein the width dimension of the second opening is smaller than that of the first opening; removing the first side wall; and forming a stress layer filling the first opening and the second opening, and forming a lightly doped region in the stress layer of the first opening. According to the invention, the lightly doped region is formed in the stress layer forming process, and the formed lightly doped region is close to the channel region, so that the lightly doped region can play a stronger electrical role, and the electrical property of the formed semiconductor device is improved.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 1 to 15 are schematic cross-sectional views illustrating a semiconductor device forming process according to an embodiment of the invention.
Referring to fig. 1, a substrate is provided.
Taking the formed semiconductor device as a CMOS device as an example, the substrate includes a first region I and a second region II, the first region I is an NMOS region or a PMOS region, the second region II is an NMOS region or a PMOS region, and the types of the first region I and the second region II are different. In this embodiment, the first region I is a PMOS region, and the second region II is an NMOS region. In other embodiments, the first region is an NMOS region and the second region is a PMOS region. In another embodiment, the substrate can further include only a PMOS region or an NMOS region, and the correspondingly formed semiconductor device is a PMOS transistor or an NMOS transistor.
In this embodiment, taking the formed semiconductor device as a fin field effect transistor as an example, the substrate includes: a substrate 101, and a fin 102 on a surface of the substrate 101.
In another embodiment, the semiconductor device is a planar transistor, the base is a planar base, the planar base is a silicon substrate, a germanium substrate, a silicon germanium substrate or a silicon carbide substrate, a silicon-on-insulator substrate or a germanium-on-insulator substrate, a glass substrate or a III-V compound substrate (such as a gallium nitride substrate or a gallium arsenide substrate, etc.), and the gate structure is formed on the surface of the planar base.
The substrate 101 is made of silicon, germanium, silicon carbide, gallium arsenide or indium gallium arsenide, and the substrate 101 can also be a silicon-on-insulator substrate or a germanium-on-insulator substrate; the material of the fin 102 includes silicon, germanium, silicon carbide, gallium arsenide, or indium gallium arsenide. In this embodiment, the substrate 101 is a silicon substrate, and the fin portion 102 is made of silicon.
In this embodiment, the process steps for forming the substrate 101 and the fin portion 102 include: providing an initial substrate; forming a graphical hard mask layer on the surface of the initial substrate; and etching the initial substrate by taking the hard mask layer as a mask, wherein the etched initial substrate is taken as the substrate 101, and the protrusion on the surface of the substrate 101 is taken as the fin part 102.
The base further comprises an isolation layer 103 located on the surface of the substrate 101, the isolation layer 103 covers part of the sidewall surface of the fin portion 102, and the top of the isolation layer 103 is lower than the top of the fin portion 102. The isolation layer 103 plays a role of electrically isolating the adjacent fins 102, and the isolation layer 103 is made of an insulating material, such as silicon oxide, silicon nitride, silicon oxynitride, or silicon oxycarbonitride. In this embodiment, the isolation layer 103 is made of silicon oxide.
Referring to fig. 2, a gate structure is formed on the surface of the substrate.
In this embodiment, a first gate structure 110 is formed on the surface of the first region I substrate, and a second gate structure 120 is formed on the surface of the second region II substrate. Specifically, the first gate structure 110 is located on the surface of the first region I partial isolation layer 103, and crosses over the first region I fin 102, and also covers a part of the top surface and the sidewall surface of the first region I fin 102; the second gate structure 120 is located on the surface of the second region II portion of the isolation layer 103, and crosses over the second region II fin 102, and also covers a portion of the top surface and the sidewall surface of the second region II fin 102.
In an embodiment, the first gate structure 110 is a dummy gate structure (dummy gate), the first dummy gate structure 110 is removed in the following, and then a first actual gate structure of the semiconductor device is formed again at a position where the first gate structure 110 is located, where the first gate structure 110 is a single-layer structure or a stacked-layer structure, the first gate structure 110 includes a dummy gate layer, or the first gate structure 110 includes a dummy oxide layer and a dummy gate layer located on a surface of the dummy oxide layer, where the dummy gate layer is made of polysilicon or amorphous carbon, and the dummy oxide layer is made of silicon oxide or silicon oxynitride.
In another embodiment, the first gate structure 110 can also be an actual gate structure of a semiconductor device, and the first gate structure 110 includes a gate dielectric layer and a gate electrode layer located on a surface of the gate dielectric layer, where the gate dielectric layer is made of silicon oxide or a high-k gate dielectric material, the gate electrode layer is made of polysilicon or a metal material, and the metal material includes one or more of Ti, Ta, TiN, TaN, TiAl, TiAlN, Cu, Al, W, Ag, or Au.
The second gate structure 120 can also be a dummy gate structure or an actual gate structure of a semiconductor device.
Taking the first gate structure 110 and the second gate structure 120 as an example, the process steps for forming the first gate structure 110 and the second gate structure include: forming a gate dielectric film on the surface of the isolation layer 103, wherein the gate dielectric film stretches across the fin portion 102 and covers the top surface and the side wall surface of the fin portion 102; forming a gate electrode film on the surface of the gate dielectric film; forming a mask layer 104 on the surface of the gate electrode film, wherein the mask layer 104 defines the patterns of a first gate structure 110 and a second gate structure 120 to be formed; and patterning the gate electrode film and the gate dielectric film by taking the mask layer 104 as a mask, forming a first gate structure 110 on the surface of the first region I isolation layer 103, and forming a second gate structure 120 on the surface of the second region II isolation layer 103.
In this embodiment, the mask layer 104 on the top surface of the first gate structure 110 and the top surface of the second gate structure 120 is remained, so that the mask layer 104 plays a role in protecting the top of the first gate structure 110 and the top of the second gate structure 120 in the subsequent process. The material of the mask layer 104 is silicon nitride, silicon oxynitride, silicon carbide, or boron nitride, and in this embodiment, the material of the mask layer 104 is not limited.
Further comprising the steps of: second sidewalls 105 are formed on the sidewall surfaces of the first gate structure 110 and the second gate structure 120. The second sidewall 105 can protect the sidewall surface of the first gate structure 110 and the sidewall surface of the second gate structure 120, and can also keep a certain distance between the subsequently formed first lightly doped region and the sidewall surface of the first gate structure 110, and keep a certain distance between the subsequently formed second lightly doped region and the sidewall surface of the second gate structure 120.
The second side wall 105 is made of silicon oxide, silicon nitride or silicon oxynitride; the second sidewall 105 has a single-layer structure or a stacked structure. In this embodiment, the second sidewall 105 is made of silicon nitride; the method for forming the second side wall 105 includes: depositing a second sidewall film on the surface of the isolation layer 103, the surface of the first gate structure 110 and the surface of the second gate structure 120; and etching the second sidewall film by using a maskless etching process until the second sidewall films on the top of the first gate structure 110 and the top of the second gate structure 120 are etched and removed, the second sidewall film on the surface of part of the isolation layer 103 is etched and removed, and the rest second sidewall film is used as a second sidewall 105. It should be noted that, in other embodiments, the process step of forming the second sidewall spacer can also be omitted.
Referring to fig. 3 and 4, fig. 3 is a schematic view based on fig. 2, wherein fig. 3 is a schematic view of a cross-sectional structure parallel to an extending direction of the fin portion 102, fig. 4 is a schematic view of a cross-sectional structure perpendicular to the extending direction of the fin portion 102 in the first region I, a substrate with a first thickness on two sides of the gate structure is etched, and a first opening 106 is formed in the substrate.
In this embodiment, the first openings 106 are formed in the substrate on both sides of the first gate structure 110, the first opening 106 in the first region I is located in the fin portion 102 in the first region I, the first openings 106 are also formed in the substrate on both sides of the second gate structure 120, and the first opening 106 in the second region II is located in the fin portion 102 in the second region II.
And etching the substrates on two sides of the first gate structure 110 and two sides of the second gate structure 120 by using a dry etching process to form the first opening 106.
Specifically, a first mask layer 121 is formed on the surface of the isolation layer 103 and the surface of the fin portion 102; and etching and removing the fin parts 102 with the first thickness on the two sides of the first gate structure 110 by using the first mask layer 121 as a mask, forming first openings 106 in the first region I fin parts 102, simultaneously etching and removing the fin parts 102 with the first thickness on the two sides of the second gate structure 102, and forming the first openings 106 in the second region II fin parts 102.
In this embodiment, the first mask layer 121 is remained after the first opening 106 is formed, so that the first mask layer 121 on the surface of the fin 102 can block the growth of the first stress layer on the surface of the fin 102 in the subsequent process of forming the first stress layer.
The first mask layer 121 is silicon nitride, boron nitride, silicon carbonitride, titanium nitride, or tantalum nitride.
A first lightly doped region is formed in the first opening 106 of the first region I, and a second lightly doped region is formed in the first opening 106 of the second region II. Therefore, the depth of the first opening 106 is the same as the depth of the first lightly doped region to be formed and the depth of the second lightly doped region to be formed.
In this embodiment, the depth of the first opening 106 is 1-4 nm. Note that the dashed lines in fig. 4 show the top position and sidewall surface of the fin 102 before the first opening 106 is formed.
Referring to fig. 5 and 6, fig. 5 is a schematic view based on fig. 3, and fig. 6 is a schematic view based on fig. 4, wherein a first sidewall film 107 is formed on the bottom and sidewall surfaces of the first opening 106, the surface of the first gate structure 110, the surface of the second gate structure 120, and the substrate surface.
In this embodiment, the first sidewall film 107 covers the bottom and sidewall surfaces of the first opening 106, the surface of the first gate structure 110, the surface of the second gate structure 120, the surface of the fin 102, and the surface of the isolation layer 103. Since the formed first mask layer 121 is not removed, the first sidewall film 107 is still on the surface of the first mask layer 121.
The first sidewall film 107 is formed by a chemical vapor deposition process, a physical vapor deposition process, and an atomic layer deposition process. In order to improve the covering capability of the first sidewall film 107 at the bottom corner of the first opening 106 and make the coverage of the subsequently formed first sidewall at the bottom corner of the first opening 106 good, in this embodiment, an atomic layer deposition process is used to form the first sidewall film 107.
The first sidewall film 107 is made of boron nitride, silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, or silicon oxycarbonitride. In this embodiment, the first sidewall film 107 is made of silicon nitride.
The thickness of the first sidewall film 107 is not too thin, otherwise the width of the subsequently formed first sidewall is too small, so that the difference between the width of the first opening 106 and the width of the subsequently formed second opening is too small; the thickness of the first sidewall film 107 should not be too thick, otherwise the width of the subsequently formed first sidewall film is too large, and the first opening 106 is easily filled with the formed first sidewall film 107, resulting in etching formation.
Therefore, in this embodiment, the thickness of the first sidewall film 107 is 4 to 8 nm.
Unless otherwise stated, the cross-sectional structure diagrams provided subsequently are all schematic diagrams based on fig. 3.
Referring to fig. 7, a first graphic layer 108 of a first sidewall film 107 covering the first region I is formed.
In the subsequent etching process of the first sidewall film 107 in the second region II and the fin portion 102 in the second region II, the first pattern layer 108 plays a role in protecting the first sidewall film 107 in the first region I and the fin portion 102 in the first region I, and prevents a material of a second stress layer from growing on the surface of the fin portion 102 in the first region I.
In this embodiment, the material of the first pattern layer 108 is a photoresist, and the process for forming the first pattern layer 108 includes: forming a first initial pattern layer on the surface of the first sidewall film 107; and performing exposure processing and development processing on the first initial graphic layer, and removing the first initial graphic layer positioned in the second area II to form the first graphic layer 106.
It should be noted that the invention is not limited to the material of the first pattern layer 108, and in other embodiments, the material of the first pattern layer can also be a hard mask material.
Referring to fig. 8, the first sidewall film 107 in the second region II is etched by a maskless etching process until a portion of the bottom surface of the first opening 106 in the second region II is exposed, and a first sidewall 117 is formed on the sidewall surface of the first opening 106 in the second region II.
During the process of etching the first sidewall film 107 in the second region II, the first pattern layer 108 protects the first sidewall film 107 in the first region I.
The maskless etching process is dry etching, and the first sidewall 117 is made of silicon nitride, silicon oxide, silicon oxynitride, silicon oxycarbonitride or boron nitride.
In this embodiment, the first sidewall 117 is made of silicon nitride, and the width of the first sidewall 117 is 4 to 8 nanometers.
After the first sidewall 117 is formed, the second region II fin 102 has a remaining first sidewall film 107 material on the sidewall surface.
Referring to fig. 9, a second thickness of the substrate is etched and removed downward along the bottom of the first opening 106 exposed by the first sidewall 117 of the second region II, and a second opening 109 is formed below the first opening 106 of the second region II.
Specifically, the fin portion 102 with the second thickness is etched and removed downward along the bottom of the first opening 106 exposed by the first sidewall 117 of the second region II, a second opening 109 is formed below the first opening 106 of the second region II, and the first opening 106 and the second opening 109 penetrate through each other.
The width of the second opening 109 is the same as the width of the first opening 106 exposed by the first sidewall 117, so the width of the second opening 109 is smaller than the width of the first opening 106.
In this embodiment, the depth of the first opening 106 is 1-4 nm; the depth of the second opening 109 is 15-30 nanometers.
The second thickness of the fin 102 below the first opening 106 is etched using an anisotropic etch process. In a specific embodiment, the anisotropic etching is reactive ion etching, and the process parameters of the reactive ion etching process are as follows: the reaction gas comprises CF4、SF6And Ar, CF4The flow rate is 50sccm to 100sccm, SF6The flow rate is 10sccm to 100sccm, the flow rate of Ar is 100sccm to 300sccm, the source power is 50 watts to 1000 watts, the bias power is 50 watts to 250 watts, the chamber pressure is 50 mTorr to 200 mTorr, and the chamber temperature is 20 ℃ to 90 ℃.
Referring to fig. 10, the first sidewall 117 (refer to fig. 9) of the second region II is removed.
And etching to remove the first side wall 117 of the second area II by using a wet etching process. In this embodiment, the first sidewall 117 is made of silicon nitride, and the etching liquid for removing the first sidewall 117 in the second region II by etching is phosphoric acid solution, wherein the phosphoric acid is 65% to 85% by mass, and the solution temperature is 120 ℃ to 200 ℃.
Referring to fig. 11, a second stress layer 142 is formed to fill the first opening 106 (refer to fig. 10) and the second opening 109 (refer to fig. 10) in the second region II, and a second lightly doped region (not shown) is formed in the second stress layer 142 of the first opening 106.
The second stress layer 142 is made of SiGe, SiB, SiGeB, SiC, SiP, or SiCP. The second stress layer 142 is doped with dopant ions, the dopant ions are N-type ions or P-type ions, the N-type ions are P, As or Sb, the P-type ions are B, Ga or In, and the dopant ion concentration In the second stress layer 142 of the second opening 109 is greater than the dopant ion concentration In the second stress layer 142 of the first opening 106.
In this embodiment, the second stress layer 142 is formed by an epitaxial process, and the dopant ions are self-doped in situ during the process of forming the second stress layer 142, so that a second lightly doped region and a second heavily doped region are formed during the process of forming the second stress layer 142, wherein the second lightly doped region is located in the second stress layer 142 of the first opening 106, the second heavily doped region is located in the second stress layer 142 of the second opening 109, and the second stress layer 142 with different dopant ion concentrations is obtained by changing the dopant ion concentration. For example, during the formation of the second stress layer 142, the flow rate of the dopant ion source material introduced into the reaction chamber is changed to change the dopant ion concentration in the second stress layer 142.
In this embodiment, the second region II is an NMOS region, the material of the second stress layer 142 is SiCP, and the second stress layer 142 provides a tensile stress effect for a channel region of the NMOS region, so as to improve carrier mobility of the NMOS region. In-situ autodoping P ions during the formation of the second stress layer 142, whereinThe P ion concentration in the first opening 106 is smaller than the P ion concentration in the second opening 109. In this embodiment, the concentration of P ions in the second stress layer 142 in the first opening 106 is 1E17atom/cm3To 1E20atom/cm3(ii) a The P ion concentration in the second stress layer 142 in the second opening 109 is 1E20atom/cm3To 5E23atom/cm3。
In one embodiment, in a direction pointing to the first opening 106 along the second opening 109, the concentration of P ions in the second stress layer 142 of the second opening 109 increases first and then decreases, or the concentration of P ions in the second stress layer 142 of the second opening 109 is the same, or the concentration of P ions in the second stress layer 142 of the second opening 109 increases.
In this embodiment, the second lightly doped region is formed while the second stress layer 142 is formed, so that adverse effects on the second lightly doped region caused by a process for forming the second stress layer 142 are avoided, the formed second lightly doped region has higher quality, and the electrical effect of the second lightly doped region is improved. In addition, in the embodiment, in-situ self-doping is performed during the process of forming the second stress layer 142 to form the second heavily doped region, so that implantation damage to the second lightly doped region caused by an ion implantation process for forming the second heavily doped region is avoided. Meanwhile, since the width of the first opening 106 is larger than that of the second opening 109, the distance between the first opening 106 and the channel region of the second region II is short, so that the stress action applied to the channel region by the second stress layer 142 is more significant, and the carrier mobility of the device formed in the second region II is improved.
The first graphics layer 108 is then removed. In this embodiment, the first pattern layer 108 is made of a photoresist, and the first pattern layer 108 is removed by an ashing process or a wet stripping process.
Referring to fig. 12, a second pattern layer 118 is formed to cover the second gate structure 120, the second stress layer 142 and the second region II substrate surface.
The description of the materials and functions of the second graphic layer 118 can refer to the description of the first graphic layer 208, and will not be repeated herein. In this embodiment, the second pattern layer 118 is made of photoresist.
Referring to fig. 13, the first sidewall film 107 (see fig. 12) in the first region I is etched by a maskless etching process until a portion of the bottom surface of the first opening 106 in the first region I is exposed, and a first sidewall 117 is formed on the sidewall surface of the first opening 106 in the first region I; and then, etching downwards along the first opening 106 exposed by the first sidewall 117 of the first region I to remove the substrate with the second thickness, and forming a second opening 109 below the first opening 106 of the first region I.
The first side wall 117 is made of silicon nitride, silicon oxide, silicon oxynitride, silicon oxycarbonitride or boron nitride. The width of the first side wall 117 is 4-8 nm.
For the description of forming the first sidewall 117 and the second opening 109 of the first region I, reference may be made to the description of forming the first sidewall 117 and the second opening 109 of the second region II, which is not repeated herein.
Referring to fig. 14, the first sidewall 117 (refer to fig. 13) of the first region I is removed; a first stress layer 141 filling the first opening 106 (refer to fig. 13) and the second opening 109 (refer to fig. 13) of the first region is formed, and a first lightly doped region is formed in the first stress layer 141 of the first opening 106.
And etching to remove the first side wall 117 of the first area I by adopting a wet etching process.
The first stress layer 141 is made of SiGe, SiB, SiGeB, SiC, SiP, or SiCP. The first stress layer 141 is doped with dopant ions, which are N-type ions or P-type ions, wherein the N-type ions are P, As or Sb, the P-type ions are B, Ga or In, and the concentration of the dopant ions In the first stress layer 141 of the second opening 109 is greater than the concentration of the dopant ions In the first stress layer 141 of the first opening 106.
In this embodiment, the first stress layer 141 is formed by an epitaxial process, and the dopant ions are self-doped in situ during the formation of the first stress layer 141, so that a first lightly doped region and a first heavily doped region are formed during the formation of the first stress layer 141, wherein the first lightly doped region is located in the first stress layer 141 of the first opening 106, the first heavily doped region is located in the first stress layer 141 of the second opening 109, and the first stress layer 141 with different dopant ion concentrations is obtained by changing the dopant ion concentration. For example, during the formation of the first stressor layer 141, the flow of dopant ion source material into the reaction chamber is varied to change the dopant ion concentration in the first stressor layer 141.
In this embodiment, the first region I is a PMOS region, the first stress layer 141 is made of SiGeB, and the first stress layer 141 provides a compressive stress effect for a channel region of the PMOS region, so as to improve carrier mobility of the PMOS region. B ions are in-situ self-doped during the formation of the first stress layer 141, wherein the concentration of the B ions in the first opening 106 is less than the concentration of the B ions in the second opening 109. In this embodiment, the concentration of B ions in the first stress layer 141 in the first opening 106 is 1E17atom/cm3To 1E20atom/cm3(ii) a The concentration of B ions in the first stress layer 141 in the second opening 109 is 1E20atom/cm3To 5E23atom/cm3. In one embodiment, in the direction pointing to the first opening 106 along the second opening 109, the concentration of B ions in the first stress layer 141 of the second opening 109 increases first and then decreases, or the concentration of B ions in the first stress layer 141 of the second opening 109 is the same, or the concentration of B ions in the first stress layer 109 of the second opening 109 increases.
In this embodiment, the first lightly doped region is formed while the first stress layer 141 is formed, so that the first lightly doped region is prevented from being adversely affected by the process of forming the first stress layer 141, the formed first lightly doped region has high quality, and the electrical function of the first lightly doped region is improved. In addition, in the embodiment, in-situ self-doping is performed during the process of forming the first stress layer 141 to form the first heavily doped region, so that implantation damage to the first lightly doped region caused by an ion implantation process for forming the first heavily doped region is avoided. Meanwhile, since the width of the first opening 106 is larger than that of the second opening 109, the distance between the first opening 106 and the channel region of the first region I is short, so that the stress layer effect of the first stress layer 141 on the channel region is more significant, and the carrier mobility of the device formed in the first region I is improved.
Referring to fig. 15, the second graphic layer 118 (refer to fig. 14) is removed.
In this embodiment, the second pattern layer 118 is made of a photoresist, and the second pattern layer 118 is removed by a wet photoresist removal or ashing process; the first mask layer 121 is also removed.
The subsequent process steps further comprise: forming a third side wall on the surface of the side wall of the grid structure; and then, carrying out ion implantation on the stress layer, wherein the ion implantation is suitable for reducing the surface resistance of the stress layer. Specifically, a third side wall is formed on the surface of the side wall of the first gate structure 110, the third side wall covers a part of the surface of the first lightly doped region, so as to prevent the ion implantation process from doping the surface of the first lightly doped region, and the third side wall also covers a part of the surface of the second lightly doped region, so as to prevent the ion implantation process from doping the surface of the second lightly doped region; then, forming a third graphic layer on the surface of the first gate structure 110 and the surface of the first stress layer 141, wherein the third graphic layer exposes the surface of the second stress layer 142 and the second gate structure 120; performing second ion implantation on the second stress layer 142, in this embodiment, the second region II is an NMOS region, and the implanted ions of the second ion implantation are N-type ions; removing the third graphic layer; forming a fourth graphic layer on the surface of the second gate structure 120 and the surface of the second stress layer 142, wherein the fourth graphic layer exposes the surface of the first stress layer 141 and the surface of the first gate structure 110; a first ion implantation is performed on the first stress layer 141, in this embodiment, the first region I is a PMOS region, and the implanted ions of the first ion implantation are P-type ions.
In this embodiment, the first sidewall of the first region and the first sidewall of the second region are sequentially formed, in other embodiments, the first sidewall of the first region and the first sidewall of the second region may also be simultaneously formed, and the following detailed description will be given with reference to the accompanying drawings. Fig. 5, 16 to 20 are schematic cross-sectional views illustrating a semiconductor device forming process according to another embodiment of the present invention.
With reference to fig. 5 and fig. 16, a first sidewall film 107 is formed on the bottom and sidewall surfaces of the first opening 106, the surface of the first gate structure 110, and the surface of the second gate structure 120; and etching the first sidewall film 107 by using a maskless etching process until the bottom surface of the first opening 106 is exposed, forming a first sidewall 217 on the sidewall surface of the first opening 106 in the first region I, and forming a second sidewall 217 on the sidewall surface of the first opening 106 in the second region II.
In this embodiment, the first sidewall film 107 is etched to form the first sidewall 217 in the first region I and the second region II in the same maskless etching process.
Referring to fig. 17, a first pattern layer 208 covering the first gate structure 110, the first opening 106 of the first region I, and the first sidewall 217 of the first region I is formed; and etching and removing the substrate with the second thickness downwards along the bottom of the first opening 106 exposed by the first side wall 217 of the second area II, and forming a second opening 209 below the first opening 106 of the second area II.
For the description of the first graphic layer 208 and the second opening 209, reference may be made to the corresponding description of the previous embodiment, and further description is omitted here.
Referring to fig. 18, the first sidewall 217 of the second region II is removed (refer to fig. 17); forming a second stress layer 242 filling the first opening 106 and the second opening 209 of the second region II, and forming a second lightly doped region in the second stress layer 242 of the first opening 106.
For the description of the second stress layer 242, reference may be made to the corresponding description of the previous embodiment, and further description is omitted here.
In this embodiment, the second lightly doped region is formed while the second stress layer 242 is formed, so that adverse effects on the second lightly doped region caused by the process of forming the second stress layer 242 are avoided, the formed second lightly doped region has higher quality, and the electrical effect of the second lightly doped region is improved. In addition, in the present embodiment, in the process of forming the second stress layer 242, in-situ self-doping is performed to form the second heavily doped region, so that implantation damage to the second lightly doped region due to the ion implantation process for forming the second heavily doped region is avoided. Meanwhile, since the width of the first opening 106 is larger than that of the second opening 209, the distance between the first opening 106 and the channel region of the second region II is short, so that the stress action applied to the channel region by the second stress layer 242 is more significant, and the carrier mobility of the device formed in the second region II is improved.
Then, the first graphics layer 208 is removed.
Referring to fig. 19, a second graphic layer 218 covering the second gate structure 120, the second stress layer 242, and the second region II substrate surface is formed; and then, etching downwards along the bottom of the first opening 106 exposed by the first sidewall 217 of the first region I to remove the substrate with the second thickness, and forming a second opening 209 below the first opening 106 of the first region I.
Referring to fig. 20, the first side walls 217 of the first region I are removed (refer to fig. 19); a first stress layer 241 filling the first opening 106 (refer to fig. 19) and the second opening 209 (refer to fig. 19) of the first region I is formed, and a first lightly doped region is formed within the first stress layer 241 of the first opening 106.
The first stress layer 241 is made of SiGe, SiB, SiGeB, SiC, SiP, or SiCP. The first stress layer 241 is doped with doped ions, the doped ions are N-type ions or P-type ions, wherein the N-type ions are P, As or Sb, the P-type ions are B, Ga or In, and the concentration of the doped ions In the first stress layer 241 of the second opening 209 is greater than the concentration of the doped ions In the first stress layer 241 of the first opening 106.
In this embodiment, the first stress layer 241 is formed by an epitaxial process, and the doped ions are self-doped in situ during the process of forming the first stress layer 241, so that a first lightly doped region and a first heavily doped region are formed during the process of forming the first stress layer 241, wherein the first lightly doped region is located in the first stress layer 241 of the first opening 106, the first heavily doped region is located in the first stress layer 241 of the second opening 209, and the first stress layer 241 with different doped ion concentrations is obtained by changing the doped ion concentration. For example, during the formation of the first stress layer 241, the flow of the dopant ion source material into the reaction chamber is changed to change the dopant ion concentration in the first stress layer 241.
For a detailed description of the first stress layer 241, reference may be made to the corresponding description of the previous embodiment, and further description is omitted here.
In this embodiment, the first lightly doped region is formed while the first stress layer 241 is formed, so that the first lightly doped region is prevented from being adversely affected by the process of forming the first stress layer 241, the formed first lightly doped region has high quality, and the electrical function of the first lightly doped region is improved. In addition, in the present embodiment, in the process of forming the first stress layer 241, in-situ self-doping is performed to form the first heavily doped region, so that implantation damage to the first lightly doped region due to an ion implantation process for forming the first heavily doped region is avoided. Meanwhile, since the width of the first opening 106 is larger than that of the second opening 209, the distance between the first opening 106 and the channel region of the first region I is short, so that the stress layer applied to the channel region by the first stress layer 241 has a more significant effect, and the carrier mobility of the device formed in the first region I is improved.
After the first stress layer 241 is formed, the second graphic layer 218 is removed (refer to fig. 19).
The subsequent process steps further comprise: forming a third side wall on the surface of the side wall of the grid structure; and then, carrying out ion implantation on the stress layer, wherein the ion implantation is suitable for reducing the surface resistance of the stress layer. Please refer to the corresponding description of the previous embodiment, which is not repeated herein.
It should be noted that, in this embodiment, the formed semiconductor device is taken as an example of a CMOS device, and in other embodiments, the formed semiconductor device can also be an NMOS device or a PMOS device.
The present invention also provides a semiconductor device, referring to fig. 20, including:
the device comprises a substrate, wherein a grid structure is formed on the surface of the substrate; the first opening is positioned in the substrate with the first thickness at two sides of the grid structure; the second opening is positioned below the first opening and mutually penetrates through the first opening, and the width dimension of the second opening is smaller than that of the first opening; and filling the stress layer of the first opening and the second opening, wherein a lightly doped region is formed in the stress layer of the first opening.
Taking the provided semiconductor device as a CMOS device as an example, the following will be described in detail with reference to the accompanying drawings.
In this embodiment, the substrate includes a first region I and a second region II, the first region I is a PMOS region or an NMOS region, the second region II is a PMOS region or an NMOS region, and the first region I and the second region II are different in region type; the gate structure comprises a first gate structure 110 positioned on the surface of a first region I substrate and a second gate structure 120 positioned on the surface of a second region II substrate, wherein a first opening and a second opening are formed in the first region I substrate on two sides of the first gate structure 110, and a first opening and a second opening are formed in the second region II substrate on two sides of the second gate structure 120; the stress layers comprise a first stress layer 141 positioned in a first region I and a second stress layer 142 positioned in a second region II; the lightly doped region comprises a first lightly doped region positioned in the first region I and a second lightly doped region positioned in the second region II.
In this embodiment, the substrate includes: the semiconductor device comprises a substrate 101, a discrete fin 102 located on the surface of the substrate 101, and an isolation layer 103 located on the surface of the substrate 101 and on a part of the sidewall surface of the fin 102, wherein the gate structure crosses over the fin 102 and covers a part of the top and sidewall surface of the fin 102, and the first opening and the second opening are located in the fin 102 on both sides of the gate structure.
The difference between the width of the first opening and the width of the second opening is 4-8 nm; the depth of the first opening is 1-4 nanometers; the depth of the second opening is 15-30 nanometers. Doped ions are doped in the stress layer, the doped ions are N-type ions or P-type ions, and the concentration of the doped ions in the stress layer of the second opening is greater than that of the doped ions in the stress layer of the first opening.
In this embodiment, the first stress layer 241 is made of SiGeB, and the concentration of B ions in the first stress layer 241 of the first opening is less than the concentration of B ions in the first stress layer 241 of the second opening. The material of the second stress layer 242 is SiCP, and the concentration of P ions in the second stress layer 242 of the first opening is less than the concentration of P ions in the second stress layer 242 of the second opening.
Because the width dimension of the first opening is larger than that of the second opening, and the distance between the first opening and the channel region of the first region I or the second region II is close, the stress action exerted on the channel region by the first stress layer 241 or the second stress layer 242 is more remarkable, so that the carrier mobility of the semiconductor device is improved, and the electrical performance of the semiconductor device is improved.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (14)
1. A method of improving performance of a semiconductor device, comprising:
providing a substrate, wherein the substrate comprises a first region and a second region, and a gate structure is formed on the surface of the substrate;
etching the substrate with the first thickness on two sides of the gate structure to form a first opening, wherein the gate structure comprises a first gate structure on the surface of the substrate in the first area and a second gate structure on the surface of the substrate in the second area;
forming a first side wall film on the bottom and the side wall surface of the first opening, wherein the first side wall film is also positioned on the surface of the grid structure and the surface of the substrate;
forming a first graphic layer of a first sidewall film covering the first region;
etching the first side wall film of the second area by using a maskless etching process until the bottom surface of the first opening part of the second area is exposed, and forming a first side wall positioned on the surface of the side wall of the first opening of the second area;
etching downwards along the bottom of the first opening exposed by the first side wall of the second area to remove the substrate with the second thickness, forming a second opening below the first opening of the second area, wherein the width dimension of the second opening is smaller than that of the first opening;
removing the first side wall of the second area;
forming a second stress layer which fills the first opening and the second opening of the second area, and forming a second lightly doped region in the second stress layer of the first opening;
forming a second graphic layer covering the second gate structure, the second stress layer and the surface of the second area substrate;
etching the first side wall film of the first area by using a maskless etching process until the bottom surface of the first opening part of the first area is exposed, and forming a first side wall on the surface of the side wall of the first opening of the first area;
etching downwards along the first opening exposed by the first side wall of the first area to remove the substrate with the second thickness, and forming a second opening below the first opening of the first area;
removing the first side wall of the first area;
forming a first stress layer which fills the first opening and the second opening of the first area, and forming a first lightly doped region in the first stress layer of the first opening;
and removing the second graphic layer.
2. The method of claim 1, wherein the width of the first sidewall is 4-8 nm; the depth of the first opening is 1-4 nanometers; the depth of the second opening is 15-30 nanometers.
3. The method of claim 1, wherein the material of the first sidewall spacers is silicon nitride, silicon oxide, silicon oxynitride, silicon oxycarbonitride, or boron nitride.
4. The method of claim 1, wherein the first sidewall spacers are etched away using a wet etch process.
5. The method of claim 1, wherein the first stressed layer and/or the second stressed layer is doped with dopant ions, the dopant ions are N-type ions or P-type ions, and the concentration of the dopant ions in the stressed layer of the second opening is greater than the concentration of the dopant ions in the stressed layer of the first opening.
6. The method of claim 5, wherein the first stress layer and/or the second stress layer is formed by an epitaxial process, and wherein the dopant ions are in-situ self-doped during the formation of the first stress layer and/or the second stress layer, and wherein a heavily doped region is formed within the stress layer of the second opening.
7. The method of claim 5, wherein the first stress layer and/or the second stress layer is SiGeB, and is in-situ autodoped with B ions during the formation of the first stress layer and/or the second stress layer, wherein the concentration of the B ions in the first opening is less than the concentration of the B ions in the second opening.
8. The method of claim 5, wherein the first stress layer and/or the second stress layer is SiCP and is in-situ self-doped with P ions during the formation of the first stress layer and/or the second stress layer, wherein a concentration of the P ions in the first opening is less than a concentration of the P ions in the second opening.
9. The method of claim 1, wherein the first region is a PMOS region or an NMOS region, the second region is a PMOS region or an NMOS region, and the region types of the first region and the second region are different; a first opening and a second opening are formed in the first area substrate on two sides of the first gate structure, and a first opening and a second opening are formed in the second area substrate on two sides of the second gate structure; the first side wall comprises a first side wall positioned in the first area and a first side wall positioned in the second area; the stress layer comprises a first stress layer positioned in the first region and a second stress layer positioned in the second region; the lightly doped region comprises a first lightly doped region positioned in the first region and a second lightly doped region positioned in the second region.
10. The method of claim 9, wherein the process step of forming the first opening comprises: and etching the substrates with the first thickness positioned at two sides of the first gate structure, simultaneously etching the substrates with the first thickness positioned at two sides of the second gate structure, and forming first openings in the substrates of the first area and the second area.
11. The method of claim 9, wherein the first sidewall film is etched by a maskless etching process to form the first sidewall, and the first sidewalls of the first region and the second region are sequentially formed.
12. The method of claim 9, wherein the process step of forming the second opening and stress layer comprises: forming a first side wall film on the bottom and the side wall surface of the first opening, the surface of the first grid structure and the surface of the second grid structure; forming a first graphic layer of a first sidewall film covering the first region; then, etching the first side wall film of the second area by using a maskless etching process, and forming a first side wall on the surface of the side wall of the first opening of the second area; etching downwards along the bottom of the first opening exposed by the first side wall of the second area to remove the substrate with the second thickness, and forming a second opening below the first opening of the second area; removing the first side wall of the second area; forming a second stress layer which fills the first opening and the second opening of the second area, and forming a second lightly doped region in the second stress layer of the first opening; removing the first graphic layer; forming a second graphic layer covering the second gate structure, the second stress layer and the surface of the second area substrate; then, etching the first side wall film of the first area by using a maskless etching process, and forming a first side wall on the surface of the side wall of the first opening of the first area; etching downwards along the first opening exposed by the first side wall of the first area to remove the substrate with the second thickness, and forming a second opening below the first opening of the first area; removing the first side wall of the first area; forming a first stress layer which fills the first opening and the second opening of the first area, and forming a first lightly doped region in the first stress layer of the first opening; and removing the second graphic layer.
13. The method of claim 1, wherein the substrate comprises: the gate structure is arranged on the substrate, the fin portion is located on the surface of the substrate, the isolation layer is located on the surface of the substrate and on the surface of the partial side wall of the fin portion, the gate structure stretches across the fin portion and covers the partial top of the fin portion and the surface of the side wall of the fin portion, and the first opening and the second opening are located in the fin portion on two sides of the gate structure.
14. The method of claim 1, wherein after the first stress layer and/or the second stress layer are formed, third side walls are formed on the surface of the side walls of the gate structure; and forming ion implantation on the surface of the first stress layer and/or the second stress layer, wherein the ion implantation is suitable for reducing the contact resistance of the surface of the stress layer.
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