CN107403835B - Semiconductor device and manufacturing process thereof - Google Patents

Semiconductor device and manufacturing process thereof Download PDF

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Publication number
CN107403835B
CN107403835B CN201610340188.3A CN201610340188A CN107403835B CN 107403835 B CN107403835 B CN 107403835B CN 201610340188 A CN201610340188 A CN 201610340188A CN 107403835 B CN107403835 B CN 107403835B
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substrate
spacer
trench
semiconductor device
epitaxial
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CN107403835A (en
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刘升旭
李镇全
吕水烟
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United Semi Integrated Circuit Manufacture Xiamen Co ltd
United Microelectronics Corp
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United Semi Integrated Circuit Manufacture Xiamen Co ltd
United Microelectronics Corp
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Priority to US15/186,523 priority patent/US20170338327A1/en
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Abstract

The invention discloses a semiconductor device and a manufacturing process of the semiconductor device. Wherein, the grid is arranged on the substrate. The epitaxial structure is arranged in the substrate and between the two grid structures, and a convex part of the substrate extends into the epitaxial structure in a projection direction.

Description

Semiconductor device and manufacturing process thereof
Technical Field
The present invention relates to a semiconductor device and a manufacturing process thereof, and more particularly, to a semiconductor device having an epitaxial structure and a manufacturing process thereof.
Background
In order to increase the carrier mobility of the semiconductor structure, the gate channel may be selectively stressed in a compressive or tensile manner. For example, if compressive stress is required, the prior art often uses a Selective Epitaxial Growth (SEG) technique to form an epitaxial structure, such as a silicon germanium (SiGe) epitaxial structure, having the same lattice arrangement as the silicon substrate. By utilizing the characteristic that the lattice constant (lattice constant) of the silicon germanium epitaxial structure is larger than that of the silicon substrate lattice, the channel region of the P-type metal oxide semiconductor transistor is stressed, the carrier mobility (carrier mobility) of the channel region is increased, and the silicon germanium epitaxial structure is used for increasing the speed of the metal oxide semiconductor transistor. On the contrary, if the N-type semiconductor transistor is used, a silicon carbide (SiC) epitaxial structure may be formed in the silicon substrate to generate a tensile stress on the gate channel region.
Although the method can effectively improve the carrier mobility of the channel region, the method leads to complexity of the overall manufacturing process and difficulty in controlling the manufacturing process, especially under the trend of continuous reduction of the size of the semiconductor element. For example, in the prior art, a trench is defined in a silicon substrate, and then a buffer layer (buffer layer) is formed in the trench and then an epitaxial layer is formed. However, the conventional process still has many drawbacks to be improved, such as uneven thickness of the buffer layer, which may cause negative effects such as short channel effect (short channel effect) or Drain Induced Barrier Lowering (DIBL), resulting in increased leakage current and loss of device quality and performance.
Disclosure of Invention
The present invention provides a semiconductor device having an optimized buffer layer, thereby achieving better device performance.
The present invention also provides a process for fabricating a semiconductor device, which can form an optimized buffer layer to avoid the above-mentioned negative effects caused by the defects of the buffer layer.
The present invention provides a semiconductor device including two gates and an epitaxial structure. The grid is set on a substrate. The epitaxial structure is arranged in the substrate and between the two grids, and a convex part of the substrate extends into the epitaxial structure in a projection direction.
The invention provides a manufacturing process of a semiconductor device, which comprises the following steps. First, two gates are formed on a substrate. Then, a spacer is formed to surround each gate. Then, a trench is formed in the substrate by using the spacer as a mask, wherein the trench is located between the two gates. After the trench is formed, the spacer is partially removed to expose a top surface of a protrusion of the substrate. Finally, an epitaxial structure is selectively formed in the groove.
The semiconductor device and the manufacturing process thereof mainly utilize two or more dry etching manufacturing processes to form a groove with a slightly circular shape or a perfect circular shape in a substrate, so that fin-shaped structures (substrates) adjacent to two sides of the groove form a convex part under the influence of the shape of the groove, and the convex part has an acute angle or an obtuse angle facing the groove. The protruding portion is then exposed by partially removing the spacer, which is an etching mask for the two or more dry etching processes. Therefore, when an epitaxial structure is formed subsequently, the buffer layer can be uniformly and conformally formed on the surfaces of the groove and the convex part, so that an optimized buffer layer with a single thickness can be formed. Therefore, the semiconductor device of the invention can effectively improve the quality of the buffer layer, and further avoid the negative effects caused by the defects of the buffer layer, such as short channel effect and the like.
Drawings
FIGS. 1 to 7 are schematic views illustrating steps of a semiconductor device according to a first embodiment of the present invention; wherein:
FIG. 1 is a schematic diagram of a semiconductor device of the present invention at the beginning of a fabrication process;
FIG. 2 is a schematic diagram of a semiconductor device after forming a sidewall material layer according to the present invention;
FIG. 3 is a schematic diagram of a semiconductor device after forming a spacer according to the present invention;
FIG. 4 is a schematic diagram of a semiconductor device after forming an initial trench according to the present invention;
FIG. 5 is a schematic diagram of a semiconductor device after forming a trench according to the present invention;
FIG. 6 is a schematic diagram of a semiconductor device after removing a spacer according to the present invention;
fig. 7 is a schematic diagram of a semiconductor device after an epitaxial structure is formed.
Fig. 8 to 11 are schematic views showing steps of a semiconductor device according to a second embodiment of the present invention, in which:
FIG. 8 is a schematic view of a semiconductor device after forming another sidewall material layer according to the present invention;
FIG. 9 is a schematic view of a semiconductor device after another spacer is formed;
FIG. 10 is a schematic diagram of a semiconductor device after forming a trench in accordance with the present invention;
fig. 11 is a schematic diagram of a semiconductor device after an epitaxial structure is formed.
Description of the main elements
300 base
320 fin 321 convex portion
321a top surface 323 convex
323a top surface
340 gate structure 341 gate dielectric layer
342 dummy gate 343 capping layer
344 spacer 345 lightly doped source/drain
346 spacer 346a second sidewall material layer
348 spacer 348a third sidewall material layer
360 groove 362 groove
364 groove
365 epitaxial structure 366 first epitaxial layer
367 a second epitaxial layer
370 epitaxial structure 368 first epitaxial layer
369 second epitaxial layer
Acute angle theta 1 and acute angle theta 2
Detailed Description
In order to make the present invention more comprehensible to those skilled in the art, several preferred embodiments accompanied with figures are described in detail below.
Referring to fig. 1 to 7, a manufacturing process of forming a semiconductor device according to a first embodiment of the invention is shown. First, as shown in fig. 1, a substrate 300, such as a silicon substrate (silicon substrate), an epitaxial silicon substrate (epitaxial silicon substrate) or a Silicon On Insulator (SOI) substrate, is provided, and at least one gate structure 340 is formed on the substrate 300. In the present embodiment, at least one fin structure 320 and an insulating layer (not shown) may be formed on the substrate 300, and then the gate structure 340 may be formed on the fin structure 320. In one embodiment, the fin structure 320 is formed by, for example, using a spacer self-aligned double-patterning (SADP) method to form a patterned mask (not shown) on the substrate 300, then transferring the pattern of the patterned mask into the substrate 300 by an etching process, removing the patterned mask to form a plurality of trenches (not shown) in the substrate 300, and then filling an insulating layer (not shown) in the trenches to form the fin structure 320 protruding from the substrate 300 of the insulating layer, wherein the insulating layer can form shallow trench isolation. In other embodiments, if the transistor is a planar transistor (planar transistor), the fin structure may be omitted and the gate structure may be formed directly on a planar substrate (not shown).
The gate structure 340 includes a gate dielectric layer (gate dielectric layer)341, a dummy gate (dummy gate)342, a capping layer (capping layer)343, and a spacer (spacer) 344. The gate dielectric layer 341 may comprise silicon oxide (SiO), for example2) Or silicon nitride (SiN); the dummy gate 342 is, for example, a polysilicon (polysilicon) material, which includes a polysilicon material without any dopant (undoped), a polysilicon material with a dopant, an amorphous silicon material, etc., but may be a combination of the above materials. The cap layer 343 may be a composite film or a single film as shown in FIG. 1, such as silicon nitride (SiN), silicon carbide (SiC), silicon carbonitride (SiCN), or a combination thereof. The spacer 344 may also be selected to be a single layer or a composite layer, such as a high temperature silicon oxide (HTO) layer, silicon nitride, silicon oxide, silicon oxynitride, or a silicon hexachlorodisilane (Si) layer2Cl6) The formed silicon nitride (HCD-SiN) and other materials with good etching resistance and covering capability, such as silicon nitride. In one embodiment, the gate structure 340 is formed by, for example, forming a gate dielectric material layer (not shown), a dummy gate material layer (not shown) and a capping material layer (not shown) on the substrate 300, and then patterning the stacked material layers to form a gate stack structure (not shown). Then, two lightly doped source/drains 345 (LDD) are formed in the fin structure 320 (substrate 300) at two sides of the gate stack structure, and finally, a first sidewall material layer (not shown) is formed on the sidewalls of the gate stack structure, and then a spacer 344 is formed by an etching process. However, it should be readily apparent to those skilled in the art that the gate structure of the present invention may be formed in other ways, and is not limited to the foregoing fabrication steps. For example, in another embodiment, direct connection may also be selectedA metal gate structure (not shown) is formed on the substrate 300, and the metal gate structure at least includes a work function layer (work function layer) and a metal gate.
Then, a spacer 346 surrounding the spacer 344 is formed. In one embodiment, the spacers 346 are formed, for example, in a manner similar to the spacers 344, including forming a second sidewall material layer 346a, for example, including silicon oxide, which is selective to the spacers 344 and is easier to etch, overlying the fin structure 320 (substrate 300) and the spacers 344, as shown in fig. 2, and then performing an etching process, for example, a dry etching process, to form the spacers 346 surrounding the gate structure, as shown in fig. 3.
As shown in fig. 4, a first etching process, such as a dry etching process, is performed using the gate structure 340 and the spacers 344 and 346 as an etching mask to form a trench 360 in the fin structure 320 (the substrate 300) on both sides of the gate structure 340. That is, the etching process vertically etches (vertical etch) the fin structure 320 (substrate 300) along the spacers 344, 346, for example, to form a trench 360 in the fin structure 320 (substrate 300) at both sides of each gate structure 340, wherein the sidewalls thereof are vertically aligned with the spacers 346 and the bottom thereof is approximately arc-shaped, as shown in fig. 4.
Then, as shown in fig. 5, a second etching process, such as a dry etching process, is performed to further etch the trench 360 etched by the first etching process, particularly to etch the sidewall of the trench 360, preferably to laterally etch the fin structure 320 (substrate 300) under the spacer 346, and further to enlarge the area of the trench 360, and finally to form a trench 362. In detail, the second etching process is, for example, to adjust the bias voltage of the processing tool, for example, to slightly reduce the applied bias power (bias power), so that the second dry etching process can expand the trench 360 in a lateral etching manner, and the phenomenon that the general wet etching process forms a diamond, hexagonal, etc. polygonal (also referred to as sigma Σ) trench structure along a specific crystal plane with a faster etching rate is not occurred. In addition, after the second dry etching process expands the area of the trench 360 by lateral etching, a substantially circular or rounded trench 362 may be formed in the fin structure 320 (substrate 300) beside the gate structure 340, as shown in fig. 5. On the other hand, the fin structure 320 (the substrate 300) adjacent to both sides of the trench 362 forms a tip extending toward the trench 362 due to the trench 362, and the tip has an acute angle θ 1 extending toward the trench 362, which is about 15 degrees to 45 degrees, as shown in fig. 5.
It should be noted that, although the present embodiment performs two dry etching processes to etch the trench 362 in a substantially circular or circular shape, the number of dry etching processes performed is not limited to two, the present invention can adjust the number of dry etching processes at any time according to the requirements of the manufacturing processes or the etching results, or the present invention is not limited to dry etching, but more than one dry etching process is used in combination with the wet etching process, and the trench 362 is approximately rectangular from the beginning to extend to a perfect circular shape by using the etchant, which also falls within the scope of the present invention.
Then, the spacers 346 are removed to expose the underlying fin structure 320 (the substrate 300) to form a protrusion 321, as shown in fig. 6. Specifically, the protruding portion 321 is formed by the portion of the tip of the fin structure 320 (substrate 300) not covered by the spacer 344, and thus has an acute angle θ 1 extending toward the trench 362, as shown in fig. 6.
After the trench 362 is formed, a pre-clean step may be optionally performed to remove native oxide or other impurities on the surface of the trench 362 by using a cleaning solution such as a diluted hydrofluoric acid (diluted hydrofluoric acid) or a SPM mixture solution containing sulfuric acid, hydrogen peroxide, and deionized water. An epitaxial structure 365 is then formed within the trench 362 to fill the trench 362, as shown in fig. 7.
The epitaxial structure 365 has a top surface that is higher than the top surface of the fin structure 320 (substrate 300) and has a length that is greater than the width of the opening of the trench 362, as shown in fig. 7. Specifically, the epitaxial structure 365 includes, for example, a first epitaxial layer 366 and a second epitaxial layer 367. The first epitaxial layer 366, which is, for example, a buffer layer, is conformally formed on the top surfaces 321a of the trenches 362 and the protrusions 321 to cover and directly contact the surfaces of the trenches 362 and the top surfaces 321a of the protrusions 321, so that the first epitaxial layer 366 preferably has a uniform thickness and completely surrounds the protrusions 321, as shown in fig. 7. A selective epitaxial growth process may then be performed to form a second epitaxial layer 367 on the first epitaxial layer 366, which may fill the trenches 362 above the top surface of the fin structure 320 (substrate 300). Thus, the protruding portion 321 of the fin structure 320 (substrate 300) extends into the epitaxial structure 365 in the vertical projection direction of the fin structure 320 (substrate 300), and is completely surrounded by the epitaxial structure 365.
First epitaxial layer 366 may alternatively comprise pure silicon (pure silicon) or silicon containing only less than 10% dopants (dopants). While the second epitaxial layer 367 may be of a different material depending on the type of Metal Oxide Semiconductor (MOS) transistor to be subsequently formed. For example, if the mos transistor is a P-type transistor (PMOS), the second epitaxial layer 367 may optionally comprise germanium silicide (SiGe), boron silicide (SiGeB), or tin silicide (SiGeSn); if the MOS transistor is an N-type transistor (NMOS), the second epitaxial layer 367 may optionally comprise silicon carbide (SiC), silicon carbon phosphide (SiCP), or silicon phosphide (SiP). In the present embodiment, the first epitaxial layer 366 (i.e., the buffer layer) and the second epitaxial layer 367 may both comprise, for example, germanium silicide, wherein the germanium concentration of the first epitaxial layer 366 is lower than the germanium concentration of the second epitaxial layer 367 and only comprises less than 10% germanium, so as to buffer the surface of the trenches 362, the protrusions 321 and the second epitaxial layer 367 subsequently formed on the first epitaxial layer 366 with a higher germanium concentration, thereby reducing the dislocation defects of the epitaxial structure 365. In addition, the selective epitaxial process may be formed in a single layer or multiple layers, and the hetero atoms (e.g., germanium atoms) may be varied in a concentration gradient for subsequent processes.
Thus, the method of forming the semiconductor device according to the first preferred embodiment of the present invention is completed. Subsequently, an ion implantation process, such as in situ doping (in situ doping) preferably performed in conjunction with the formation of the second epitaxial layer 367, may be performed to form a source/drain (not shown) in at least a portion of the epitaxial structure 365; a metal gate replacement (replacement metal gate) process, which converts the dummy gate 342 into a metal gate; a metal silicide process, for example, a silicon cap layer (silicon cap) may be formed on the top surface of the source/drain (epi structure 365), and then a metal silicide layer may be formed on at least a portion of the surface of the source/drain; and/or a contact plug manufacturing process, forming a contact plug electrically connected with the source/drain and/or the metal grid.
The fabrication process of the present embodiment mainly utilizes two or more dry etching processes to form a trench having a slightly circular shape or a regular circular shape in the substrate, so that the fin-shaped structure (substrate) adjacent to both sides of the trench forms a tip having an acute angle toward the trench (and the epitaxial structure) due to the influence of the trench shape. Then, the spacer used as the etching mask of the two or more dry etching processes is partially removed to expose a portion of the tip and form a convex portion. Therefore, when an epitaxial structure is formed subsequently, the buffer layer can be uniformly and conformally formed on the surfaces of the groove and the convex part, and the buffer layer with single thickness can be formed. Therefore, the semiconductor device of the invention can effectively improve the quality of the buffer layer, and further avoid the negative effects caused by the defects of the buffer layer, such as short channel effect and the like.
Other embodiments of the semiconductor device fabrication process of the present invention will be described below. For simplicity, the following description mainly refers to the differences of the embodiments, and the description of the same parts is not repeated. In addition, the same elements in the embodiments of the present invention are denoted by the same reference numerals to facilitate the comparison between the embodiments.
Referring to fig. 8 to 11, steps for forming a semiconductor device according to a second preferred embodiment of the present invention are shown. A part of the manufacturing process of the semiconductor device of this embodiment is substantially the same as that of fig. 1 to 4 of the first embodiment, and is not repeated herein. The main difference between this embodiment and the previous embodiment is that after the semiconductor structure shown in fig. 4 is formed, a spacer 348 surrounding the spacer 346 is additionally formed. In one embodiment, the spacer 348 is formed in a manner similar to the spacers 344 and 346, including forming a third sidewall material layer 348a, such as a silicon oxynitride (SiON) material that is selective to the spacer 344 and is easier to etch, covering the fin structure 320 (substrate 300) and the spacer 346, as shown in fig. 8, and performing an etching process, such as a dry etching process, to form a spacer 348 surrounding the gate structure, wherein the spacer 348 further extends to the sidewalls of the trench 360, as shown in fig. 9.
As shown in fig. 10, a third etching process, such as a dry etching process, is performed using the gate structure 340 and the spacer 348 as an etching mask to further etch the trench 360 etched by the first etching process. Since the sidewalls of the trench 360 are covered by the spacers 348, the third etching process only laterally etches the fin structure 320 (the substrate 300) under the spacers 348, and further enlarges the area of the trench 360, thereby forming the trench 364. In detail, the third etching process is performed by, for example, adjusting the bias of the processing tool, for example, reducing the applied bias power, so that the third etching process mainly expands the trench 360 by lateral etching, and a substantially circular or true circular trench 364 may be formed in the fin structure 320 (substrate 300) beside the gate structure 340, as shown in fig. 10. In addition, because the trench 360 is covered by the spacer 348, the slightly rounded portion or the rounded portion of the trench 364 is located in a deeper portion of the fin-shaped structure 320 (the substrate 300) (the increased depth is the depth of the trench 362 in the first embodiment) than the trench 362 of the first embodiment, and the spacer 348 forms a sidewall perpendicular to the top surface of the fin-shaped structure 320 (the substrate 300) in part, as shown in fig. 10. That is, in the present embodiment, after the third dry etching process expands the area of the trench 360 by lateral etching, although the fin structure 320 (the substrate 300) adjacent to the two sides of the trench 362 may also form a tip due to the trench 364, the tip has an obtuse angle θ 2 extending toward the trench 364, as shown in fig. 10. In another embodiment, the third sidewall material layer may be directly used as an etching mask to further expand the area of the trench 360, so that the third spacer 348 and the trench 364 can be formed in the same etching process (not shown).
Then, the spacers 348 and 346 are removed to expose the fin structure 320 (the substrate 300) under the spacers 346, thereby forming a protrusion 323, as shown in fig. 10. Specifically, the protruding portion 323 is formed by the tip of the fin structure 320 (the substrate 300) not covered by the spacer 344, and thus has an obtuse angle θ 2 extending toward the groove 364, as shown in fig. 10.
Then, a pre-cleaning step may be optionally performed to remove native oxide or other impurities on the surface of the trench 364 by using a cleaning solution such as a diluted hydrofluoric acid solution or a SPM mixture solution containing sulfuric acid, hydrogen peroxide, and deionized water. An epitaxial structure 370 is then formed within the trench 364 to fill the trench 364.
Epitaxial structure 370 may have a top surface that is higher than the top surface of fin structure 320 (substrate 300). Specifically, the epitaxial structure 370 includes, for example, a first epitaxial layer 368 and a second epitaxial layer 369. The first epitaxial layer 368, for example, serves as a buffer layer, and is conformally formed on the top surfaces 323a of the trenches 364 and the protrusions 323 to cover all surfaces of the trenches 364 and the top surfaces 323 of the protrusions 323, so that the first epitaxial layer 368 preferably has a uniform thickness and completely surrounds the protrusions 323, as shown in fig. 11. A selective epitaxial growth process may then be performed to form a second epitaxial layer 369 on the first epitaxial layer 368, which may fill the trenches 364 above the top surface of the fin structure 320 (substrate 300). Thus, the convex portion 323 of the fin structure 320 (the substrate 300) extends into the epitaxial structure 370 in the vertical projection direction of the fin structure 320 (the substrate 300), and is completely surrounded by the epitaxial structure 370.
The first epitaxial layer 368 may alternatively comprise pure silicon or silicon containing only less than 10% dopants. The second epitaxial layer 369 may be of a different material depending on the type of mos transistor to be subsequently formed. For example, if the mos transistor is a P-type transistor, the second epitaxial layer 369 may optionally comprise germanosilicide, boron germanosilicide, tin germanosilicide, or the like; if the mos transistor is an N-type transistor, the second epitaxial layer 369 may optionally comprise silicon carbide, silicon carbide phosphide, silicon phosphide, or the like. In the present embodiment, the first epitaxial layer 368 (i.e., the buffer layer) and the second epitaxial layer 369 may both comprise, for example, germanium silicide, wherein the germanium concentration of the first epitaxial layer 368 is lower than the germanium concentration of the second epitaxial layer 369 and only comprises less than 10% germanium, so as to buffer the trench 364, the surface of the protrusion 323, and the second epitaxial layer 369 subsequently formed on the first epitaxial layer 368 and having a higher germanium concentration, thereby reducing dislocation defects of the epitaxial structure 370. In addition, the selective epitaxial process may be formed in a single layer or multiple layers, and the hetero atoms (e.g., germanium atoms) may be changed in a graded manner to facilitate the subsequent processes.
Thus, the method of forming the semiconductor device according to the second preferred embodiment of the present invention is completed. Subsequently, an ion implantation process, such as an in-situ doping process preferably performed in conjunction with the formation of the second epitaxial layer 369, may be performed to form a source/drain (not shown) in at least a portion of the epitaxial structure 370; a metal gate replacement process, converting the dummy gate 342 into a metal gate; a metal silicide process, for example, a silicon cap layer may be formed on the top surface of the source/drain (epi structure 370) and a metal silicide layer may be formed on at least a portion of the surface of the source/drain; and/or a contact plug manufacturing process, forming a contact plug electrically connected with the source/drain and/or the metal grid.
In the manufacturing process of the present embodiment, after an initial trench is formed by first dry etching, a spacer partially covering the initial trench is additionally formed, and then a trench having a slightly circular shape or a regular circular shape is formed in the substrate by one or more dry etching processes, so that the fin structures (substrate) adjacent to both sides of the trench also form a tip under the influence of the shape of the trench, which has a vertical sidewall facing the trench (and the epitaxial structure) and an obtuse angle. Then, the spacer is partially removed as an etching mask in the dry etching process to expose a portion of the tip and form a protrusion. Therefore, when an epitaxial structure is formed subsequently, the buffer layer can be uniformly and conformally formed on the surfaces of the groove and the convex part, and the buffer layer with single thickness can be formed. Therefore, the semiconductor device of the invention can effectively improve the quality of the buffer layer, and further avoid the negative effects caused by the defects of the buffer layer, such as short channel effect and the like.
In addition, although the foregoing embodiments have been described with reference to the fabrication of non-planar transistors (non-planar transistors), such as Fin-FETs, as an example, it should be understood by those skilled in the art that the present invention may also be applied to other planar transistors, and the embodiments are within the scope of the present invention.
The above-mentioned embodiments are merely preferred embodiments of the present invention, and all equivalent changes and modifications made by the claims of the present invention should be covered by the scope of the present invention.

Claims (19)

1. A semiconductor device, comprising:
two grids, set up on a basement; and
an epitaxial structure disposed in the substrate and between the two gates, the epitaxial structure having an outer surface in the substrate in the shape of a circular arc, wherein a convex portion of the substrate extends into the epitaxial structure in a projection direction, and the epitaxial structure includes a first epitaxial layer continuously and conformally extending from a bottom surface of the epitaxial structure to a top surface of the convex portion; and
first spacers surrounding the gates, wherein a top surface of the protrusion of the substrate is not covered by the first spacers.
2. The semiconductor device of claim 1, wherein a top surface of the protrusion of the substrate directly contacts the epitaxial structure.
3. The semiconductor device of claim 1, wherein the protrusion of the substrate comprises an acute angle toward the epitaxial structure.
4. The semiconductor device according to claim 1, wherein the protrusion of the substrate comprises an obtuse angle toward the epitaxial structure.
5. The semiconductor device of claim 1, wherein the protrusion of the substrate comprises a sidewall perpendicular to a top surface of the substrate.
6. The semiconductor device of claim 1 wherein a top surface of the epitaxial structure is higher than a top surface of the substrate.
7. The semiconductor device of claim 1, wherein the epitaxial structure comprises:
a first epitaxial layer; and
a second epitaxial layer disposed on the first epitaxial layer.
8. The semiconductor device of claim 1, wherein the first epitaxial layer surrounds the protrusion of the substrate.
9. The semiconductor device according to claim 1, further comprising:
the fin structure is arranged in the substrate, and the two gates cross the fin structure.
10. A process for fabricating a semiconductor device, comprising the steps of:
forming two gates on a substrate;
forming a spacer surrounding each of the gates, the spacer including a first spacer;
forming a trench in the substrate by using the spacer as a mask, wherein the trench is arranged between the two gates and has an arc-shaped sidewall;
after the trench is formed, partially removing the spacer to expose a top surface of a protrusion of the substrate, wherein a top surface of the protrusion of the substrate is not covered by the first spacer; and
an epitaxial structure is formed within the trench, wherein the epitaxial structure includes a first epitaxial layer that extends continuously and conformally from a bottom surface of the trench to a top surface of the protrusion.
11. The process of claim 10, wherein the protrusion of the substrate extends into the epitaxial structure in a projection direction.
12. The process of claim 10, wherein the top surface of the protrusion of the substrate contacts the epitaxial structure.
13. The process of claim 10, wherein the spacer further comprises a second spacer, the second spacer being removed when the spacer is partially removed.
14. The process of claim 13, wherein the step of forming the spacers comprises:
forming a first material layer on the substrate to cover the gates;
operating a first etching process to form the first spacer;
forming a second material layer on the substrate to cover the gates; and
a second etching process is performed to form the second spacer.
15. The process of claim 14, wherein the second material layer is formed after the first spacer is formed.
16. The process of claim 13, wherein the trench forming step comprises:
vertically etching the substrate to form an initial trench, wherein the initial trench is vertically aligned with the second spacer;
forming a material layer covering the second spacer, the first spacer and the two gates;
forming a third spacer surrounding the second spacer and the first spacer; and
the initial trench is further etched to form the trench.
17. The process of claim 16, further comprising:
the third spacer is removed when the spacer is partially removed.
18. The process of claim 16, wherein the third spacer and the trench are formed simultaneously.
19. A process for fabricating a semiconductor device according to claim 10, wherein the forming of the epitaxial structure comprises:
forming a first epitaxial layer on the surface of the convex part and the groove of the substrate; and
and forming a second epitaxial layer to fill the trench.
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Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9934970B1 (en) * 2017-01-11 2018-04-03 International Business Machines Corporation Self aligned pattern formation post spacer etchback in tight pitch configurations
US10297675B1 (en) * 2017-10-27 2019-05-21 Globalfoundries Inc. Dual-curvature cavity for epitaxial semiconductor growth
CN108470681B (en) * 2018-03-14 2020-06-12 上海华力集成电路制造有限公司 Method for manufacturing grid
CN108520865B (en) * 2018-03-21 2021-02-02 上海华力集成电路制造有限公司 Method for manufacturing grid
DE102020112695A1 (en) * 2019-05-31 2020-12-03 Taiwan Semiconductor Manufacturing Co., Ltd. OPTIMIZED SEWING PROFILE FOR TENSIONED SOURCE / DRAIN FEATURES AND METHOD OF MANUFACTURING IT
TWI707385B (en) * 2019-10-15 2020-10-11 力晶積成電子製造股份有限公司 Method of manufacturing semiconductor structure
CN111048627B (en) * 2019-12-26 2021-06-22 中国科学院微电子研究所 Method for manufacturing semiconductor device
KR20210092360A (en) * 2020-01-15 2021-07-26 삼성전자주식회사 Semiconductor device
CN111509078B (en) * 2020-01-20 2023-03-21 中国科学院微电子研究所 Silicon-based photoelectric detector and manufacturing method thereof
US11282890B2 (en) 2020-01-21 2022-03-22 Omnivision Technologies, Inc. Shallow trench isolation (STI) structure for suppressing dark current and method of forming
US11289530B2 (en) * 2020-01-21 2022-03-29 Omnivision Technologies, Inc. Shallow trench isolation (STI) structure for CMOS image sensor
CN113611736B (en) * 2020-05-29 2022-11-22 联芯集成电路制造(厦门)有限公司 Semiconductor element and manufacturing method thereof
US11393819B2 (en) * 2020-07-09 2022-07-19 Qualcomm Incorporated Semiconductor device implemented with buried rails

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080128746A1 (en) * 2006-12-05 2008-06-05 Yin-Pin Wang Dual-SiGe epitaxy for MOS devices
US20080277699A1 (en) * 2007-05-11 2008-11-13 Texas Instruments Incorporated Recess Etch for Epitaxial SiGe
US20140127893A1 (en) * 2012-11-08 2014-05-08 Taiwan Semiconductor Manufacturing Company, Ltd. Method for fabricating a semiconductor device

Family Cites Families (45)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6313008B1 (en) * 2001-01-25 2001-11-06 Chartered Semiconductor Manufacturing Inc. Method to form a balloon shaped STI using a micro machining technique to remove heavily doped silicon
US6621131B2 (en) * 2001-11-01 2003-09-16 Intel Corporation Semiconductor transistor having a stressed channel
JP4369359B2 (en) * 2004-12-28 2009-11-18 富士通マイクロエレクトロニクス株式会社 Semiconductor device
US7545023B2 (en) * 2005-03-22 2009-06-09 United Microelectronics Corp. Semiconductor transistor
US7442618B2 (en) * 2005-07-16 2008-10-28 Chartered Semiconductor Manufacturing, Ltd Method to engineer etch profiles in Si substrate for advanced semiconductor devices
US7303999B1 (en) * 2005-12-13 2007-12-04 Lam Research Corporation Multi-step method for etching strain gate recesses
JP5145672B2 (en) * 2006-02-27 2013-02-20 富士通セミコンダクター株式会社 Manufacturing method of semiconductor device
US7772071B2 (en) * 2006-05-17 2010-08-10 Chartered Semiconductor Manufacturing Ltd. Strained channel transistor and method of fabrication thereof
US7592231B2 (en) * 2006-08-01 2009-09-22 United Microelectronics Corp. MOS transistor and fabrication thereof
US7691752B2 (en) * 2007-03-30 2010-04-06 Intel Corporation Methods of forming improved EPI fill on narrow isolation bounded source/drain regions and structures formed thereby
DE102010038737B4 (en) * 2010-07-30 2017-05-11 Globalfoundries Dresden Module One Llc & Co. Kg A method of fabricating transistors having metal gate electrode structures and embedded strain-inducing semiconductor alloys
US8405155B2 (en) * 2010-09-23 2013-03-26 United Microelectronics Corp. Semiconductor structure with gate structure, source/drain region and recess filling with epitaxial layer
KR20120038195A (en) * 2010-10-13 2012-04-23 삼성전자주식회사 Semiconductor device and manufacturing method thereof
US8431460B2 (en) * 2011-05-27 2013-04-30 United Microelectronics Corp. Method for fabricating semiconductor device
CN102810481B (en) * 2011-06-02 2016-03-30 中芯国际集成电路制造(北京)有限公司 The manufacture method of semiconductor device
CN102881591B (en) * 2011-07-15 2015-12-16 中芯国际集成电路制造(北京)有限公司 The manufacture method of semiconductor device
US9064892B2 (en) * 2011-08-30 2015-06-23 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor devices utilizing partially doped stressor film portions and methods for forming the same
US8659089B2 (en) * 2011-10-06 2014-02-25 Taiwan Semiconductor Manufacturing Company, Ltd. Nitrogen passivation of source and drain recesses
US8877614B2 (en) * 2011-10-13 2014-11-04 Taiwan Semiconductor Manufacturing Company, Ltd. Spacer for semiconductor structure contact
US8754448B2 (en) * 2011-11-01 2014-06-17 United Microelectronics Corp. Semiconductor device having epitaxial layer
US9246004B2 (en) * 2011-11-15 2016-01-26 Taiwan Semiconductor Manufacturing Company, Ltd. Strained structures of semiconductor devices
US8723266B2 (en) * 2011-12-13 2014-05-13 Taiwan Semiconductor Manufacturing Company, Ltd. Pinch-off control of gate edge dislocation
US8664069B2 (en) * 2012-04-05 2014-03-04 United Microelectronics Corp. Semiconductor structure and process thereof
US8574978B1 (en) * 2012-04-11 2013-11-05 United Microelectronics Corp. Method for forming semiconductor device
US8912608B2 (en) * 2012-08-17 2014-12-16 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and fabrication method thereof
US8710632B2 (en) * 2012-09-07 2014-04-29 United Microelectronics Corp. Compound semiconductor epitaxial structure and method for fabricating the same
US8883621B2 (en) * 2012-12-27 2014-11-11 United Microelectronics Corp. Semiconductor structure and method of fabricating MOS device
US9034706B2 (en) * 2013-03-13 2015-05-19 Taiwan Semiconductor Manufacturing Company, Ltd. FinFETs with regrown source/drain and methods for forming the same
US9034705B2 (en) * 2013-03-26 2015-05-19 United Microelectronics Corp. Method of forming semiconductor device
US8853060B1 (en) * 2013-05-27 2014-10-07 United Microelectronics Corp. Epitaxial process
US9076652B2 (en) * 2013-05-27 2015-07-07 United Microelectronics Corp. Semiconductor process for modifying shape of recess
CN104217953B (en) * 2013-06-05 2017-06-13 中芯国际集成电路制造(上海)有限公司 PMOS transistor and preparation method thereof
US9293586B2 (en) * 2013-07-17 2016-03-22 Globalfoundries Inc. Epitaxial block layer for a fin field effect transistor device
US9401365B2 (en) * 2013-12-19 2016-07-26 Texas Instruments Incorporated Epitaxial source/drain differential spacers
CN104851911A (en) * 2014-02-14 2015-08-19 中芯国际集成电路制造(上海)有限公司 Semiconductor device, manufacturing method therefor, and electronic device
EP2930752A3 (en) * 2014-04-08 2016-01-20 IMEC vzw Method for manufacturing a transistor device
US9419136B2 (en) * 2014-04-14 2016-08-16 Taiwan Semiconductor Manufacturing Co., Ltd. Dislocation stress memorization technique (DSMT) on epitaxial channel devices
CN105304481A (en) * 2014-06-10 2016-02-03 联华电子股份有限公司 Semiconductor element and manufacturing method therefor
US9627480B2 (en) * 2014-06-26 2017-04-18 Globalfoundries Inc. Junction butting structure using nonuniform trench shape
US10263108B2 (en) * 2014-08-22 2019-04-16 Taiwan Semiconductor Manufacturing Company, Ltd. Metal-insensitive epitaxy formation
CN105448991B (en) * 2014-09-01 2019-05-28 中芯国际集成电路制造(上海)有限公司 Transistor and forming method thereof
US20160155818A1 (en) * 2014-11-27 2016-06-02 United Microelectronics Corp. Method for fabricating semiconductor device
TWI637514B (en) * 2015-04-24 2018-10-01 聯華電子股份有限公司 Semiconductor structure and manufacturing method thereof
US9691901B2 (en) * 2015-10-02 2017-06-27 United Microelectronics Corp. Semiconductor device
CN106601681A (en) * 2015-10-20 2017-04-26 上海新昇半导体科技有限公司 Cmos structure and preparation method thereof

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080128746A1 (en) * 2006-12-05 2008-06-05 Yin-Pin Wang Dual-SiGe epitaxy for MOS devices
US20080277699A1 (en) * 2007-05-11 2008-11-13 Texas Instruments Incorporated Recess Etch for Epitaxial SiGe
US20140127893A1 (en) * 2012-11-08 2014-05-08 Taiwan Semiconductor Manufacturing Company, Ltd. Method for fabricating a semiconductor device

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