CN102881591B - The manufacture method of semiconductor device - Google Patents

The manufacture method of semiconductor device Download PDF

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Publication number
CN102881591B
CN102881591B CN201110197909.7A CN201110197909A CN102881591B CN 102881591 B CN102881591 B CN 102881591B CN 201110197909 A CN201110197909 A CN 201110197909A CN 102881591 B CN102881591 B CN 102881591B
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groove
coating
oxide skin
substrate
sidewall
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CN102881591A (en
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韦庆松
吕伟
刘武平
何永根
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Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Beijing Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30604—Chemical etching
    • H01L21/30608—Anisotropic liquid etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H01L21/26533—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically inactive species in silicon to make buried insulating layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66636—Lateral single gate silicon transistors with source or drain recessed by etching or first recessed by etching and then refilled
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
    • H01L29/7848—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System
    • H01L29/161—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System including two or more of the elements provided for in group H01L29/16, e.g. alloys
    • H01L29/165—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System including two or more of the elements provided for in group H01L29/16, e.g. alloys in different semiconductor regions, e.g. heterojunctions

Abstract

Disclosure embodiment provides a kind of method, semi-conductor device manufacturing method.First, by dry etching process, Formation cross-section is the groove of general rectangular in the substrate.Then, by O +ion implanted process, oxide skin(coating) is formed on the bottom and sidewall of groove, wherein, the oxide skin(coating) in recess sidewall is thinner than the oxide skin(coating) of bottom portion of groove.Afterwards, fully remove the oxide skin(coating) in recess sidewall, only retain the portions of oxide layer on bottom portion of groove.Then, the sidewall of groove, as stop-layer, by crystal orientation optionally wet etching treatment, is formed as having ∑ shape by the oxide skin(coating) retained on bottom portion of groove.Finally, the oxide skin(coating) on bottom portion of groove is removed.The method of disclosure embodiment, by forming silicon oxide layer at bottom portion of groove, as the stop-layer of follow-up crystal orientation optionally wet etching treatment, thus prevents the bottom occurring point when forming ∑ connected in star.

Description

The manufacture method of semiconductor device
Technical field
The disclosure relates to the method manufacturing semiconductor device, especially relates to the method that manufacture comprises the semiconductor device of the PMOS device with embedded SiGe (eSiGe).
Background technology
In order to meet the demand of terminal use to small size electronic device, in very lagre scale integrated circuit (VLSIC) (VLSI) technique improved, stress technique is adopted to improve the performance of device.Wherein a kind of effective method adopts embedded SiGe (eSiGe) structure to improve the hole mobility of PMOS device channel region.
In the eSiGe structure of ∑ shape, the lattice constant due to SiGe is greater than the lattice constant of Si, and the SiGe of ∑ shape reduces the spacing between source region and drain region, so effectively increase the stress in channel region.
Figure 1A to 1D shows the method forming ∑ shape SiGe in the pmos devices of prior art.After Si substrate forms gate dielectric layer (not shown) and is positioned at the grid on gate dielectric layer and is positioned at the sidewall spacer (see Figure 1A) on the sidewall of grid both sides, pass through dry etching, in Si substrate between neighboring gates, Formation cross-section is the groove of rectangular shape, as shown in Figure 1B.Such as, the crystal plane direction on the surface of substrate can be selected for (100).
Then, as shown in Figure 1 C, adopt and there is crystal orientation optionally wet etchant, such as, comprise the etchant of Tetramethylammonium hydroxide (TMAH), the groove of general rectangular is etched, so that this groove is expanded to ∑ shape.Finally, as shown in figure ip, epitaxial growth SiGe in formed ∑ connected in star, thus the source region and the drain region that form SiGe.
The present inventor finds that after furtheing investigate the method forming ∑ shape SiGe the method for above-mentioned prior art exists and is difficult to epitaxial growth SiGe and the high problem of load effect.
Crystal orientation is in fig. 1 c optionally in wet etching process, such as when employing comprises the etchant of Tetramethylammonium hydroxide (TMAH), along the etch rate in <100> crystal orientation far above the etch rate along <111> crystal orientation.Thus, the crystal plane direction for surface is the substrate of (100), is difficult to control etch technological condition, make (111) crystal face in groove both sides intersect before stop etching.So the result of this crystal orientation optionally wet etching often causes the bottom of groove to be sharp, instead of flat, as shown in fig. 1e.The groove of this shape can cause being difficult to carry out SiGe epitaxial growth in follow-up technique, and makes obtained semiconductor device existing defects.
And in VLSI manufacturing process, the device density on substrate in zones of different may be different.Such as, the density in the region for the manufacture of logical device is usually higher than for the manufacture of the density in the region of static RAM (SRAM).Due to the load effect be associated with wet etching, the etching in the region that the etching in the region that device density is low is higher than device density is carried out faster.Therefore, bulk of substrate is carried out above-mentioned crystal orientation optionally wet etching treatment time, if to be as the criterion control etch technological condition with low-density device, can cause in the etching at high-density device place incomplete; And if to be as the criterion control etch technological condition with high-density device, high-density device can be caused to occur, and the bottom shown in Fig. 1 E is the ∑ connected in star of point.
Summary of the invention
In order to eliminate or alleviate some or all the problems referred to above of the prior art at least in part, propose the present invention.
Embodiment of the present disclosure by utilize dry etching in the substrate the Formation cross-section groove that is general rectangular, then utilize O +ion implanted process to form oxide skin(coating) in the bottom of the groove of this general rectangular, then carry out crystal orientation optionally wet etching using this oxide skin(coating) as stop-layer to groove, prevent the ∑ connected in star at the point end.
Embodiment of the present disclosure provides a kind of method manufacturing semiconductor device, comprises the following steps: Formation cross-section is substantially the groove of rectangle in the substrate; By O +ion implanted process, the sidewall and bottom of described groove form oxide skin(coating), the oxide skin(coating) on the sidewall of wherein said groove is thinner than the oxide skin(coating) on the bottom of described groove; By the first isotropism wet etching treatment, fully remove the oxide skin(coating) in described recess sidewall, and partly remove the oxide skin(coating) on described bottom portion of groove; Using the oxide skin(coating) on described bottom portion of groove as stop-layer, crystal orientation optionally wet etching is carried out to described groove, so that the sidewall of described groove is formed as having ∑ shape; And by the second isotropism wet etching treatment, remove the oxide skin(coating) on described bottom portion of groove.
In one embodiment, with the Implantation Energy of 2 to 15keV and 10 13ion/cm 2to 10 15ion/cm 2implantation dosage carry out described O +ion implanted process.
In one embodiment, described O +ion implanted process is carried out along the direction substantially parallel with the sidewall of described groove.
In one embodiment, the thickness of the oxide skin(coating) on the bottom portion of groove utilizing O +ion implanted process to obtain is 5 dust to 100 dusts.
In one embodiment, the thickness of the oxide skin(coating) in the recess sidewall utilizing O +ion implanted process to obtain is 3 dust to 10 dusts.
In one embodiment, after described first isotropism wet etching treatment, the thickness of the oxide skin(coating) on described bottom portion of groove is 2 dust to 97 dusts.
In one embodiment, described first isotropism wet etching treatment comprises and utilizes HF solution or HF steam to remove oxide skin(coating).
In one embodiment, described second isotropism wet etching treatment comprises and utilizes HF solution or HF steam to remove oxide skin(coating).
In one embodiment, the step that described Formation cross-section is in the substrate substantially the groove of rectangle comprises: utilize dry etching process, forms the groove that described cross section is substantially rectangle in the substrate.
In one embodiment, the step that described Formation cross-section is in the substrate substantially the groove of rectangle comprises: on substrate, form gate dielectric layer and be positioned at the grid on gate dielectric layer, top portions of gates is formed with top mask layer; Form the sidewall spacer be positioned on the sidewall of described grid both sides; With described top mask layer and described sidewall spacer for mask, dry etching is carried out to described substrate, is substantially the groove of rectangle with Formation cross-section in the substrate between adjacent sidewall spacer.
In one embodiment, described the step that described groove carries out crystal orientation optionally wet etching to be comprised: adopt Tetramethylammonium hydroxide (TMAH) to carry out wet etching to described groove.
In one embodiment, described crystal orientation optionally wet etching be greater than etch rate along <111> crystal orientation along the etch rate in <100> crystal orientation.
In one embodiment, the grid formed over the substrate is polysilicon gate.
In one embodiment, after removing the oxide skin(coating) on bottom portion of groove by the second isotropism wet etching treatment, at the groove epitaxial growth SiGe of ∑ shape.
In one embodiment, described method carries out ion implantation to form source region and drain region before being also included in and carrying out dry etching to described substrate in described substrate.
In one embodiment, described method carries out ion implantation to form source region and drain region after being also included in groove epitaxial growth SiGe in described substrate.
In one embodiment, before described method is also included in and carries out dry etching to described substrate, form mask at the overlying regions that will form nmos device, and expose the region that will form PMOS device.
The method of disclosure embodiment, by forming oxide skin(coating) at bottom portion of groove, as the stop-layer of follow-up crystal orientation optionally wet etching treatment, thus prevents the bottom occurring point when forming ∑ connected in star.
In embodiment of the present disclosure, the degree of depth of the final ∑ connected in star formed mainly is controlled by dry etching process, and therefore, the method for disclosure embodiment can obtain lower load effect value.
By referring to the detailed description of accompanying drawing to exemplary embodiment of the present disclosure, further feature of the present invention and advantage thereof will become clear.
Accompanying drawing explanation
Accompanying drawing as the part of specification exemplified with embodiment of the present disclosure, and together with the description for explaining principle of the present invention.Reference numeral identical in each accompanying drawing will refer to identical parts or step.
With reference to accompanying drawing, according to detailed description below, clearly the present invention can be understood, wherein:
Figure 1A to 1D shows the method forming ∑ shape SiGe in the pmos devices of prior art.Wherein, Figure 1A shows the grid formed on substrate and the sidewall spacer be positioned on the sidewall of grid both sides; It is the groove of general rectangular that Figure 1B shows the cross section formed in the substrate by being dry-etched between neighboring gates; The rectangular recess that Fig. 1 C shows being formed carries out crystal orientation optionally wet etching, thus this rectangular recess is expanded to ∑ shape; Fig. 1 D illustrates epitaxial growth SiGe in formed ∑ connected in star, thus forms source region and the drain region of SiGe.
It is sharp groove that Fig. 1 E shows by the bottom that optionally wet etching is formed in the substrate, crystal orientation.
Fig. 2 schematically shows the flow chart forming the method for ∑ connected in star in the substrate of PMOS device according to disclosure embodiment.
Fig. 3 A to 3F is the sectional view of each step in the method for the formation ∑ connected in star be shown schematically in Fig. 2.Wherein, Fig. 3 A shows the gate dielectric layer formed on substrate, the grid on gate dielectric layer, at the top mask layer of top portions of gates and the sidewall spacer that is positioned on the sidewall of grid both sides; Fig. 3 B shows with top mask layer and sidewall spacer for mask, by being dry-etched in the groove forming general rectangular in the substrate between adjacent wall distance piece; Fig. 3 C shows by O +ion implanted process, and bottom portion of groove with sidewall are formed the oxide skin(coating) that thickness is different; Fig. 3 D shows by isotropism wet etching, fully removes the oxide skin(coating) in recess sidewall, partly removes the oxide skin(coating) on bottom portion of groove simultaneously; Fig. 3 E show with bottom portion of groove retain oxide skin(coating) for stop-layer, crystal orientation optionally wet etching is carried out to general rectangular groove, thus this groove is expanded to ∑ shape; And Fig. 3 F shows the oxide skin(coating) removed bottom portion of groove and retain.
Embodiment
Various exemplary embodiment of the present invention is described in detail now with reference to accompanying drawing.It should be noted that: unless specifically stated otherwise, otherwise positioned opposite, the numerical expression of the parts of setting forth in these embodiments and step and numerical value do not limit the scope of the invention.
Meanwhile, it should be understood that for convenience of description, the size of the various piece shown in accompanying drawing is not draw according to the proportionate relationship of reality.
Illustrative to the description only actually of at least one exemplary embodiment below, never as any restriction to the present invention and application or use.
May not discuss in detail for the known technology of person of ordinary skill in the relevant, method and apparatus, but in the appropriate case, described technology, method and apparatus should be regarded as a part of authorizing specification.
In all examples with discussing shown here, any occurrence should be construed as merely exemplary, instead of as restriction.Therefore, other example of exemplary embodiment can have different values.
It should be noted that: represent similar terms in similar label and letter accompanying drawing below, therefore, once be defined in an a certain Xiang Yi accompanying drawing, then do not need to be further discussed it in accompanying drawing subsequently.
In embodiment of the present disclosure, a point three phases forms ∑ connected in star in the substrate: first, by dry etching process, in the substrate between neighboring gates, Formation cross-section is the groove of general rectangular; Then, by O +ion implanted process, oxide skin(coating) is formed on the bottom and sidewall of groove, wherein, oxide skin(coating) in described recess sidewall is thinner than the oxide skin(coating) of bottom portion of groove, remove the oxide skin(coating) in recess sidewall by wet processing afterwards, only retain the portions of oxide layer on bottom portion of groove; Finally, the sidewall of groove, as stop-layer, by crystal orientation optionally wet etching treatment, is formed as having ∑ shape by the oxide skin(coating) retained on bottom portion of groove, removes the oxide skin(coating) on bottom portion of groove more afterwards by wet processing.
Fig. 2 schematically shows the flow chart forming the method for ∑ connected in star in the substrate of PMOS device according to disclosure embodiment.Fig. 3 A to 3F is the sectional view of each step in the method for the formation ∑ connected in star be shown schematically in Fig. 2.Embodiment of the present disclosure is described in detail below with reference to Fig. 2 and Fig. 3 A to 3F.
First, in the step S210 of Fig. 2, substrate 300 is provided and on substrate 300, forms the grid 301 on gate dielectric layer and gate dielectric layer, be formed with top mask layer 302 at grid 301 top, and on the sidewall of grid both sides, be formed with sidewall spacer 303 (see Fig. 3 A).In the present embodiment, sidewall spacer 303 comprises biased distance piece 305 closer to grid 301 and the master space part 304 that is positioned on biased distance piece 305 outside side wall.In other embodiments, sidewall spacer 303 can have other configurations, such as, be made up of the distance piece of individual layer or more than three layers or three layers.
Substrate such as can be made up of silicon.Gate dielectric layer can be such as Si oxide.Grid in the present embodiment can be such as polysilicon gate.Top mask layer 302 and sidewall spacer 303 for protecting grid 301 in dry etching subsequently, O +ion implanted process, wet etching and source/drain regions ion implantation technology.Top mask layer 302 can be such as silicon nitride.Master space part 304 can be such as silicon nitride, and biased distance piece 305 can be such as Si oxide.Grid 301, the formation of top mask layer 302 and sidewall spacer 303 can utilize and well known to a person skilled in the art that technique realizes, and does not repeat them here.
Next, in the step S220 of Fig. 2, with top mask layer 302 and sidewall spacer 303 for mask, dry etching is carried out to substrate 300, to form groove 306 in the substrate between adjacent sidewall spacer 303.As shown in Figure 3 B, the cross section of groove 306 is rectangular shape.Here dry etching such as can adopt HBr or Cl 2as key reaction gas.
It should be noted that, although this embodiment illustrates the groove forming general rectangular in the substrate between adjacent grid, such as, but groove also can be formed in other regions of substrate in other embodiments, in the substrate between fleet plough groove isolation structure and grid.
In addition, although it should be noted that the cross section of illustrative groove 306 in Fig. 3 B is rectangular shape, the groove of other cross sectional shapes can also be adopted in other embodiments, such as " U " tee section.
Then, in the step S230 of Fig. 2, O +ion implanted process is carried out to substrate 300, to form oxide skin(coating) 307 on the bottom of groove 306, and form oxide skin(coating) 308 on the sidewall of groove 306.Oxide skin(coating) 307 and 308 is such as silicon oxide layer.As shown in Figure 3 C, the oxide skin(coating) 308 in recess sidewall is thinner than the oxide skin(coating) 307 on bottom portion of groove.In one embodiment, the thickness of the oxide skin(coating) 307 on bottom portion of groove can be 5 dust to 100 dusts, and the thickness of oxide skin(coating) 308 in recess sidewall can be 3 dust to 10 dusts.
In one example, under the Implantation Energy of 2keV to 15keV, oxonium ion can be injected to substrate 300 and reaches 10 13ion/cm 2to 10 15ion/cm 2implantation dosage.As shown in FIG. 3 C, can along the direction of arrow 309 (that is, with the direction that the sidewall of groove 306 is substantially parallel) by O +ion implanted in groove 306.In the present embodiment, due to the injection direction of oxonium ion and the sidewall of groove 306 substantially parallel, so oxidation mainly occurs on the bottom of groove, thus the oxide skin(coating) 307 that bottom portion of groove is formed is much thicker than the oxide skin(coating) 308 that recess sidewall is formed.
Next, in the step S240 of Fig. 2, by isotropism wet etching treatment, such as utilize the method for HF solution or HF steam or other removal Si oxides well known in the art, fully remove the oxide skin(coating) 308 in recess sidewall, and the oxide skin(coating) 307 partly removed on bottom portion of groove, as shown in Figure 3 D.Such as, in step S230 when the thickness of the oxide skin(coating) 307 that bottom portion of groove is formed is 5 dust to 100 dust, after the wet treatment of step S240, the thickness of the oxide skin(coating) 307 on bottom portion of groove can be 2 dust to 97 dusts.
Then, in the step S250 of Fig. 2, using the oxide skin(coating) 307 on bottom portion of groove as stop-layer, crystal orientation optionally wet etching is carried out to groove 306, so that the inwall of groove 306 is formed as having ∑ shape, as shown in FIGURE 3 E.In one embodiment, can adopt mass concentration be 10% to 25% Tetramethylammonium hydroxide (TMAH) etch at temperature 70 C to 90 DEG C.
Due to the existence of oxide skin(coating) 307, make in above-mentioned crystal orientation optionally wet etching treatment, along the etching stopping in <100> crystal orientation.Thus, the ∑ connected in star occurring the point end is avoided.And the degree of depth of the final ∑ connected in star formed mainly is controlled by the dry etching process in step S220, and therefore, the method for disclosure embodiment can obtain gratifying load effect value.In the disclosure, " load effect value " is defined as the ratio of the etching depth at different components region place in same substrate.In the present embodiment, load effect value can in the scope of 1% to 5%.
Finally, in the step S260 of Fig. 2, by isotropism wet etching treatment, remove the oxide skin(coating) 307 on bottom portion of groove, obtain finally in order to the ∑ connected in star 306 of epitaxial growth SiGe thus, as illustrated in Figure 3 F.In one embodiment, HF solution or HF steam or the method that other remove Si oxide well known in the art such as can be utilized to carry out above-mentioned wet etching treatment.
It should be noted that and before substrate being carried out to dry etching (that is, the step S220 in Fig. 2) or after groove epitaxial growth SiGe, ion implantation can be carried out in the substrate to form source region and drain region.
It should be noted that eSiGe structure is generally for PMOS transistor as source region and drain region.Therefore, for the semiconductor device comprising PMOS transistor and nmos pass transistor simultaneously, being formed in the process of ∑ shape for PMOS transistor, need to cover nmos pass transistor part with mask etc.
The method of disclosure embodiment, by forming silicon oxide layer at bottom portion of groove, as the stop-layer of follow-up crystal orientation optionally wet etching treatment, thus prevents the bottom occurring point when forming ∑ connected in star, and obtains lower load effect value.
So far, the method according to manufacture semiconductor device of the present invention has been described in detail.In order to avoid covering design of the present invention, details more known in the field are not described.Those skilled in the art, according to description above, can understand how to implement technical scheme disclosed herein completely.
Although be described in detail specific embodiments more of the present invention by example, it should be appreciated by those skilled in the art, above example is only to be described, instead of in order to limit the scope of the invention.It should be appreciated by those skilled in the art, can without departing from the scope and spirit of the present invention, above embodiment be modified.Scope of the present invention is limited by claims.

Claims (17)

1. manufacture a method for semiconductor device, comprise the following steps:
Formation cross-section is substantially the groove of rectangle in the substrate;
On the sidewall and bottom of described groove, form oxide skin(coating) by O +ion implanted process, the oxide skin(coating) on the sidewall of wherein said groove is thinner than the oxide skin(coating) on the bottom of described groove;
By the first isotropism wet etching treatment, fully remove the oxide skin(coating) in described recess sidewall, and partly remove the oxide skin(coating) on described bottom portion of groove;
Using the oxide skin(coating) on described bottom portion of groove as stop-layer, crystal orientation optionally wet etching is carried out to described groove, the sidewall of described groove is formed as ∑ shape and makes the bottom flat of described groove; And
By the second isotropism wet etching treatment, remove the oxide skin(coating) on described bottom portion of groove.
2. the method for claim 1, wherein with the Implantation Energy of 2keV to 15keV and 10 13ion/cm 2to 10 15ion/cm 2implantation dosage carry out described O +ion implanted process.
3. the method for claim 1, wherein carry out described O +ion implanted process along the direction substantially parallel with the sidewall of described groove.
4. the thickness of the oxide skin(coating) on the bottom portion of groove the method for claim 1, wherein utilizing O +ion implanted process to obtain is 5 dust to 100 dusts.
5. method as claimed in claim 4, wherein, the thickness of the oxide skin(coating) in the recess sidewall utilizing O +ion implanted process to obtain is 3 dust to 10 dusts.
6. method as claimed in claim 4, wherein, after described first isotropism wet etching treatment, the thickness of the oxide skin(coating) on described bottom portion of groove is 2 dust to 97 dusts.
7. the method for claim 1, wherein described first isotropism wet etching treatment comprises and utilizes HF solution or HF steam to remove oxide skin(coating).
8. the method for claim 1, wherein described second isotropism wet etching treatment comprises and utilizes HF solution or HF steam to remove oxide skin(coating).
9. the method for claim 1, wherein described in Formation cross-section is substantially the groove of rectangle in the substrate step comprise: utilize dry etching process, form the groove that described cross section is substantially rectangle in the substrate.
10. the method for claim 1, wherein described in Formation cross-section is substantially the groove of rectangle in the substrate step comprise:
Grid substrate being formed gate dielectric layer and is positioned on gate dielectric layer, top portions of gates is formed with top mask layer;
Described grid both sides sidewall forms sidewall spacer;
With described top mask layer and described sidewall spacer for mask, dry etching is carried out to described substrate, is substantially the groove of rectangle with Formation cross-section in the substrate between adjacent sidewall spacer.
11. the method for claim 1, wherein describedly comprise the step that described groove carries out crystal orientation optionally wet etching: adopt Tetramethylammonium hydroxide (TMAH) to carry out wet etching to described groove.
12. methods as described in claim 1 or 10, wherein, described crystal orientation optionally wet etching be greater than etch rate along <111> crystal orientation along the etch rate in <100> crystal orientation.
13. grids the method for claim 1, wherein formed over the substrate are polysilicon gate.
14. the method for claim 1, also comprise: after removing the oxide skin(coating) on bottom portion of groove by the second isotropism wet etching treatment, at the groove epitaxial growth SiGe of ∑ shape.
15. the method for claim 1, are also included in before carrying out dry etching to described substrate and in described substrate, carry out ion implantation to form source region and drain region.
16. methods as claimed in claim 14, carry out ion implantation to form source region and drain region in described substrate after being also included in groove epitaxial growth SiGe.
17. the method for claim 1, are also included in before carrying out dry etching to described substrate, form mask, and expose the region that will form PMOS device at the overlying regions that will form nmos device.
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