CN108538724B - Semiconductor structure and forming method thereof - Google Patents

Semiconductor structure and forming method thereof Download PDF

Info

Publication number
CN108538724B
CN108538724B CN201710117757.2A CN201710117757A CN108538724B CN 108538724 B CN108538724 B CN 108538724B CN 201710117757 A CN201710117757 A CN 201710117757A CN 108538724 B CN108538724 B CN 108538724B
Authority
CN
China
Prior art keywords
layer
forming
region
fin
silicon
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201710117757.2A
Other languages
Chinese (zh)
Other versions
CN108538724A (en
Inventor
李勇
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
Original Assignee
Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Semiconductor Manufacturing International Shanghai Corp, Semiconductor Manufacturing International Beijing Corp filed Critical Semiconductor Manufacturing International Shanghai Corp
Priority to CN201710117757.2A priority Critical patent/CN108538724B/en
Publication of CN108538724A publication Critical patent/CN108538724A/en
Application granted granted Critical
Publication of CN108538724B publication Critical patent/CN108538724B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823821—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0924—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

A semiconductor structure and a method of forming the same, the method comprising: providing a substrate and a discrete fin part on the substrate; forming an isolation structure covering the side wall of the fin part on the substrate; after the isolation structure is formed, forming a pseudo gate structure which crosses the fin part and covers the top of the fin part and the surface of the side wall; forming a side wall on the side wall of the pseudo gate structure; after the side walls are formed, grooves are formed in the fin parts on the two sides of the pseudo gate structure; forming a doped epitaxial layer in the groove; after the doped epitaxial layer is formed, forming an interlayer dielectric layer on the isolation structure exposed out of the pseudo gate structure, wherein the interlayer dielectric layer is exposed out of the top of the pseudo gate structure; removing the pseudo gate structure, and forming an opening in the interlayer dielectric layer; forming a barrier layer at the bottom of the opening; removing the barrier layer in the opening; and after the barrier layer is removed, filling a metal layer in the opening to form a metal gate structure. According to the invention, the doped epitaxial layer and the metal layer are isolated through the barrier layer, so that the probability of bridging between the metal gate structure and the doped epitaxial layer is reduced.

Description

Semiconductor structure and forming method thereof
Technical Field
The present invention relates to the field of semiconductors, and more particularly, to a semiconductor structure and a method for forming the same.
Background
In semiconductor manufacturing, integrated circuit feature sizes continue to decrease with the trend toward very large scale integrated circuits. To accommodate the reduction in feature size, the channel length of MOSFETs has also been correspondingly shortened. However, as the channel length of the device is shortened, the distance between the source and the drain of the device is also shortened, so that the control capability of the gate to the channel is deteriorated, the difficulty of the gate voltage to pinch off the channel is increased, and the sub-threshold leakage (SCE) phenomenon, so-called short-channel effect (SCE), is easier to occur.
Therefore, in order to better accommodate the reduction of feature sizes, semiconductor processes are gradually starting to transition from planar MOSFETs to three-dimensional transistors with higher power efficiency, such as fin field effect transistors (finfets). In the FinFET, the gate can control the ultrathin body (fin part) at least from two sides, and compared with a planar MOSFET, the gate has stronger control capability on a channel and can well inhibit a short-channel effect; and finfets have better compatibility with existing integrated circuit fabrication relative to other devices.
However, the electrical performance and yield of the semiconductor devices formed by the prior art are still to be improved.
Disclosure of Invention
The invention provides a semiconductor structure and a forming method thereof, which can optimize the electrical performance and yield of a semiconductor device.
To solve the above problems, the present invention provides a method for forming a semiconductor structure, comprising: providing a base, wherein the base comprises a substrate and a discrete fin part positioned on the substrate; forming an isolation structure on the substrate with the exposed fin portion, wherein the isolation structure covers part of the side wall of the fin portion, and the top of the isolation structure is lower than the top of the fin portion; after the isolation structure is formed, forming a pseudo-gate structure crossing the fin part, wherein the pseudo-gate structure covers part of the top surface and the side wall surface of the fin part; forming a side wall on the side wall of the pseudo gate structure; after the side walls are formed, grooves are formed in the fin parts on two sides of the pseudo gate structure; forming a doped epitaxial layer in the groove; after the doped epitaxial layer is formed, forming an interlayer dielectric layer on the isolation structure exposed out of the pseudo gate structure, wherein the interlayer dielectric layer is exposed out of the top of the pseudo gate structure; removing the pseudo gate structure, and forming an opening in the interlayer dielectric layer; forming a barrier layer at the bottom of the opening; removing the barrier layer in the opening; and after removing the barrier layer in the opening, filling a metal layer in the opening to form a metal gate structure.
Accordingly, the present invention also provides a semiconductor structure comprising: the base comprises a substrate and a discrete fin part positioned on the substrate; the isolation structure is positioned on the substrate with the exposed fin part, covers partial side walls of the fin part, and has the top lower than the top of the fin part; the interlayer dielectric layer is positioned on the isolation structure and is internally provided with an opening for exposing the fin part and the isolation structure; the doped epitaxial layer is positioned in the fin parts at two sides of the opening; the side wall is positioned on the side wall of the opening; and the barrier layer is positioned at the bottom of the opening.
Compared with the prior art, the technical scheme of the invention has the following advantages:
the invention provides a method for forming a semiconductor structure, which comprises the following steps: providing a base, wherein the base comprises a substrate and a discrete fin part positioned on the substrate; forming an isolation structure on the substrate with the exposed fin part; forming a pseudo gate structure crossing the fin portion; forming a side wall on the side wall of the pseudo gate structure; after the side walls are formed, grooves are formed in the fin parts on two sides of the pseudo gate structure; forming a doped epitaxial layer in the groove; after the doped epitaxial layer is formed, forming an interlayer dielectric layer on the isolation structure exposed out of the pseudo gate structure, wherein the interlayer dielectric layer is exposed out of the top of the pseudo gate structure; removing the pseudo gate structure, and forming an opening in the interlayer dielectric layer; forming a barrier layer at the bottom of the opening; removing the barrier layer in the opening; and after removing the barrier layer in the opening, filling a metal layer in the opening to form a metal gate structure. In the process of forming grooves in the fin parts on two sides of the pseudo gate structure, because the isolation structure is exposed in an etching process environment for etching the fin parts, the etching process is easy to cause etching loss on the pseudo gate structure, the isolation structure exposed out of the fin parts and the isolation structure below the side wall, so that gaps generated by the loss of the isolation structure are formed below the side wall; in the process of forming the barrier layer, the barrier layer also fills the gap, and under the protection action of the side wall, the barrier layer in the gap is reserved after the barrier layer in the opening is removed; therefore, when the opening is filled with the metal layer, the barrier layer in the gap can play a role in isolating the doped epitaxial layer from the metal layer, and the probability of bridging (bridge) between the metal gate structure and the doped epitaxial layer is low.
In an alternative scheme, the barrier layer is made of silicon oxide, silicon nitride or silicon oxynitride, and the barrier layer is made of a dielectric material, so that the barrier layer has high process compatibility, and adverse effects on the electrical performance and yield of a semiconductor device can be avoided.
The present invention provides a semiconductor structure, comprising: the base comprises a substrate and a discrete fin part positioned on the substrate; the isolation structure is positioned on the substrate with the exposed fin part, covers partial side walls of the fin part, and the top of the isolation structure is lower than the top of the fin part; the interlayer dielectric layer is positioned on the isolation structure and is internally provided with an opening of the fin part and the isolation structure; the doped epitaxial layer is positioned in the fin parts at two sides of the opening; the side wall is positioned on the side wall of the opening; and the barrier layer is positioned at the bottom of the opening. In the process of manufacturing a semiconductor, the process of forming the doped epitaxial layer is easy to cause etching loss on the isolation structure and also easy to cause etching loss on the isolation structure below the side wall, so that a gap generated by the loss of the isolation structure is formed below the side wall; in the forming process of the barrier layer, the barrier layer also fills the gap, and under the protection effect of the side wall, when the barrier layer in the opening is removed, the barrier layer in the gap can be reserved; the manufacturing process of the semiconductor also comprises the step of filling a metal layer in the opening to form a metal gate structure, so that when the opening is filled with the metal layer, the barrier layer in the gap can play a role in isolating the doped epitaxial layer from the metal layer, and the probability of bridging (bridge) between the metal gate structure and the doped epitaxial layer is lower.
Drawings
FIGS. 1 and 2 are schematic structural diagrams corresponding to steps in a method of forming a semiconductor structure;
fig. 3 to 33 are schematic structural diagrams corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention.
Detailed Description
As is known in the art, the electrical performance and yield of semiconductor devices are still to be improved. The reason for this analysis is:
referring to fig. 1 and fig. 2 in combination, a schematic structural diagram corresponding to each step in a method for forming a semiconductor structure is shown, fig. 1 is a perspective view, and fig. 2 is a schematic structural diagram of a cross-section of a line (shown as a cut line X1X2 in fig. 1) cut along a fin extending direction at an isolation structure position based on fig. 1.
Referring to fig. 1, a base is provided, the base including a substrate 10 and a discrete fin portion 11 on the substrate 10; forming an isolation structure 12 on the substrate 10 exposed out of the fin portion 11, wherein the isolation structure 12 covers a part of the sidewall of the fin portion 11, and the top of the isolation structure 12 is lower than the top of the fin portion 11; after the isolation structure 12 is formed, forming a dummy gate structure 13 crossing the fin portion 11, wherein the dummy gate structure 13 covers part of the top surface and the side wall surface of the fin portion 11; and forming a side wall 14 on the side wall of the dummy gate structure 13.
Referring to fig. 2 in combination, after the sidewalls 14 are formed, the fin portions 11 (as shown in fig. 1) on both sides of the dummy gate structure 13 are etched, and a groove (not shown) is formed in the fin portion 11; a doped epitaxial layer 15 is formed within the recess.
After the doped epitaxial layer 15 is formed, the following steps further include: forming an interlayer dielectric layer (not shown) on the isolation structure 12 exposed by the dummy gate structure 13; removing the dummy gate structure 13, and forming an opening (not shown) in the interlayer dielectric layer; and filling a metal layer in the opening to form a metal gate structure.
When the fin portions 11 on the two sides of the dummy gate structure 13 are etched, the isolation structure 12 is exposed in an etching environment for etching the fin portions 11, so that the etching process easily causes etching loss to the isolation structure 12 exposed by the dummy gate structure 13 and the fin portions 11 and the isolation structure 12 below the sidewall 14 (as shown by a dotted line circle 50 in fig. 1), thereby causing a gap to be formed below the sidewall 14 (as shown by a dotted line circle 51 in fig. 2). Therefore, when the opening is filled with the metal layer, the metal layer fills the gap in addition to the opening; therefore, bridging (bridging) between the metal layer and the doped epitaxial layer 15 through the gap is easily caused, that is, bridging between the doped epitaxial layer 15 and the formed metal gate structure is easily caused, and thus the electrical performance and yield of the semiconductor device are reduced.
When the formed doped epitaxial layer 15 is of a P type, the etching amount of etching the fin parts 11 on the two sides of the dummy gate structure 13 is large, the height of the fin parts 11 protruding out of the isolation structure 12 after the corresponding etching is low, and the doped epitaxial layer 15 is closer to the isolation structure 12 in the direction along the normal line of the surface of the substrate 10; the problem of bridging of the doped epitaxial layer 15 with the metal gate structure is therefore exacerbated when the substrate 10 is used to form a P-type device.
In order to solve the technical problem, the invention provides a method for forming a semiconductor structure, which comprises the following steps: providing a base, wherein the base comprises a substrate and a discrete fin part positioned on the substrate; forming an isolation structure on the substrate with the exposed fin part; forming a pseudo gate structure crossing the fin portion; forming a side wall on the side wall of the pseudo gate structure; after the side walls are formed, grooves are formed in the fin parts on two sides of the pseudo gate structure; forming a doped epitaxial layer in the groove; after the doped epitaxial layer is formed, forming an interlayer dielectric layer on the isolation structure exposed out of the pseudo gate structure, wherein the interlayer dielectric layer is exposed out of the top of the pseudo gate structure; removing the pseudo gate structure, and forming an opening in the interlayer dielectric layer; forming a barrier layer at the bottom of the opening; removing the barrier layer in the opening; and after removing the barrier layer in the opening, filling a metal layer in the opening to form a metal gate structure. In the process of forming grooves in the fin parts on two sides of the pseudo gate structure, because the isolation structure is exposed in an etching process environment for etching the fin parts, the etching process is easy to cause etching loss on the pseudo gate structure, the isolation structure exposed out of the fin parts and the isolation structure below the side wall, so that gaps generated by the loss of the isolation structure are formed below the side wall; in the process of forming the barrier layer, the barrier layer also fills the gap, and under the protection action of the side wall, the barrier layer in the gap is reserved after the barrier layer in the opening is removed; therefore, when the opening is filled with the metal layer, the barrier layer in the gap can play a role in isolating the doped epitaxial layer from the metal layer, and the probability of bridging (bridge) between the metal gate structure and the doped epitaxial layer is low.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 3 to 33 are schematic structural diagrams corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention.
Referring to fig. 3, fig. 3 is a perspective view (only two fins are shown) providing a base (not labeled) comprising a substrate 100 and discrete fins (not labeled) on the substrate 100.
The substrate is used for forming a fin field effect transistor, the substrate 100 provides a process platform for the subsequent formation of the fin field effect transistor, and the fin portion is used for providing a channel of the formed fin field effect transistor.
In this embodiment, taking the formed finfet as a CMOS device as an example, the substrate 100 includes a PMOS region I for forming a P-type device and an NMOS region II for forming an N-type device. In other embodiments, the substrate may include only PMOS regions for forming P-type devices, or only NMOS regions for forming N-type devices.
Correspondingly, the fin portion on the PMOS region I substrate 100 is a first fin portion 110, and the fin portion on the NMOS region II substrate 100 is a second fin portion 120.
In this embodiment, the substrate 100 is a silicon substrate. In other embodiments, the material of the substrate can also be germanium, silicon carbide, gallium arsenide, or indium gallium, and the substrate can also be a silicon-on-insulator substrate, a germanium-on-insulator substrate, or a glass substrate. The material of the substrate 100 may be selected to be suitable for process requirements or easy integration.
The material of the fin is the same as the material of the substrate 100. In this embodiment, the fin portion is made of silicon, that is, the first fin portion 110 and the second fin portion 120 are made of silicon. In other embodiments, the material of the fin may also be germanium, silicon carbide, gallium arsenide, or indium gallium arsenide.
Specifically, the steps of forming the substrate 100 and the fin portion include: providing an initial substrate; forming a patterned fin mask layer 200 on the surface of the initial substrate; and etching the initial substrate by taking the fin part mask layer 200 as a mask, taking the etched initial substrate as the substrate 100, and taking the protrusion on the surface of the substrate 100 as a fin part.
In this embodiment, after the substrate 100 and the fin portion are formed, the fin portion mask layer 200 on the top of the fin portion is remained. The fin mask layer 200 is made of silicon nitride, and when a planarization process is performed subsequently, the top surface of the fin mask layer 200 is used for defining a stop position of the planarization process and plays a role in protecting the top of the fin.
Referring to fig. 4, an isolation structure 101 is formed on the substrate 100 where the fin (not labeled) is exposed, where the isolation structure 101 covers a portion of the sidewall of the fin, and the top of the isolation structure 101 is lower than the top of the fin.
The isolation structure 101 serves as an isolation structure of a semiconductor device, and is used for isolating adjacent devices and also used for isolating adjacent fins. In this embodiment, the isolation structure 101 is made of silicon oxide. In other embodiments, the material of the isolation structure may also be silicon nitride or silicon oxynitride.
Specifically, the step of forming the isolation structure 101 includes: filling an isolation film on the substrate 100 exposed by the first fin 110 and the second fin 120, wherein the top of the isolation film is higher than the top of the fin mask layer 200 (shown in fig. 3); grinding to remove the isolation film higher than the top of the fin mask layer 200; etching back the remaining isolation film with a partial thickness to expose the tops and partial sidewalls of the first fin portion 110 and the second fin portion 120, thereby forming the isolation structure 101; the fin mask layer 200 is removed.
Referring to fig. 5 to 7 in combination, fig. 5 is a perspective view based on fig. 4, fig. 6 is a schematic cross-sectional structure of fig. 5 along a cut line B1B2, fig. 7 is a schematic cross-sectional structure of fig. 5 along a cut line A1a2 and a cut line D1D2, respectively, after the isolation structures 101 are formed, dummy gate structures (dummy gate)130 crossing the fins (not shown) are formed, and the dummy gate structures 130 cover a portion of the top surface and the sidewall surfaces of the fins.
In this embodiment, the metal gate structure is formed by a process of forming a high-k gate dielectric layer and then forming a gate electrode layer (high-k metal gate last), and the dummy gate structure 130 occupies a space for forming the metal gate structure subsequently.
In this embodiment, the dummy gate structure 130 is a stacked structure. The dummy gate structure 130 includes a dummy oxide layer 131 and a dummy gate layer 132 on the dummy oxide layer 131. The dummy gate layer 132 is made of polysilicon, silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride or amorphous carbon, and the dummy oxide layer 131 is made of silicon oxide or silicon oxynitride. Specifically, in this embodiment, the material of the dummy oxide layer 131 is silicon oxide, and the material of the dummy gate layer 132 is polysilicon.
In other embodiments, the dummy gate structure may also be a single-layer structure, and correspondingly, the dummy gate structure includes a dummy gate layer.
Specifically, the step of forming the dummy gate structure 130 includes: forming a dummy oxide layer 131 on the isolation structure 101, wherein the dummy oxide layer 131 spans the fin portion and covers the top surface and the sidewall surface of the fin portion; forming a dummy gate film on the dummy oxide layer 131; forming a gate mask 210 on the surface of the dummy gate film, wherein the gate mask 210 defines a pattern of the dummy gate layer 132 to be formed; and patterning the dummy gate film by taking the gate mask 210 as a mask to form a dummy gate structure 130 on the isolation structure 101.
In this embodiment, the dummy gate structure 130 in the PMOS region I crosses over the first fin 110, and covers a portion of the top surface and a portion of the sidewall surface of the first fin 110; the dummy gate structure 130 of the NMOS region II crosses over the second fin 120 and covers a portion of the top surface and a portion of the sidewall surface of the second fin 120.
It should be noted that after the dummy gate structure 130 is formed, the gate mask 210 on the top of the dummy gate structure 130 is remained. The gate mask 210 is made of silicon nitride, and the gate mask 210 is used for protecting the top of the dummy gate structure 130 in a subsequent process. In other embodiments, the material of the gate mask may also be silicon oxynitride, silicon carbide, or boron nitride.
With reference to fig. 8 to 12, fig. 8 is a schematic cross-sectional structure based on fig. 6, fig. 9 is a schematic cross-sectional structure based on fig. 7, fig. 10 is a schematic cross-sectional structure based on fig. 8, fig. 11 is a schematic cross-sectional structure based on fig. 9, and fig. 12 is a schematic cross-sectional structure of a cut line perpendicular to the extending direction of the fin portion at the position of the sidewall (as indicated by a cut line C1C2 in fig. 5), and a sidewall 300 (as shown in fig. 11) is formed on the sidewall of the pseudo gate structure 130.
The sidewall spacers 300 are used to define the position of the doped epitaxial layer in the subsequent process and also used to protect the dummy gate structure 130.
The material of the sidewall 300 may be silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride or boron carbonitride, and the sidewall 300 may be a single-layer structure or a stacked-layer structure. In this embodiment, the sidewall spacer 300 has a single-layer structure, and the material of the sidewall spacer 300 is silicon nitride.
Specifically, the step of forming the sidewall spacer 300 includes: forming a sidewall film 125 (shown in fig. 9) conformally covering the PMOS region I and NMOS region II dummy gate structures 130; removing the top of the dummy gate structure 130 and the sidewall film 125 on the dummy oxide layer 131, remaining the sidewall film 125 on the sidewall of the dummy gate structure 130, and using the remaining sidewall film 125 as the sidewall 300.
As shown in fig. 10 and 11, in this embodiment, after the sidewall spacers 300 are formed, the dummy oxide layer 131 exposed by the sidewall spacers 300 is also removed, and the dummy oxide layer 131 covered by the sidewall spacers 300 and the dummy gate layer 132 is remained.
It should be noted that, after the side wall 300 is formed, the forming method further includes: forming P-type source and drain lightly doped regions (PLDD) (not shown) in the first fin 110 on two sides of the PMOS region I pseudo gate structure 130 by using the sidewalls 300 of the PMOS region I as a mask, wherein doped ions of the P-type source and drain lightly doped regions are P-type ions; and forming N-type source and drain lightly doped regions (PLDD) (not shown) in the second fin portions 120 on the two sides of the dummy gate structure 130 of the NMOS region II by using the sidewalls 300 of the NMOS region II as a mask, wherein doped ions of the N-type source and drain lightly doped regions are N-type ions.
With reference to fig. 13 to fig. 24, after the sidewalls 300 are formed, grooves (not shown) are formed in the fin portions (not shown) on both sides of the dummy gate structure 130; a doped epitaxial layer (not shown) is formed within the recess.
The groove provides a space position for a subsequent doped epitaxial layer to be formed, and the doped epitaxial layer is used as a source region (source) or a drain region (drain) of the semiconductor device.
In this embodiment, the substrate 100 includes a PMOS region I and an NMOS region II, and thus the step of forming the recess and the doped epitaxial layer includes: forming P-region grooves 111 in the first fins 110 on both sides of the PMOS region I dummy gate structure 130 (as shown in fig. 16); forming a P-type doped epitaxial layer 112 in the P-region groove 111 (as shown in fig. 19); forming N-region grooves 121 in the second fins 120 on both sides of the NMOS region II pseudo gate structure 130 (as shown in fig. 21); an N-doped epitaxial layer 122 is formed within the N-region recess 121 (as shown in fig. 24).
In this embodiment, the steps of forming the P-type doped epitaxial layer 112 and the N-type doped epitaxial layer 122 are described in detail by taking the example of forming the P-type doped epitaxial layer 112 first and then forming the N-type doped epitaxial layer 122.
Referring to fig. 13 and 14 in combination, fig. 13 is a schematic cross-sectional structure based on fig. 10, and fig. 14 is a schematic cross-sectional structure based on fig. 11, wherein a P-region mask layer 310 is formed on the top and sidewalls of the fin (not labeled) in the PMOS region I, and the P-region mask layer 310 is further located on the top and sidewalls of the fin in the NMOS region II.
Specifically, the P-region mask layer 310 is located on the top and sidewalls of the first fins 110 and on the top and sidewalls of the second fins 120.
The process of forming the P-region mask layer 310 may be a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process. In this embodiment, the P-region mask layer 310 is formed by an atomic layer deposition process. Therefore, the P-region mask layer 310 is also located on the top and the sidewall of the dummy gate structure 130 in the PMOS region I, the top and the sidewall of the dummy gate structure 130 in the NMOS region II, and is also located on the isolation structure 101.
The P-region mask layer 310 functions include: when the first fin portion 110 with the partial thickness of the PMOS region I is subsequently etched, the P region mask layer 310 on the sidewall of the first fin portion 110 is used as a mask, so that a certain distance is provided between the subsequently formed P region groove 111 (as shown in fig. 16) and the formed P type source/drain lightly doped region, thereby preventing the P type source/drain lightly doped region from being completely etched and removed; moreover, the P-region mask layer 310 on the fin sidewalls can protect the fin sidewalls, thereby avoiding performing an epitaxial growth process on the sidewalls of the first fin 110 and the second fin 120; in addition, the P-region mask layer 310 in the NMOS region II will be subsequently used as a part of the N-region mask layer in the NMOS region II.
The P-region mask layer 310 may be made of silicon nitride (SiN), silicon carbonitride (SiCN), silicon boronitride (SiBN), silicon oxycarbonitride (SiOCN), or silicon oxynitride (SiON). The material of the P-region mask layer 310 is different from the material of the fin portion, and the material of the P-region mask layer 310 is different from the material of the isolation structure 101. In this embodiment, the P-region mask layer 310 is made of silicon nitride.
With reference to fig. 15 to 17, fig. 15 is a schematic cross-sectional structure based on fig. 13, fig. 16 is a schematic cross-sectional structure based on fig. 14 along a cut line in the extending direction of the first fin portion (as indicated by a cut line A1a2 in fig. 5), fig. 17 is a schematic cross-sectional structure along a cut line perpendicular to the extending direction of the fin portion (as indicated by a cut line C1C2 in fig. 5) at the position of the sidewall, the P-region mask layer 310 on the tops of the fins (not indicated) on both sides of the PMOS-region I dummy gate structure 130 is etched to expose the top surfaces of the fins on both sides of the PMOS-region I dummy gate structure 130, and the PMOS-region I fin portion with a partial thickness is also etched, and a P-region recess 111 is formed in the etched fin portion.
The P-region recess 111 provides a spatial location for the subsequent formation of a P-doped epitaxial layer 112 (shown in fig. 19).
It should be noted that, before etching the P-region mask layer 310 on the tops of fins (not labeled) on both sides of the PMOS region I dummy gate structure 130, the forming method further includes: forming a first graphic layer 220 on the NMOS area II, wherein the first graphic layer 220 covers the P-area mask layer 310 of the NMOS area II. The first pattern layer 220 plays a role of protecting the P region mask layer 310 of the NMOS region II, and the first pattern layer 220 may also cover an area which is not desired to be etched in the PMOS region I.
In this embodiment, the first pattern layer 220 is made of a photoresist material. After the P-region groove 111 is formed, the first pattern layer 220 is removed by a wet stripping or ashing process.
Specifically, a dry etching process is adopted to etch and remove the P-region mask layer 310 on the tops of the first fin portions 110 on two sides of the PMOS region I pseudo gate structure 130; in the process of etching the P-region mask layer 310, the P-region mask layer 310 on the top of the PMOS region I dummy gate structure 130 and on the isolation structure 101 is also etched; after the tops of the first fins 110 on the two sides of the PMOS region I pseudo-gate structure 130 are exposed, continuously etching a part of the first fins 110, and forming the P-region groove 111 in the first fins 110.
In this embodiment, the first fin portion 110 with a partial thickness is etched by using an anisotropic etching process, where the anisotropic etching processThe etching process is a reactive ion etching process, and the parameters of the reactive ion etching process comprise: the reaction gas comprises CF4、SF6And Ar, CF4The flow rate is 50sccm to 100sccm, SF6The flow rate is 10sccm to 100sccm, the flow rate of Ar is 100sccm to 300sccm, the source power is 50W to 1000W, the bias power is 50W to 250W, the process pressure is 50mTorr to 200mTorr, and the process temperature is 20 ℃ to 90 ℃.
It should be noted that, as shown in fig. 15, in this embodiment, in order to increase the volume of the P-type doped epitaxial layer 112 formed in the P-region groove 111 subsequently, the P-region mask layer 310 on the sidewall of the first fin 110 is etched while the first fin 110 is etched, so that after the P-region groove 111 is formed, the remaining P-region mask layer 310 on the sidewall of the first fin 110 is flush with the top of the first fin 110.
It should be further noted that, as shown in fig. 17, in the step of etching the first fin portions 110 at the two sides of the dummy gate structure 130, since the isolation structure 101 in the PMOS region I is exposed to an etching process environment, the etching process is also easy to etch the dummy gate structure 130 in the PMOS region I, the isolation structure 101 exposed by the first fin portions 110, and the isolation structure 101 located at the bottom of the PMOS region I sidewall 300, so that a gap (shown by a dotted circle in fig. 17) generated by loss of the isolation structure 101 is easily formed below the PMOS region I sidewall 300.
In addition, in order to provide a good interface foundation for a subsequent process of forming the P-type doped epitaxial layer 112 to improve the quality of forming the P-type doped epitaxial layer 112, after the P-region groove 111 is formed and before the P-type doped epitaxial layer 112 is formed, the forming method further includes: and cleaning the P-region groove 111.
The cleaning process is used to remove both the impurities in the P-region groove 111 and a native oxide layer (not shown) on the fin surface.
It should be noted that, the isolation structure 101 is exposed in the environment of the cleaning process, so that in order to reduce the loss of the cleaning process to the isolation structure 101 and avoid worsening the gap problem below the PMOS region I-side wall 300, in this embodiment, the cleaning process is a SiCoNi process, and the main etching gas adopted by the SiCoNi process is gaseous hydrofluoric acid.
Referring to fig. 18 and 19, fig. 18 is a schematic cross-sectional view based on fig. 15, and fig. 19 is a schematic cross-sectional view based on fig. 16, wherein a P-type doped epitaxial layer 112 is formed in the P-region recess 111 (shown in fig. 16).
In this embodiment, a selective epitaxy process is adopted, a P-region stress layer is formed in the P-region groove 111, and in the process of forming the P-region stress layer, P-type ions are self-doped in situ to form the P-type doped epitaxial layer 112. In other embodiments, after a P-region stress layer is formed in the P-region groove, P-type ion doping may be performed on the P-region stress layer to form the P-type doped epitaxial layer.
Specifically, the material of the P-region stress layer is Si or SiGe, and the material of the P-type doped epitaxial layer 112 is P-type doped Si or SiGe. The stress layer of the P region provides a pressure stress effect for the channel region of the P type device, so that the carrier mobility of the P type device is improved. In this embodiment, the P-type doped epitaxial layer 112 is made of SiGe.
With reference to fig. 20 to 22, fig. 20 is a schematic cross-sectional structure based on fig. 18, fig. 21 is a schematic cross-sectional structure along a cut line in the extending direction of the second fin (as indicated by a cut line D1D2 in fig. 5), fig. 22 is a schematic cross-sectional structure along a cut line perpendicular to the extending direction of the fin at the position of a sidewall (as indicated by a cut line C1C2 in fig. 5), after forming the P-type doped epitaxial layer 112 (as shown in fig. 18), an N-region mask sidewall 320 is formed on the P-region mask layer 310 in the NMOS region II, wherein the P-region mask layer 310 and the N-region mask 320 in the NMOS region II are used as N-region mask layers (not labeled); the N-region mask layer on the tops of fins (not labeled) on both sides of the NMOS region II dummy gate structure 130 is etched, and the NMOS region II fins with a partial thickness are also etched, forming the N-region groove 121 in the fins (as shown in fig. 21).
The N-region recess 121 provides a spatial location for the subsequent formation of an N-doped epitaxial layer 122 (shown in fig. 24).
In this embodiment, the N-region mask layer is located on the top and the sidewall of the second fin 120, the top and the sidewall of the NMOS region II dummy gate structure 130, and is also located on the isolation structure 101 of the NMOS region II; and etching the second fin part 120 with a part of thickness, and forming the N-region groove 121 in the second fin part 120.
In this embodiment, the process of forming the N-region mask sidewall 320 may be a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process. In this embodiment, the N-region mask sidewall 320 is formed by an atomic layer deposition process. Therefore, the N-region mask sidewall spacers 320 are also located on the P-type doped epitaxial layer 112 and the isolation structure 101 of the PMOS region I, and are also located on the sidewalls and the top of the dummy gate structure 130 (as shown in fig. 19) of the PMOS region I.
The N-region mask spacer 320 has the following functions: on one hand, the N-region mask sidewall 320 and the P-region mask layer 310 form an N-region mask layer of a stacked structure, and when the second fin portions 120 of the thicknesses of the two sides of the NMOS region II pseudo gate structure 130 are subsequently etched, the N-region mask layer of the stacked structure is used as a mask, so that the distance between the subsequently formed N-region groove 121 (shown in fig. 21) and the channel region can be increased through the N-region mask sidewall 320, which is beneficial to improving the short channel effect.
The materials and the formation process of the N-region mask sidewall spacers 320 may refer to the description of the P-region mask layer 310, which is not repeated herein.
Therefore, the material of the N-region mask layer can be silicon nitride, silicon carbonitride, silicon boronitride, silicon oxycarbide or silicon oxynitride. In this embodiment, the N-region mask sidewall spacer 320 is made of silicon nitride. Correspondingly, the N-region mask layer is made of silicon nitride.
Specifically, the step of forming the N-region groove 121 in the second fin 120 includes: etching the N-region mask layer on the tops of the second fins 120 on the two sides of the NMOS region II pseudo-gate structure 130, wherein in the process of etching the N-region mask layer on the tops of the second fins 120, the N-region mask layer on the tops of the NMOS region II pseudo-gate structure 130 is also etched, and the N-region mask layer on the NMOS region II isolation structure 101 is also etched; after the tops of the second fins 120 on the two sides of the NMOS region II pseudo gate structure 12 are exposed, the second fins 120 with a partial thickness are continuously etched, and the N region groove 121 is formed in the second fins 120.
For the etching process for forming the N-region recess 121, reference may be made to the aforementioned description for forming the P-region recess 111 (as shown in fig. 16), and further description is omitted here.
In this embodiment, in order to increase the volume of the N-type doped epitaxial layer 122 formed in the N-region groove 121 subsequently, the N-region mask layer on the sidewall of the second fin 120 is etched while the second fin 120 is etched, so that after the N-region groove 121 is formed, the remaining N-region mask layer on the sidewall of the second fin 120 is flush with the top of the second fin 120.
It should be noted that, according to actual process requirements, the etching amount of the second fin portion 120 is smaller than that of the first fin portion 110 when the P-region groove 111 is formed.
It should be further noted that, before etching the N-region mask layer, the forming method further includes: forming a second pattern layer 230 in the PMOS region I (as shown in fig. 20), where the second pattern layer 230 covers the P-type doped epitaxial layer 112, and the second pattern layer 230 also covers the dummy gate structure 130 in the PMOS region I (as shown in fig. 19).
Specifically, the second pattern layer 230 is formed on the N-region mask sidewall 320 of the PMOS region I, the second pattern layer 230 may play a role in protecting the PMOS region I, and the second pattern layer 230 may also cover an area that is not desired to be etched in the NMOS region II.
In this embodiment, the second pattern layer 230 is made of a photoresist material. After the N-region recess 121 is formed, a wet stripping or ashing process is used to remove the second pattern layer 230.
With reference to fig. 22, it should be noted that, for an NMOS region II, a sidewall 300 is formed on a sidewall of the dummy gate structure 130 of the NMOS region II, a P-region mask layer 310 is formed on a sidewall of the sidewall 300, and an N-region mask sidewall 320 is formed on a sidewall of the P-region mask layer 310, so that, for the N-region mask sidewall 320, the P-region mask layer 310, and the sidewall 300 on the same side of the dummy gate structure 130, a distance between a sidewall of the N-region mask sidewall 320 on a side facing away from the dummy gate structure 130 and a sidewall of the sidewall 300 on a side facing toward the dummy gate structure 130 is larger in an extending direction of the second fin portion 120, where the distance is a sum of thicknesses of the N-region mask sidewall 320, the P-region mask layer 310, and the sidewall 300; compared with the PMOS region I, when the second fin portions 120 with the thickness of the portions on both sides of the NMOS region II pseudo gate structure 130 are etched, the possibility that the etching process causes etching loss to the isolation structure 101 below the NMOS region II sidewall 300 is low, and the possibility that a gap occurs below the NMOS region II sidewall 300 is also correspondingly low.
It should be further noted that, after the N-region groove 121 is formed, the forming method further includes: and cleaning the N region groove 121 by adopting a SiCoNi process, wherein the main etching gas adopted by the SiCoNi process is gaseous hydrofluoric acid.
The cleaning process is used to remove both the impurities in the N-region recess 121 and a native oxide layer (not shown) on the fin surface.
For the cleaning process of the N-region groove 121, reference may be made to the aforementioned description of the cleaning process of the P-region groove 111 (as shown in fig. 16), and further description is omitted here.
Referring to fig. 23 and 24 in combination, fig. 23 is a schematic cross-sectional view based on fig. 20, and fig. 24 is a schematic cross-sectional view based on fig. 21, wherein an N-type doped epitaxial layer 122 is formed in the N-region recess 121 (shown in fig. 21).
In this embodiment, an N-region stress layer is formed in the N-region groove 121 by using a selective epitaxy process, and in the process of forming the N-region stress layer, N-type ions are in-situ self-doped to form the N-type doped epitaxial layer 122. In other embodiments, after an N region stress layer is formed in the N region groove, N-type ion doping may be performed on the N region stress layer to form the N-type doped epitaxial layer.
Specifically, the material of the N-region stress layer is Si or SiC, and the material of the N-type doped epitaxial layer 122 is N-type doped Si or SiC. The N-region stress layer provides a tensile stress effect for a channel region of the N-type device, so that the carrier mobility of the N-type device is improved. In this embodiment, the material of the N-type doped epitaxial layer 122 is SiGe.
Referring to fig. 25 and 26 in combination, fig. 25 is a schematic cross-sectional structure based on fig. 23, fig. 26 is a schematic cross-sectional structure of a cut along the extending direction of the first fin (as shown by a cut of A1a2 in fig. 5) and a cut along the extending direction of the second fin (as shown by a cut of D1D2 in fig. 5), respectively, after forming the doped epitaxial layer (not shown), an interlayer dielectric layer 102 is formed on the isolation structure 101 exposed by the dummy gate structure 130 (as shown in fig. 26), and the interlayer dielectric layer 102 exposes the top of the dummy gate structure 130.
Specifically, after the P-type doped epitaxial layer 112 (shown in fig. 25) and the N-type doped epitaxial layer 122 (shown in fig. 25) are formed, the interlayer dielectric layer 102 is formed.
The interlayer dielectric layer 102 is used for realizing electrical isolation between semiconductor structures and also for defining the size and position of a metal gate structure formed subsequently. In this embodiment, the interlayer dielectric layer 102 is made of silicon oxide. In other embodiments, the interlayer dielectric layer may also be made of other dielectric materials such as silicon nitride, silicon oxynitride, silicon oxycarbonitride, and the like.
Specifically, the step of forming the interlayer dielectric layer 102 includes: forming a dielectric material layer on the isolation structure 101 exposed by the dummy gate structure 130, wherein the dielectric material layer covers the dummy gate structure 130; removing the dielectric material layer higher than the top of the dummy gate structure 130 by chemical mechanical polishing and the like to expose the top of the dummy gate structure 130, and using the residual dielectric material layer as the interlayer dielectric layer 102.
It should be noted that a gate mask 210 is formed on the top of the dummy gate structure 130, so in the step of forming the interlayer dielectric layer 102, the dielectric material layer higher than the top of the gate mask 210 is removed. In this embodiment, after the interlayer dielectric layer 102 is formed, the top of the interlayer dielectric layer 102 is flush with the top of the gate mask 210.
Referring to fig. 27, fig. 27 is a schematic cross-sectional view of fig. 26, in which the dummy gate structure 130 (shown in fig. 26) is removed, and an opening 152 is formed in the interlayer dielectric layer 102.
The opening provides a spatial location for the subsequent formation of a metal gate structure.
In this embodiment, in the step of removing the dummy gate structure 130, the dummy gate layer 132 and the dummy oxide layer 131 in the PMOS region I are removed, an opening 152 penetrating through the interlayer dielectric layer 102 in the PMOS region I and exposing the first fin portion 110 is formed, the dummy gate layer 132 and the dummy oxide layer 131 in the NMOS region II are removed, and an opening 152 penetrating through the interlayer dielectric layer 102 in the NMOS region II and exposing the second fin portion 120 is formed.
In this embodiment, in order to reduce the loss of the isolation structure 101, a dry etching process is used to remove the dummy oxide layer 131.
It should be noted that, as can be seen from the foregoing analysis, a gap (as shown by a dashed circle in fig. 22) is easily formed below the PMOS region I-side wall 300 due to the loss of the isolation structure 101, so that in the step of removing the pseudo oxide layer 131, the material of the isolation structure 101 remaining in the gap may also be removed, so as to increase the gap, so as to fill the gap with the barrier layer in the following step.
Referring to fig. 28 and 29 in combination, fig. 28 is a schematic cross-sectional view based on fig. 27, and fig. 29 is a schematic cross-sectional view taken along a line perpendicular to the extending direction of the fin at the location of the sidewall (as indicated by a line C1C2 in fig. 5), and a barrier layer 350 is formed at the bottom of the opening 152.
The barrier layer 350 is used for filling a gap below the PMOS region I-side wall 300 at the position of the isolation structure 101, and when a metal layer is subsequently filled into the opening 152, the barrier layer 350 in the gap can play a role in isolating the P-type doped epitaxial layer 112 from the metal layer, and accordingly, the probability that a subsequently formed metal gate structure is bridged (bridge) with the P-type doped epitaxial layer 112 through the gap is low.
In order to improve process compatibility, the material of the blocking layer 350 may be an insulating dielectric material such as silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, or silicon oxycarbonitride. In this embodiment, the gap is formed by the loss of the isolation structure 101, so the material of the barrier layer 350 is the same as the material of the isolation structure 101, that is, the material of the barrier layer 350 is silicon oxide.
In this embodiment, the process of forming the barrier layer 350 is an atomic layer deposition process; correspondingly, the barrier layer 350 is also located on the sidewalls of the opening 152 and on the top of the interlayer dielectric layer 102. The ald process has good step coverage and can better fill the corners of the opening 152. As shown in fig. 29, and by utilizing the characteristics of the atomic layer deposition process, the barrier layer 350 may also better fill the gap (shown by the dashed circle in fig. 22) below the PMOS region I-sidewall 300 at the position of the isolation structure 101.
It should be noted that the thickness of the barrier layer 350 is not too small, nor too large. If the thickness of the barrier layer 350 is too small, the effect of filling the gap below the I-side wall 300 of the PMOS region is not obvious, and correspondingly, the effect of the barrier layer 350 on isolating the P-type doped epitaxial layer 112 from the metal layer is not obvious; if the thickness of the barrier layer 350 is too large, material waste and process cost increase are wasted. For this reason, in this embodiment, the thickness of the barrier layer 350 is
Figure BDA0001236098450000171
To
Figure BDA0001236098450000172
Referring to fig. 30 and 31 in combination, fig. 30 is a schematic cross-sectional view based on fig. 28, and fig. 31 is a schematic cross-sectional view based on fig. 29, wherein the barrier layer 350 in the opening 152 (shown in fig. 30) is removed.
The opening 152 is used for forming a metal gate structure in the following, so that after the gap (shown by a dotted circle in fig. 22) below the PMOS region I-sidewall 300 is filled with the barrier layer 350, the barrier layer 350 in the opening 152 is removed.
In this embodiment, the process of removing the barrier layer 350 in the opening 152 is a dry etching process. Specifically, the dry etching process is a SiCoNi process, and the main etching gas adopted by the SiCoNi process is gaseous hydrofluoric acid. The specific etching process parameters may be determined according to the thickness of the barrier layer 350.
Compared with a wet etching process, the dry etching process has better anisotropic etching characteristics, so that the loss of the barrier layer 350 in the gap caused by the etching process can be reduced, and the adverse effect on the filling effect of the barrier layer 350 in the gap is avoided. Therefore, under the protection of the sidewall spacers 300, in the step of removing the barrier layer 350 in the opening 152, the barrier layer 350 in the gap is retained.
Referring to fig. 32 and 33 in combination, fig. 32 is a schematic cross-sectional structure based on fig. 30, fig. 33 is a schematic cross-sectional structure based on fig. 31, and after removing the barrier layer 350 (shown in fig. 28) in the opening 152 (shown in fig. 30), a metal layer 520 is filled in the opening 152 to form a metal gate structure 500.
The metal gate structure 500 is used to control the conduction and the cut-off of the channel of the formed semiconductor device.
After removing the barrier layer 350 in the opening 152 and before filling the metal layer 520 in the opening 152, the forming method further includes: a gate dielectric layer (not labeled) is formed on the bottom and sidewalls of the opening 152, and is also located on top of the interlayer dielectric layer 102. Specifically, the gate dielectric Layer includes an Interfacial Layer (IL) (not shown) and a high-k gate dielectric Layer 510 located on a surface of the Interfacial Layer.
The interface layer is formed at the bottom of the opening 152 in the PMOS region I and the NMOS region II, and provides a good interface foundation for forming the high-k gate dielectric layer 510, so as to improve the quality of the high-k gate dielectric layer 510, reduce the interface state density between the high-k gate dielectric layer 510 and the first fin portion 110 and the second fin portion 120, and avoid adverse effects caused by direct contact between the high-k gate dielectric layer 510 and the first fin portion 110 and the second fin portion 120. The interface layer is made of silicon oxide or silicon oxynitride.
The high-k gate dielectric layer 510 is made of a gate dielectric material having a relative dielectric constant greater than that of silicon oxide. In this embodiment, the material of the high-k gate dielectric layer 510 is HfO2. In other embodiments, the material of the high-k gate dielectric layer may also be HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, or ZrO2Or Al2O3。
The step of forming the metal gate junction 500 thus comprises: forming a metal layer 520 on the gate dielectric layers of the PMOS region I and the NMOS region II; and removing the metal layer 520 higher than the top of the interlayer dielectric layer 102, and also removing the high-k gate dielectric layer 510 higher than the top of the interlayer dielectric layer 102, wherein the residual gate dielectric layer and the metal layer 520 in the opening 152 of the PMOS region I are used for forming the metal gate junction 500 of the PMOS region I, the residual gate dielectric layer and the metal layer 520 in the opening 152 of the NMOS region II are used for forming the metal gate junction 500 of the NMOS region II, and the top 500 of the metal gate junction is flush with the top of the interlayer dielectric layer 102.
In this embodiment, in the process of forming the P-region groove 111 (as shown in fig. 16) in the first fin 110 (as shown in fig. 16) on both sides of the dummy gate structure 130 (as shown in fig. 16), since the isolation structure 101 (as shown in fig. 17) is exposed in the environment of the etching process for etching the first fin 110, the etching process is prone to cause etching loss to the isolation structure 101 exposed by the dummy gate structure 130 and the first fin 110, and the isolation structure 101 below the sidewall 300 (as shown in fig. 17), so that a gap (as shown by a dashed circle in fig. 17) generated by the loss of the isolation structure 101 occurs below the sidewall 300; after removing the dummy gate structure 130 to form the opening 152 (as shown in fig. 27) in the interlayer dielectric layer 102, in the process of forming the barrier layer 350 (as shown in fig. 28) in the opening 152, the barrier layer 350 also fills the gap, and under the protection effect of the sidewall 300, after removing the barrier layer 350 in the opening 152, the barrier layer 350 in the gap is retained; therefore, when the metal layer 520 (as shown in fig. 32) is filled in the opening 152, the barrier layer 350 in the gap can isolate the P-type doped epitaxial layer 112 (as shown in fig. 32) from the metal layer 520, and the probability of bridging between the metal gate structure 500 and the P-type doped epitaxial layer 112 is low, that is, the problem of bridging between the P-type doped epitaxial layer 112 and the metal gate structure 500 can be solved by the scheme of the present invention, so that the electrical performance and yield of the semiconductor device can be improved.
Referring to fig. 25, 28 and 29 together, fig. 25 is a schematic cross-sectional structure of a cutting line perpendicular to the extending direction of the fin (as indicated by a cutting line B1B2 in fig. 5), fig. 28 is a schematic cross-sectional structure of a cutting line along the extending direction of the first fin (as indicated by a cutting line A1a2 in fig. 5) and a cutting line along the extending direction of the second fin (as indicated by a cutting line D1D2 in fig. 5), respectively, and fig. 29 is a schematic cross-sectional structure of a cutting line perpendicular to the extending direction of the fin (as indicated by a cutting line C1C2 in fig. 5) at the location of the sidewall. Accordingly, the present invention also provides a semiconductor structure comprising:
a base comprising a substrate 100 and discrete fins (not labeled) on the substrate 100; the isolation structure 101 is located on the substrate 100 with the exposed fin portion, the isolation structure 101 covers part of the side wall of the fin portion, and the top of the isolation structure 101 is lower than the top of the fin portion; an interlayer dielectric layer 102 (shown in fig. 25) on the isolation structure 101, wherein the interlayer dielectric layer 102 has an opening 152 (shown in fig. 28) therein to expose the fin and the isolation structure 101; a doped epitaxial layer (not labeled) located in the fin portions at both sides of the opening 152; a sidewall 300 located on a sidewall of the opening 152; and a barrier layer 350 at the bottom of the opening 152.
The substrate is used for forming a fin field effect transistor, the substrate 100 provides a process platform for forming the fin field effect transistor, and the fin portion is used for providing a channel of the fin field effect transistor.
In this embodiment, taking the formed finfet as a CMOS device as an example, the substrate 100 includes a PMOS region I for forming a P-type device and an NMOS region II for forming an N-type device. In other embodiments, the substrate may include only PMOS regions for forming P-type devices, or only NMOS regions for forming N-type devices.
Correspondingly, the fin portion on the PMOS region I substrate 100 is a first fin portion 110, and the fin portion on the NMOS region II substrate 100 is a second fin portion 120.
In this embodiment, the substrate 100 is a silicon substrate. In other embodiments, the material of the substrate can also be germanium, silicon carbide, gallium arsenide, or indium gallium, and the substrate can also be a silicon-on-insulator substrate, a germanium-on-insulator substrate, or a glass substrate. The material of the substrate 100 may be selected to be suitable for process requirements or easy integration.
The material of the fin is the same as the material of the substrate 100. In this embodiment, the fin portion is made of silicon, that is, the first fin portion 110 and the second fin portion 120 are made of silicon. In other embodiments, the material of the fin may also be germanium, silicon carbide, gallium arsenide, or indium gallium arsenide.
The isolation structure 101 serves as an isolation structure of a semiconductor device, and is used for isolating adjacent devices and also used for isolating adjacent fins 110. In this embodiment, the isolation structure 101 is made of silicon oxide. In other embodiments, the material of the isolation structure may also be silicon nitride or silicon oxynitride.
The interlayer dielectric layer 102 is used for realizing electrical isolation between semiconductor structures and also for defining the size and position of a metal gate structure in the semiconductor manufacturing process. In this embodiment, the interlayer dielectric layer 102 is made of silicon oxide. In other embodiments, the interlayer dielectric layer may also be made of other dielectric materials such as silicon nitride, silicon oxynitride, silicon oxycarbonitride, and the like.
The interlayer dielectric layer 102 has an opening 152; the opening 152 in the PMOS region I penetrates through the interlayer dielectric layer 102 in the PMOS region I and exposes the first fin portion 110, and the opening 152 in the NMOS region II penetrates through the interlayer dielectric layer 102 in the NMOS region II and exposes the second fin portion 120; the opening 152 of the PMOS region I provides a spatial location for forming a metal gate structure of the PMOS region I, and the opening 152 of the NMOS region II provides a spatial location for forming a metal gate structure of the NMOS region II.
The doped epitaxial layer is used as a source region (source) or a drain region (drain) of the semiconductor device.
In this embodiment, the substrate 100 includes a PMOS region I and an NMOS region II, so the doped epitaxial layer in the first fin 110 at two sides of the PMOS region I opening 152 is a P-type doped epitaxial layer 112, and the doped epitaxial layer in the second fin 120 at two sides of the NMOS region II opening 152 is an N-type doped epitaxial layer 122. Accordingly, the P-type doped epitaxial layer 112 serves as a source or drain region of a P-type device, and the N-type doped epitaxial layer 122 serves as a source or drain region of an N-type device.
The forming process of the P-type doped epitaxial layer 112 and the N-type doped epitaxial layer 122 is a selective epitaxial process, so that the P-type doped epitaxial layer 112 is made of P-type doped Si or SiGe, and the N-type doped epitaxial layer 122 is made of N-type doped Si or SiC. In this embodiment, the P-type doped epitaxial layer 112 is SiGe, and the N-type doped epitaxial layer 122 is SiP.
Accordingly, the semiconductor structure further comprises: a P-region mask layer 310 on sidewalls of the PMOS region I first fin 110, and an N-region mask layer (not labeled) on sidewalls of the NMOS region II second fin 120.
When the P-type doped epitaxial layer 112 is formed, the P-region mask layer 310 serves as an etching mask for etching the first fin portion 110, and the P-region mask layer 310 can also avoid performing an epitaxial growth process on the sidewalls of the first fin portion 110 and the second fin portion 120.
The P-region mask layer 310 may be made of silicon nitride (SiN), silicon carbonitride (SiCN), silicon boronitride (SiBN), silicon oxycarbonitride (SiOCN), or silicon oxynitride (SiON). The material of the P-region mask layer 310 is different from the material of the fin portion, and the material of the P-region mask layer 310 is different from the material of the isolation structure 101. In this embodiment, the P-region mask layer 310 is made of silicon nitride.
In this embodiment, in the process of forming the P-region mask layer 310, the P-region mask layer 310 is further formed on the sidewall of the second fin 120, so that the N-region mask layer includes the P-region mask layer 310 on the sidewall of the second fin 120 and an N-region mask sidewall 320 on the sidewall of the P-region mask layer 310, and the N-region mask sidewall 320 is further located on the P-type doped epitaxial layer 112.
That is, the N-region mask layer has a stacked structure; when the N-type doped epitaxial layer 122 is formed, the N-region mask layer is used as an etching mask for etching the second fin portion 120, and the distance between the N-type doped epitaxial layer 122 and the channel region is increased, so that the short channel effect is improved.
Therefore, the N-region mask layer is made of silicon nitride, silicon carbonitride, silicon boride, silicon oxycarbide or silicon oxynitride. In this embodiment, the N-region mask sidewall spacer 320 is made of silicon nitride, and correspondingly, the N-region mask layer is made of silicon nitride.
The spacers 300 are used to define the positions of the P-type doped epitaxial layer 112 and the N-type doped epitaxial layer 122.
The material of the sidewall 300 may be silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride or boron carbonitride, and the sidewall 300 may be a single-layer structure or a stacked-layer structure. In this embodiment, the sidewall spacer 300 has a single-layer structure, and the material of the sidewall spacer 300 is silicon nitride.
It should be noted that, in the semiconductor manufacturing process, a dummy gate structure crossing the fin portion is generally formed first; etching fin parts with partial thicknesses on two sides of the pseudo gate structure, and forming grooves in the fin parts on the two sides of the pseudo gate structure; forming the doped epitaxial layer in the groove; and after the doped epitaxial layer is formed, removing the pseudo gate structure and filling a metal layer at the position of the pseudo gate structure to form the metal gate structure.
When the fin portion is etched, the isolation structure 101 is exposed in an etching process environment, so that the etching process is easy to damage the isolation structure exposed by the dummy gate structure and the fin portion and the isolation structure 101 at the bottom of the sidewall 300, and the loss of the isolation structure 101 below the PMOS region I-sidewall 300 is especially serious, which easily causes a gap (shown by a dotted circle in fig. 22) generated by the loss of the isolation structure 101 below the PMOS region I-sidewall 300.
For the NMOS region II, the sidewall of the opening 152 is provided with a sidewall 300, the sidewall of the sidewall 300 is provided with a P-region mask layer 310, and the sidewall of the P-region mask layer 310 is provided with an N-region mask sidewall 320, so that, for the N-region mask sidewall 320, the P-region mask layer 310 and the sidewall 300 on the same side of the opening 152 in the extending direction of the second fin portion 120, the distance between the sidewall of the N-region mask sidewall 320 on the side opposite to the opening 152 and the sidewall 300 exposed from the opening 152 is larger, and the distance is the sum of the thicknesses of the N-region mask sidewall 320, the P-region mask layer 310 and the sidewall 300; compared with the PMOS region I, when the second fin portion 120 is etched, the possibility that the etching process causes etching loss to the isolation structure 101 below the NMOS region II sidewall 300 is low, and the possibility that a gap appears below the NMOS region II sidewall 300 is also correspondingly low.
Therefore, in the forming process of the barrier layer 350, the barrier layer 350 can fill the gap below the PMOS region I-sidewall 300, and under the protection effect of the sidewall 300, when the barrier layer 350 in the opening 152 is removed, the barrier layer 350 in the gap is retained; the semiconductor manufacturing process further includes filling a metal layer in the opening 152 to form a metal gate structure, so that when the metal layer is filled in the opening 152, the barrier layer 350 in the gap can play a role in isolating the P-type doped epitaxial layer 112 from the metal layer, and the probability of bridging between the metal gate structure and the P-type doped epitaxial layer 112 is low, that is, the problem of bridging between the P-type doped epitaxial layer 112 and the metal gate structure can be solved by the barrier layer 350, so that the electrical performance and yield of the semiconductor device are improved.
In order to improve process compatibility, the material of the blocking layer 350 may be an insulating dielectric material such as silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, or silicon oxycarbonitride. In this embodiment, the gap is formed by the loss of the isolation structure 101, so the material of the barrier layer 350 is the same as the material of the isolation structure 101, that is, the material of the barrier layer 350 is silicon oxide.
In this embodiment, in order to enable the barrier layer 350 to fill the gap below the PMOS region I-side wall 300, the process of forming the barrier layer 350 is an atomic layer deposition process; the barrier layer 350 is thus also located on the sidewalls of the opening 152 and on top of the interlevel dielectric layer 102.
It should be noted that the thickness of the barrier layer 350 is not too small, nor too large. If the thickness of the barrier layer 350 is too small, the effect of filling the gap below the I-side wall 300 of the PMOS region is not obvious, and correspondingly, the effect of the barrier layer 350 on isolating the P-type doped epitaxial layer 112 from the metal layer is not obvious; if the thickness of the barrier layer 350 is too large, material waste and process cost increase are wasted. For this reason, in this embodiment, the thickness of the barrier layer 350 is
Figure BDA0001236098450000231
To
Figure BDA0001236098450000232
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims (18)

1. A method of forming a semiconductor structure, comprising:
providing a substrate, wherein the substrate comprises a substrate and a discrete fin part positioned on the substrate, and the substrate comprises a PMOS area for forming a P-type device and an NMOS area for forming an N-type device;
forming an isolation structure on the substrate with the exposed fin portion, wherein the isolation structure covers part of the side wall of the fin portion, and the top of the isolation structure is lower than the top of the fin portion;
after the isolation structure is formed, forming a pseudo-gate structure crossing the fin part, wherein the pseudo-gate structure covers part of the top surface and the side wall surface of the fin part;
forming a side wall on the side wall of the pseudo gate structure;
after the side walls are formed, grooves are formed in the fin parts on two sides of the pseudo gate structure;
forming a doped epitaxial layer in the groove;
the step of forming the recess and doping the epitaxial layer comprises: forming a P-region mask layer on the top and the side wall of the fin part of the PMOS region, wherein the P-region mask layer is also positioned on the top and the side wall of the fin part of the NMOS region; forming P-region grooves in the fin parts on two sides of the PMOS region pseudo-gate structure; forming a P-type doped epitaxial layer in the P region groove; after the P-type doped epitaxial layer is formed, forming N-region mask side walls on the P-region mask layer of the NMOS region, wherein the P-region mask layer and the N-region mask side walls located in the NMOS region serve as N-region mask layers; forming N-region grooves in the fin parts on two sides of the NMOS region pseudo-gate structure; forming an N-type doped epitaxial layer in the N-region groove;
in the etching process of forming the groove, the pseudo gate structure, the isolation structure exposed out of the fin part and the isolation structure positioned at the bottom of the side wall are also etched, and a gap is formed between the isolation structure in the PMOS region and the side wall;
after the doped epitaxial layer is formed, forming an interlayer dielectric layer on the isolation structure exposed out of the pseudo gate structure, wherein the interlayer dielectric layer is exposed out of the top of the pseudo gate structure;
removing the pseudo gate structure, and forming an opening in the interlayer dielectric layer;
forming a barrier layer at the bottom of the opening, wherein the barrier layer also fills the gap;
removing the barrier layer in the opening and reserving the barrier layer in the gap;
and after removing the barrier layer in the opening, filling a metal layer in the opening to form a metal gate structure.
2. The method of claim 1, wherein the barrier layer is formed of a material selected from the group consisting of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon oxycarbonitride.
3. The method of forming a semiconductor structure of claim 1, wherein the barrier layer has a thickness of
Figure FDA0003306573080000021
To
Figure FDA0003306573080000022
4. The method of forming a semiconductor structure of claim 1, wherein the process of forming the barrier layer is an atomic layer deposition process.
5. The method of claim 1, wherein the process of removing the barrier layer in the opening is a dry etching process.
6. The method of claim 1, wherein the step of forming the recess in the fin on both sides of the dummy gate structure comprises: and etching the fin parts with partial thickness at two sides of the pseudo-gate structure by adopting a dry etching process, and forming grooves in the fin parts.
7. The method of forming a semiconductor structure of claim 1, wherein after forming a recess in the fin on both sides of the dummy gate structure, before forming a doped epitaxial layer in the recess, the method further comprises: and carrying out a cleaning process on the groove.
8. The method of claim 7, wherein the cleaning process is a SiCoNi process, and wherein a main etching gas used in the SiCoNi process is gaseous hydrofluoric acid.
9. The method of forming a semiconductor structure of claim 1, wherein the step of forming the P-doped epitaxial layer and the N-doped epitaxial layer further comprises: etching the P-region mask layers on the tops of the fin parts on the two sides of the PMOS region pseudo-gate structure, exposing the top surfaces of the fin parts on the two sides of the PMOS region pseudo-gate structure, etching the fin parts of the PMOS region with partial thickness, and forming P-region grooves in the etched fin parts;
forming a P-type doped epitaxial layer in the P region groove;
etching N-region mask layers on the tops of fin parts on two sides of the NMOS region pseudo-gate structure, etching the fin parts of the NMOS region with partial thickness, and forming N-region grooves in the fin parts;
and forming an N-type doped epitaxial layer in the N-region groove.
10. The method of claim 9, wherein the P-region mask layer is made of silicon nitride, silicon carbonitride, silicon boronitride, silicon oxycarbonitride, or silicon oxynitride; the N-region mask layer is made of silicon nitride, silicon carbide nitride, silicon boride nitride, silicon oxycarbide or silicon oxynitride.
11. The method of claim 1, wherein for forming a PMOS region of a P-type device, in the step of forming a doped epitaxial layer in the recess, the material of the doped epitaxial layer is P-type doped Si or SiGe;
and in the step of forming a doped epitaxial layer in the groove, the material of the doped epitaxial layer is N-type doped Si or SiC.
12. The method of claim 1, wherein after removing the barrier layer in the opening and before filling the opening with a metal layer, the method further comprises: and forming gate dielectric layers on the bottom and the side wall of the opening, wherein the gate dielectric layers comprise an interface layer and a high-k gate dielectric layer positioned on the surface of the interface layer.
13. A semiconductor structure, comprising:
the substrate comprises a PMOS area used for forming a P type device and an NMOS area used for forming an N type device;
the isolation structure is positioned on the substrate with the exposed fin part, covers partial side walls of the fin part, and has the top lower than the top of the fin part;
the interlayer dielectric layer is positioned on the isolation structure and is internally provided with an opening for exposing the fin part and the isolation structure;
the doped epitaxial layer is positioned in the fin parts at two sides of the opening;
the side wall is positioned on the side wall of the opening;
the P-area mask layer is positioned on the side wall of the fin part of the PMOS area, and the P-area mask layer is also positioned on the side wall of the fin part of the NMOS area;
the N-area mask layer comprises a P-area mask layer positioned in the NMOS area and N-area mask side walls, wherein the N-area mask side walls are positioned on the side walls of the P-area mask layer in the NMOS area;
and the barrier layer is positioned at the bottom of the opening and is filled in a gap between the isolation structure and the side wall of the PMOS region.
14. The semiconductor structure of claim 13, wherein the material of the barrier layer is silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, or silicon oxycarbonitride.
15. The semiconductor structure of claim 13, wherein the barrier layer has a thickness of
Figure FDA0003306573080000041
To
Figure FDA0003306573080000042
16. The semiconductor structure of claim 13, wherein a material used to form a PMOS region of a P-type device, the doped epitaxial layer is P-type doped Si or SiGe;
and the material of the doped epitaxial layer is N-type doped Si or SiC.
17. The semiconductor structure of claim 13,
the doped epitaxial layers in the fin parts on the two sides of the opening of the PMOS region are P-type doped epitaxial layers, and the doped epitaxial layers in the fin parts on the two sides of the opening of the NMOS region are N-type doped epitaxial layers.
18. The semiconductor structure of claim 17, wherein the P-region mask layer is made of silicon nitride, silicon carbide nitride, silicon boride nitride, silicon oxycarbide, or silicon oxynitride; the N-region mask layer is made of silicon nitride, silicon carbide nitride, silicon boride nitride, silicon oxycarbide or silicon oxynitride.
CN201710117757.2A 2017-03-01 2017-03-01 Semiconductor structure and forming method thereof Active CN108538724B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201710117757.2A CN108538724B (en) 2017-03-01 2017-03-01 Semiconductor structure and forming method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201710117757.2A CN108538724B (en) 2017-03-01 2017-03-01 Semiconductor structure and forming method thereof

Publications (2)

Publication Number Publication Date
CN108538724A CN108538724A (en) 2018-09-14
CN108538724B true CN108538724B (en) 2021-12-14

Family

ID=63488500

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201710117757.2A Active CN108538724B (en) 2017-03-01 2017-03-01 Semiconductor structure and forming method thereof

Country Status (1)

Country Link
CN (1) CN108538724B (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111312800B (en) * 2018-12-12 2023-03-28 联华电子股份有限公司 Semiconductor structure with epitaxial layer and manufacturing method thereof
CN111463173B (en) * 2019-01-18 2023-04-28 中芯国际集成电路制造(上海)有限公司 Semiconductor structure and forming method thereof
CN111599755B (en) * 2019-02-21 2023-04-25 中芯国际集成电路制造(上海)有限公司 Method for forming semiconductor device
CN113871352B (en) * 2020-06-30 2024-03-08 中芯国际集成电路制造(上海)有限公司 Method for manufacturing semiconductor structure

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105514041A (en) * 2014-09-26 2016-04-20 中芯国际集成电路制造(上海)有限公司 Transistor forming method
CN105529357A (en) * 2014-10-17 2016-04-27 台湾积体电路制造股份有限公司 Method and Structure for FinFET
CN106373924A (en) * 2015-07-23 2017-02-01 中芯国际集成电路制造(上海)有限公司 Semiconductor structure forming method

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10050147B2 (en) * 2015-07-24 2018-08-14 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and manufacturing method thereof

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105514041A (en) * 2014-09-26 2016-04-20 中芯国际集成电路制造(上海)有限公司 Transistor forming method
CN105529357A (en) * 2014-10-17 2016-04-27 台湾积体电路制造股份有限公司 Method and Structure for FinFET
CN106373924A (en) * 2015-07-23 2017-02-01 中芯国际集成电路制造(上海)有限公司 Semiconductor structure forming method

Also Published As

Publication number Publication date
CN108538724A (en) 2018-09-14

Similar Documents

Publication Publication Date Title
US9647118B2 (en) Device having EPI film in substrate trench
US8900956B2 (en) Method of dual EPI process for semiconductor device
EP3166136A1 (en) Semiconductor structures and fabrication methods thereof
US10529863B2 (en) Flat STI surface for gate oxide uniformity in Fin FET devices
US8343872B2 (en) Method of forming strained structures with compound profiles in semiconductor devices
KR101946765B1 (en) Semiconductor device and manufacturing method thereof
CN108461544B (en) Semiconductor structure and forming method thereof
US10026641B2 (en) Isolation structure of semiconductor device
CN112309861B (en) Semiconductor structure, forming method thereof and transistor
US9865709B2 (en) Selectively deposited spacer film for metal gate sidewall protection
CN108538724B (en) Semiconductor structure and forming method thereof
CN108389905B (en) Semiconductor structure and forming method thereof
CN110634798A (en) Semiconductor structure and forming method thereof
CN110854194B (en) Semiconductor structure and forming method thereof
CN109003899B (en) Semiconductor structure, forming method thereof and forming method of fin field effect transistor
CN117652014A (en) Semiconductor structure and forming method thereof
CN109003976B (en) Semiconductor structure and forming method thereof
CN109087892B (en) Semiconductor structure, forming method thereof and forming method of fin field effect transistor
TWI785537B (en) Semiconductor device and method of forming thereof
CN110875390B (en) Semiconductor structure and forming method thereof
US20210226030A1 (en) Field effect transistor and method of manufacturing the same
CN115602726A (en) Semiconductor structure and forming method thereof
CN117673147A (en) Semiconductor structure and forming method thereof
CN113903809A (en) Semiconductor device and method of forming the same
CN117476461A (en) Method for forming semiconductor structure

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant