CN110875390B - Semiconductor structure and forming method thereof - Google Patents
Semiconductor structure and forming method thereof Download PDFInfo
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- CN110875390B CN110875390B CN201811010724.9A CN201811010724A CN110875390B CN 110875390 B CN110875390 B CN 110875390B CN 201811010724 A CN201811010724 A CN 201811010724A CN 110875390 B CN110875390 B CN 110875390B
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
Abstract
A semiconductor structure and a method for forming the same, the method for forming the same includes: providing a substrate, wherein the substrate comprises a substrate and a plurality of discrete fin parts positioned on the substrate, a first grid structure and a second grid structure are formed on the substrate, the first grid structure spans the grid structure of the fin parts and covers part of the top and part of the side walls of the fin parts, the second grid structure is positioned on the substrate between adjacent fin parts in the extending direction of the fin parts, a first dielectric layer is formed on the exposed substrate of the first grid structure and the second grid structure, and the side walls of the first grid structure and the second grid structure are covered by the first dielectric layer; removing the second grid structure and forming a first opening in the first dielectric layer; the first opening is filled with a dielectric material, and the dielectric material in the first opening is used as an isolation structure. According to the embodiment of the invention, the isolation structure is made of dielectric materials, so that the isolation structure has insulativity, and the problem of short circuit between the source and drain doped layers and the isolation structure is avoided.
Description
Technical Field
The present disclosure relates to semiconductor manufacturing, and more particularly, to a semiconductor structure and a method for forming the same.
Background
With the rapid development of semiconductor manufacturing technology, semiconductor devices are being developed toward higher element density, and higher integration. Transistors are currently being widely used as one of the basic semiconductor devices. Therefore, with the improvement of the density and the integration level of the semiconductor device, the gate size of the planar transistor is also shorter and shorter, the control capability of the conventional planar transistor on the channel current is weakened, a short channel effect occurs, the leakage current is increased, and the electrical performance of the semiconductor device is finally affected.
To better accommodate the reduction in feature sizes, semiconductor processes are increasingly beginning to transition from planar MOSFETs to three-dimensional transistors with higher efficiency, such as fin field effect transistors (finfets). In the FinFET, the gate can control the ultrathin body (fin part) from at least two sides, and compared with a planar MOSFET, the gate has stronger control capability on a channel, and can well inhibit short channel effect; and finfets have better compatibility with existing integrated circuit fabrication than other devices.
However, as semiconductor device dimensions continue to shrink, the distance between adjacent finfet devices also shrinks. In order to prevent the adjacent fin field effect transistors from being connected (merge), the prior art introduces a manufacturing technology of a single diffusion barrier (single diffusion break, SDB) isolation structure.
Disclosure of Invention
The embodiment of the invention solves the problem of providing a semiconductor structure and a forming method thereof, and improves the performance of a device.
In order to solve the above problems, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate, wherein the substrate comprises a substrate and a plurality of discrete fin parts positioned on the substrate, a first grid structure and a second grid structure are formed on the substrate, the first grid structure spans across the fin parts and covers part of the top and part of the side walls of the fin parts, the second grid structure is positioned on the substrate between the adjacent fin parts in the extending direction of the fin parts, a first dielectric layer is formed on the exposed substrate of the first grid structure and the second grid structure, and the first dielectric layer covers the side walls of the first grid structure and the second grid structure; removing the second grid structure and forming a first opening in the first dielectric layer; and filling dielectric materials in the first openings, wherein the dielectric materials in the first openings are used as isolation structures.
Optionally, the dielectric material is silicon oxide, silicon oxynitride, silicon nitride, silicon carbonitride or silicon boron nitride carbide.
Optionally, the process of filling the first opening with the dielectric material is a PECVD process, an FCVD process or an LPCVD process.
Optionally, after forming the first opening in the first dielectric layer, before filling the dielectric material in the first opening, the method further includes: forming a filling layer in the first opening; after a filling layer is formed in the first opening, removing part of the first dielectric layer with the thickness, and exposing part of the side walls of the first grid structure and the filling layer from the rest of the first dielectric layer; and removing the filling layer after removing the first dielectric layer with partial thickness.
Optionally, after removing the filling layer, the method further includes: forming a second dielectric layer on the residual first dielectric layer, wherein the second dielectric layer covers the side wall of the first grid structure exposed by the residual first dielectric layer; in the step of forming the second dielectric layer, the isolation structure is formed in the first opening. Optionally, the step of forming the second dielectric layer and the isolation structure includes: forming a dielectric material covering the first gate structure on the remaining first dielectric layer, wherein the dielectric material is also filled in the first opening; and carrying out planarization treatment on the dielectric material, wherein after the planarization treatment, the residual dielectric material positioned on the residual first dielectric layer is used as a second dielectric layer, the second dielectric layer covers the side wall of the first grid structure exposed by the residual first dielectric layer, and the dielectric material positioned in the first opening is used as an isolation structure.
Optionally, the process of forming the filling layer in the first opening is an atomic layer deposition process.
Optionally, the material of the filling layer is an organic material.
Optionally, the process of removing the filling layer is an ashing process or a dry etching process.
Optionally, the material of the filling layer is BARC material, ODL material, photoresist or DUO material.
Optionally, after removing a part of the thickness of the first dielectric layer, the thickness of the remaining first dielectric layer is
To->
Optionally, the process of removing the second gate structure is a dry etching process.
Optionally, after forming the isolation structure, the method further includes: sequentially etching the first dielectric layers and the fin parts on two sides of the first gate structure, and forming grooves in the fin parts on two sides of the first gate structure; and forming a source-drain doping layer in the groove.
Optionally, in the step of providing the substrate, a sidewall is formed between the sidewall of the first gate structure and the first dielectric layer, and between the sidewall of the second gate structure and the first dielectric layer; and removing the second grid structure, wherein in the step of forming a first opening in the first dielectric layer, the first opening is surrounded by the side wall and the substrate.
Optionally, in the step of providing a substrate, the first gate structure and the second gate structure are dummy gate structures; after forming the isolation structure, the method further comprises: removing the first grid structure and forming a second opening in the first dielectric layer; and forming a metal gate structure in the second opening.
Correspondingly, the embodiment of the invention also provides a semiconductor structure, which comprises: a base comprising a substrate, and a plurality of discrete fins located on the substrate; a gate structure crossing the fin, the gate structure covering a portion of a top and a portion of a sidewall of the fin; the isolation structure is positioned on the substrate between the adjacent fin parts in the extending direction of the fin parts, and the isolation structure is made of dielectric materials; and the dielectric layer is positioned on the substrate with the exposed gate structure and the exposed isolation structure, and covers the side walls of the gate structure and the isolation structure.
Optionally, the dielectric material is silicon oxide, silicon oxynitride, silicon nitride, silicon carbonitride or silicon boron nitride carbide.
Optionally, openings are formed in the dielectric layers at two sides of the gate structure; the semiconductor structure further includes: and the source-drain doped layer is positioned in the fin part exposed by the opening.
Optionally, the gate structure is a metal gate structure.
Optionally, the semiconductor structure further includes: the side wall is positioned between the side wall of the grid structure and the dielectric layer and is also positioned between the side wall of the isolation structure and the dielectric layer.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following advantages:
in the embodiment of the invention, the second grid structure is removed, and after a first opening is formed in the first dielectric layer, dielectric materials are filled in the first opening, wherein the dielectric materials in the first opening are used as isolation structures. In the field of semiconductors, a metal gate structure process is generally adopted, and active drain doped layers are formed in fin portions on two sides of the metal gate structure.
In an alternative scheme, after the isolation structure is formed, source-drain doping layers are formed in the fin portions on two sides of the gate structure, so that damage to source-drain doping caused by a process of removing the second gate structure is avoided, and further electrical performance of the semiconductor structure is improved.
Drawings
Fig. 1 to 3 are schematic structural views corresponding to steps in a method for forming a semiconductor structure;
fig. 4 to 11 are schematic structural views corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention;
fig. 12 is a schematic diagram of a semiconductor structure according to an embodiment of the present invention.
Detailed Description
As can be seen from the background art, the devices formed at present still have the problem of poor performance. The reason for the poor performance of the device is analyzed by combining a forming method of a semiconductor structure.
Referring to fig. 1 to 3, schematic structural diagrams corresponding to steps in a method for forming a semiconductor structure are shown.
Referring to fig. 1, a base is provided, the base includes a substrate 500 and a plurality of discrete fins 510 located on the substrate 500, a first gate structure 540 and a second gate structure 550 are formed on the substrate 500, the first gate structure 540 spans across the fins 510 and covers part of the top and part of the sidewalls of the fins 510, the second gate structure 550 is located on the substrate 500 between adjacent fins 510 in the extending direction of the fins 510, and sidewalls 535 are formed on the sidewalls of the first gate structure 540 and the second gate structure 550.
Referring to fig. 2, fin portions 510 on both sides of the first gate structure 540 are etched, and grooves 600 are formed in the fin portions 510 on both sides of the first gate structure 540.
Referring to fig. 3, a source drain doped layer 560 is formed within the recess 600 (shown in fig. 2).
When forming the side wall 535 on the side wall of the second gate structure 550, the side wall 535 may not completely cover the side wall of the second gate structure 550, and therefore, during the process of forming the groove 600 in the fin 510 at both sides of the first gate structure 540, part of the side wall surface of the second gate structure 550 may be exposed, which may easily cause the contact between the source and drain doped layer 560 and the second gate structure 550 after the formation of the source and drain doped layer 560 in the groove 600, and in the semiconductor field, a metal gate structure process is generally adopted, which may easily cause a short circuit between the source and drain doped layer 560 and the adjacent fin 510 in the extending direction, thereby resulting in poor performance of the formed semiconductor device.
In order to solve the technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate, wherein the substrate comprises a substrate and a plurality of discrete fin parts positioned on the substrate, a first grid structure and a second grid structure are formed on the substrate, the first grid structure spans across the fin parts and covers part of the top and part of the side walls of the fin parts, the second grid structure is positioned on the substrate between the adjacent fin parts in the extending direction of the fin parts, a first dielectric layer is formed on the exposed substrate of the first grid structure and the second grid structure, and the first dielectric layer covers the side walls of the first grid structure and the second grid structure; removing the second grid structure and forming a first opening in the first dielectric layer; and filling dielectric materials in the first openings, wherein the dielectric materials in the first openings are used as isolation structures.
In the embodiment of the invention, the second grid structure is removed, and after a first opening is formed in the first dielectric layer, dielectric materials are filled in the first opening, wherein the dielectric materials in the first opening are used as isolation structures. In the field of semiconductors, a metal gate structure process is generally adopted, and active drain doped layers are formed in fin parts at two sides of the metal gate structure.
In order that the above objects, features and advantages of embodiments of the invention may be readily understood, a more particular description of the invention will be rendered by reference to specific embodiments thereof which are illustrated in the appended drawings.
Fig. 4 to 11 are schematic structural views corresponding to each step in an embodiment of a method for forming a semiconductor structure according to the present invention.
Referring to fig. 4, a base is provided, the base includes a substrate 100 and a plurality of discrete fins 110 located on the substrate 100, a first gate structure 140 and a second gate structure 150 are formed on the substrate 100, the first gate structure 140 spans across the fins 110 and covers part of the top and part of the sidewalls of the fins 110, the second gate structure 150 is located on the substrate 100 between adjacent fins 110 in the extending direction of the fins 110, a first dielectric layer 155 is formed on the exposed substrate 100 of the first gate structure 140 and the second gate structure 150, and the first dielectric layer 155 covers the sidewalls of the first gate structure 140 and the second gate structure 150.
The substrate 100 provides a process platform for the subsequent formation of semiconductor structures.
In this embodiment, the substrate 100 is a silicon substrate. In other embodiments, the substrate material may also be germanium, silicon carbide, gallium arsenide, or indium gallium, and the substrate may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate.
The fin 110 is made of the same material as the substrate 100. In this embodiment, the fin 110 is made of silicon. In other embodiments, the fin may also be germanium, silicon carbide, gallium arsenide, or indium gallium arsenide.
In this embodiment, an isolation layer 111 is further formed on the substrate 100 exposed by the fin portion 110.
The isolation layer 111 is used for isolating adjacent devices, and the material of the isolation layer 111 may be silicon oxide, silicon nitride or silicon oxynitride. In this embodiment, the material of the isolation layer 111 is silicon oxide.
In this embodiment, the first gate structure 140 is a dummy gate structure, and the first gate structure 140 includes a gate oxide layer 112 and a gate layer 130 on the gate oxide layer 112.
The gate oxide layer 112 is made of silicon oxide or silicon oxynitride; the gate layer 130 is made of polysilicon, silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, or amorphous carbon. In this embodiment, the material of the gate oxide layer 112 is silicon oxide, and the material of the gate layer 130 is polysilicon.
In this embodiment, the gate oxide layer 112 also covers the surface of the fin portion 110 exposed by the gate layer 130.
In other embodiments, the first gate structure may also be a metal gate structure.
In this embodiment, the second gate structure 150 is formed on the isolation layer 111 between adjacent fin portions 110 in the extending direction of the fin portions 110, and the second gate structure 150 and the first gate structure 140 are formed in the same process step, so that the second gate structure 150 is also a dummy gate structure, and the material of the second gate structure 150 is the same as that of the gate layer 130.
Specifically, the material of the second gate structure 150 is polysilicon. In other embodiments, the material of the second gate structure may be silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride oxide, or amorphous carbon.
The second gate structure 150 is used to provide a process basis for forming a single diffusion blocking isolation structure, where the single diffusion blocking isolation structure is used to isolate adjacent devices, thereby reducing leakage current between the adjacent devices.
It should be noted that, a gate mask layer 131 is formed on top of the first gate structure 140 and the second gate structure 150, the gate mask layer 131 is used as an etching mask for forming the first gate structure 140 and the second gate structure 150, and the gate mask layer 131 is also used for protecting the top of the first gate structure 140 and the top of the second gate structure 150 in the subsequent process. In this embodiment, the material of the gate mask layer 131 is silicon nitride.
The first dielectric layer 155 is used for isolating adjacent devices, and the material of the first dielectric layer 155 is an insulating material, such as one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon oxycarbonitride.
In this embodiment, the first dielectric layer 155 has a single-layer structure, and the material of the first dielectric layer 155 is silicon oxide.
In this embodiment, the first dielectric layer 155 is formed by using a flowable chemical vapor deposition process (Flowable Chemical Vapor Deoposition, FCVD), which has a better filling effect and is beneficial to improving the quality of the first dielectric layer 155.
In this embodiment, a sidewall 135 is formed between the sidewall of the first gate structure 140 and the first dielectric layer 155, and between the sidewall of the second gate structure 150 and the first dielectric layer 155.
The sidewall 135 is used to protect the sidewalls of the first gate structure 140 and the second gate structure 150. Specifically, the sidewall 135 also covers the sidewall of the gate mask layer 131.
The material of the side wall 135 may be one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbide or silicon oxycarbonitride, boron nitride and boron carbonitride, and the side wall 135 may have a single-layer structure or a stacked-layer structure. In this embodiment, the side wall 135 has a single-layer structure, and the material of the side wall 135 is silicon nitride.
Referring to fig. 5, the second gate structure 150 is removed (as shown in fig. 4), and a first opening 200 is formed in the first dielectric layer 155.
The first opening 200 is used to provide a spatial location for the subsequent formation of isolation structures.
In this embodiment, the sidewall of the second gate structure 150 is formed with a sidewall 135, so that the first opening 200 is surrounded by the sidewall 135 and the substrate, and the first opening 200 exposes the top of the isolation layer 111.
In this embodiment, the process of removing the second gate structure 150 is a dry etching process.
The dry etching process is an anisotropic etching process, has good controllability of etching profile, is favorable for enabling the morphology of the first opening 200 to meet the process requirement, and is also favorable for improving the removal efficiency of the second gate structure 150. In other embodiments, the second gate structure may also be removed by a wet etching process or a process combining wet etching and dry etching.
It should be noted that, before removing the second gate structure 150, the gate mask layer 131 (as shown in fig. 4) located on top of the second gate structure 150 is also removed.
Referring to fig. 6-9, a dielectric material is filled in the first opening 200 (shown in fig. 5), and the dielectric material in the first opening 200 is used as the isolation structure 175 (shown in fig. 9).
In the semiconductor field, a metal gate structure process is generally adopted, and the isolation structure 175 is made of a dielectric material, so that the isolation structure 175 has an insulating property, which is beneficial to avoiding the problem of shorting between a source-drain doped layer formed later and the isolation structure 175, thereby improving the electrical performance of the semiconductor structure.
Thus, the dielectric material may be silicon oxide, silicon oxynitride, silicon nitride, silicon carbonitride or silicon boron nitride carbide. In this embodiment, the dielectric material is silicon oxide.
Referring to fig. 6 in combination, after forming the first opening 200 (as shown in fig. 5) in the first dielectric layer 155, before forming the isolation structure 175 in the first opening 200, the method further includes: a filling layer 170 is formed in the first opening 200.
The filling layer 170 covers the top of the isolation layer 111 exposed by the first opening 200, the filling layer 170 can protect the isolation layer 111 exposed by the first opening 200 in the subsequent step of removing a part of the first dielectric layer 155 with a thickness, and the filling layer 170 occupies a space for forming an isolation structure in the first opening.
The material of the filling layer 170 is an organic material. The organic material is easily removed, which is advantageous in reducing the process difficulty of removing the filler layer 170 in a subsequent process step by selecting the organic material.
Specifically, the material of the filling layer 170 may be BARC (bottom anti-reflective coating) material, ODL (organic dielectric layer ) material, photoresist, or DUO (Deep UV Light Absorbing Oxide, deep ultraviolet light absorbing oxide layer) material. In this embodiment, the material of the filling layer 170 is BARC material.
In this embodiment, the process of forming the filling layer 170 in the first opening 200 is an atomic layer deposition (Atomic Layer Deposition) process.
The atomic layer deposition process has better deposition uniformity, and is beneficial to improving the thickness uniformity and the film forming quality of the filling layer 170.
Referring to fig. 7 in combination, after the filling layer 170 is formed in the first opening 200 (as shown in fig. 5), a portion of the thickness of the first dielectric layer 155 is removed, and a portion of the sidewalls of the first gate structure 140 and the filling layer 170 are exposed by the remaining first dielectric layer 155.
And removing part of the thickness of the first dielectric layer 155, so as to provide a process foundation for the subsequent formation of a second dielectric layer with higher density.
In this embodiment, the filling layer 170 is further removed later, and an isolation structure is formed in the first opening 200 during the process of forming the second dielectric layer, so that the process steps for forming the isolation structure are simplified; and the second dielectric layer has higher density, which is beneficial to further improving the insulation characteristic of the isolation structure.
After removing a portion of the thickness of the first dielectric layer 155, the thickness of the remaining first dielectric layer 155 should not be too small or too large. If the thickness of the remaining first dielectric layer 155 is too small, it takes longer to remove a part of the thickness of the first dielectric layer 155, which not only reduces manufacturing efficiency, increases process cost, but also easily reduces the quality of the subsequent second dielectric layer; if the thickness of the remaining first dielectric layer 155 is too large, the subsequently formed second dielectric layer is correspondingly too thin, and the time for depositing the second dielectric layer on the remaining first dielectric layer 155 is correspondingly short, which not only tends to reduce the surface flatness of the second dielectric layer, but also tends to cause insufficient dielectric material to fill the opening 200. For this purpose, in this embodiment, the thickness of the remaining first dielectric layer 155 is
To the point of
In this embodiment, the step of removing a portion of the thickness of the first dielectric layer 155 includes: a dry etching process is used to remove a portion of the thickness of the first dielectric layer 155.
The dry etching process is an anisotropic etching process, which is beneficial to improving the shape quality of the remaining first dielectric layer 155.
In other embodiments, a wet etching process or a process combining dry etching and wet etching may be used to remove a portion of the thickness of the first dielectric layer.
Referring to fig. 8 in combination, after removing a portion of the thickness of the first dielectric layer 155, the fill layer 170 is removed (as shown in fig. 7).
The first opening 200 is exposed by removing the filling layer 170, thereby providing a process basis for filling the dielectric material in the first opening 200.
In this embodiment, the material of the filling layer 170 is an organic material, and the material for removing the filling layer 170 is an ashing process or a dry etching process.
Referring to fig. 9, after the filling layer 170 (as shown in fig. 7) is removed, a second dielectric layer 160 is formed on the remaining first dielectric layer 155, the second dielectric layer 160 covers the sidewalls of the first gate structure 140 exposed by the remaining first dielectric layer 155, and in the step of forming the second dielectric layer 160, the isolation structure 175 is formed in the first opening 200 (as shown in fig. 8).
Specifically, the step of forming the second dielectric layer 160 and the isolation structure 175 includes: forming a dielectric material on the remaining first dielectric layer 155 to cover the first gate structure 140, the dielectric material further filling the first opening 200; and flattening the dielectric material, wherein after the flattening, the residual dielectric material on the residual first dielectric layer 155 is used as a second dielectric layer 160, the second dielectric layer 160 covers the side wall of the first gate structure 140 exposed by the residual first dielectric layer 155, and the dielectric material in the first opening 200 is used as an isolation structure 175.
In this embodiment, the remaining first dielectric layer 155 and the second dielectric layer 160 form an interlayer dielectric layer (Inter Layer Dielectrics, ILD), and the second dielectric layer 160 is used to isolate adjacent devices.
In this embodiment, in order to improve process compatibility, the materials of the second dielectric layer 160 and the first dielectric layer 155 are the same, the material of the second dielectric layer 160 is silicon oxide, and the material of the isolation structure 175 is correspondingly silicon oxide.
In this embodiment, a PECVD (Plasma Enhanced Chemical Vapor Deposition, plasma-enhanced chemical vapor deposition) process is used to form a dielectric material that covers the remaining first dielectric layer 155 and fills the first opening 200.
The deposition rate of the PECVD process is high, which is beneficial to improving the process manufacturing efficiency, the film forming quality of the PECVD process is good, the filling property is good, the film quality of the isolation structure 175 and the second dielectric layer 160 is beneficial to improving, and in addition, the dielectric material formed by the PECVD process is high in density, so that the surface flatness of the residual dielectric material is high after the planarization treatment.
In other embodiments, a dielectric material covering the remaining first dielectric layer and filling the first opening may also be formed using an FCVD process or an LPCVD process.
In this embodiment, the isolation structure 175 is formed in the step of forming the second dielectric layer 160. In other embodiments, it may also be: removing the second grid structure after the second dielectric layer is formed, and forming a first opening in the second dielectric layer and the first dielectric layer; after the first opening is formed, the isolation structure is formed in the first opening.
Referring to fig. 10 to 11, after forming the isolation structure 175 in the first opening 200 (as shown in fig. 8), further includes: sequentially etching the first dielectric layer 155 and the fin portions 110 on two sides of the first gate structure 140, and forming grooves 300 (as shown in fig. 10) in the fin portions 110 on two sides of the first gate structure 140; a source-drain doped layer 180 (shown in fig. 11) is formed in the recess 300.
It should be noted that, in the step of forming the recess 300 in the fin 110 at two sides of the first gate structure 140, the second dielectric layer 160 at two sides of the first gate structure 140 is also etched.
In this embodiment, in the step of forming the second dielectric layer 160, the isolation structure 175 is formed in the first opening 200; after the second dielectric layer 160 is formed, the source-drain doped layer 180 is formed. In the semiconductor field, the dielectric layer is generally formed after the source-drain doped layer is formed, and the second gate structure is removed after the dielectric layer is formed, so that the process of removing the second gate structure 150 is beneficial to avoiding damage to the source-drain doped layer 180 by forming the source-drain doped layer 180 after the second dielectric layer 160 and the isolation structure 175 are formed, thereby further improving the electrical performance of the semiconductor structure.
When the substrate is used for forming an NMOS transistor, the material of the source-drain doped layer 180 is a stress layer doped with N-type ions, the material of the stress layer may be Si or SiC, and the stress layer provides a tensile stress effect for a channel region of the NMOS transistor, so As to be beneficial to improving carrier mobility of the NMOS transistor, where the N-type ions are P ions, as ions or Sb ions; when the substrate is used to form a PMOS transistor, the material of the source-drain doped layer 180 is a stress layer doped with P-type ions, which may be Si or SiGe, and the stress layer provides a compressive stress to the channel region of the PMOS transistor, so as to facilitate improving carrier mobility of the PMOS transistor, where the P-type ions are B ions, ga ions, or In ions.
In this embodiment, the shape of the recess 300 is square. In other embodiments, the shape of the groove may be U-shaped or Sigma-shaped according to actual process requirements.
It should be noted that after the source-drain doped layer 180 is formed in the recess 300 (as shown in fig. 10), the method further includes: removing the first gate structure 140, and forming a second opening (not shown) in the first dielectric layer 155; a metal gate structure (not shown) is formed in the second opening.
In the step of removing the first gate structure 140, the gate mask layer 131 on top of the first gate structure 140 is also removed.
As can be seen from the foregoing, the material of the isolation structure 175 is a dielectric material, so that the isolation structure 175 has insulation property, which is beneficial to avoiding the problem of shorting the source-drain doped layer 180 and the isolation structure 175, thereby improving the electrical performance of the semiconductor structure.
Correspondingly, the invention further provides a semiconductor structure. Referring to fig. 12, a schematic structure diagram of an embodiment of the semiconductor structure of the present invention is shown.
The semiconductor structure includes: a base comprising a substrate 400 and a plurality of discrete fins 410 on the substrate 400; a gate structure 440 spanning the fin 410, the gate structure 440 covering a portion of the top and a portion of the sidewalls of the fin 410; an isolation structure 475 located on the substrate 400 between adjacent fin portions 410 in the extending direction of the fin portions 410, wherein the isolation structure 475 is made of a dielectric material; and a dielectric layer 470 located on the substrate 400 where the gate structure 440 and the isolation structure 475 are exposed, wherein the dielectric layer 470 covers the sidewalls of the gate structure 440 and the isolation structure 475.
The substrate 400 provides a process platform for the formation of semiconductor structures.
In this embodiment, the substrate 400 is a silicon substrate. In other embodiments, the substrate material may also be germanium, silicon carbide, gallium arsenide, or indium gallium, and the substrate may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate.
The fin 410 is of the same material as the substrate 400. In this embodiment, the fin 410 is made of silicon. In other embodiments, the fin may also be germanium, silicon carbide, gallium arsenide, or indium gallium arsenide.
In this embodiment, the semiconductor structure further includes: and the isolation layer 411 is located on the substrate 400 exposed by the fin portion 410.
The isolation layer 411 is used to isolate adjacent devices, and the material of the isolation layer 411 may be silicon oxide, silicon nitride or silicon oxynitride. In this embodiment, the material of the isolation layer 411 is silicon oxide.
In this embodiment, the gate structure 440 is a metal gate structure, and the gate structure 440 includes a gate dielectric layer 413 and a gate electrode layer 430 disposed on the gate dielectric layer 413.
In this embodiment, the gate dielectric layer 413 is made of a high-k dielectric material; the high-k dielectric material refers to a dielectric material with a relative dielectric constant larger than that of silicon oxide. Specifically, the gate dielectric layer 413 is made of HfO 2 . In other embodiments, the gate dielectricThe material of the mass layer may also be selected from ZrO 2 HfSiO, hfSiON, hfTaO, hfTiO, hfZrO or Al 2 O 3 Etc.
The gate electrode layer 430 is made of Al, cu, ag, au, pt, ni, ti or W. In this embodiment, the material of the gate electrode layer 430 is W.
In this embodiment, the gate structure 440 is formed by a process of forming the high-k gate dielectric layer 413 and then forming the metal gate (high k last metal gate last), so that the semiconductor structure further includes: the gate oxide layer 412 is located between the dielectric layer 470 and the fin 410, and the material of the gate oxide layer 412 may be silicon oxide. In other embodiments, the gate oxide layer may also be silicon oxynitride.
For this purpose, in this embodiment, the gate electrode layer 430 is located in the dielectric layer 470, and the gate dielectric layer 413 is located between the gate electrode layer 430 and the substrate, and between the sidewall of the gate electrode layer 430 and the dielectric layer 470.
In other embodiments, the gate oxide layer may also be located between the gate dielectric layer and the fin portion, according to device performance requirements.
The material of the isolation structure 475 is a dielectric material, so that the isolation structure 475 has insulation property, which is beneficial to avoiding the problem of shorting between the source-drain doped layer 480 and the isolation structure 475, thereby improving the electrical performance of the semiconductor structure.
The dielectric material may be silicon oxide, silicon oxynitride, silicon nitride, silicon carbonitride or silicon boron carbide nitride. In this embodiment, the dielectric material is silicon oxide.
The dielectric layer 470 is an interlayer dielectric layer, the dielectric layer 470 is used for isolating adjacent devices, and the material of the dielectric layer 470 is an insulating material, such as one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride and silicon oxycarbonitride.
In this embodiment, the dielectric layer 470 has a stacked structure, and includes a first dielectric layer 455 disposed on the substrate 400 where the gate structure 440 and the isolation structure 475 are exposed, and a second dielectric layer 460 disposed on the first dielectric layer 455.
In this embodiment, the materials of the first dielectric layer 455 and the second dielectric layer 460 are the same, and the density of the second dielectric layer 460 is greater than that of the first dielectric layer 455, so that the surface flatness of the dielectric layer 470 can be improved during the planarization process for forming the dielectric layer 470.
Specifically, the material of the first dielectric layer 455 is silicon oxide, and the material of the second dielectric layer 460 is silicon oxide.
In this embodiment, openings 500 are formed in the dielectric layers 470 on both sides of the gate structure 440; the semiconductor structure further includes: the source-drain doped layer 480 is located in the fin portion 410 exposed by the opening 500.
The openings 500 are formed in the dielectric layer 470 at two sides of the gate structure 440, because the source-drain doped layer 480 is formed after the dielectric layer 470 is formed in the process of forming the semiconductor structure. Specifically, after forming a groove (not shown) in the fin portion 410 by sequentially etching the dielectric layer 470 and the fin portion 410 at two sides of the gate structure 440, the source-drain doped layer 480 is formed in the groove; thus, the openings 500 expose the top of the source drain doped layer 480.
The gate structure 440 is formed by a process of forming a metal gate after forming the high-k dielectric layer 413, so that in the process of forming the semiconductor structure, before forming the isolation structure 475, a dummy gate structure is formed at a position of the isolation structure 475, and a space position is reserved for forming the isolation structure 475 by removing the dummy gate structure at the position. In this embodiment, by forming the source/drain doped layer 480 after forming the dielectric layer 470 and the isolation structure 475, damage to the source/drain doped layer 480 caused by a process of removing the dummy gate structure at the position of the isolation structure 470 can be avoided, thereby further improving the electrical performance of the semiconductor structure.
When the NMOS transistor is formed on the substrate, the material of the source-drain doped layer 480 is a stress layer doped with N-type ions, the material of the stress layer may be Si or SiC, and the stress layer provides a tensile stress effect for a channel region of the NMOS transistor, so As to be beneficial to improving carrier mobility of the NMOS transistor, where the N-type ions are P-ions, as ions or Sb ions; when the PMOS transistor is formed on the substrate, the material of the source-drain doped layer 480 is a stress layer doped with P-type ions, where the material of the stress layer may be Si or SiGe, and the stress layer provides a compressive stress effect for a channel region of the PMOS transistor, so as to facilitate improving carrier mobility of the PMOS transistor, and the P-type ions are B ions, ga ions, or In ions.
In this embodiment, the source-drain doped layer 480 has a square shape. In other embodiments, the shape of the source-drain doped layer may be U-shaped or Sigma-shaped according to actual process requirements.
In this embodiment, the semiconductor structure further includes: the spacers 435 are located between the sidewalls of the gate structure 440 and the dielectric layer 470, and the spacers 435 are also located between the isolation structures 475 and the dielectric layer 470.
The spacers 435 are used to protect the sidewalls of the gate structure 440 and isolation structure 475.
The material of the side wall 435 may be one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride oxide, silicon oxynitride, boron nitride and boron carbonitride, and the side wall 435 may have a single-layer structure or a stacked-layer structure. In this embodiment, the side wall 435 has a single-layer structure, and the material of the side wall 435 is silicon nitride.
The semiconductor structure may be formed by the forming method described in the foregoing embodiments, or may be formed by other forming methods. For a specific description of the semiconductor structure in this embodiment, reference may be made to the corresponding description in the foregoing embodiment, which is not repeated here.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.
Claims (19)
1. A method of forming a semiconductor structure, comprising:
providing a substrate, wherein the substrate comprises a substrate and a plurality of discrete fin parts positioned on the substrate, a first grid structure and a second grid structure are formed on the substrate, the first grid structure spans across the fin parts and covers part of the top and part of the side walls of the fin parts, the second grid structure is positioned on the substrate between the adjacent fin parts in the extending direction of the fin parts, a first dielectric layer is formed on the exposed substrate of the first grid structure and the second grid structure, and the first dielectric layer covers the side walls of the first grid structure and the second grid structure;
removing the second grid structure and forming a first opening in the first dielectric layer;
and filling dielectric materials in the first opening, wherein the dielectric materials in the first opening are used as isolation structures, and the isolation structures have insulating properties.
2. The method of claim 1, wherein the dielectric material is silicon oxide, silicon oxynitride, silicon nitride, silicon carbonitride, or silicon boron carbide nitride.
3. The method of claim 1, wherein the process of filling the first opening with a dielectric material is a PECVD process, an FCVD process, or an LPCVD process.
4. The method of forming a semiconductor structure of claim 1, further comprising, after forming a first opening in the first dielectric layer, prior to filling the first opening with a dielectric material: forming a filling layer in the first opening;
after a filling layer is formed in the first opening, removing part of the first dielectric layer with the thickness, and exposing part of the side walls of the first grid structure and the filling layer from the rest of the first dielectric layer;
and removing the filling layer after removing the first dielectric layer with partial thickness.
5. The method of forming a semiconductor structure of claim 4, further comprising, after removing the fill layer: forming a second dielectric layer on the residual first dielectric layer, wherein the second dielectric layer covers the side wall of the first grid structure exposed by the residual first dielectric layer;
in the step of forming the second dielectric layer, the isolation structure is formed in the first opening.
6. The method of forming a semiconductor structure of claim 5, wherein forming the second dielectric layer and isolation structure comprises: forming a dielectric material covering the first gate structure on the remaining first dielectric layer, wherein the dielectric material is also filled in the first opening;
and carrying out planarization treatment on the dielectric material, wherein after the planarization treatment, the residual dielectric material positioned on the residual first dielectric layer is used as a second dielectric layer, the second dielectric layer covers the side wall of the first grid structure exposed by the residual first dielectric layer, and the dielectric material positioned in the first opening is used as an isolation structure.
7. The method of forming a semiconductor structure of claim 4, wherein the process of forming a fill layer within the first opening is an atomic layer deposition process.
8. The method of forming a semiconductor structure of claim 4, wherein the material of the fill layer is an organic material.
9. The method of forming a semiconductor structure of claim 8, wherein the process of removing the filler layer is an ashing process or a dry etching process.
10. The method of claim 4, wherein the material of the filling layer is BARC material, ODL material, photoresist, or DUO material.
11. The method of forming a semiconductor structure according to claim 4, wherein after removing a portion of the first dielectric layer, the remaining first dielectric layer has a thickness of
To->
12. The method of forming a semiconductor structure of claim 1, wherein the process of removing the second gate structure is a dry etching process.
13. The method of forming a semiconductor structure of claim 1, further comprising, after forming the isolation structure: sequentially etching the first dielectric layers and the fin parts on two sides of the first gate structure, and forming grooves in the fin parts on two sides of the first gate structure;
and forming a source-drain doping layer in the groove.
14. The method of forming a semiconductor structure of claim 1, wherein in the step of providing a substrate, sidewalls are formed between the first gate structure sidewall and the first dielectric layer, and between the second gate structure sidewall and the first dielectric layer;
and removing the second grid structure, wherein in the step of forming a first opening in the first dielectric layer, the first opening is surrounded by the side wall and the substrate.
15. The method of forming a semiconductor structure of claim 1, wherein in the step of providing a substrate, the first gate structure and the second gate structure are dummy gate structures;
after forming the isolation structure, the method further comprises: removing the first grid structure and forming a second opening in the first dielectric layer; and forming a metal gate structure in the second opening.
16. A semiconductor structure, comprising:
a base comprising a substrate and a plurality of discrete fins located on the substrate;
a gate structure crossing the fin, the gate structure covering a portion of a top and a portion of a sidewall of the fin;
the isolation structure is positioned on the substrate between the adjacent fin parts in the extending direction of the fin parts, and the isolation structure is made of dielectric materials and has insulating characteristics;
the dielectric layer is positioned on the substrate with the exposed gate structure and the exposed isolation structure, and covers the side walls of the gate structure and the exposed isolation structure;
the side wall is positioned between the side wall of the grid structure and the dielectric layer and is also positioned between the side wall of the isolation structure and the dielectric layer.
17. The semiconductor structure of claim 16, wherein the dielectric material is silicon oxide, silicon oxynitride, silicon nitride, silicon carbonitride, or silicon boron carbide nitride.
18. The semiconductor structure of claim 16, wherein openings are formed in the dielectric layer on both sides of the gate structure;
the semiconductor structure further includes: and the source-drain doped layer is positioned in the fin part exposed by the opening.
19. The semiconductor structure of claim 16, wherein the gate structure is a metal gate structure.
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