CN111554636B - Semiconductor structure and forming method thereof - Google Patents
Semiconductor structure and forming method thereof Download PDFInfo
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- CN111554636B CN111554636B CN201910110249.0A CN201910110249A CN111554636B CN 111554636 B CN111554636 B CN 111554636B CN 201910110249 A CN201910110249 A CN 201910110249A CN 111554636 B CN111554636 B CN 111554636B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 72
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- 238000002955 isolation Methods 0.000 claims abstract description 100
- 239000000758 substrate Substances 0.000 claims abstract description 97
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823481—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823431—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/0886—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Element Separation (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
A semiconductor structure and a method for forming the same, the method for forming the same includes: providing a substrate, wherein the substrate comprises a device region and an isolation region positioned between adjacent device regions, a grid structure is formed on the substrate of the device region and the isolation region, an interlayer dielectric layer is formed on the substrate exposed by the grid structure, and the top of the grid structure is exposed; removing the gate structure of the isolation region and a part of the thickness substrate at the bottom of the gate structure, and forming openings in the interlayer dielectric layer and the substrate; forming a grinding stop layer, covering the top of the dielectric layer between the layers and the top of the grid structure of the device region; forming a dielectric material layer filling the opening and covering the grinding stop layer; and taking the grinding stop layer positioned at the top of the interlayer dielectric layer as a stop position, carrying out planarization treatment on the dielectric material layer, removing the dielectric material layer positioned at the top of the interlayer dielectric layer and the top of the grid structure, and reserving the dielectric material layer positioned in the opening as an isolation structure. The embodiment of the invention improves the height consistency of the top of the grid structure and the top of the interlayer dielectric layer.
Description
Technical Field
Embodiments of the present disclosure relate to semiconductor manufacturing, and more particularly, to a semiconductor structure and a method for forming the same.
Background
With the rapid development of semiconductor manufacturing technology, semiconductor devices are being developed toward higher element density, and higher integration. Transistors are currently being widely used as one of the basic semiconductor devices. Therefore, with the improvement of the density and the integration level of the semiconductor device, the gate size of the planar transistor is also shorter and shorter, the control capability of the conventional planar transistor on the channel current is weakened, a short channel effect occurs, the leakage current is increased, and the electrical performance of the semiconductor device is finally affected.
To better accommodate the reduction in feature sizes, semiconductor processes are increasingly beginning to transition from planar MOSFETs to three-dimensional transistors with higher efficiency, such as fin field effect transistors (finfets). In the FinFET, the gate can control the ultrathin body (fin part) from at least two sides, and compared with a planar MOSFET, the gate has stronger control capability on a channel, and can well inhibit short channel effect; and finfets have better compatibility with existing integrated circuit fabrication than other devices.
However, as semiconductor device dimensions continue to shrink, the distance between adjacent finfet devices also shrinks. In order to prevent the adjacent fin field effect transistors from being connected (merge), the prior art introduces a manufacturing technology of a single diffusion barrier (single diffusion break, SDB) isolation structure.
Disclosure of Invention
The embodiment of the invention solves the problem of providing a semiconductor structure and a forming method thereof, and optimizes the performance of the semiconductor structure.
In order to solve the above problems, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate, wherein the substrate comprises a device region for forming a device and an isolation region between adjacent device regions, a gate structure is formed on the substrate of the device region and the isolation region, an interlayer dielectric layer is formed on the substrate exposed by the gate structure, and the interlayer dielectric layer is exposed from the top of the gate structure; removing the gate structure of the isolation region and a part of thickness substrate at the bottom of the gate structure of the isolation region, and forming openings in the interlayer dielectric layer and the substrate; forming an grinding stop layer to cover the top of the interlayer dielectric layer and the top of the grid structure of the device region; forming a dielectric material layer filling the opening, wherein the dielectric material layer also covers the grinding stop layer; and taking the grinding stop layer positioned at the top of the interlayer dielectric layer as a stop position, carrying out planarization treatment on the dielectric material layer, removing the dielectric material layer positioned at the top of the interlayer dielectric layer and the top of the grid structure, and reserving the dielectric material layer positioned in the opening as an isolation structure.
Correspondingly, the embodiment of the invention also provides a semiconductor structure, which comprises: a substrate including device regions for forming devices and isolation regions between adjacent device regions; the grid structure is positioned on the substrate of the device region; the interlayer dielectric layer is positioned on the substrate exposed by the gate structure, and the top of the gate structure is exposed by the interlayer dielectric layer; the isolation structure is positioned in the interlayer dielectric layer and the substrate of the isolation region; and the grinding stopping layer is positioned on the top of the grid structure and the interlayer dielectric layer, and is suitable for defining a stopping position of planarization treatment in the process of forming the isolation structure.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following advantages:
according to the embodiment of the invention, the opening is formed in the interlayer dielectric layer and the substrate, and after the grinding stop layer covering the top of the interlayer dielectric layer and the top of the gate structure of the device region is formed, the dielectric material layer filling the opening is formed, and the dielectric material layer also covers the grinding stop layer, so that the dielectric material layer can be flattened by taking the grinding stop layer at the top of the interlayer dielectric layer as a stop position.
In an alternative, after forming the gate structure, the method further includes: removing part of the thickness of the gate structure, forming a groove in the interlayer dielectric layer, and forming a grinding stop layer in the groove in the subsequent step of forming the grinding stop layer; in the field of semiconductor manufacturing, the subsequent processes typically further include: forming a dielectric layer on the interlayer dielectric layer, wherein the dielectric layer covers the top of the grinding stop layer positioned in the groove; and etching the dielectric layer at the top of the gate structure, forming a gate contact hole in the dielectric layer, wherein the grinding stop layer in the groove can play a role in defining the etching stop position in the step of etching the dielectric layer, so that the probability of loss at the top of the gate structure is further reduced, and the performance of the semiconductor structure is improved.
Drawings
Fig. 1 to 4 are schematic structural views corresponding to steps in a method for forming a semiconductor structure;
fig. 5 to 11 are schematic structural views corresponding to each step in an embodiment of a method for forming a semiconductor structure according to the present invention.
Detailed Description
The devices formed at present still have the problem of poor performance. The reason for the poor performance of the device is analyzed by combining a forming method of a semiconductor structure.
Referring to fig. 1 to 4, schematic structural diagrams corresponding to steps in a method for forming a semiconductor structure are shown.
Referring to fig. 1, a substrate 1 is provided, the substrate 1 includes a device region i for forming a device and an isolation region ii located between adjacent device regions i, a gate structure 2 is formed on the substrate 1 of the device region i and the isolation region ii, an interlayer dielectric layer 3 is formed on the substrate 1 exposed by the gate structure 2, and the interlayer dielectric layer 3 is exposed on top of the gate structure 2.
Referring to fig. 2, the gate structure 2 of the isolation region ii and a portion of the thickness of the substrate 1 at the bottom of the gate structure 2 of the isolation region ii are removed, and an opening 10 is formed in the interlayer dielectric layer 3 and the substrate 1.
Referring to fig. 3, a dielectric material layer 4 is formed filling the opening 10, the dielectric material layer 4 also covering the top of the gate structure 2 and the interlayer dielectric layer 3.
Referring to fig. 4, the dielectric material layer 4 is planarized, the dielectric material layer 4 on top of the interlayer dielectric layer 3 and on top of the gate structure 2 is removed, and the dielectric material layer 4 in the opening 10 remains as the isolation structure 5.
In the forming method, in the step of flattening the dielectric material layer 4, it is difficult to ensure that the polishing rates of the regions are the same, so that the probability of loss of the top of the interlayer dielectric layer 3 and the top of the gate structure 2 is high, especially the probability of loss of the top of the gate structure 2 and the top of the interlayer dielectric layer 3 in the peripheral region of the opening 10 is high, and the uniformity of the heights of the top of the gate structure 2 and the top of the interlayer dielectric layer 3 is easily reduced, which results in poor performance of the formed semiconductor structure.
In order to solve the technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate, wherein the substrate comprises a device region for forming a device and an isolation region between adjacent device regions, a gate structure is formed on the substrate of the device region and the isolation region, an interlayer dielectric layer is formed on the substrate exposed by the gate structure, and the interlayer dielectric layer is exposed from the top of the gate structure; removing the gate structure of the isolation region and a part of thickness substrate at the bottom of the gate structure of the isolation region, and forming openings in the interlayer dielectric layer and the substrate; forming an grinding stop layer to cover the top of the interlayer dielectric layer and the top of the grid structure of the device region; forming a dielectric material layer filling the opening, wherein the dielectric material layer also covers the grinding stop layer; and taking the grinding stop layer positioned at the top of the interlayer dielectric layer as a stop position, carrying out planarization treatment on the dielectric material layer, removing the dielectric material layer positioned at the top of the interlayer dielectric layer and the top of the grid structure, and reserving the dielectric material layer positioned in the opening as an isolation structure.
In the embodiment of the invention, openings are formed in the interlayer dielectric layer and the substrate, and after forming the grinding stop layer which covers the top of the gate structure and the interlayer dielectric layer and the top of the gate structure of the device region; and forming a dielectric material layer filling the opening, wherein the dielectric material layer also covers the grinding stop layer, so that the dielectric material layer can be subjected to planarization treatment by taking the grinding stop layer at the top of the interlayer dielectric layer as a stop position.
In order that the above objects, features and advantages of embodiments of the invention may be readily understood, a more particular description of the invention will be rendered by reference to specific embodiments thereof which are illustrated in the appended drawings.
Fig. 5 to 11 are schematic structural views corresponding to each step in an embodiment of a method for forming a semiconductor structure according to the present invention.
Referring to fig. 5, a substrate (not shown) is provided, the substrate including a device region I for forming a device and an isolation region II located between adjacent device regions I, a gate structure 123 is formed on the substrate of the device region I and the isolation region II, an interlayer dielectric layer 117 is formed on the exposed substrate of the gate structure 123, and the interlayer dielectric layer 117 exposes the top of the gate structure 123.
The substrate is used for providing a process platform for the subsequent formation of the semiconductor structure.
In this embodiment, the substrate is used to form a fin field effect transistor. Thus, the base comprises the substrate 100 and the fin 110 protruding from the substrate 100. In other embodiments, when the substrate is used to form a planar field effect transistor, the substrate includes only the substrate, respectively.
In this embodiment, the substrate 100 is a silicon substrate. In other embodiments, the substrate may also be made of other materials such as germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, and the substrate may also be made of other types of substrates such as silicon on insulator substrates or germanium on insulator substrates. The material of the substrate may be a material suitable for process requirements or easy integration.
In this embodiment, the fin 110 and the substrate 100 are obtained by etching the same semiconductor layer. In other embodiments, the fin may be a semiconductor layer epitaxially grown on the substrate, so as to achieve the purpose of precisely controlling the height of the fin.
Therefore, in this embodiment, the material of the fin portion 110 is the same as the material of the substrate 100, and the material of the fin portion 110 is silicon. In other embodiments, the fin may be made of semiconductor material such as germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, which are suitable for forming the fin.
Note that, an isolation layer 111 is further formed on the substrate 100 where the fin portion 110 is exposed, and the isolation layer 111 covers a portion of the sidewall of the fin portion 110.
The isolation layer 111 is used to isolate adjacent devices from each other.
In this embodiment, the material of the isolation layer 111 is silicon oxide. In other embodiments, the material of the isolation layer may be silicon nitride or other insulating materials such as silicon oxynitride.
The gate structure 123 in the device region I is used to control the switching on and off of the conduction channel of the field effect transistor. Source-drain doped layers are typically also formed in the substrate on both sides of the gate structure 123 in the device region I, and the gate structure 123 in the isolation region II is used to isolate the adjacent device region I, so as to avoid the problem of shorting (merge) between the adjacent source-drain doped layers.
In this embodiment, the gate structure 123 spans a portion of the top and a portion of the sidewalls of the fin 110.
In this embodiment, the gate structure 123 is a metal gate structure, and the gate structure 123 includes a high-k gate dielectric layer 121 and a gate electrode layer 122 disposed on the high-k gate dielectric layer 121.
In this embodiment, the material of the high-k gate dielectric layer 121 is a high-k dielectric material; the high-k dielectric material refers to a dielectric material with a relative dielectric constant larger than that of silicon oxide. Specifically, the material of the high-k gate dielectric layer 121 is HfO 2 . In other embodiments, the material of the high-k gate dielectric layer may also be selected from ZrO 2 HfSiO, hfSiON, hfTaO, hfTiO, hfZrO or Al 2 O 3 Etc.
The gate electrode layer 122 is made of Al, cu, ag, au, pt, ni, ti or W. In this embodiment, the material of the gate electrode layer 122 is W.
In other embodiments, the gate structure may also be a polysilicon gate structure. Accordingly, the gate structure includes a gate oxide layer and a gate layer on the gate oxide layer.
In this embodiment, the sidewall of the gate structure 123 is further formed with a sidewall 116.
The side walls 116 are used for protecting the side walls of the gate structure 123, source-drain doped layers are usually formed in the substrate at two sides of the gate structure 123, and the side walls 116 are also used for defining the formation regions of the source-drain doped layers.
The material of the side wall 116 may be one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride oxide, silicon oxycarbide, boron nitride and boron carbonitride, and the side wall 116 may have a single-layer structure or a stacked-layer structure. In this embodiment, the side wall 116 is a single-layer structure, and the material of the side wall 116 is silicon nitride.
Note that, the gate structure 123 is formed by a process of forming a metal gate (high k last metal gate last) by forming a high-k gate dielectric layer, and the dummy gate structure is a stacked structure before forming the gate structure 123, so that the dummy gate oxide layer 112 is further formed between the sidewall 116 and the fin 110. In the process of removing the dummy gate structure to form the gate structure 123, the dummy gate oxide 112 between the sidewall 116 and the fin 110 is maintained under the protection of the sidewall 116.
In this embodiment, the material of the dummy gate oxide layer 112 is silicon oxide. In other embodiments, the material of the dummy gate oxide layer may also be silicon oxynitride.
In this embodiment, the dummy gate oxide layer 112 is further located on the surface of the fin portion 110 exposed by the gate structure 126. In other embodiments, the dummy gate oxide layer may be located only between the sidewall and the fin. In other embodiments, when the dummy gate structure is a single layer structure, the dummy gate oxide layer may not be formed on the substrate.
It should be further noted that the source-drain doped layer 120 is also formed in the substrate at both sides of the gate structure 123. In this embodiment, the source-drain doped layer 120 is located in the fin portion 110 at two sides of the gate structure 123.
When forming an NMOS transistor, the source-drain doped layer 120 includes a stress layer doped with N-type ions, where the stress layer is made of Si or SiC, and the stress layer provides a tensile stress for a channel region of the NMOS transistor, so As to facilitate improving carrier mobility of the NMOS transistor, and the N-type ions are P ions, as ions, or Sb ions; when forming the PMOS transistor, the source-drain doped layer 120 includes a stress layer doped with P-type ions, where the stress layer is made of Si or SiGe, and the stress layer provides compressive stress to the channel region of the PMOS transistor, so as to facilitate improving carrier mobility of the PMOS transistor, and the P-type ions are B ions, ga ions, or In ions.
The interlayer dielectric layer 117 is used for isolating adjacent devices, and the interlayer dielectric layer 117 is also used for providing a process platform for the formation of a subsequent isolation structure.
Thus, the material of the interlayer dielectric layer 117 is an insulating material, such as one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon oxycarbonitride. In this embodiment, the interlayer dielectric layer 117 has a single-layer structure, and the material of the interlayer dielectric layer 117 is silicon oxide.
In this embodiment, the interlayer dielectric layer 117 is formed on the substrate 100 exposed by the gate structure 123, and the interlayer dielectric layer 117 exposes the top of the gate structure 123. Specifically, the top of the interlayer dielectric layer 117 is flush with the top of the gate structure 123.
Referring to fig. 6, the gate structure 123 of the isolation region II and a portion of the thickness of the substrate at the bottom of the gate structure 123 of the isolation region II are removed, and an opening 200 is formed in the interlayer dielectric layer 117 and the substrate.
The opening 200 is configured to provide a spatial position for the subsequent formation of an isolation structure, thereby isolating the adjacent devices, and reducing the probability of occurrence of problems such as leakage current and short circuit between the adjacent devices.
Specifically, in this embodiment, the gate structure 123 of the isolation region II and the fin 110 with a partial thickness at the bottom of the gate structure 123 of the isolation region II are removed, and the opening 200 is formed in the interlayer dielectric layer 117 and the fin 110.
In this embodiment, a dry etching process is used to remove the gate structure 123 of the isolation region II and the fin 110 with a partial thickness at the bottom of the gate structure 123 of the isolation region II.
The dry etching process has the characteristic of anisotropic etching, and has better controllability of etching profile, thereby being beneficial to enabling the appearance of the opening 200 to meet the process requirements. In other embodiments, a wet etching process, or a process combining wet etching and dry etching may be further used to remove the gate structure of the isolation region and a portion of the fin thickness at the bottom of the gate structure of the isolation region.
Referring to fig. 7 in combination, after forming the gate structure 123, further includes: a portion of the thickness of the gate structure 123 is removed and a recess 300 is formed in the interlayer dielectric layer 117.
The subsequent process further comprises: forming a polish stop layer overlying the interlayer dielectric layer 117 and the top of the device region I gate structure 123, so that the polish stop layer can also be formed within the recess 300; in the field of semiconductor manufacturing, the subsequent processes typically further include: forming a dielectric layer on the interlayer dielectric layer 117, the dielectric layer further covering the top of the polish stop layer located in the recess 300; and etching the dielectric layer on top of the gate structure 123 to form a gate contact hole in the dielectric layer, wherein the polish stop layer in the recess 300 can play a role in defining an etching stop position in the subsequent step of etching the dielectric layer on top of the gate structure 123, thereby further reducing the probability of loss of the top of the gate structure 123 and improving the performance of the semiconductor structure.
It should be noted that the depth of the recess 300 is not too small or too large. If the depth of the recess 300 is too small, the thickness of the polish stop layer formed in the recess 300 is too small, so that the effect of defining the etch stop position of the polish stop layer in the recess 300 in the subsequent etching process for forming the gate contact hole is easily reduced; if the depth of the recess 300 is too large, the height of the remaining gate structure 123 in the device region I is too small, which tends to reduce the control capability of the gate structure 123 on the fin 110, thereby adversely affecting the electrical performance of the semiconductor structure. For this purpose, in the present embodiment, the depth of the groove 300 is 100 to 300 a.
In this embodiment, after the opening 200 is formed, the recess 300 is formed, which is advantageous to reduce the influence of the process of forming the opening 200 on the gate structure 123.
Therefore, in order to avoid the process of forming the recess 300 from affecting the shape of the opening 200 and to avoid the process of forming the recess 300 from damaging the fin 110 exposed by the opening 200, in this embodiment, after forming the opening 200, before forming the recess 300, the method further includes: a protective layer (not shown) is formed to fill the opening 200.
In order to reduce the difficulty in the subsequent removal of the protective layer, the material of the protective layer is easy to remove. In this embodiment, the material of the protective layer is an organic material. Specifically, the material of the protective layer may be BARC (bottom anti-reflective coating) material, ODL (organic dielectric layer ) material, photoresist, or DUO (Deep UV Light Absorbing Oxide, deep ultraviolet light absorbing oxide layer) material. In this embodiment, the material of the protective layer is BARC material.
Accordingly, the step of forming the recess 300 includes: forming a mask layer (not shown) covering the interlayer dielectric layer 117 and exposing the top of the gate structure 123 of the device region I; and taking the mask layer as a mask, removing part of the thickness of the gate structure 123, and forming a groove 300 in the interlayer dielectric layer 117.
In this embodiment, the mask layer is made of photoresist. The photoresist is a mask material commonly used in the field of semiconductor manufacturing, and is beneficial to improving process compatibility.
In this embodiment, a dry etching process is used to remove a portion of the thickness of the gate structure 123, which is favorable for precisely controlling the removal thickness of the device region I gate structure 123, so that the shape and depth of the recess 300 meet the process requirements.
In this embodiment, after the recess 300 is formed, the forming method further includes: and removing the mask layer and the protective layer.
The photoresist material is also an organic material, so that the mask layer and the protective layer can be removed in the same step, which is beneficial to simplifying the process steps. Accordingly, the mask layer and the protective layer can be removed by wet etching after the ashing process is performed.
In other embodiments, the opening may be formed after the recess is formed, where the step of forming the recess includes: forming a mask layer on the top of the interlayer dielectric layer exposed by the gate structure; removing part of the thickness of the grid structure by taking the mask layer as a mask, and forming a groove in the interlayer dielectric layer; and removing the mask layer after the grooves are formed.
Referring to fig. 8, a polish stop layer 124 is formed overlying the top of the interlayer dielectric layer 117 and the top of the device region I gate structure 123.
The subsequent process further comprises: the dielectric material layer filling the opening 200 is formed, and the dielectric material layer also covers the polish stop layer 124, so that the polish stop layer 124 at the top of the interlayer dielectric layer 117 can be used as a stop position for performing planarization treatment on the dielectric material layer, and compared with the scheme without forming the polish stop layer, the arrangement of the polish stop layer 124 in this embodiment reduces the probability of loss of the top of the gate structure 123 and the top of the interlayer dielectric layer 117 in the planarization treatment step, particularly reduces the probability of loss of the top of the gate structure 123 and the top of the interlayer dielectric layer 117 in the peripheral area of the opening 200, further improves the height consistency of the top of the gate structure 123 and the top of the interlayer dielectric layer 117, and optimizes the performance of the semiconductor structure.
The polish stop layer 124 has a higher hardness and higher density than the dielectric material layer, and thus can serve to define a stop position during subsequent planarization of the dielectric material layer.
In this embodiment, the material of the polish stop layer 124 is a dielectric material, so that the influence of the polish stop layer 124 on the semiconductor structure can be reduced.
Specifically, the material of the polish stop layer 124 is a nitrogen-containing dielectric material, such as silicon nitride, silicon oxynitride, silicon oxycarbonitride, silicon boron carbonitride, and the like. By selecting a dielectric material containing nitrogen, it is advantageous to ensure the effectiveness of the polish stop layer 124 in defining the stop location for the planarization process.
In this embodiment, the material of the polish stop layer 124 is silicon nitride. The silicon nitride material is a common material in the semiconductor manufacturing process, which is beneficial to improving the process compatibility and reducing the process cost, and the silicon nitride material has higher density and hardness, so that the effect of the polishing stop layer 124 for defining the planarization stop position is more remarkable.
In the step of forming the polish stop layer 124, the thickness of the polish stop layer 124 on top of the interlayer dielectric layer 117 should not be too small or too large. If the thickness of the polish stop layer 124 on top of the interlayer dielectric layer 117 is too small, the effect of defining the planarization position of the polish stop layer 124 on top of the interlayer dielectric layer 117 is easily reduced; if the thickness of the polish stop layer 124 on top of the interlayer dielectric layer 117 is too large, the time required to form the polish stop layer 124 is too long, which tends to reduce the throughput and increase the process cost. For this purpose, in this embodiment, the thickness of the polish stop layer 124 on top of the interlayer dielectric layer 117 is 150 to 350 a.
In this embodiment, the polish stop layer 124 is formed using an atomic layer deposition process (Atomic layer deposition, ALD). By selecting an atomic layer deposition process, the thickness uniformity of the polish stop layer 124 is advantageously improved, such that the thickness of the polish stop layer 124 can be precisely controlled. In other embodiments, the polish stop layer may also be formed using a chemical vapor deposition process.
Furthermore, the atomic layer deposition process has a better conformal coverage, and in this embodiment, after the opening 200 is formed, the polish stop layer 124 is formed, so in the step of forming the polish stop layer 124, the polish stop layer 124 also conformally covers the bottom and the sidewalls of the opening 200.
In the subsequent step of forming the dielectric material layer filling the opening 200, the polish stop layer 124 located at the bottom and the sidewall of the opening 200 can protect the fin 110 exposed by the opening 200, so as to reduce the influence of the process of forming the dielectric material layer on the fin 110 exposed by the opening 200. Moreover, the hardness and compactness of the polish stop layer 124 are relatively high, and the polish stop layer 124 at the bottom and the sidewall of the opening 200 can correspondingly support the sidewall of the opening 200, so that the probability of dishing (dishing) of the top of the dielectric material layer in the opening 200 is relatively low in the subsequent planarization step, and accordingly, the probability of damage to the top of the gate structure 123 and the top of the interlayer dielectric layer 117 in the peripheral region of the opening 200 can be further reduced.
In this embodiment, a case where the polish stop layer 124 is formed after the opening 200 is formed is taken as an example. In other embodiments, the openings may also be formed after the polish stop layer is formed. Accordingly, the polish stop layer is not formed within the opening.
In this embodiment, a recess 300 is further formed in the interlayer dielectric layer 117 on top of the gate structure 123, so in the step of forming the polish stop layer 124, the polish stop layer 124 is further formed in the recess 300.
When the polish stop layer 124 above the top of the interlayer dielectric layer 117 is subsequently removed, the polish stop layer 124 in the recess 300 can still be retained, so as to define an etching stop position in a subsequent etching step for forming a gate contact hole.
In this embodiment, the atomic layer deposition process for forming the polish stop layer 124 has a better conformal coverage capability, so that the polish stop layer 124 conformally covers the bottom and the sidewalls of the recess 300 during the process of forming the polish stop layer 124, and the material of the polish stop layer 124 on the sidewalls of the recess 300 gradually contacts with the increase of the thickness of the deposited material based on the set value of the thickness of the polish stop layer 124 on the top of the interlayer dielectric layer 117 during the process of forming the polish stop layer 124, so that the finally formed polish stop layer 124 fills the recess 300.
Specifically, in this embodiment, the top surface of the polish stop layer 124 on top of the gate structure 123 and the top surface of the polish stop layer 124 on top of the interlayer dielectric layer 177 are flush, which is beneficial to improving the effect of the polish stop layer 124 on top of the gate structure 123 in defining the stop position for the subsequent planarization of the dielectric material layer.
Referring to fig. 9, a dielectric material layer 125 is formed to fill the opening 200 (shown in fig. 8), the dielectric material layer 125 also covering the polish stop layer 124.
The dielectric material layer 125 is used for forming an isolation structure subsequently, so that isolation between adjacent devices is realized, the probability of leakage current and short circuit problems between the adjacent devices is reduced, and the density and uniformity of the layout are improved.
Thus, the material of the dielectric material layer 125 is an insulating material. The material of the dielectric material layer 125 may be silicon oxide, silicon oxynitride, silicon nitride, silicon carbonitride or silicon boron nitride carbide. In this embodiment, the material of the dielectric material layer 125 is silicon oxide. Silicon oxide is a dielectric material with common process and low cost, has high process compatibility, and is beneficial to reducing the forming difficulty and the process cost of the dielectric material layer 125; in addition, the silicon oxide has smaller dielectric constant, which is beneficial to improving the isolation effect of the subsequent isolation structure on the adjacent devices.
In this embodiment, the dielectric material layer 125 is formed using a flowable chemical vapor deposition (Flowable Chemical Vapor Deposition, FCVD) process. The flowable chemical vapor deposition process has good filling capability, is suitable for filling the openings with high aspect ratio, is beneficial to reducing the probability of generating defects such as holes in the dielectric material layer 125 positioned in the openings 200, and correspondingly improves the film forming quality of the subsequent isolation structure. In other embodiments, the dielectric material layer may also be formed using a deposition process such as a plasma chemical vapor deposition process or a low pressure chemical vapor deposition process.
Referring to fig. 10, with the polish stop layer 124 located on top of the interlayer dielectric layer 117 as a stop position, the dielectric material layer 125 is planarized, the dielectric material layer 125 (shown in fig. 9) located on top of the interlayer dielectric layer 117 and on top of the gate structure 123 is removed, and the dielectric material layer 125 located in the opening 200 (shown in fig. 8) remains as the isolation structure 126.
Compared with the scheme that no polish stop layer is formed, the arrangement of the polish stop layer 124 reduces the probability of loss of the top of the gate structure 123 and the top of the interlayer dielectric layer 117 in the planarization process, particularly reduces the probability of loss of the top of the gate structure 123 and the top of the interlayer dielectric layer 117 in the peripheral area of the opening 200, further improves the consistency of the heights of the top of the gate structure 123 and the top of the interlayer dielectric layer 117, and optimizes the electrical performance of the semiconductor structure.
The isolation structure 126 is used for realizing isolation between adjacent devices, reducing the probability of leakage current and short circuit problems between adjacent devices, and being beneficial to improving the uniformity and density of layout.
In this embodiment, the isolation structure 126 is a single diffusion partition (single diffusion break, SDB) isolation structure, which is beneficial to reduce the area occupied by the semiconductor structure, thereby meeting the requirements of high density and high integration of chip design.
In this embodiment, the planarization process is performed on the dielectric material layer 125 by using a chemical mechanical polishing process. Thus, after planarizing the dielectric material layer 125, the top of the isolation structure 126 is level with the top of the polish stop layer 124 on the interlayer dielectric layer 117.
Referring to fig. 11 in combination, after forming the isolation structure 126, the method further includes: the polish stop layer 124 is removed above the top of the interlayer dielectric layer 117.
By removing the polish stop layer 124 above the top of the interlayer dielectric layer 117, only the recesses 300 (shown in fig. 7) remain, thereby reducing the thickness of the polish stop layer 124 on top of the gate structure 123 and reducing the difficulty in subsequently forming gate contact holes exposing the top of the gate structure 123.
In this embodiment, the dry etching process is used to remove the polish stop layer 124 higher than the top of the interlayer dielectric layer 117, which is favorable for precisely controlling the etching amount, and can reduce the loss of the interlayer dielectric layer 117 while removing the polish stop layer 124 higher than the top of the interlayer dielectric layer 117.
In this embodiment, in the step of removing the polish stop layer 124 above the top of the interlayer dielectric layer 117, a part of the thickness of the isolation structure 126 is also removed.
It should be noted that, since the material of the polish stop layer 124 is a dielectric material, in other embodiments, the step of removing the polish stop layer higher than the top of the interlayer dielectric layer may not be performed, which simplifies the process flow accordingly.
Correspondingly, the invention further provides a semiconductor structure. Referring to fig. 10, a schematic structure diagram of an embodiment of the semiconductor structure of the present invention is shown.
The semiconductor structure includes: a substrate including a device region I for forming a device and an isolation region II located between adjacent device regions I; a gate structure 123 on the substrate of the device region I; an interlayer dielectric layer 117 located on the exposed substrate of the gate structure 123, wherein the interlayer dielectric layer 117 exposes the top of the gate structure 123; isolation structures 126 located within the interlayer dielectric layer 117 and the substrate of the isolation region I; a polish stop layer 124 on top of the gate structure 123 and interlayer dielectric layer 117, the polish stop layer 124 being adapted to define a stop location for planarization during formation of the isolation structure 126.
Compared with the scheme without forming the polish stop layer, the arrangement of the polish stop layer 124 in this embodiment reduces the probability of loss of the top of the gate structure 123 and the top of the interlayer dielectric layer 117 in the planarization step, particularly reduces the probability of loss of the top of the gate structure 123 and the top of the interlayer dielectric layer 117 in the peripheral region of the isolation structure 126, further improves the height consistency of the top of the gate structure 123 and the top of the interlayer dielectric layer 117, and optimizes the electrical performance of the semiconductor structure.
The substrate is used to provide a process platform for the formation of semiconductor structures.
In this embodiment, the semiconductor structure is used to form a fin field effect transistor. Thus, the base comprises the substrate 100 and the fin 110 protruding from the substrate 100. In other embodiments, when the substrate is used to form a planar field effect transistor, the substrate includes only the substrate, respectively.
In this embodiment, the substrate 100 is a silicon substrate. In other embodiments, the substrate may also be made of other materials such as germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, and the substrate may also be made of other types of substrates such as silicon on insulator substrates or germanium on insulator substrates. The material of the substrate may be a material suitable for process requirements or easy integration.
In this embodiment, the fin 110 and the substrate 100 are obtained by etching the same semiconductor layer. In other embodiments, the fin may be a semiconductor layer epitaxially grown on the substrate, so as to achieve the purpose of precisely controlling the height of the fin.
Therefore, in this embodiment, the material of the fin portion 110 is the same as the material of the substrate 100, and the material of the fin portion 110 is silicon. In other embodiments, the fin may be made of semiconductor material such as germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, which are suitable for forming the fin.
It should be noted that the semiconductor structure further includes: and the isolation layer 111 is positioned on the substrate 100 exposed by the fin portion 110, and the isolation layer 111 covers part of the side wall of the fin portion 110.
The isolation layer 111 is used to isolate adjacent devices from each other.
In this embodiment, the material of the isolation layer 111 is silicon oxide. In other embodiments, the material of the isolation structure may be silicon nitride or other insulating materials such as silicon oxynitride.
The gate structure 123 in the device region I is used to control the switching on and off of the conduction channel of the field effect transistor.
In this embodiment, the gate structure 123 spans a portion of the top and a portion of the sidewalls of the fin 110.
In this embodiment, the gate structure 123 is a metal gate structure, and the gate structure 123 includes a high-k gate dielectric layer 121 and a gate electrode layer 122 disposed on the high-k gate dielectric layer 121.
In this embodiment, the material of the high-k gate dielectric layer 121 is a high-k dielectric material; the high-k dielectric material refers to a dielectric material with a relative dielectric constant larger than that of silicon oxide. Specifically, the material of the high-k gate dielectric layer 121 is HfO 2 . In other embodiments, the material of the high-k gate dielectric layer may also be selected from ZrO 2 HfSiO, hfSiON, hfTaO, hfTiO, hfZrO or Al 2 O 3 Etc.
The gate electrode layer 122 is made of Al, cu, ag, au, pt, ni, ti or W. In this embodiment, the material of the gate electrode layer 122 is W.
In other embodiments, the gate structure may also be a polysilicon gate structure. Accordingly, the gate structure includes a gate oxide layer and a gate layer on the gate oxide layer.
In this embodiment, the semiconductor structure further includes: and a sidewall 116 on the sidewall of the gate structure 123.
The sidewall 116 is used for protecting the sidewall of the gate structure 123, and the semiconductor structure generally further includes a source-drain doped layer, and the sidewall 116 is further used for defining a formation region of the source-drain doped layer.
The material of the side wall 116 may be one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride oxide, silicon oxycarbide, boron nitride and boron carbonitride, and the side wall 116 may have a single-layer structure or a stacked-layer structure. In this embodiment, the side wall 116 is a single-layer structure, and the material of the side wall 116 is silicon nitride.
Note that, the gate structure 123 is formed by a process of forming a metal gate by forming a high-k gate dielectric layer, and the dummy gate structure is a stacked structure before forming the gate structure 123, so the semiconductor structure further includes: and the dummy gate oxide 112 is located between the side wall 116 and the fin 110. In the process of removing the dummy gate structure to form the gate structure 123, the dummy gate oxide 112 between the sidewall 116 and the fin 110 is maintained under the protection of the sidewall 116.
In this embodiment, the material of the dummy gate oxide layer 112 is silicon oxide. In other embodiments, the material of the dummy gate oxide layer may also be silicon oxynitride.
In this embodiment, the dummy gate oxide layer 112 is further located on the surface of the fin portion 110 exposed by the gate structure 126. In other embodiments, the dummy gate oxide layer may be located only between the sidewall and the fin. In other embodiments, when the dummy gate structure is a single layer structure, the dummy gate oxide layer may not be formed on the substrate.
It should also be noted that the semiconductor structure further includes: the source/drain doped layer 120 is located in the substrate at two sides of the gate structure 123. In this embodiment, the source-drain doped layer 120 is located in the fin portion 110 at two sides of the gate structure 123.
When the formed semiconductor structure is an NMOS transistor, the source-drain doped layer 120 includes a stress layer doped with N-type ions, where the material of the stress layer is Si or SiC, and the stress layer provides a tensile stress effect for a channel region of the NMOS transistor, so As to facilitate improving carrier mobility of the NMOS transistor, and the N-type ions are P ions, as ions, or Sb ions; when the semiconductor structure is a PMOS transistor, the source-drain doped layer 120 includes a stress layer doped with P-type ions, where the stress layer is made of Si or SiGe, and the stress layer provides a compressive stress to a channel region of the PMOS transistor, so as to facilitate improving carrier mobility of the PMOS transistor, and the P-type ions are B ions, ga ions, or In ions.
The interlayer dielectric layer 117 is used for isolating adjacent devices, and the interlayer dielectric layer 117 is also used for providing a process platform for forming the isolation structure 126. In this embodiment, the interlayer dielectric layer 117 is located on the substrate 100 where the gate structure 123 is exposed.
Thus, the material of the interlayer dielectric layer 117 is an insulating material, such as one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon oxycarbonitride. In this embodiment, the interlayer dielectric layer 117 has a single-layer structure, and the material of the interlayer dielectric layer 117 is silicon oxide.
The isolation structure 126 is used for realizing isolation between adjacent devices, reducing the probability of leakage current and short circuit problems between adjacent devices, and being beneficial to improving the uniformity and density of layout.
Thus, the material of the isolation structure 126 is an insulating material. Specifically, the material of the isolation structure 126 may be silicon oxide, silicon oxynitride, silicon nitride, silicon carbonitride, or silicon boron carbide nitride. In this embodiment, the isolation structure 126 is made of silicon oxide.
Silicon oxide is a dielectric material with common process and low cost, has high process compatibility, and is beneficial to reducing the forming difficulty and the process cost of the isolation structure 126; in addition, the smaller dielectric constant of the silicon oxide is also beneficial to improving the isolation effect of the isolation structure 126 on adjacent devices.
In this embodiment, the isolation structure 126 is a single diffusion isolation structure, which is beneficial to reduce the area occupied by the semiconductor structure, so as to meet the requirements of high density and high integration of chip design.
The isolation structure 126 is typically formed by a planarization process, and the polish stop layer 124 on top of the interlayer dielectric layer 117 is used to define a stop location for the planarization process.
The polish stop layer 124 has a higher hardness and higher density than the isolation structures 126 and thus can function to define a stop position during the planarization process.
In this embodiment, the material of the polish stop layer 124 is a dielectric material, so that the influence of the polish stop layer 124 on the semiconductor structure can be reduced.
Specifically, the material of the polish stop layer 124 is a nitrogen-containing dielectric material, such as silicon nitride, silicon oxynitride, silicon oxycarbonitride, silicon boron carbonitride, and the like. By selecting a nitrogen-containing dielectric material, it is advantageous to ensure the effectiveness of the polish stop layer 124 in defining the planarization stop position.
In this embodiment, the material of the polish stop layer 124 is silicon nitride. The silicon nitride material is a common material in the semiconductor manufacturing process, which is beneficial to improving the process compatibility and reducing the process cost, and the silicon nitride material has higher density and hardness, so that the effect of the polishing stop layer 124 for defining the stop position of the planarization treatment is more remarkable.
The thickness of the polish stop layer 124 on top of the interlayer dielectric layer 117 should not be too small or too large. If the thickness of the polish stop layer 124 on top of the interlayer dielectric layer 117 is too small, the effect of defining the planarization position of the polish stop layer 124 on top of the interlayer dielectric layer 117 is easily reduced; if the thickness of the polish stop layer 124 on top of the interlayer dielectric layer 117 is too large, the time required to form the polish stop layer 124 is too long, which tends to reduce the throughput and increase the process cost. For this purpose, in this embodiment, the thickness of the polish stop layer 124 on top of the interlayer dielectric layer 117 is 150 to 350 a.
In this embodiment, the polish stop layer 124 is further disposed between the isolation structure 126 and the interlayer dielectric layer 117, and between the isolation structure 126 and the substrate. Specifically, the polish stop layer 124 is further located between the isolation structure 126 and the interlayer dielectric layer 117, and between the isolation structure 126 and the fin 110.
During the step of forming the isolation structure 126, the polish stop layer 124 between the isolation structure 126 and the fin 110 may protect the fin 110 material, thereby advantageously reducing the impact of the process of forming the isolation structure 126 on the fin 110 material on the bottom and sidewalls thereof.
Moreover, the hardness and the compactness of the polish stop layer 124 are relatively high, and the polish stop layer 124 between the isolation structure 126 and the interlayer dielectric layer 117 and between the isolation structure 126 and the fin 110 can correspondingly play a supporting role in the step of forming the planarization treatment, so that the probability of occurrence of a dishing problem on the top of the isolation structure 126 is reduced, and accordingly the probability of occurrence of damage on the top of the gate structure 123 and the top of the interlayer dielectric layer 117 in the peripheral region of the isolation structure 126 can be further reduced.
Note that, in this embodiment, the top of the gate structure 123 is lower than the top of the interlayer dielectric layer 117, and the polish stop layer 124 is further located in a recess 300 (shown in fig. 7) surrounded by the top of the gate structure 123 and the interlayer dielectric layer 117.
In the field of semiconductor manufacturing, the subsequent processes typically further include: forming a dielectric layer on the interlayer dielectric layer 117, the dielectric layer covering the top of the polish stop layer 124 located in the recess 300; the dielectric layer on top of the gate structure 123 is etched, a gate contact hole is formed in the dielectric layer, and the polish stop layer 124 in the recess 300 can also play a role in defining an etching stop position in the step of etching the dielectric layer on top of the gate structure 123, so that the probability of loss of the top of the gate structure 123 is further reduced, and the electrical performance of the semiconductor structure is improved.
The depth of the recess 300 is not too small nor too large. If the depth of the recess 300 is too small, the thickness of the polish stop layer 124 in the recess 300 is too small, which tends to reduce the effect of defining the etch stop position of the polish stop layer 124 in the recess 300 in the subsequent etching process for forming the gate contact hole; if the depth of the recess 300 is too large, the height of the remaining gate structure 123 in the device region I is too small, which tends to reduce the control capability of the gate structure 123 on the fin 110, thereby adversely affecting the electrical performance of the semiconductor structure. For this purpose, in the present embodiment, the depth of the groove 300 is 100 to 300 a.
The semiconductor structure may be formed by the forming method described in the foregoing embodiments, or may be formed by other forming methods. For a specific description of the semiconductor structure in this embodiment, reference may be made to the corresponding description in the foregoing embodiment, which is not repeated here.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.
Claims (15)
1. A method of forming a semiconductor structure, comprising:
providing a substrate, wherein the substrate comprises a device region for forming a device and an isolation region between adjacent device regions, a gate structure is formed on the substrate of the device region and the isolation region, an interlayer dielectric layer is formed on the substrate exposed by the gate structure, and the interlayer dielectric layer is exposed from the top of the gate structure;
removing the gate structure of the isolation region and a part of thickness substrate at the bottom of the gate structure of the isolation region, and forming openings in the interlayer dielectric layer and the substrate;
after the opening is formed, removing part of the thickness of the gate structure of the device region, and forming a groove in the interlayer dielectric layer;
forming a grinding stop layer, covering the top of the interlayer dielectric layer and the side wall and the bottom of the opening, wherein the grinding stop layer is filled in the groove, and the top of one side of the grinding stop layer, which is far away from the groove, is flush;
forming a dielectric material layer filling the opening, wherein the dielectric material layer also covers the grinding stop layer; and taking the grinding stop layer positioned at the top of the interlayer dielectric layer as a stop position, carrying out planarization treatment on the dielectric material layer, removing the dielectric material layer positioned at the top of the interlayer dielectric layer and the top of the grid structure, and reserving the dielectric material layer positioned in the opening as an isolation structure.
2. The method of claim 1, wherein in the step of forming the polish stop layer, a thickness of the polish stop layer on top of the interlayer dielectric layer is 150 to 350 a.
3. The method of claim 1, wherein the polish stop layer is formed using an atomic layer deposition process.
4. The method of forming a semiconductor structure of claim 1, wherein the recess is formed after the opening is formed;
after forming the opening, before forming the groove, further comprising: forming a protective layer filled in the opening;
the step of forming the groove includes: forming a mask layer which covers the interlayer dielectric layer and exposes the top of the grid structure of the device region; taking the mask layer as a mask, and removing part of the thickness of the grid structure;
after forming the groove, the method further comprises: and removing the mask layer and the protective layer.
5. The method of forming a semiconductor structure of claim 1, wherein a dry etching process is used to remove a portion of the thickness of the gate structure.
6. The method of forming a semiconductor structure of claim 1, wherein in the step of forming a recess in the interlayer dielectric layer, a depth of the recess is 100 to 300 a.
7. The method of claim 1, wherein in forming the polish stop layer, the polish stop layer is a dielectric material.
8. The method of claim 1, wherein in forming the polish stop layer, the polish stop layer is made of silicon nitride, silicon oxynitride, silicon oxycarbonitride, silicon boron carbonitride.
9. The method of forming a semiconductor structure of claim 1, further comprising, after forming the isolation structure: and removing the grinding stop layer higher than the top of the interlayer dielectric layer.
10. The method of claim 9, wherein a dry etching process is used to remove the polish stop layer above the top of the interlevel dielectric layer.
11. A semiconductor structure, comprising:
a substrate including device regions for forming devices and isolation regions between adjacent device regions;
the grid structure is positioned on the substrate of the device region;
the interlayer dielectric layer is positioned on the substrate exposed by the gate structure, the top of the interlayer dielectric layer is exposed out of the top of the gate structure, and the top of the interlayer dielectric layer is higher than the top of the gate structure;
The isolation structure is positioned in the interlayer dielectric layer and the substrate of the isolation region;
a polish stop layer on top of the gate structure and the interlayer dielectric layer, between the isolation structure and the substrate, and in a recess defined by the top of the gate structure and the interlayer dielectric layer, and on top of one side of the polish stop layer away from the gate structure, the polish stop layer being flush with the top of one side of the gate structure, the polish stop layer being adapted to define a stop for planarization during formation of the isolation structure
And (5) placing.
12. The semiconductor structure of claim 11, wherein a thickness of a polish stop layer on top of the interlevel dielectric layer is 150 to 350 a.
13. The semiconductor structure of claim 11, wherein a depth of the recess is 100 to 300 angstroms.
14. The semiconductor structure of claim 11, wherein the material of the polish stop layer is a dielectric material.
15. The semiconductor structure of claim 11, wherein the material of the polish stop layer is silicon nitride, silicon oxynitride, silicon oxycarbonitride, silicon boron carbonitride.
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| CN105097521A (en) * | 2014-05-04 | 2015-11-25 | 中芯国际集成电路制造(上海)有限公司 | Formation method of semiconductor device |
| CN105225950A (en) * | 2014-05-29 | 2016-01-06 | 中芯国际集成电路制造(上海)有限公司 | The formation method of fin formula field effect transistor, the formation method of MOS transistor |
| CN109309048A (en) * | 2017-07-26 | 2019-02-05 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| CN110634798A (en) * | 2018-06-25 | 2019-12-31 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
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| CN105097521A (en) * | 2014-05-04 | 2015-11-25 | 中芯国际集成电路制造(上海)有限公司 | Formation method of semiconductor device |
| CN105225950A (en) * | 2014-05-29 | 2016-01-06 | 中芯国际集成电路制造(上海)有限公司 | The formation method of fin formula field effect transistor, the formation method of MOS transistor |
| CN109309048A (en) * | 2017-07-26 | 2019-02-05 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| CN110634798A (en) * | 2018-06-25 | 2019-12-31 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
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