CN112151606B - Semiconductor structure and forming method thereof - Google Patents
Semiconductor structure and forming method thereof Download PDFInfo
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- CN112151606B CN112151606B CN201910577060.2A CN201910577060A CN112151606B CN 112151606 B CN112151606 B CN 112151606B CN 201910577060 A CN201910577060 A CN 201910577060A CN 112151606 B CN112151606 B CN 112151606B
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
Abstract
A semiconductor structure and a method of forming the same, the method comprising: providing a substrate; forming a source doping layer on a substrate; forming a semiconductor column on the source doped layer; forming a drain doped layer covering the top of the semiconductor column and surrounding the side wall of the semiconductor column part on one side of the top of the semiconductor column; forming a gate structure surrounding a portion of the sidewall of the semiconductor pillar and exposing the drain doped layer; after the grid structure is formed, a drain plug is formed on the top of the drain doping layer, and the drain plug is electrically connected with the drain doping layer. According to the invention, the drain doping layer which covers the top of the semiconductor column and surrounds the side wall of the semiconductor column part is formed, so that the width of the drain doping layer is increased, the top surface area of the drain doping layer is correspondingly increased, the process window for forming the drain plug is increased, the drain plug is easy to form on the top of the drain doping layer, and the electric connection effect of the drain plug and the drain doping layer is improved, thereby improving the performance of the VGAA transistor.
Description
Technical Field
Embodiments of the present disclosure relate to semiconductor manufacturing, and more particularly, to a semiconductor structure and a method for forming the same.
Background
With the rapid development of semiconductor manufacturing technology, semiconductor devices are being developed toward higher element density and higher integration, and the development trend of semiconductor process nodes following moore's law is continuously decreasing. As the channel length decreases, the gate structure's ability to control the channel becomes weak, causing subthreshold leakage (subthreshold leakage) phenomenon, the so-called short channel effect (short channel effect, SCE).
To better accommodate the demand for device scaling, semiconductor processes are increasingly beginning to transition from planar transistors to three-dimensional transistors with higher power, such as gate-all-around (GAA) transistors. In the fully-enclosed gate transistor, the gate structure surrounds the channel region, and compared with a planar transistor, the gate structure of the fully-enclosed gate transistor has stronger control capability on the channel and can better inhibit short channel effect.
The full-surrounding gate transistors include a lateral gate-all-around (LGAA) transistor and a vertical gate-all-around (VGAA) transistor. Wherein the channel of the VGAA transistor extends in a direction perpendicular to the substrate surface, which increases the area utilization efficiency of the semiconductor structure, thereby enabling a further feature size reduction.
Disclosure of Invention
The embodiment of the invention solves the problem of providing a semiconductor structure and a forming method thereof, and improves the performance of VGAA transistors.
In order to solve the above problems, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate; forming a source doping layer on the substrate; forming a semiconductor column on the source doped layer; forming a drain doping layer which covers the top of the semiconductor column and surrounds the side wall of the semiconductor column part on one side of the top of the semiconductor column; forming a gate structure surrounding a portion of the sidewall of the semiconductor pillar and exposing the drain doped layer; and after the grid structure is formed, forming a drain plug at the top of the drain doping layer, wherein the drain plug is electrically connected with the drain doping layer.
Optionally, in the step of forming the drain doped layer, the height of the semiconductor column surrounded by the drain doped layer is 2nm to 6nm.
Optionally, in the step of forming the leakage doped layer, the thickness of the leakage doped layer is 2nm to 5nm.
Optionally, the drain doped layer is formed by a selective epitaxial process.
Optionally, after forming the semiconductor pillar, before forming the drain doped layer, the method further includes: forming a protective layer on the source doping layer exposed by the semiconductor column, wherein the protective layer covers part of the side wall of the semiconductor column; in the step of forming the drain doped layer, the drain doped layer covers the semiconductor column exposed by the protective layer.
Optionally, the step of forming the protective layer includes: forming a protective material layer on the source doping layer exposed by the semiconductor column; and etching back a part of the protective material layer with the thickness to expose part of the side wall of the semiconductor column, and taking the rest of the protective material layer as the protective layer.
Optionally, the material of the protective layer is a dielectric material; after forming the drain doped layer, before forming the gate structure, the method further comprises: and etching back part of the protective layer with the thickness, exposing part of the side wall of the semiconductor column, and taking the rest of the protective layer as an isolation layer.
Optionally, after the gate structure is formed, the top of the gate structure is lower than the bottom of the drain doped layer.
Optionally, a distance from the top of the gate structure to the bottom of the drain doped layer is 3nm to 5nm.
Optionally, the step of forming the gate structure includes: forming a gate material layer conformally covering the semiconductor column, wherein the gate material layer also extends to part of the source doping layer on one side of the semiconductor column; forming an interlayer dielectric layer on the source doped layer, wherein the interlayer dielectric layer covers part of the side wall of the semiconductor column, and the top of the interlayer dielectric layer is lower than the bottom of the drain doped layer; and removing the gate material layer exposed from the interlayer dielectric layer to form the gate structure.
Optionally, before forming the gate structure, the method further includes: and forming a gate dielectric layer which conformally covers the semiconductor column and the leakage doped layer.
Correspondingly, the embodiment of the invention also provides a semiconductor structure, which comprises: a substrate; a source doped layer located on the substrate; a semiconductor pillar located on the source doped layer; the leakage doping layer is positioned on one side of the top of the semiconductor column, covers the top of the semiconductor column and surrounds part of the side wall of the semiconductor column; a gate structure surrounding a portion of the sidewall of the semiconductor pillar and exposing the drain doped layer; and the drain plug is positioned on the top of the drain doping layer and is electrically connected with the drain doping layer.
Optionally, the height of the semiconductor column surrounded by the drain doped layer is 2nm to 6nm.
Optionally, the thickness of the leakage doped layer is 2nm to 5nm.
Optionally, the drain doped layer comprises an epitaxial layer doped with conductive ions.
Optionally, the semiconductor structure further includes: and the isolation layer is positioned between the gate structure and the source doping layer and covers part of the side wall of the semiconductor column.
Optionally, the top of the gate structure is lower than the bottom of the drain doped layer.
Optionally, a distance from the top of the gate structure to the bottom of the drain doped layer is 3nm to 5nm.
Optionally, the semiconductor structure further includes: and the gate dielectric layer is positioned between the semiconductor column and the gate structure and conformally covers the top and the side wall of the drain doping layer exposed by the gate structure.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following advantages:
according to the embodiment of the invention, the drain doping layer which covers the top of the semiconductor column and surrounds the side wall of the semiconductor column is formed on one side of the top of the semiconductor column, so that the width of the drain doping layer is increased, the top surface area of the drain doping layer is correspondingly increased, a process window for forming a drain plug is increased, the drain plug is easy to form on the top of the drain doping layer, the electric connection effect of the drain plug and the drain doping layer is improved, and the performance of the VGAA transistor is further improved, for example: the contact resistance between the drain doped layer and the drain plug is reduced.
Drawings
FIG. 1 is a schematic diagram of a semiconductor structure;
fig. 2 to 11 are schematic structural views corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention.
Detailed Description
The performance of the VGAA transistors is still to be improved. The reason why the performance of VGAA transistors is still to be improved is now analyzed in connection with a semiconductor structure.
Referring to fig. 1 in combination, fig. 1 is a schematic structural diagram of a semiconductor structure.
The semiconductor structure includes: a substrate 10; a source doped layer 11 on the substrate 10; a semiconductor pillar 12 located on the source doped layer 11; a drain doped layer 14 located on top of the semiconductor pillars 13; an isolation layer 13 on the source doped layer 11 where the semiconductor pillar 12 is exposed, and the isolation layer 13 covers a portion of the sidewall of the semiconductor pillar 12; a gate structure 15 surrounding a portion of the sidewall of the semiconductor pillar 12 exposed by the isolation layer 13, and the gate structure 15 exposing the drain doped layer 14; a drain plug 18 is located on the drain doped layer 14 and is electrically connected to the drain doped layer 14.
The drain doped layer 14 is located on top of the semiconductor pillars 12, but as the device feature size is reduced, the width of the semiconductor pillars 12 is smaller and smaller, resulting in a smaller width of the drain doped layer 14. Accordingly, during the process of forming the drain plug 18, the control difficulty of overlay (overlay) precision is increased, so that the process difficulty of forming the drain plug 18 is increased, the electrical connection effect between the drain plug 18 and the drain doped layer 14 is reduced, and the performance of the transistor is also adversely affected, for example: resulting in an increased contact resistance between the drain plug 18 and the drain doped layer 14.
In order to solve the technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate; forming a source doping layer on the substrate; forming a semiconductor column on the source doped layer; forming a drain doping layer which covers the top of the semiconductor column and surrounds the side wall of the semiconductor column part on one side of the top of the semiconductor column; forming a gate structure surrounding a portion of the sidewall of the semiconductor pillar and exposing the drain doped layer; and after the grid structure is formed, forming a drain plug at the top of the drain doping layer, wherein the drain plug is electrically connected with the drain doping layer.
Compared with the drain doped layer only formed at the top of the semiconductor column, the embodiment of the invention enlarges the width of the drain doped layer, which correspondingly enlarges the top surface area of the drain doped layer, thereby enlarging a process window for forming a drain plug, easily forming the drain plug at the top of the drain doped layer, improving the electric connection effect of the drain plug and the drain doped layer, and further improving the performance of the VGAA transistor, for example: the contact resistance between the drain doped layer and the drain plug is reduced.
In order that the above objects, features and advantages of the invention will be readily understood, a more particular description of the invention will be rendered by reference to specific embodiments thereof which are illustrated in the appended drawings.
Fig. 2 to 11 are schematic structural views corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention.
Referring to fig. 2, a substrate 100 is provided.
The substrate 100 is used to provide a process platform for subsequent formation of VGAA transistors.
In this embodiment, the substrate 100 is a silicon substrate. In other embodiments, the substrate may also be made of other materials such as germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, and the substrate may also be made of other types of substrates such as silicon on insulator substrates or germanium on insulator substrates.
With continued reference to fig. 2, a source doped layer 110 is formed on the substrate 100.
The source doped layer 110 serves as the source of the VGAA transistor.
In this embodiment, a selective epitaxial growth process is used to form the first epitaxial layer, and ions are self-doped in situ during the process of forming the first epitaxial layer, so as to form the source doped layer 110.
In this embodiment, the semiconductor structure formed is a PMOS (positive channel metal oxide semiconductor) transistor, and the material of the source doped layer 110 is silicon germanium doped with P-type ions, i.e. the material of the first epitaxial layer is silicon germanium. The first epitaxial layer is used for providing a compressive stress effect for a channel region of the PMOS transistor, so that the carrier mobility of the PMOS transistor is improved. Wherein the P-type ions comprise B, ga or In.
In other embodiments, the semiconductor structure may also be a NMOS (negative channel metal oxide semiconductor) transistor, and the material of the source doped layer is silicon carbide or silicon phosphide doped with N-type ions, i.e. the material of the first epitaxial layer is silicon carbide or silicon phosphide, respectively. The first epitaxial layer is used for providing a tensile stress effect for a channel region of the NMOS transistor, so that the carrier mobility of the NMOS transistor is improved. Wherein the N-type ions comprise P, as or Sb.
With continued reference to fig. 2, a semiconductor pillar 120 is formed on the source doped layer 110.
The semiconductor pillars 120 are used to provide channels for transistors.
In this embodiment, the material of the semiconductor pillar 120 is silicon. In other embodiments, the material of the semiconductor pillar may be germanium, silicon carbide, gallium arsenide, or indium gallium arsenide.
Specifically, the step of forming the semiconductor pillars 120 includes: after forming the source doping layer 110, a semiconductor material layer (not shown in the drawing) is formed on the source doping layer 110; forming a mask layer 130 on the semiconductor material layer; and etching the semiconductor material layer by taking the mask layer 130 as a mask to form the semiconductor column 120.
In this embodiment, a semiconductor material layer is formed on the source doping layer 110 using a selective epitaxial growth method.
In this embodiment, the mask layer 130 is a hard mask layer, and the material of the mask layer 130 is silicon nitride.
It should be noted that the height (not shown) of the semiconductor pillars 120 is not too small or too large. In the step of forming the drain doped layer later, the drain doped layer surrounds a part of the side wall of the semiconductor column near the top, if the height of the semiconductor column 120 is too small, in order to enable the height of the semiconductor column surrounded by the drain doped layer to meet the process requirement, the gate structure on the side wall of the subsequent semiconductor column 120 is correspondingly too short, so that the control capability of the gate structure on a channel is easily reduced, and the channel region formed later is also too short, and short channel effect is easily generated; if the height of the semiconductor pillars 120 is too large, the semiconductor pillars 120 are prone to collapse, and the process difficulty of forming the semiconductor pillars 120 is also increased. For this purpose, in the present embodiment, the height (not labeled) of the semiconductor pillars 120 is 30nm to 200nm.
Referring to fig. 3 to 4 in combination, a protective layer 140 (as shown in fig. 4) is formed on the source doping layer 110 exposed from the semiconductor pillar 120, the protective layer 140 covering a portion of the sidewalls of the semiconductor pillar 120.
The protection layer 140 exposes the top and part of the sidewall of the semiconductor pillar 120, and the protection layer 140 is used to define the formation location of the subsequent drain doped layer on the semiconductor pillar 120.
Specifically, the step of forming the protective layer 140 includes: forming a protective material layer 145 (shown in fig. 3) on the source doping layer 110 exposed from the semiconductor pillars 120; a part of the protective material layer 145 is etched back to expose a part of the sidewall of the semiconductor pillar 120, and the remaining protective material layer 145 is used as the protective layer 140.
In this embodiment, after forming the protective material layer 145 in order to improve the surface flatness of the protective layer 140, before etching back the protective material layer 145 with a partial thickness, the method further includes: and taking the top of the mask layer 130 as a stop position, and carrying out planarization treatment on the protective material layer 145.
In this embodiment, the protection layer 140 is made of a dielectric material, and the formation of the protection layer 140 is also used to prepare for the subsequent formation of the isolation layer.
By selecting the dielectric material, the step of forming a film layer for protecting a portion of the sidewall of the semiconductor pillar 120 is omitted, the modification to the existing process is small, the process compatibility is high, and the process cost and the process time are saved.
Thus, the material of the protective layer 140 includes one or more of silicon oxide, silicon nitride, silicon carbonitride oxide, silicon oxynitride, boron nitride, and boron carbonitride. In this embodiment, the material of the protection layer 140 is silicon oxide.
In this embodiment, the protective material layer 145 is formed by a flowable chemical vapor deposition (flowable chemical vapor deposition, FCVD) process. The flowable chemical vapor deposition process has good filling capability, which is beneficial to reducing the probability of forming defects such as cavities in the protective material layer 145, and correspondingly improving the film forming quality of the protective material layer 145, thereby improving the quality of the protective layer 140.
In this embodiment, the material of the protection layer 140 is silicon oxide. Silicon oxide is a dielectric material with common process and lower cost, and has higher process compatibility; in addition, the silicon oxide has smaller dielectric constant, which is beneficial to improving the electric isolation effect of the subsequent isolation layer.
In this embodiment, after forming the protective layer 140, the method further includes: the mask layer 130 is removed.
The mask layer 130 is removed to expose the top of the semiconductor pillars 120 for preparation for subsequent formation of a drain doped layer.
Moreover, the mask layer 130 protects the top of the semiconductor pillars 120 during the formation of the protective layer 140 by removing the mask layer 130 after the formation of the protective layer 140.
Referring to fig. 5, a drain doping layer 150 covering the top of the semiconductor pillar 120 and surrounding a portion of the sidewall of the semiconductor pillar 120 is formed on the top side of the semiconductor pillar 120.
The drain doped layer 150 serves as the drain of the VGAA transistor.
In this embodiment, the drain doped layer 150 covers the top of the semiconductor pillar 120 and surrounds the drain doped layer 150 on a portion of the sidewall of the semiconductor pillar 120, and compared with a drain doped layer formed only on the top of the semiconductor pillar, the width of the drain doped layer 150 is increased in this embodiment, which correspondingly increases the top surface area of the drain doped layer 150, thereby increasing the subsequent process window for forming the drain plug, facilitating the formation of the drain plug on the top of the drain doped layer 150, and improving the electrical connection effect between the drain plug and the drain doped layer 150, thereby improving the performance of the VGAA transistor, for example: the contact resistance between the drain doped layer 150 and the drain plug is reduced.
In this embodiment, in the step of forming the drain doped layer 150, the drain doped layer 150 covers the semiconductor pillar 120 exposed by the protection layer 140.
Specifically, the second epitaxial layer is formed by a selective epitaxial growth process, and ions are self-doped in situ during the formation of the second epitaxial layer, forming the drain doped layer 150.
By selecting a selective epitaxial growth process, the drain doped layer 150 is formed only on the surface of the semiconductor pillar 120 exposed by the protective layer 140, so that the complexity of the process for forming the drain doped layer 150 is reduced, and the formation quality of the drain doped layer 150 is improved.
In this embodiment, taking the formed semiconductor structure as a PMOS transistor as an example, P-type ions are doped in the second epitaxial layer, and the material of the second epitaxial layer is silicon germanium. In other embodiments, when the semiconductor structure is an NMOS transistor, N-type ions are doped in the second epitaxial layer, and the material of the second epitaxial layer is silicon carbide or silicon phosphide.
For a specific description of the drain doped layer 150, reference may be made to the foregoing corresponding description of the source doped layer 110, which is not repeated herein.
The thickness T1 of the leaky doped layer 150 is not too small nor too large. If the thickness T1 of the drain doped layer 150 is too small, the width of the drain doped layer 150 increases too little, which is not beneficial to increasing the process window for forming the drain plug, and is correspondingly not beneficial to improving the electrical connection effect between the drain plug and the drain doped layer 150; if the thickness T1 of the drain doped layer 150 is too large, bridging of adjacent drain doped layers 150 is easily caused. For this reason, in this embodiment, the thickness T1 of the leaky doped layer 150 is 2nm to 5nm.
The height H of the semiconductor pillar 120 surrounded by the drain doped layer 150 is preferably not too small or too large. If the height H is too small, the difficulty in controlling the height H is easily increased, which correspondingly increases the difficulty in etching back the partial thickness protection material layer 145; if the height H is too large, the gate structure on the sidewall of the subsequent semiconductor pillar 120 is too short under the condition that the height of the semiconductor pillar 120 is certain, so that the control capability of the gate structure on the channel is easily reduced, and the channel region formed subsequently is also too short, which is easy to generate a short channel effect. For this reason, in this embodiment, the height H of the semiconductor pillar 120 surrounded by the drain doped layer 150 is 2nm to 6nm.
Referring to fig. 6, after the formation of the drain doped layer 150, the forming method further includes: and etching back a part of the protective layer 140 (as shown in fig. 5), exposing a part of the sidewall of the semiconductor pillar 120, and using the remaining protective layer 140 as an isolation layer 160.
The spacer 160 is used to electrically isolate the subsequently formed gate structure from the source doped layer 160 by exposing a portion of the sidewall of the semiconductor pillar 120 to provide for the formation of the subsequently formed gate structure.
In this embodiment, the isolation layer 160 is formed by etching back the protection layer 140. By performing the etching back process twice on the protective material layer 145 (as shown in fig. 3), the protective layer 140 and the isolation layer 160 are obtained, so that the protective layer 140 and the isolation layer 160 respectively play respective roles in different steps, which simplifies the process complexity of forming the semiconductor structure and reduces the process cost.
In this embodiment, a dry etching process is used to etch back a portion of the protective layer 140. The dry etching process has an anisotropic etching characteristic, and by selecting the dry etching process, the surface flatness of the isolation layer 160 is easily improved, and the etching amount of the protection layer 140 is easily controlled.
It should be noted that the thickness T2 of the isolation layer 160 is not too small or too large. If the thickness T2 of the isolation layer 160 is too small, it is easy to reduce the electrical isolation effect of the isolation layer 160 on the gate structure and the source doping layer 160; if the thickness T2 of the isolation layer 160 is too large, the heights of the semiconductor pillars 120 exposed by the drain doped layer 150 and the isolation layer 160 are too small, and if the height H (as shown in fig. 5) of the semiconductor pillar 120 surrounded by the drain doped layer 150 is to be ensured to meet the process requirement, the gate structure on the sidewall of the subsequent semiconductor pillar 120 is correspondingly too short, which may easily result in a decrease in the control capability of the gate structure on the channel, and may also result in an excessively short channel region formed subsequently, which may easily generate a short channel effect. For this purpose, in the present embodiment, the thickness T2 of the isolation layer 160 is 2nm to 10nm.
Referring to fig. 7 to 10 in combination, a gate structure 300 (shown in fig. 10) is formed surrounding a portion of the sidewalls of the semiconductor pillars 120 and exposing the drain doped layer 150.
The gate structure 300 is used to control the turning on and off of the channel region of the transistor.
In this embodiment, the gate structure 300 is a metal gate structure, and the gate structure 300 includes a work function layer 310 (shown in fig. 10) surrounding a portion of the sidewall of the semiconductor pillar 120 and a gate layer 320 (shown in fig. 10) covering the work function layer 310.
In this embodiment, taking the formed semiconductor structure as a PMOS transistor as an example, the material of the work function layer 310 is a P-type work function material, and the material of the work function layer 310 includes one or more of TiN, taN, taSiN, taAlN and TiAlN.
In other embodiments, when the semiconductor structure formed is an NMOS transistor, the material of the work function layer is an N-type work function material, and the material of the work function layer includes one or more of TiAl, mo, moN, alN and TiAlC.
In this embodiment, the material of the gate layer 320 is Al. In other embodiments, the material of the gate layer may also be W, cu, ag, au, pt, ni or Ti, etc.
In this embodiment, after the gate structure 300 is formed, the top of the gate structure 300 is lower than the bottom of the drain doped layer 150, so that the gate structure 300 is isolated from the drain doped layer 150, thereby reducing the probability of bridging between the gate structure 300 and the drain doped layer 150.
It should be noted that the distance (not shown) from the top of the gate structure 300 to the bottom of the drain doped layer 150 should not be too small or too large. If the distance is too small, the probability of bridging between the gate structure 300 and the drain doped layer 150 is correspondingly increased; if the distance is too large, the gate structure 300 is too short, which may easily result in a decrease in the control capability of the gate structure 300 on the channel, and may also result in an excessively short channel region formed later, which may easily generate a short channel effect. For this reason, in this embodiment, the distance from the top of the gate structure 300 to the bottom of the drain doped layer 150 is 3nm to 5nm.
The steps for forming the gate structure 300 are described in detail below with reference to the accompanying drawings.
Referring to fig. 7, a gate material layer 305 is formed conformally covering the semiconductor pillars 120, the gate material layer 305 also extending onto a portion of the source doped layer 160 on one side of the semiconductor pillars 120.
In this embodiment, the gate material layer 305 includes a work function material layer 315 and a gate material layer 325 on the work function material layer 315.
The work function material layer 315 provides for a subsequent formation of a work function layer and the gate material layer 325 provides for a subsequent formation of a gate layer.
In this embodiment, the gate material layer 305 is formed by a deposition process and an etching process that are sequentially performed, so that a portion of the source doped layer 160 is exposed by the gate material layer 305.
Specifically, the deposition process is an atomic layer deposition process.
Referring to fig. 8 to 9 in combination, an interlayer dielectric layer 170 is formed on the source doped layer 110 (as shown in fig. 9), the interlayer dielectric layer 170 covers a portion of the sidewalls of the semiconductor pillars 120, and the top of the interlayer dielectric layer 170 is lower than the bottom of the drain doped layer 150.
The interlayer dielectric layer 170 provides for subsequent removal of the gate material layer 305 exposed by the interlayer dielectric layer 170.
In addition, the interlayer dielectric layer 170 is used to achieve electrical isolation between adjacent devices.
Therefore, the interlayer dielectric layer 170 is made of an insulating material. In this embodiment, the material of the interlayer dielectric layer 170 is silicon oxide. In other embodiments, the material of the interlayer dielectric layer may be another insulating material such as silicon nitride or silicon oxynitride.
Specifically, the step of forming the interlayer dielectric layer 170 includes: forming an interlayer dielectric material layer 175 (shown in fig. 8) covering the gate material layer 305; and etching back a part of the interlayer dielectric material layer 175 to form an interlayer dielectric layer 170 covering a part of the side wall of the gate material layer 30.
In this embodiment, a dry etching process is used to etch back a portion of the interlayer dielectric material layer 175. The dry etching process has the characteristic of anisotropic etching, and the top surface position of the interlayer dielectric layer 170 is easy to control by selecting the dry etching process.
In this embodiment, the top of the interlayer dielectric layer 170 is lower than the bottom of the drain doped layer 150, so that the gate structure formed later is isolated from the drain doped layer 150.
Specifically, the distance from the top of the interlayer dielectric layer 170 to the bottom of the leaky doped layer 150 is 3nm to 5nm.
Referring to fig. 10, the gate material layer 305 (as shown in fig. 9) exposed by the interlayer dielectric layer 170 is removed, so as to form a gate structure 300.
In this embodiment, a dry etching process is used to remove the gate material layer 305 exposed by the interlayer dielectric layer 170. The dry etching process is advantageous in precisely controlling the removal amount of the gate material layer 305 and reducing damage to other film layers.
With continued reference to fig. 7, it should be noted that the method for forming the semiconductor structure further includes: after forming the isolation layer 160, a gate dielectric layer 200 conformally covering the semiconductor pillars 120 and the drain doped layer 150 is formed prior to forming the gate material layer 305.
The gate dielectric layer 200 is used to electrically isolate the subsequent gate structure from the semiconductor pillar 120.
The gate structure formed subsequently is a metal gate structure, and thus the material of the gate dielectric layer 200 includes HfO 2 、ZrO 2 HfSiO, hfSiON, hfTaO, hfTiO, hfZrO and Al 2 O 3 One or more of them. In this embodiment, the gate dielectric layer 200 is made of HfO 2 。
In other embodiments, when the gate structure is a polysilicon gate structure, the material of the gate dielectric layer includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride oxide, and amorphous carbon, respectively.
In this embodiment, the gate dielectric layer 200 is formed by an atomic layer deposition process. In other embodiments, the gate dielectric layer may also be formed by a chemical vapor deposition process.
Thus, with continued reference to fig. 10, after the gate structure 300 is formed, the gate structure 300 exposes the gate dielectric layer 200 on the surface of the drain doped layer 150.
In this embodiment, the gate dielectric layer 200 on the surface of the drain doped layer 150 is reserved, so that the gate dielectric layer 200 protects the drain doped layer 150, thereby better realizing the isolation between the drain doped layer 150 and the gate structure 300.
Referring to fig. 11, after the gate structure 300 is formed, the method for forming a semiconductor structure further includes: a top dielectric layer 180 is formed overlying the interlayer dielectric layer 170 and the drain doped layer 150.
The top dielectric layer 180 is used to provide a process platform for the subsequent formation of conductive plugs. In addition, the top dielectric layer 180 also serves to achieve electrical isolation between adjacent transistors.
For this purpose, in this embodiment, the material of the top dielectric layer 180 is silicon oxide. In other embodiments, the material of the top dielectric layer may be silicon nitride or silicon oxynitride, or other insulating materials.
Specifically, the top dielectric layer 180 covers the interlayer dielectric layer 170 and the gate dielectric layer 200.
With continued reference to fig. 11, a drain plug 191 is formed on top of the drain doped layer 150, the drain plug 191 electrically connecting the drain doped layer 150.
The drain plug 191 is used to electrically connect the drain doped layer 150 to an external circuit.
Specifically, the step of forming the drain plug 191 includes: etching the top dielectric layer 180 and the gate dielectric layer 200, and forming a through hole exposing the drain doped layer 150 in the top dielectric layer 180 and the gate dielectric layer 200; the conductive material in the via hole is filled as a drain plug 191.
Wherein the drain doped layer 150 covers the top of the semiconductor pillar 120 and surrounds the drain doped layer 150 of a portion of the sidewall of the semiconductor pillar 120, which increases the process window for forming the via, which tends to expose the drain doped layer 150.
In this embodiment, the drain plug 191 is made of W. In other embodiments, the drain plug may also be made of Al, cu, ag, au, or the like.
In this embodiment, the forming method further includes: a gate plug 192 connected to the gate structure 300 and a source plug 193 electrically connected to the source doping layer 110 are formed.
The gate plug 192 is used to electrically connect the gate structure 300 to an external circuit, and the source plug 193 is used to electrically connect the source doped layer 110 to an external circuit.
Specifically, the source plug 193 is formed in the top dielectric layer 180 and the interlayer dielectric layer 170 on one side of the semiconductor pillar 120 and is connected to the source doped layer 110 on the isolation layer 160; the gate plug 192 is formed in the top dielectric layer 180, the interlayer dielectric layer 170 and the isolation layer 160 on the other side of the semiconductor pillar 120.
The gate plug 192 and the source plug 193 may be formed in the same step, and the forming method of the gate plug 192 and the source plug 193 is similar to that of the drain plug 191, which is not described herein.
Correspondingly, the invention further provides a semiconductor structure. Referring to fig. 11, a schematic structure diagram of an embodiment of the semiconductor structure of the present invention is shown.
The semiconductor structure includes: a substrate 100; a source doped layer 110 on the substrate 100; a semiconductor pillar 120 located on the source doped layer 110; a drain doping layer 150 located at a top side of the semiconductor pillar 120, the drain doping layer 150 covering the top of the semiconductor pillar 120 and surrounding a portion of the sidewall of the semiconductor pillar 120; a gate structure 300 surrounding a portion of the sidewalls of the semiconductor pillar 120 and exposing the drain doped layer 150; a drain plug 191 is positioned on top of the drain doped layer 150 and electrically connected to the drain doped layer 150.
The substrate 100 is used to provide a process platform for forming VGAA transistors.
In this embodiment, the substrate 100 is a silicon substrate. In other embodiments, the substrate may also be made of other materials such as germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, and the substrate may also be made of other types of substrates such as silicon on insulator substrates or germanium on insulator substrates.
The semiconductor pillars 120 are used to provide channels for transistors.
In this embodiment, the material of the semiconductor pillar 120 is silicon. In other embodiments, the material of the semiconductor pillar may be germanium, silicon carbide, gallium arsenide, or indium gallium arsenide.
It should be noted that the height (not shown) of the semiconductor pillars 120 is not too small or too large. If the height H (as shown in fig. 5) of the semiconductor column 120 surrounded by the drain doped layer 150 is too small, the gate structure 300 on the sidewall of the semiconductor column 120 is too short, which easily causes the decrease of the control capability of the gate structure 300 on the channel, and also causes the excessively short channel region to generate a short channel effect; if the height of the semiconductor pillars 120 is too large, the semiconductor pillars 120 are prone to collapse, and the process difficulty of forming the semiconductor pillars 120 is also increased. For this purpose, in the present embodiment, the height (not labeled) of the semiconductor pillars 120 is 30nm to 200nm.
The source doped layer 110 serves as the source of the VGAA transistor and the drain doped layer 150 serves as the drain of the VGAA transistor.
The source doped layer 110 and the drain doped layer 150 are used to provide stress to the channel during operation of the semiconductor structure, thereby improving the carrier mobility of the transistor.
In this embodiment, the source doped layer 110 includes a first epitaxial layer doped with conductive ions, and the drain doped layer 150 includes a second epitaxial layer doped with conductive ions.
In this embodiment, taking the semiconductor structure as a PMOS transistor as an example, the conductive ions are P-type ions, the materials of the first epitaxial layer and the second epitaxial layer are silicon germanium, and the first epitaxial layer and the second epitaxial layer are used for providing a compressive stress effect for a channel region of the PMOS transistor. Wherein the P-type ions comprise B, ga or In.
In other embodiments, when the semiconductor structure is an NMOS transistor, the conductive ions are N-type ions, the material of the first epitaxial layer is silicon carbide or silicon phosphide, the material of the second epitaxial layer is silicon carbide or silicon phosphide, and the first epitaxial layer and the second epitaxial layer are used for providing a tensile stress effect to a channel region of the NMOS transistor. Wherein the N-type ions comprise P, as or Sb.
In this embodiment, the drain doped layer 150 covers the top of the semiconductor pillar 120 and surrounds the drain doped layer 150 on a portion of the sidewall of the semiconductor pillar 120, and compared with a drain doped layer formed only on the top of the semiconductor pillar, the width of the drain doped layer 150 is increased, which correspondingly increases the top surface area of the drain doped layer 150, thereby increasing the process window for forming the drain plug 191, facilitating the formation of the drain plug 191 on the top of the drain doped layer 150, and improving the electrical connection effect between the drain plug 191 and the drain doped layer 150, thereby improving the performance of the VGAA transistor, for example: the contact resistance between the drain doped layer 150 and the drain plug 191 is reduced.
The thickness T1 (shown in fig. 5) of the leaky doped layer 150 is not too small or too large. If the thickness T1 of the drain doped layer 150 is too small, the width of the drain doped layer 150 increases too little, which is not beneficial to increasing the process window for forming the drain plug, and is correspondingly not beneficial to improving the electrical connection effect between the drain plug 191 and the drain doped layer 150; if the thickness T1 of the drain doped layer 150 is too large, bridging of adjacent drain doped layers 150 is easily caused. For this reason, in this embodiment, the thickness T1 of the leaky doped layer 150 is 2nm to 5nm.
The height H (shown in fig. 5) of the semiconductor pillar 120 surrounded by the drain doped layer 150 is not too small or too large. If the height H is too small, the difficulty in controlling the height H is easily increased; if the height H is too large, the gate structure 300 on the sidewall of the semiconductor pillar 120 is too short under the condition that the height of the semiconductor pillar 120 is certain, so that the control capability of the gate structure 300 on the channel is easily reduced, and the channel region of the transistor is also too short, which is easy to generate a short channel effect. For this reason, in this embodiment, the height H of the semiconductor pillar 120 surrounded by the drain doped layer 150 is 2nm to 6nm.
The gate structure 300 is used to control the turning on and off of the channel region of the transistor.
In this embodiment, the gate structure 300 is a metal gate structure, and the gate structure 300 includes a work function layer 310 surrounding a portion of the sidewall of the semiconductor pillar 120 and a gate layer 320 covering the work function layer 310.
It should be noted that the gate layer 320 also extends onto a portion of the source doped layer 160 on one side of the semiconductor pillar 120, thereby providing a process basis for forming a gate plug electrically connected to the gate layer 320.
In this embodiment, taking the semiconductor structure as a PMOS transistor as an example, the material of the work function layer 310 is a P-type work function material, and the material of the work function layer 310 includes one or more of TiN, taN, taSiN, taAlN and TiAlN.
In other embodiments, when the semiconductor structure is an NMOS transistor, the material of the work function layer is an N-type work function material, and the material of the work function layer includes one or more of TiAl, mo, moN, alN and TiAlC.
In this embodiment, the material of the gate layer 320 is Al. In other embodiments, the material of the gate layer may also be W, cu, ag, au, pt, ni or Ti, etc.
In this embodiment, the top of the gate structure 300 is lower than the bottom of the drain doped layer 150, so that the gate structure 300 is isolated from the drain doped layer 150, thereby reducing the probability of bridging between the gate structure 300 and the drain doped layer 150.
It should be noted that the distance (not shown) from the top of the gate structure 300 to the bottom of the drain doped layer 150 should not be too small or too large. If the distance is too small, the probability of bridging between the gate structure 300 and the drain doped layer 150 is correspondingly increased; if the distance is too large, the gate structure 300 is too short, which may easily result in a decrease in the control capability of the gate structure 300 on the channel, and may also result in an excessively short channel region formed later, which may easily generate a short channel effect. For this reason, in this embodiment, the distance from the top of the gate structure 300 to the bottom of the drain doped layer 150 is 3nm to 5nm.
In this embodiment, the semiconductor structure further includes: the gate dielectric layer 200 is located between the semiconductor pillar 120 and the gate structure 300, and conformally covers the top and sidewalls of the drain doped layer 150 exposed by the gate structure 300.
The gate dielectric layer 200 is used to electrically isolate the gate structure 300 from the semiconductor pillars 120.
The gate structure 300 is a metal gate structure, and thus the material of the gate dielectric layer 200 includes HfO 2 、ZrO 2 HfSiO, hfSiON, hfTaO, hfTiO, hfZrO and Al 2 O 3 One or more of them. In this embodiment, the gate dielectric layer 200 is made of HfO 2 。
In other embodiments, when the gate structure is a polysilicon gate structure, the material of the gate dielectric layer includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride oxide, and amorphous carbon, respectively.
In this embodiment, the gate dielectric layer 200 conformally covers the top and the sidewall of the drain doped layer 150 exposed by the gate structure 300, and the gate dielectric layer 200 protects the drain doped layer 150, thereby isolating the drain doped layer 150 from the gate structure 300.
In this embodiment, the semiconductor structure further includes: an isolation layer 160 between the gate structure 300 and the source doping layer 110, the isolation layer 160 covering a portion of the sidewalls of the semiconductor pillars 120.
The isolation layer 160 is used to electrically isolate the gate structure 300 from the source doped layer 160.
Therefore, the material of the isolation layer 160 is an insulating material. Specifically, the material of the isolation layer 160 includes one or more of silicon oxide, silicon nitride, silicon carbonitride oxide, silicon oxynitride, boron nitride, and boron carbonitride. In this embodiment, the material of the isolation layer 160 is silicon oxide.
In this embodiment, the isolation layer 160 further covers the source doped layer 110 exposed by the semiconductor pillar 120.
It should be noted that the thickness T2 (as shown in fig. 6) of the isolation layer 160 is not too small or too large. If the thickness T2 of the isolation layer 160 is too small, the electrical isolation effect of the isolation layer 160 on the gate structure 300 and the source doped layer 160 is easily reduced, and the probability of bridging between the gate structure 300 and the source doped layer 160 is high; if the thickness T2 of the isolation layer 160 is too large, the heights of the semiconductor pillars 120 exposed by the drain doped layer 150 and the isolation layer 160 are too small, and if the height H of the semiconductor pillars 120 surrounded by the drain doped layer 150 is required to meet the process requirement, the gate structure 300 on the sidewall of the semiconductor pillars 120 is correspondingly too short, which easily results in a decrease in the control capability of the gate structure 300 on the channel, and also results in an excessively short channel region formed subsequently, which easily results in a short channel effect. For this purpose, in the present embodiment, the thickness T2 of the isolation layer 160 is 2nm to 10nm.
In this embodiment, the semiconductor structure further includes: the interlayer dielectric layer 170 covers the sidewalls of the gate structure 300 and exposes the top of the gate structure 300.
The interlayer dielectric layer 170 is used to electrically isolate adjacent devices.
Therefore, the interlayer dielectric layer 170 is made of an insulating material. In this embodiment, the material of the interlayer dielectric layer 170 is silicon oxide. In other embodiments, the material of the interlayer dielectric layer may be another insulating material such as silicon nitride or silicon oxynitride.
In this embodiment, the semiconductor structure further includes: a top dielectric layer 180 overlying the interlayer dielectric layer 170 and the drain doped layer 150.
The top dielectric layer 180 is used to provide a process platform for the formation of conductive plugs. In addition, the top dielectric layer 180 also serves to achieve electrical isolation between adjacent transistors.
For this purpose, in this embodiment, the material of the top dielectric layer 180 is silicon oxide. In other embodiments, the material of the top dielectric layer may be silicon nitride or silicon oxynitride, or other insulating materials.
Specifically, the top dielectric layer 180 covers the interlayer dielectric layer 170 and the gate dielectric layer 200.
The drain plug 191 is used to electrically connect the drain doped layer 150 to an external circuit.
In this embodiment, the drain plug 191 penetrates the top dielectric layer 180 and the gate dielectric layer 200 on top of the drain doped layer 150.
Wherein the process of forming the drain plug 191 generally includes a step of forming a via hole and a step of filling the via hole, the drain doped layer 150 covers the top of the semiconductor pillar 120 and surrounds the drain doped layer 150 of a portion of the sidewall of the semiconductor pillar 120, which increases a process window for forming the via hole, and facilitates exposing the via hole to the drain doped layer 150.
In this embodiment, the drain plug 191 is made of W. In other embodiments, the drain plug may also be made of Al, cu, ag, au, or the like.
In this embodiment, the semiconductor structure further includes: a gate plug 192 connected to the gate structure 300, and a source plug 193 electrically connected to the source doping layer 110.
The gate plug 192 is used to electrically connect the gate structure 300 to an external circuit, and the source plug 193 is used to electrically connect the source doped layer 110 to an external circuit.
Specifically, the source plug 193 is located in the top dielectric layer 180 and the interlayer dielectric layer 170 on the side of the semiconductor pillar 120 and is connected to the source doped layer 110 located on the isolation layer 160; the gate plug 192 is located in the top dielectric layer 180, the interlayer dielectric layer 170 and the isolation layer 160 on the other side of the semiconductor pillar 120.
In this embodiment, for the specific description of the gate plug 192 and the source plug 193, reference may be made to the corresponding description of the drain plug 191, which is not repeated here.
The semiconductor structure may be formed by the forming method described in the foregoing embodiments, or may be formed by other forming methods. For a specific description of the semiconductor structure in this embodiment, reference may be made to the corresponding description in the foregoing embodiment, which is not repeated here.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.
Claims (17)
1. A method of forming a semiconductor structure, comprising:
providing a substrate;
forming a source doping layer on the substrate;
forming a semiconductor column on the source doped layer;
forming a drain doping layer which covers the top of the semiconductor column and surrounds the side wall of the semiconductor column part on one side of the top of the semiconductor column;
forming a gate dielectric layer which conformally covers the semiconductor column and the drain doping layer;
Forming a gate structure which surrounds part of the side wall of the semiconductor column and exposes the gate dielectric layer positioned on the surface of the drain doping layer;
and after the grid structure is formed, forming a drain plug at the top of the drain doping layer, wherein the drain plug is positioned in the grid dielectric layer and is electrically connected with the drain doping layer.
2. The method of forming a semiconductor structure of claim 1, wherein in the step of forming the drain doped layer, the drain doped layer surrounds a semiconductor pillar having a height of 2nm to 6nm.
3. The method of forming a semiconductor structure of claim 1, wherein in the step of forming the drain doped layer, a thickness of the drain doped layer is 2nm to 5nm.
4. The method of forming a semiconductor structure of claim 1, wherein the drain doped layer is formed by a selective epitaxial process.
5. The method of forming a semiconductor structure of claim 1, wherein after forming the semiconductor pillars, prior to forming the drain doped layer, further comprising: forming a protective layer on the source doping layer exposed by the semiconductor column, wherein the protective layer covers part of the side wall of the semiconductor column;
In the step of forming the drain doped layer, the drain doped layer covers the semiconductor column exposed by the protective layer.
6. The method of forming a semiconductor structure of claim 5, wherein the step of forming the protective layer comprises:
forming a protective material layer on the source doping layer exposed by the semiconductor column;
and etching back a part of the protective material layer with the thickness to expose part of the side wall of the semiconductor column, and taking the rest of the protective material layer as the protective layer.
7. The method of forming a semiconductor structure of claim 5, wherein the material of the protective layer is a dielectric material;
after forming the drain doped layer, before forming the gate structure, the method further comprises: and etching back part of the protective layer with the thickness, exposing part of the side wall of the semiconductor column, and taking the rest of the protective layer as an isolation layer.
8. The method of forming a semiconductor structure of claim 1, wherein after forming said gate structure, a top portion of said gate structure is lower than a bottom portion of said drain doped layer.
9. The method of forming a semiconductor structure of claim 8, wherein a distance from a top of the gate structure to a bottom of the drain doped layer is 3nm to 5nm.
10. The method of forming a semiconductor structure of claim 1, wherein the step of forming the gate structure comprises:
forming a gate material layer conformally covering the semiconductor column, wherein the gate material layer also extends to part of the source doping layer on one side of the semiconductor column;
forming an interlayer dielectric layer on the source doped layer, wherein the interlayer dielectric layer covers part of the side wall of the semiconductor column, and the top of the interlayer dielectric layer is lower than the bottom of the drain doped layer;
and removing the gate material layer exposed from the interlayer dielectric layer to form the gate structure.
11. A semiconductor structure, comprising:
a substrate;
a source doped layer located on the substrate;
a semiconductor pillar located on the source doped layer;
the leakage doping layer is positioned on one side of the top of the semiconductor column, covers the top of the semiconductor column and surrounds part of the side wall of the semiconductor column;
a gate structure surrounding a portion of the sidewall of the semiconductor pillar and exposing the drain doped layer;
the gate dielectric layer is positioned between the semiconductor column and the gate structure and conformally covers the top and the side wall of the drain doping layer exposed by the gate structure;
The drain plug is positioned at the top of the drain doping layer, penetrates through the gate dielectric layer at the top of the drain doping layer and is electrically connected with the drain doping layer.
12. The semiconductor structure of claim 11, wherein the drain doped layer surrounds a semiconductor pillar having a height of 2nm to 6nm.
13. The semiconductor structure of claim 11, wherein the thickness of the leaky doped layer is from 2nm to 5nm.
14. The semiconductor structure of claim 11, wherein the drain doped layer comprises an epitaxial layer doped with conductive ions.
15. The semiconductor structure of claim 11, wherein the semiconductor structure further comprises: and the isolation layer is positioned between the gate structure and the source doping layer and covers part of the side wall of the semiconductor column.
16. The semiconductor structure of claim 11, wherein a top of the gate structure is lower than a bottom of the drain doped layer.
17. The semiconductor structure of claim 16, wherein a distance from a top of the gate structure to a bottom of the drain doped layer is 3nm to 5nm.
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| CN101877317A (en) * | 2009-04-29 | 2010-11-03 | 台湾积体电路制造股份有限公司 | Non-planar transistors and methods of fabrication thereof |
| US9960271B1 (en) * | 2017-04-18 | 2018-05-01 | Globalfoundries Inc. | Method of forming vertical field effect transistors with different threshold voltages and the resulting integrated circuit structure |
| US10229986B1 (en) * | 2017-12-04 | 2019-03-12 | International Business Machines Corporation | Vertical transport field-effect transistor including dual layer top spacer |
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