CN117410333A - Semiconductor structure and forming method thereof - Google Patents

Semiconductor structure and forming method thereof Download PDF

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Publication number
CN117410333A
CN117410333A CN202210794118.0A CN202210794118A CN117410333A CN 117410333 A CN117410333 A CN 117410333A CN 202210794118 A CN202210794118 A CN 202210794118A CN 117410333 A CN117410333 A CN 117410333A
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Prior art keywords
layer
channel
substrate
gate structure
side wall
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贺晓东
卜伟海
汪涵
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North Ic Technology Innovation Center Beijing Co ltd
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North Ic Technology Innovation Center Beijing Co ltd
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Priority to CN202210794118.0A priority Critical patent/CN117410333A/en
Publication of CN117410333A publication Critical patent/CN117410333A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28247—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon passivation or protection of the electrode, e.g. using re-oxidation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823821—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823864—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
    • H—ELECTRICITY
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    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0924—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

A semiconductor structure and a method for forming the same, the method for forming the same includes: providing a substrate, wherein a laminated structure is formed on the substrate, the laminated structure comprises one or more stacked channel laminated layers, the channel laminated layers comprise a sacrificial layer and a channel layer positioned on the sacrificial layer, a pseudo gate structure crossing the laminated structure is also formed on the substrate, and the pseudo gate structure covers the side wall and the top of the laminated structure; removing part of the sacrificial layer with the width along the direction perpendicular to the side wall of the pseudo gate structure to form a groove surrounded by the channel layer and the residual sacrificial layer; performing filling treatment for multiple times to form an inner side wall in the groove; wherein the filling process comprises: forming an inner side wall material layer covering the pseudo gate structure, the laminated structure and the substrate, wherein the inner side wall material layer is also positioned in the groove; removing the inner side wall material layer covering the pseudo gate structure, the side wall of the channel layer and the top of the substrate, and reserving the inner side wall material layer in the groove as a sub-inner side wall; the inner side walls are formed by overlapping multiple layers of sub inner side walls. The invention is beneficial to improving the working performance of the semiconductor structure.

Description

Semiconductor structure and forming method thereof
Technical Field
Embodiments of the present disclosure relate to semiconductor manufacturing, and more particularly, to a semiconductor structure and a method for forming the same.
Background
In semiconductor manufacturing, with the trend of very large scale integrated circuits, the feature size of integrated circuits is continuously reduced, and in order to adapt to smaller feature sizes, the channel length of Metal-Oxide-semiconductor field effect transistors (MOSFETs) is also continuously shortened. However, as the channel length of the device is shortened, the distance between the source and the drain of the device is also shortened, so that the control capability of the gate structure on the channel is further and further reduced, and the difficulty of pinching off (pin off) the channel by the gate voltage is further and further increased, so that the phenomenon of subthreshold leakage (subthreshold leakage), namely the so-called short-channel effect (SCE), is more likely to occur.
Accordingly, to better accommodate the demand for device scaling, semiconductor processes are increasingly beginning to transition from planar transistors to three-dimensional transistors with higher power, such as Gate-all-around (GAA) transistors. In the fully-enclosed metal gate transistor, the gate encloses the region where the channel is located from the periphery, and compared with a planar transistor, the gate of the fully-enclosed metal gate transistor has stronger control capability on the channel and can better inhibit the short channel effect.
Disclosure of Invention
The embodiment of the invention solves the problem of providing a semiconductor structure and a forming method thereof, and improves the working performance of the semiconductor structure.
To solve the above problems, an embodiment of the present invention provides a semiconductor structure, including: a substrate; the channel layer structure is suspended above the substrate and comprises one or more channel layers arranged at intervals; a gate structure on the substrate, the gate structure crossing the channel layer structure and surrounding the channel layer; the source-drain doped layers are positioned on two sides of the grid structure and are contacted with the end parts of the channel layer, and the bottoms of the source-drain doped layers are lower than the surface of the substrate; the inner side wall is positioned between adjacent channel layers and between the channel layers and the bottom fin parts, is positioned between the grid structure and the source-drain doping layer in the extending direction of the channel layer structure, and is formed by overlapping a plurality of sub-inner side walls along the direction perpendicular to the side wall of the grid structure.
Correspondingly, the embodiment of the invention also provides a method for forming the semiconductor structure, which comprises the following steps: providing a substrate, wherein a laminated structure is formed on the substrate, the laminated structure comprises one or more stacked channel laminated layers, the channel laminated layers comprise a sacrificial layer and a channel layer positioned on the sacrificial layer, a pseudo gate structure crossing the laminated structure is also formed on the substrate, the pseudo gate structure covers the side wall and the top of the laminated structure, and two ends of the laminated structure are exposed; removing part of the sacrificial layer with the width along the direction perpendicular to the side wall of the pseudo gate structure to form a groove surrounded by the channel layer and the residual sacrificial layer; performing filling treatment for multiple times to form an inner side wall in the groove; wherein the filling process comprises: forming an inner side wall material layer covering the pseudo gate structure, the laminated structure and the substrate, wherein the inner side wall material layer is also positioned in the groove; removing the inner side wall material layer covering the pseudo gate structure, the side wall of the channel layer and the top of the substrate, and reserving the inner side wall material layer in the groove as a sub-inner side wall; the inner side walls are formed by overlapping multiple layers of sub inner side walls.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following advantages:
in the structure provided by the embodiment of the invention, the inner side wall is formed by superposing a plurality of sub-inner side walls along the direction vertical to the side wall of the grid structure; in the embodiment of the invention, the inner side wall is formed by superposing the plurality of sub-inner side walls, so that the inheritance of the innermost sub-inner side wall to the shape of the groove in the groove for forming the inner side wall is weakened, the probability of generating the inward concave defect of the inner side wall is reduced, the inner side wall with higher side wall flatness is obtained, in addition, in the process of respectively forming the grid structure and the source-drain doped layer on the two sides of the inner side wall, the probability of generating residues or cavities at the positions of the inner side wall is reduced, the parasitic capacitance between the grid structure and the source-drain doped layer is reduced, and the working performance of the semiconductor structure is improved.
In the forming method provided by the embodiment of the invention, filling treatment is carried out for a plurality of times, and an inner side wall is formed in the groove, wherein the filling treatment comprises the following steps: forming an inner side wall material layer covering the pseudo gate structure, the laminated structure and the substrate, removing the inner side wall material layer covering the pseudo gate structure, the side wall of the channel layer and the top of the substrate, and reserving the inner side wall material layer in the groove as an inner side wall; in the embodiment of the invention, the inheritance of the inner side wall material layer covering the groove to the shape of the groove is weakened by adopting multiple filling treatment, so that the probability of the formed inner side wall generating the inward concave defect is reduced, the inner side wall with higher side wall flatness is facilitated to be obtained, in addition, in the process of forming the source and drain doped layers on two sides of the pseudo gate structure and forming the gate structure at the positions of the pseudo gate structure and the sacrificial layer, the probability of generating residues or cavities at the positions of the inner side wall is also facilitated to be reduced, and the parasitic capacitance between the gate structure and the source and drain doped layers is also facilitated to be reduced, so that the working performance of the semiconductor structure is further facilitated to be improved.
Drawings
Fig. 1 to 3 are schematic structural views corresponding to steps in a method for forming a semiconductor structure;
fig. 4 to 5 are schematic structural views corresponding to an embodiment of the semiconductor structure of the present invention;
fig. 6 to 16 are schematic structural views corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention.
Detailed Description
The performance of current semiconductor structures is to be improved. The reason why the performance of a semiconductor structure is to be improved is now analyzed in conjunction with a method of forming the semiconductor structure.
Fig. 1 to 3 are schematic structural views corresponding to steps in a method for forming a semiconductor structure.
Referring to fig. 1, a substrate 10 is provided, a stack structure 20 is formed on the substrate 10, the stack structure 20 includes one or more channel stacks 21, the channel stacks 21 include a sacrificial layer 22 and a channel layer 23 on the sacrificial layer 22, a dummy gate structure 30 is further formed on the substrate 10 across the stack structure 20, the dummy gate structure 30 covers a portion of the sidewalls and a portion of the top of the stack structure 20, and a mask layer 40 is further formed on top of the dummy gate structure 30; the sacrificial layer 22 with a partial width is removed along a direction perpendicular to the sidewall of the dummy gate structure 30, and a trench 31 surrounded by the channel layer 23 and the remaining sacrificial layer 22 is formed.
Referring to fig. 2, an inner sidewall material layer 50 is formed to conformally cover the dummy gate structure 30, the stack structure 20, and the substrate 10, the inner sidewall material layer 50 also filling the trench 31.
Referring to fig. 3, the inner sidewall material layer 50 covering the dummy gate structure 30, the sidewalls of the channel layer 23, and the top of the substrate 10 is removed, leaving the inner sidewall material layer 50 located in the trench 31 as the inner sidewall wall 51.
It is found that, in the step of forming the inner sidewall material layer 50, the inner sidewall material layer 50 covering the trench 31 has inheritance of morphology to the trench 31, and in the step of removing the inner sidewall material layer 50 covering the dummy gate structure 30, the sidewall of the channel layer 23 and the top of the substrate 10, if an isotropic etching process is adopted, the formed inner sidewall 51 is easy to inherit the morphology of the inner sidewall material layer 50, so as to generate an inward concave defect (as shown by a dotted circle in fig. 3), and in the subsequent process of forming source-drain doped layers on both sides of the dummy gate structure 30 and forming gate structures at positions of the dummy gate structure 30 and the sacrificial layer 22, residues or voids are easy to be generated at positions of the inner sidewall, thereby increasing parasitic capacitance between the gate structure and the source-drain doped layers and affecting the working performance of the semiconductor structure; if an anisotropic etching process is adopted, the depth-to-width ratio of the etching process is relatively large when the material layer 50 covering the dummy gate structure 30, the sidewall of the channel layer 23 and the top of the substrate 10 is removed, more mask layers 40 are easily consumed in the etching process, and even the mask layers 40 are removed to damage the dummy gate structure 30, so that the thickness of the mask layers 40 is generally relatively large, the process cost is increased, the depth-to-width ratio of the etching process is further increased, the difficulty of forming the inner side wall is increased, the film quality of the inner side wall is easily affected, and the working performance of the semiconductor structure is further affected.
In order to solve the technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate, wherein a laminated structure is formed on the substrate, the laminated structure comprises one or more stacked channel laminated layers, the channel laminated layers comprise a sacrificial layer and a channel layer positioned on the sacrificial layer, a pseudo gate structure crossing the laminated structure is also formed on the substrate, the pseudo gate structure covers the side wall and the top of the laminated structure, and two ends of the laminated structure are exposed; removing part of the sacrificial layer with the width along the direction perpendicular to the side wall of the pseudo gate structure to form a groove surrounded by the channel layer and the residual sacrificial layer; forming an inner side wall material layer which covers the pseudo gate structure, the laminated structure and the substrate in a conformal manner, wherein the inner side wall material layer is also filled in the groove; forming a protective layer covering the inner side wall material layer at the end part of the laminated structure; removing the exposed inner side wall material layer of the protective layer; removing the protective layer around the laminated structure to expose the inner side wall material layer at the end part of the laminated structure; and removing the exposed inner side wall material layer outside the groove after removing the protective layer around the laminated structure, and reserving the inner side wall material layer in the groove as an inner side wall.
In the forming method provided by the embodiment of the invention, the inner side wall material layer at the end part of the laminated structure is covered by the protective layer, and the inner side wall material layer covering the pseudo gate structure and the inner side wall material layer of the laminated structure are removed in a separated mode to form the inner side wall, so that the depth-to-width ratio of each removing process is reduced, the difficulty in removing the inner side wall material layer to form the inner side wall is reduced, the inner side wall with higher film quality is formed, and the working performance of the semiconductor structure is improved.
In order that the above objects, features and advantages of the invention will be readily understood, a more particular description of the invention will be rendered by reference to specific embodiments thereof which are illustrated in the appended drawings.
Fig. 4 to 5 are schematic structural views of a semiconductor structure according to an embodiment of the present invention, fig. 4 is a top view of a gate structure and a source-drain doped layer, and fig. 5 is a cross-sectional view of fig. 4 based on AA direction.
The semiconductor structure includes: a substrate 101; a channel layer structure 201 suspended above the substrate 101, the channel layer structure 201 including one or more channel layers 231 disposed at intervals; a gate structure 601 on the substrate 101, the gate structure 601 crossing the channel layer structure 201 and surrounding the channel layer 231; the source-drain doped layer 171 is located at two sides of the gate structure 601 and contacts with the end of the channel layer 231, and the bottom of the source-drain doped layer 171 is lower than the surface of the substrate 101; the inner side walls 501 are located between adjacent channel layers 231 and between the channel layers 231 and the substrate 101, and in the extending direction of the channel layer structure 201, the inner side walls 501 are located between the gate structure 601 and the source-drain doped layer 171, and the inner side walls 501 are formed by overlapping a plurality of sub-inner side walls 511 along the direction perpendicular to the side walls of the gate structure 601.
The substrate 101 provides a process operation basis for the formation process of the semiconductor structure. Among other things, semiconductor structures include gate-all-around (GAA) transistors and fork-gate (fork) transistors.
In this embodiment, the base 101 includes a substrate 111, and a bottom fin 121 protruding from the substrate 111.
In this embodiment, the material of the substrate 111 is silicon. In other embodiments, the substrate may be made of other materials such as germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, and the substrate may be made of other types of substrates such as silicon on insulator substrates or germanium on insulator substrates. The material of the substrate may be a material suitable for process requirements or easy integration.
In this embodiment, the bottom fin 121 and the substrate 111 are integrally formed, so that the material of the bottom fin 121 is the same as that of the substrate 111, or the material of the bottom fin 121 is the same as that of the topmost semiconductor layer in the substrate 111. In this embodiment, the material of the substrate 111 is silicon, and the material of the bottom fin 121 is correspondingly silicon.
In this embodiment, the semiconductor structure further includes: an isolation layer (not shown) is located between adjacent substrates 111.
The isolation layer is a shallow trench isolation structure for realizing insulation between different devices, for example, in a CMOS manufacturing process, a shallow trench isolation structure is usually formed between an NMOS transistor and a PMOS transistor.
In this embodiment, the material of the isolation layer is an insulating material. As an example, the material of the isolation layer is silicon oxide.
The channel layer structure 201 includes one or more channel layers 231 spaced apart in a longitudinal direction (as shown in the Z-direction in fig. 5), the channel layers 231 serving as channels of transistors.
In this embodiment, the material of the channel layer 231 includes silicon, germanium, silicon germanium, or a group iii-v semiconductor material. As an example, the material of the channel layer 231 is silicon. In other embodiments, the material of the channel layer is determined by the type and performance of the transistor.
In this embodiment, the materials of the channel layer 231 and the substrate 111 are the same, and in other embodiments, the materials of the channel layer and the substrate may be different.
The gate structure 601 is used to control the turning on and off of the channel of the transistor.
The gate structure 601 circumferentially covers the channel layer 231, and thus, the top, bottom and sidewalls of the channel layer 231 can all serve as channels, increasing the area of the channel layer 231 for serving as channels, thereby increasing the operating current of the semiconductor structure.
In this embodiment, the gate structure 601 includes a gate dielectric layer 611 surrounding the channel layer 231 along the extending direction of the gate structure 601, and a gate electrode layer 621 on the gate dielectric layer 611.
The gate dielectric layer 611 is used to isolate the gate electrode layer 621 from the channel layer 231, and the gate electrode layer 621 from the substrate 101.
The material of the gate dielectric layer 611 includes HfO 2 、ZrO 2 、HfSiO、HfSiON、HfTaO、HfTiO、HfZrO、Al 2 O 3 、SiO 2 And La (La) 2 O 3 One or more of the following. In this embodiment, the gate dielectric layer 611 includes a high-k gate dielectric layer, and the material of the high-k gate dielectric layer includes a high-k dielectric material. The high-k dielectric material refers to a dielectric material with a relative dielectric constant larger than that of silicon oxide. Specifically, the material of the high-k gate dielectric layer comprises HfO 2 、ZrO 2 HfSiO, hfSiON, hfTaO, hfTiO, hfZrO or Al 2 O 3 Etc.
Note that the gate dielectric layer 611 may further include a gate oxide layer, which is located between the high-k gate dielectric layer and the channel layer 231. Specifically, the material of the gate oxide layer may be silicon oxide.
In this embodiment, the gate structure 601 is a metal gate structure, and thus, the material of the gate electrode layer 621 includes one or more of TiN, taN, ta, ti, tiAl, W, al, tiSiN and TiAlC.
Specifically, the gate electrode layer 621 includes a work function layer (not shown), and an electrode layer (not shown) located on the work function layer. The work function layer is used for adjusting the threshold voltage of the transistor, and the electrode layer is used for leading out the electricity of the metal gate structure.
In other embodiments, the gate electrode layer may also include only the work function layer.
In other embodiments, the gate structure may be a polysilicon gate structure, depending on the process requirements.
In this embodiment, the semiconductor structure further includes: the gate sidewall 311 covers the sidewall of the gate structure 601.
The gate sidewall 311 is used to protect the sidewall of the gate structure 601. The gate sidewall 311 may have a single-layer structure or a stacked-layer structure, and the material of the gate sidewall 311 includes one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride oxide, silicon oxynitride, boron nitride, and boron carbonitride. In this embodiment, the gate sidewall 311 has a single-layer structure, and the material of the gate sidewall 311 is silicon nitride.
In this embodiment, the semiconductor structure further includes: and an interlayer dielectric layer 181 covering the sidewalls of the gate structure 601, the interlayer dielectric layer 181 exposing the top of the gate structure 601.
The interlayer dielectric layer 181 is used for isolating adjacent devices, and the interlayer dielectric layer 181 is also used for providing a process basis for forming the gate structure 601.
The interlayer dielectric layer 181 is made of an insulating material, and includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride and silicon oxycarbonitride.
The source-drain doped layer 171 serves as a source region or a drain region of the transistor. Specifically, the doping type of the source-drain doping layer 171 is the same as the channel conductivity type of the corresponding transistor.
The doping type of the source-drain doping layer 171 is the same As the channel conductivity type of the corresponding transistor, specifically, when the substrate 101 is used to form an NMOS transistor, the doping ions in the source-drain doping layer 171 are N-type ions, which include P-ions, as-ions, or Sb-ions; when the substrate 101 is used to form a PMOS transistor, the dopant ions In the source-drain dopant layer 171 are P-type ions, including B ions, ga ions, or In ions.
The sidewall spacer 501 is used to isolate the gate structure 601 from the source/drain doped layer 171 to reduce parasitic capacitance between the device gate structure 601 and the source/drain doped layer 171.
In this embodiment, the sidewall 501 is formed by performing multiple filling processes in the trench of the sidewall 501, where the filling processes include: forming an inner sidewall material layer covering the dummy gate structure, the stacked structure, and the substrate 101; the inner sidewall material layer covering the dummy gate structure, the sidewall of the channel layer 231 and the top of the substrate 101 is removed, and the inner sidewall material layer in the inner sidewall trench is reserved as a sub-inner sidewall, so that in this embodiment, the inner sidewall 501 is formed by overlapping a plurality of sub-inner sidewalls 511 along the direction perpendicular to the sidewall of the gate structure 601.
In this embodiment, the plurality of sub-inner side 511 walls are overlapped to form the inner side wall 501, which is favorable for weakening the inheritance of the innermost sub-inner side wall 511 to the shape of the trench in the trench for forming the inner side wall 501, thereby being favorable for reducing the probability of generating the defect of inward recessing of the inner side wall 501, being favorable for obtaining the inner side wall 501 with higher side wall flatness, and being favorable for reducing the probability of generating residues or cavities at the position of the inner side wall 501 in the process of respectively forming the gate structure 601 and the source-drain doped layer 171 on both sides of the inner side wall 501, thereby being favorable for reducing the parasitic capacitance between the gate structure 601 and the source-drain doped layer 171, and further being favorable for improving the working performance of the semiconductor structure.
In this embodiment, the inner side wall 501 is formed by performing 2 times of filling processing in the trench of the inner side wall 501, so that fewer filling processing times can be adopted, that is, the inner side wall 501 with higher sidewall flatness can be obtained, which is beneficial to reducing complexity of the forming process of the inner side wall 501.
In this embodiment, multiple filling processes are performed in the trench of the inner sidewall 501, the first filling process is used for basically filling the trench of the inner sidewall 501, and the subsequent refilling processes are all used for filling the recess of the first formed sub-sidewall 511, so that the thickness of the first formed sub-inner sidewall 511 is larger, and in this embodiment, along the direction perpendicular to the sidewall of the gate structure 601, the sub-inner sidewall 511 closest to the gate structure 601 has a first thickness, and the remaining sub-inner sidewall 511 has a second thickness, which is smaller than the first thickness.
According to the actual deposition process, in this embodiment, the first thickness is 6nm to 12nm, and the second thickness is less than or equal to 8nm.
In this embodiment, the material of the inner sidewall 501 is an insulating material, and the material of the inner sidewall 501 includes SiN, siON, siOCN, siOC or SiOCH.
The smaller k value of SiN, siON, siOCN, siOC or SiOCH is more beneficial to better isolate the gate structure 601 from the source-drain doped layer 171 and reduce the parasitic capacitance between the gate structure 601 and the source-drain doped layer 171.
Fig. 6 to 16 are schematic structural views corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention.
Referring to fig. 6 to 9 in combination, fig. 6 is a cross-sectional view of an initial channel stack, fig. 7 is a top view of a dummy gate structure and the initial channel stack, fig. 8 is a cross-sectional view based on the AA direction of fig. 7, fig. 9 is a cross-sectional view based on fig. 8, a substrate 100 is provided, a stack structure 200 is formed on the substrate 100, the stack structure 200 includes one or more stacked channel stacks 210, the channel stack 210 includes a sacrificial layer 220 and a channel layer 230 on the sacrificial layer 220, a dummy gate structure 300 is further formed on the substrate 100 across the stack structure 200, the dummy gate structure 300 covers sidewalls and a top of the stack structure 200, and both ends of the stack structure 200 are exposed.
The substrate 100 provides a process operation basis for the formation process of the semiconductor structure. Wherein the semiconductor structure includes a fully surrounding gate transistor and a fork gate transistor.
In this embodiment, the base 100 includes a substrate 110 and a bottom fin 120 protruding from the substrate 110, and the stacked structure 200 is located on the bottom fin 120.
In this embodiment, the material of the substrate 110 is silicon. In other embodiments, the substrate may be made of other materials such as germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, and the substrate may be made of other types of substrates such as silicon on insulator substrates or germanium on insulator substrates. The material of the substrate may be a material suitable for process requirements or easy integration.
In this embodiment, the bottom fin 120 and the substrate 110 are integrally formed, so that the material of the bottom fin 120 is the same as that of the substrate 110, or the material of the bottom fin 120 is the same as that of the topmost semiconductor layer in the substrate 110. In this embodiment, the material of the substrate 110 is silicon, and the material of the bottom fin 120 is correspondingly silicon.
In this embodiment, an isolation layer (not shown) is also formed in the base 100, and is located between adjacent substrates 100.
The isolation layer is a shallow trench isolation structure for realizing insulation between different devices, for example, in a CMOS manufacturing process, a shallow trench isolation structure is usually formed between an NMOS transistor and a PMOS transistor.
The material of the isolation layer is an insulating material. In this embodiment, the material of the isolation layer is silicon oxide.
The channel layer 230 in the stacked structure 200 is used as a channel of a semiconductor structure, and the sacrificial layer 220 is used to provide a process basis for the subsequent suspension of the channel layer 230 and also to occupy a space for the subsequently formed gate structure. In a subsequent process, the sacrificial layer 220 is removed, so that the channel layer 230 is suspended, and a gate structure is formed between the channel layer 230 and the substrate 100, and between adjacent channel layers 230.
The surface of the channel layer 230 covered by the gate structure is used as a channel, and in this embodiment, the top, bottom and side walls of the channel layer 230 can be used as channels, so that the area of the channel layer 230 used as a channel is increased, and the operating current of the semiconductor structure is increased.
In this embodiment, the material of channel layer 230 includes silicon, germanium, silicon germanium, or a group iii-v semiconductor material. As one example, the material of the channel layer 230 is silicon. In other embodiments, the material of the channel layer is determined by the type and performance of the transistor.
In this embodiment, the materials of the channel layer 230 and the substrate 110 are the same, and in other embodiments, the materials of the channel layer and the substrate may be different.
In this embodiment, the material of the sacrificial layer 220 includes silicon germanium.
The silicon germanium and silicon can form a larger etching selectivity ratio, which is beneficial to the subsequent removal of the sacrificial layer 220 and reduces the damage to the channel layer 230.
In other embodiments, the sacrificial layer may be selected from a material compatible with the channel layer having an etch selectivity to reduce damage to the channel layer when the sacrificial layer is subsequently removed.
The dummy gate structure 300 is used to occupy a spatial location for subsequent gate structure formation.
Specifically, the dummy gate structure 300 is a stacked structure including a dummy gate oxide layer (not shown) and a dummy gate layer (not shown) covering the dummy gate oxide layer.
As an example, the material of the dummy gate oxide layer is silicon oxide, and the material of the dummy gate layer is polysilicon.
In this embodiment, a gate sidewall 310 is further formed on the substrate 100 to cover the top and the sidewall of the dummy gate structure 300.
After the gate structure is formed later, the gate sidewall 310 is used to protect the sidewall of the gate structure.
The gate sidewall 310 may have a single-layer structure or a stacked-layer structure, and the material of the gate sidewall 310 includes one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride oxide, silicon oxynitride, boron nitride, and boron carbonitride. In this embodiment, the gate sidewall 310 has a single-layer structure, and the material of the gate sidewall 310 is silicon nitride.
In this embodiment, a mask layer 400 is formed on top of the dummy gate structure 300.
The mask layer 400 is used as an etching mask for forming the dummy gate structure 300, and also used for protecting the top of the dummy gate structure 300 during the subsequent formation of the sidewall.
In this embodiment, the material of the mask layer 400 includes one or more of silicon oxide and silicon nitride. As an example, the material of the mask layer 400 is silicon nitride.
Specifically, referring to fig. 6, before forming the stacked structure 200, further includes: an initial channel stack 130 is formed on a substrate 100, the initial channel stack 130 including one or more stacked channel stacks 210, the channel stack 210 including a sacrificial layer 220 and a channel layer 230 on the sacrificial layer 220.
The initial channel stack 130 is used to directly form the stack structure 200.
In this embodiment, the initial channel stack 130 is formed in the same process, which simplifies the process flow, improves the process efficiency, and saves the process cost.
In this embodiment, an epitaxial growth process is used to form the initial channel stack 130.
The epitaxial growth process can better control the process parameters, has higher process controllability, is easy to obtain more accurate film thickness dimension, and is easy to form a film with fewer impurities, so that the quality of the initial channel stack 130 is higher.
Referring to fig. 7 and 8 in combination, a dummy gate structure 300 is formed across the initial channel stack 130, the dummy gate structure 300 covering a portion of the sidewalls and a portion of the top of the initial channel stack 130.
The initial channel stack 130 is subsequently etched along the sidewalls of the dummy gate structure 300, thereby patterning the initial channel layer 130.
Referring to fig. 9, the initial channel stack 130 on both sides of the dummy gate structure 300 is removed, leaving the remaining initial channel stack 130 as the stack structure 200.
In this embodiment, the initial channel stack 130 may be used to form a plurality of stacked structures 200 in a plurality of regions at the same time, so as to simplify the process flow, improve the process efficiency, and save the process cost.
In this embodiment, a dry etching process is used to remove the initial channel stack 130 on both sides of the dummy gate structure 300.
The dry etching process is an anisotropic dry etching process, so that damage to the substrate 100 is reduced by selecting the dry etching process, and meanwhile, the dry etching has more etching directionality, and is beneficial to improving the shape quality and the dimensional accuracy of the side wall of the laminated structure 200.
Referring to fig. 10, a part of the width of the sacrificial layer 220 is removed in a direction perpendicular to the sidewall of the dummy gate structure 300, and a trench 430 surrounded by the channel layer 230 and the remaining sacrificial layer 220 is formed.
The grooves 430 are used to provide a spatial location for the subsequent formation of the interior side wall.
In this embodiment, an isotropic etching process is used to remove a portion of the width of the sacrificial layer 220, thereby forming a trench 430.
In this embodiment, the isotropic etching process is a wet etching process, and the etching solution includes a hydrochloric acid solution.
The hydrochloric acid solution has a good etching selectivity ratio to silicon germanium and silicon, and is beneficial to reducing damage to the channel layer 230 in the process of removing the sacrificial layer 220 with partial width.
Referring to fig. 11 to 14 in combination, a plurality of filling processes are performed to form the inner sidewall 500 in the trench 430.
The sidewall spacers 500 serve to isolate the gate structure from the source and drain doped layers to reduce parasitic capacitance between the device gate structure and the source and drain doped layers.
Wherein the filling process comprises: forming an inner sidewall material layer 530 covering the dummy gate structure 300, the stack structure 200, and the substrate 100, the inner sidewall material layer 530 being further located in the trench 430; removing the inner sidewall material layer 530 covering the dummy gate structure 300, the sidewalls of the channel layer 230 and the top of the substrate 100, leaving the inner sidewall material layer 530 located in the trench 430 as the sub-inner sidewall 510; the multiple layers of sub-interior sidewalls 510 are stacked to form the interior sidewall 500.
In this embodiment, the multiple filling processes are adopted, so that the inheritance of the inner sidewall material layer 530 covering the trench 430 to the morphology of the trench 430 is facilitated to be weakened, the probability of the formed inner sidewall 500 generating an inward concave defect is reduced, the inner sidewall 500 with higher sidewall flatness is facilitated to be obtained, in addition, in the subsequent process of forming source-drain doped layers on both sides of the dummy gate structure 300 and forming the gate structure at the positions of the dummy gate structure 300 and the sacrificial layer 220, the probability of generating residues or voids at the positions of the inner sidewall 500 is also facilitated to be reduced, and therefore parasitic capacitance between the gate structure and the source-drain doped layers is facilitated to be reduced, and further the working performance of the semiconductor structure is facilitated to be improved.
In this embodiment, the number of filling processes is 2, so that fewer filling processes can be used to obtain the inner sidewall 500 with higher sidewall flatness, which is beneficial to reducing complexity of the forming process of the inner sidewall 500, and therefore, in this embodiment, the inner sidewall 500 is formed by stacking 2 sub-inner sidewalls 510.
The 1 st filling process is illustrated in fig. 11 and 12, the 2 nd filling process is illustrated in fig. 13 and 14, and in other embodiments, the filling process is performed a plurality of times, only in a cycle of steps as in fig. 13 and 14.
In this embodiment, a plurality of filling processes are performed, the first filling process is used for basically filling the trench 430 of the inner sidewall 500, and the subsequent refilling processes are all used for filling the recess of the first formed sub-sidewall 510, so that the thickness of the first formed sub-inner sidewall 510 is larger.
According to the actual deposition process, in this embodiment, the first thickness is 6nm to 12nm, and the second thickness is less than or equal to 8nm.
In this embodiment, the material of the inner sidewall 500 is an insulating material, and the material of the inner sidewall 500 includes SiN, siON, siOCN, siOC or SiOCH.
The k value of SiN, siON, siOCN, siOC or SiOCH is smaller, which is more favorable for better isolating the gate structure and the source-drain doped layer and reducing the parasitic capacitance between the gate structure and the source-drain doped layer.
The steps of the one-time filling process will be described in detail with reference to fig. 11 and 12.
Referring to fig. 11, an inner sidewall material layer 530 is formed covering the dummy gate structure 300, the stack structure 200, and the substrate 100 in a conformal manner, the inner sidewall material layer 530 also being located in the trench 430.
The inner sidewall material layer 530 is used to form the sub-inner sidewall 510.
Accordingly, in the present embodiment, the material of the inner wall material layer 530 includes SiN, siON, siOCN, siOC or SiOCH.
In the step of forming the conformal covering dummy gate structure 300, the stacked structure 200, and the inner sidewall material layer 530 of the substrate 100, the inner sidewall material layer 530 also covers the mask layer 400.
In this embodiment, the inner sidewall material layer 530 is formed by an atomic layer deposition process.
The thickness uniformity of the inner sidewall material layer 530 formed by the atomic layer deposition process is good, and the inner sidewall material layer 530 has good step coverage (step coverage) capability, so that the inner sidewall material layer 530 can well cover the dummy gate structure 300, the stacked structure 200 and the substrate 100 in a conformal manner.
Referring to fig. 12, the inner sidewall material layer 530 covering the dummy gate structure 300, the sidewalls of the channel layer 230, and the top of the substrate 100 is removed, leaving the inner sidewall material layer 530 located in the trench 430 as the sub-inner sidewall 510.
In this embodiment, an isotropic etching process is used to remove the inner sidewall material layer 530 covering the dummy gate structure 300, the sidewall of the channel layer 230, and the top of the substrate 100.
The isotropic etching process has similar etching rate in all directions, and the exposed inner side wall material layer 530 can be removed completely without using a mask layer 400 with larger thickness, which is beneficial to saving the process cost.
In this embodiment, the isotropic etching process includes an isotropic dry etching process, and the process is simple and convenient to operate, and the process parameters are easy to control, so that the removal amount of the etched inner side wall material layer 530 is better controlled.
Referring to fig. 15, after forming the inner sidewall 510 in the trench 430, the forming method further includes: source and drain doped layers 170 are formed on both sides of the dummy gate structure 300 in contact with ends of the channel layer 230.
The source drain doped layer 170 is used as a source or drain region of the transistor being formed.
The source-drain doped layer 170 is epitaxially grown on the basis of the channel layer 230, so in this embodiment, in the step of forming the source-drain doped layer 170, the source-drain doped layer 170 contacts the inner sidewall 510.
The doping type of the source-drain doping layer 170 is the same As the channel conductivity type of the corresponding transistor, specifically, when the substrate 100 is used to form an NMOS transistor, the doping ions in the source-drain doping layer 170 are N-type ions, and the N-type ions include P-ions, as ions, or Sb ions; when the substrate 100 is used to form a PMOS transistor, the dopant ions In the source-drain doped layer 170 are P-type ions, including B-ions, ga-ions, or In-ions.
Referring to fig. 16, an interlayer dielectric layer 180 is formed to cover sidewalls of the dummy gate structure 300 and the source drain doped layer 170.
The interlayer dielectric layer 180 is used for isolating adjacent devices, and in this embodiment, the interlayer dielectric layer 180 exposes the top of the dummy gate structure 300, so as to prepare for removing the dummy gate structure 300, and the interlayer dielectric layer 180 is also used for providing a process basis for forming a gate structure subsequently.
The material of the interlayer dielectric layer 180 is an insulating material, including one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon oxycarbonitride.
In this embodiment, the dummy gate structure 300 is removed, and a gate opening (not shown) is formed in the interlayer dielectric layer 180, and the gate opening exposes the sacrificial layer 220.
The gate opening provides a spatial location for subsequent formation of the gate structure while providing for removal of the sacrificial layer 220.
In this embodiment, the sacrificial layer 220 is removed through the gate opening to form a through trench (not shown), and the through trench is surrounded by the adjacent channel layer 230 or is surrounded by the adjacent channel layer 230 and the substrate 100.
The sacrificial layer 220 is removed through the gate opening, exposing the respective surfaces of the channel layer 230, such that a subsequently formed gate structure circumferentially covers the channel layer 230.
In this embodiment, after the sacrificial layer 220 is removed, a gate structure 600 is formed in the gate opening, and the gate structure 600 surrounds the channel layer 230.
The gate structure 600 is used to control the turning on or off of the channel of the transistor.
The gate structure 600 wraps around the channel layer 230, and thus the top, bottom and sidewalls of the channel layer 230 can all serve as channels, increasing the area of the channel layer 230 used as channels, thereby increasing the operating current of the semiconductor structure.
In this embodiment, the gate structure 600 includes a gate dielectric layer 610 surrounding the channel layer 230 along the extending direction of the gate structure 600, and a gate electrode layer 620 on the gate dielectric layer 610.
The gate dielectric layer 610 is used to isolate the gate electrode layer 620 from the channel layer 230 and the gate electrode layer 620 from the substrate 100.
The material of gate dielectric layer 610 includes HfO 2 、ZrO 2 、HfSiO、HfSiON、HfTaO、HfTiO、HfZrO、Al 2 O 3 、SiO 2 And La (La) 2 O 3 One or more of the following. In this embodiment, the gate dielectric layer 610 includes a high-k gate dielectric layer, and the material of the high-k gate dielectric layer includes a high-k dielectric material. The high-k dielectric material refers to a dielectric material with a relative dielectric constant larger than that of silicon oxide. Specifically, the material of the high-k gate dielectric layer comprises HfO 2 、ZrO 2 HfSiO, hfSiON, hfTaO, hfTiO, hfZrO or Al 2 O 3 Etc.
Note that the gate dielectric layer 610 may further include a gate oxide layer, which is located between the high-k gate dielectric layer and the channel layer 230. Specifically, the material of the gate oxide layer may be silicon oxide.
In this embodiment, the gate structure 600 is a metal gate structure, and thus, the material of the gate electrode layer 620 includes one or more of TiN, taN, ta, ti, tiAl, W, al, tiSiN and TiAlC.
Specifically, the gate electrode layer 620 includes a work function layer (not shown), and an electrode layer (not shown) located on the work function layer. The work function layer is used for adjusting the threshold voltage of the transistor, and the electrode layer is used for leading out the electricity of the metal gate structure.
In other embodiments, the gate electrode layer may also include only the work function layer.
In other embodiments, the gate structure may be a polysilicon gate structure, depending on the process requirements.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.

Claims (17)

1. A semiconductor structure, comprising:
a substrate;
the channel layer structure is suspended above the substrate and comprises one or more layers of channel layers arranged at intervals;
a gate structure on the substrate, the gate structure crossing the channel layer structure and surrounding the channel layer;
the source-drain doped layers are positioned on two sides of the grid structure and are in contact with the end parts of the channel layer, and the bottoms of the source-drain doped layers are lower than the surface of the substrate;
and the inner side walls are positioned between adjacent channel layers and between the channel layers and the substrate, are positioned between the grid structure and the source-drain doping layers in the extending direction of the channel layer structure, and are formed by superposing a plurality of sub-inner side walls along the direction perpendicular to the side wall of the grid structure.
2. The semiconductor structure of claim 1, wherein said inner side wall is comprised of 2 of said sub-inner side walls stacked.
3. The semiconductor structure of claim 1, wherein a sub-interior sidewall closest to the gate structure has a first thickness in a direction perpendicular to the gate structure sidewall, and the remaining sub-interior sidewall has a second thickness, the second thickness being less than the first thickness.
4. The semiconductor structure of claim 3, wherein the first thickness is 6nm to 12nm and the second thickness is less than or equal to 8nm in a direction perpendicular to the gate structure sidewall.
5. The semiconductor structure of claim 1, wherein the material of the interior sidewall comprises SiN, siON, siOCN, siOC or SiOCH.
6. A method of forming a semiconductor structure, comprising:
providing a substrate, wherein a laminated structure is formed on the substrate, the laminated structure comprises one or more stacked channel laminates, the channel laminates comprise a sacrificial layer and a channel layer positioned on the sacrificial layer, a pseudo gate structure crossing the laminated structure is also formed on the substrate, the pseudo gate structure covers the side wall and the top of the laminated structure, and two ends of the laminated structure are exposed;
removing part of the sacrificial layer with the width along the direction perpendicular to the side wall of the pseudo gate structure to form a groove surrounded by the channel layer and the rest of the sacrificial layer;
performing multiple filling treatments to form an inner side wall in the groove;
wherein the filling process includes: forming an inner side wall material layer covering the pseudo gate structure, the laminated structure and the substrate, wherein the inner side wall material layer is also positioned in the groove; removing the inner side wall material layer covering the pseudo gate structure, the side wall of the channel layer and the top of the substrate, and reserving the inner side wall material layer in the groove as a sub inner side wall; and a plurality of layers of the sub inner side walls are overlapped to form the inner side wall.
7. The method of claim 6, wherein the filling is performed by atomic layer deposition to form the inner sidewall material layer.
8. The method of forming a semiconductor structure of claim 7, wherein the first fill process forms the interior sidewall material layer to a first thickness and the remaining fill process forms the interior sidewall material layer to a second thickness that is less than the first thickness.
9. The method of forming a semiconductor structure of claim 8, wherein the first thickness is 6nm to 12nm and the second thickness is less than or equal to 8nm.
10. The method of forming a semiconductor structure of claim 6, wherein in said filling step, an isotropic etching process is used to remove an inner sidewall material layer covering said dummy gate structure, channel layer sidewalls and substrate top.
11. The method of forming a semiconductor structure of claim 10, wherein the isotropic etching process comprises an isotropic dry etching process.
12. The method of forming a semiconductor structure of claim 6, wherein the number of fill processes is 2.
13. The method of forming a semiconductor structure of claim 6, wherein in the step of providing a substrate, a mask layer is formed on top of the dummy gate structure;
in the step of forming an inner sidewall material layer covering the dummy gate structure, the stacked structure and the substrate, the inner sidewall material layer also covers the mask layer.
14. The method of forming a semiconductor structure of claim 6, wherein the step of providing a substrate, prior to forming the stacked structure, further comprises: forming an initial channel stack on the substrate, the initial channel stack comprising one or more stacked channel stacks, the channel stack comprising a sacrificial layer and a channel layer on the sacrificial layer;
forming a dummy gate structure across the initial channel stack, the dummy gate structure covering a portion of the sidewalls and a portion of the top of the initial channel stack;
and removing the initial channel laminated layers at two sides of the pseudo gate structure, and reserving the rest initial channel laminated layers as the laminated structure.
15. The method of forming a semiconductor structure of claim 6, wherein an isotropic etching process is used to remove a portion of the width of the sacrificial layer to form a trench surrounded by the channel layer and the remaining sacrificial layer.
16. The method of forming a semiconductor structure of claim 6, wherein after forming a sidewall wall in the trench, the method further comprises: forming source-drain doped layers which are contacted with the end parts of the channel layer on two sides of the pseudo gate structure;
forming an interlayer dielectric layer covering the side wall of the pseudo gate structure and the source-drain doped layer, wherein the interlayer dielectric layer exposes the top of the pseudo gate structure;
removing the pseudo gate structure, and forming a gate opening in the interlayer dielectric layer, wherein the gate opening exposes the sacrificial layer;
removing the sacrificial layer through the gate opening to form a through groove, wherein the through groove is surrounded by adjacent channel layers or is surrounded by adjacent channel layers and a substrate;
and after the sacrificial layer is removed, forming a gate structure in the gate opening and the through groove, wherein the gate structure circumferentially covers the channel layer.
17. The method of claim 6, wherein the material of the inner sidewall material layer comprises SiN, siON, siOCN, siOC or SiOCH.
CN202210794118.0A 2022-07-07 2022-07-07 Semiconductor structure and forming method thereof Pending CN117410333A (en)

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