CN117672971A

CN117672971A - Semiconductor structure and forming method thereof

Info

Publication number: CN117672971A
Application number: CN202211011550.4A
Authority: CN
Inventors: 涂武涛; 王彦; 邱晶
Original assignee: Semiconductor Manufacturing International Shanghai Corp
Current assignee: Semiconductor Manufacturing International Shanghai Corp
Priority date: 2022-08-23
Filing date: 2022-08-23
Publication date: 2024-03-08

Abstract

A semiconductor structure and a method of forming the same, the method comprising: forming a dummy gate structure crossing the device fin, wherein the dummy gate structure comprises a sacrificial fin positioned on the top of the device fin, a barrier layer positioned on the top of the sacrificial fin, and a sacrificial gate covering the top of the barrier layer, the sidewalls of the sacrificial fin and the barrier layer, and part of the sidewalls of the device fin; removing the sacrificial grid and the sacrificial fin part to form grid openings exposing the barrier layer and the device fin part, wherein the barrier layer and the device fin part are arranged in a suspending manner at intervals; forming a gate dielectric layer on the top and the side wall of the fin part of the device exposed by the gate opening and on the surface of the barrier layer; a first gate material layer located in the gate opening of the first region and a second gate material layer located in the gate opening of the second region are formed on the gate dielectric layer, the first gate material layer and the second gate material layer having different stack types and/or material types. The embodiment of the invention reduces the possibility of damaging the top of the fin part of the device and improves the performance of the semiconductor structure.

Description

Semiconductor structure and forming method thereof

Technical Field

Embodiments of the present disclosure relate to semiconductor manufacturing, and more particularly, to a semiconductor structure and a method for forming the same.

Background

To better accommodate the demands of device scaling, semiconductor processes are increasingly beginning to transition from planar transistors to three-dimensional transistors with higher power, such as: fin field effect transistors (finfets), and the like. In the Fin-type field effect transistor, three sides of a gate surround a channel of a Fin shape (Fin); in the fully-enclosed gate transistor, compared with a planar transistor, the gate of the fin field effect transistor has stronger control capability on a channel, and can better inhibit short channel effect.

And, the gate structure typically includes a work function layer, and the work function value of the gate structure in different regions is typically adjusted by adjusting the material type and thickness of the work function layer metal in different regions, thereby adjusting the threshold voltage Vt of different devices.

However, the probability of damage to the fin top during formation of the gate structure is high, resulting in reduced device reliability.

Disclosure of Invention

The embodiment of the invention solves the problem of providing a semiconductor structure and a forming method thereof, and improves the performance of the semiconductor structure.

To solve the above problems, an embodiment of the present invention provides a semiconductor structure, including: a substrate comprising a first region and a second region; the base comprises a substrate and a device fin part separated on the substrate; the stopping layer is positioned above the top of the device fin part and is arranged in suspension at intervals with the top of the device fin part; a first gate structure located on the substrate of the first region and crossing the device fin of the first region, wherein the first gate structure is filled between the device fin of the first region and the stop layer; a second gate structure located on the substrate of the second region and crossing the device fin of the second region, wherein the second gate structure is filled between the device fin of the second region and the stop layer; wherein the first gate structure and the second gate structure have different stack types and/or material types; the gate dielectric layer is positioned between the first gate structure and the device fin part and between the second gate structure and the device fin part; and the source-drain doped region is positioned in the fin parts of the devices at two sides of the first grid electrode structure and the second grid electrode structure.

Correspondingly, the embodiment of the invention also provides a method for forming the semiconductor structure, which comprises the following steps: providing a substrate, wherein the substrate comprises a first area and a second area; the base comprises a substrate and a device fin part separated on the substrate; forming a dummy gate structure crossing the device fin on the substrate, wherein the dummy gate structure comprises a sacrificial fin positioned on the top of the device fin, a barrier layer positioned on the top of the sacrificial fin, and a sacrificial gate covering the top of the barrier layer, sidewalls of the sacrificial fin and the barrier layer, and sidewalls of a part of the device fin; forming source-drain doped regions in the fin parts of the devices at two sides of the pseudo gate structure, wherein the source-drain doped regions expose the sacrificial fin parts and the barrier layer; removing the sacrificial grid and the sacrificial fin part to form grid openings exposing the barrier layer and the device fin part, wherein the barrier layer and the device fin part are arranged in a suspending manner at intervals; forming a gate dielectric layer on the top and the side wall of the device fin part exposed by the gate opening and on the surface of the barrier layer; a first gate material layer located in the gate opening of the first region and a second gate material layer located in the gate opening of the second region are formed on the gate dielectric layer, the first gate material layer and the second gate material layer having different stack types and/or material types.

Compared with the prior art, the technical scheme of the embodiment of the invention has the following advantages:

according to the semiconductor structure provided by the embodiment of the invention, the stop layers are further arranged above the tops of the fin parts of the devices in a suspending manner at intervals, and because the barrier layers are further arranged above the tops of the fin parts of the devices in a suspending manner in the forming process of the semiconductor structure, the gate dielectric layers are further formed on the surfaces of the barrier layers, and the gate dielectric layers positioned on the bottom surfaces of the barrier layers are used as the stop layers; the process of forming the first gate structure and the second gate structure includes the steps of forming a first gate material layer across the device fin of the first region and a second gate material layer across the device fin of the second region, and removing the first gate material layer and the second gate material layer above the top surface of the stop layer, and the barrier layer; the forming of the first gate material layer and the second gate material layer generally includes a step of forming a mask covering layer on the first region or the second region to etch a region exposed by the mask covering layer, wherein the mask covering layer correspondingly exposes the second region or the first region to form the first gate material layer and the second gate material layer with different lamination types and/or material types, and the forming of the mask covering layer generally includes a step of adopting an anisotropic etching process to etch and remove a covering material layer in a gate opening of the second region or the first region, and a step of suspending a barrier layer above the top of the device fin at intervals during the anisotropic etching process, so that the top of the device fin can be protected, the risk of damaging a film layer (for example, a gate dielectric layer) at the top of the device fin is reduced, the performance of the first gate structure and the second gate structure is correspondingly improved, and the performance of the semiconductor structure is further improved.

In addition, the top surface of the stop layer can define the stop position of the removal of the first gate material layer and the second gate material layer, so that the heights of the first gate structure and the second gate structure are defined, the heights of the first gate structure and the second gate structure can be controlled correspondingly, and the height consistency of the first gate structure and the height consistency of the second gate structure are improved.

In the method for forming the semiconductor structure provided by the embodiment of the invention, the dummy gate structure comprises a sacrificial fin part positioned on the top of the fin part of the device, a blocking layer positioned on the top of the sacrificial fin part, and a sacrificial gate covering the top of the blocking layer, the side walls of the sacrificial fin part and the blocking layer and part of the side walls of the fin part of the device; the forming of the first gate material layer and the second gate material layer generally includes forming a mask covering layer on the first region or the second region, so as to etch the region exposed by the mask covering layer, wherein the mask covering layer correspondingly exposes the second region or the first region, so that the first gate material layer and the second gate material layer with different lamination types and/or material types are formed, the forming of the mask covering layer generally includes adopting an anisotropic etching process, the step of etching and removing the covering material layer in the gate opening of the second region or the first region, and the step of carrying out the anisotropic etching process, wherein a blocking layer is suspended above the top of the device fin at intervals, so that the top of the device fin can be protected, the risk of damaging the film layer at the top of the device fin can be reduced, the performance of the first gate material layer or the second gate material layer is correspondingly improved, and the performance of the semiconductor structure is further improved.

In an alternative scheme, the gate dielectric layer positioned on the bottom surface of the barrier layer is used as a stop layer; the method for forming the semiconductor structure further comprises the following steps: after the first gate material layer and the second gate material layer are formed, the first gate material layer and the second gate material layer which are higher than the top surface of the stop layer and the barrier layer are removed, the remaining first gate material layer is used as a first gate structure, and the remaining second gate material layer is used as a second gate structure, so that the stop layer can also play a role in defining the heights of the first gate structure and the second gate structure, thereby being beneficial to precisely controlling the heights of the first gate structure and the second gate structure and improving the height consistency of the first gate structure and the height consistency of the second gate structure.

Drawings

Fig. 1 to 11 are schematic structural views corresponding to steps in a method for forming a semiconductor structure;

FIGS. 12-13 are schematic diagrams illustrating the structure of an embodiment of a semiconductor structure according to the present invention;

fig. 14 to 39 are schematic structural views corresponding to each step in an embodiment of a method for forming a semiconductor structure according to the present invention.

Detailed Description

As known from the background art, the probability of damage to the top of the fin during the formation of the gate structure is high.

In combination with a method for forming a semiconductor structure, the reason that the probability of damage of the top of the fin part in the process of forming the gate structure is high is analyzed. Fig. 1 to 11 are schematic structural views corresponding to steps in a method for forming a semiconductor structure.

Referring to fig. 1 and 2, fig. 1 is a top view, fig. 2 (a) is a cross-sectional view along the X-X direction of fig. 1, fig. 2 (b) is a cross-sectional view along the Y-Y direction of fig. 1, a base is provided, including a substrate 10 and a fin 11 separated from the substrate 10, the base including a first region 10a and a second region 10b; forming an isolation layer 12 surrounding the fin 11 on the substrate 10, the top of the isolation layer 12 being lower than the top of the fin 11; forming a dummy gate structure 13 crossing the fin 11 on the isolation layer 12, wherein the dummy gate structure 13 covers part of the top and part of the side wall of the fin 11; source-drain doped regions 14 are formed in the fin portions 11 at two sides of the dummy gate structure 13; an interlayer dielectric layer 15 is formed on the isolation layer 12 at the side of the dummy gate structure 13 to cover the source-drain doped regions 14.

Referring to fig. 3 to 4, fig. 3 is a top view, fig. 4 (a) is a cross-sectional view along the X-X direction of fig. 3, and fig. 4 (b) is a cross-sectional view along the Y-Y direction of fig. 3, the dummy gate structure 13 is removed, and a gate opening 16 is formed.

Referring to fig. 5 to 6, fig. 5 is a top view, fig. 6 (a) is a cross-sectional view of fig. 5 along the X-X direction, and fig. 6 (b) is a cross-sectional view of fig. 5 along the Y-Y direction, a gate dielectric layer 17 is formed on the bottom and sidewalls of the gate opening 16, and a first work function layer 18 is located on the gate dielectric layer 17.

Referring to fig. 7 to 9, fig. 7 is a top view, fig. 8 (a) is a cross-sectional view along the X-X direction of fig. 7, fig. 8 (b) is a cross-sectional view along the Y-Y direction of fig. 7, and fig. 9 is a partially enlarged view at fig. 8 (b) C, removing the first work function layer 18 of the first region 10a, exposing the gate dielectric layer 17 under the gate opening 16 of the first region 10 a.

Referring to fig. 10 to 11, fig. 10 is a top view, fig. 11 (a) is a cross-sectional view along the X-X direction of fig. 10, fig. 11 (b) is a cross-sectional view along the Y-Y direction of fig. 10, a second work function layer 19 is formed on the gate dielectric layer 17 exposed by the gate opening 16 of the first region 10a, and the thickness of the second work function layer 19 is smaller than the thickness of the first work function layer 18; forming a third work function layer 20 within the gate opening 16, the third work function layer 20 of the first region 10a having a thickness less than the third work function layer 20 of the second region 10b, the third work function layer 20 of the second region 10b filling the gate opening 16 of the second region 10 b; filling the gate opening 16 of the first region 10a with a metal electrode layer 21; the gate dielectric layer 17 and the second work function layer 19 of the first region 10a, the third work function layer 20, and the metal electrode layer 21 are used to form a first gate structure, and the gate dielectric layer 17, the first work function layer 18, and the third work function layer 20 of the second region 10b are used to form a second gate structure.

As shown in fig. 7 to 9, in the method for forming a semiconductor structure, the step of removing the first work function layer 18 of the first region 10a generally includes: forming a capping material layer (not shown) on the substrate that fills the gate opening 16; etching to remove the covering material layer in the gate opening 16 of the first region 10a by using an anisotropic etching process, and using the remaining covering material layer in the gate opening 16 of the second region 10b as the covering layer 22; the first work function layer 17 exposed by the cap layer 22 is removed.

In the process of etching to remove the covering material layer in the gate opening 16 of the first region 10a by using an anisotropic etching process, the anisotropic etching process etches the covering material layer along a direction perpendicular to the substrate, which is easy to over-etch the film layer (e.g., the gate dielectric layer 17) on top of the fin 11 under the gate opening 16 of the first region 10a, thereby resulting in a high probability of damaging the film layer (the gate dielectric layer 17) on top of the fin 11 (as shown by a dotted circle in fig. 9), and resulting in reduced performance of the device.

In order to solve the technical problems, the embodiment of the invention provides a semiconductor structure, wherein a stop layer is arranged above the top of a fin part of a device at intervals in a suspending way, and a barrier layer is also arranged above the top of the fin part of the device in a suspending way in the forming process of the semiconductor structure, a gate dielectric layer is also formed on the surface of the barrier layer, and the gate dielectric layer positioned on the bottom surface of the barrier layer is used as the stop layer; the process of forming the first gate structure and the second gate structure includes the steps of forming a first gate material layer across the device fin of the first region and a second gate material layer across the device fin of the second region, and removing the first gate material layer and the second gate material layer above the top surface of the stop layer, and the barrier layer; the step of forming the first gate material layer and the second gate material layer generally comprises the step of forming a mask covering layer on the first area or the second area so as to etch the area exposed by the mask covering layer, wherein the mask covering layer correspondingly exposes the second area or the first area so as to form the first gate material layer and the second gate material layer with different lamination types and/or material types, the step of etching and removing the covering material layer in the gate opening of the second area or the first area by adopting an anisotropic etching process is generally included in the process of forming the mask covering layer, and the step of etching and removing the covering material layer in the second area or the gate opening of the first area is carried out.

In order that the above objects, features and advantages of embodiments of the invention may be readily understood, a more particular description of the invention will be rendered by reference to specific embodiments thereof which are illustrated in the appended drawings. Referring to fig. 12-13, schematic structural diagrams of an embodiment of the semiconductor structure of the present invention are shown. Fig. 12 is a plan view, fig. 13 (a) is a cross-sectional view of fig. 12 along the X-X direction, and fig. 13 (b) is a cross-sectional view of fig. 12 along the Y-Y direction.

As shown in fig. 12 to 13, in the present embodiment, the semiconductor structure includes: a substrate including a first region 100a and a second region 100b; the base includes a substrate 100 and a device fin 110 discrete on the substrate 100; the stop layer 370 is located above the top of the device fin 110 and is suspended from the top of the device fin 110 at intervals; a first gate structure 350 on the substrate 100 of the first region 100a and crossing the device fin 110 of the first region 100a, wherein the first gate structure 350 is filled between the device fin 110 and the stop layer 370 of the first region 100 a; a second gate structure 360 located on the substrate 100 of the second region 100b and crossing the device fin 110 of the second region 100b, wherein the second gate structure 360 is filled between the device fin 110 and the stop layer 370 of the second region 100b; wherein the first gate structure 350 and the second gate structure 360 have different stack types and/or material types; a gate dielectric layer 250 between the first gate structure 350 and the device fin 110, and between the second gate structure 360 and the device fin 110; the source-drain doped regions 230 are located in the device fin 110 on both sides of the first gate structure 350 and the second gate structure 360.

The substrate is used for providing a process platform for the formation process of the semiconductor structure.

In this embodiment, the first region 100a is used to form a first device, and the second region 100b is used to form a second device.

As an example, the first region 100a is used to form a first type MOS transistor, and the second region 100b is used to form a second type MOS transistor, the channel conductivity types of the first type MOS transistor and the second type MOS transistor being different.

As a specific embodiment, the first type MOS transistor is a PMOS transistor, and the second type MOS transistor is an NMOS transistor. In other implementations, the first type MOS transistor may also be an NMOS transistor, and the second type MOS transistor may be a PMOS transistor.

In still other embodiments, the first device and the second device may also be other different types of devices.

In this embodiment, the substrate 100 is a silicon substrate, i.e., the material of the substrate 100 is monocrystalline silicon. In other embodiments, the material of the substrate may also be one or more of germanium, silicon carbide, gallium nitride, gallium arsenide, and indium gallium arsenide.

The device fin 110 is used to provide a conductive channel when the device is in operation. The material of the device fin 110 is a semiconductor material. The material of the device fin 110 includes one or more of silicon, germanium, silicon carbide, gallium nitride, gallium arsenide, and indium gallium arsenide.

In this embodiment, the device fin 110 and the substrate 100 are formed as a unitary structure. The material of the device fin 110 is the same as the material of the substrate 100, both being silicon. In other embodiments, the material of the device fin may also be different from the material of the substrate.

In this embodiment, the semiconductor structure further includes: an isolation layer 105 is located on the substrate 100 and surrounds the device fin 110, and the top of the isolation layer 105 is lower than the top of the device fin 110.

The isolation layer 105 is used to isolate between adjacent device fins 110, and also to isolate the substrate 100 from the first and second gate structures 350 and 360, and to isolate the substrate 100 from the first and second gate structures 350 and 360.

In this embodiment, the isolation layer 105 is a shallow trench isolation structure (Shallow trench isolation, STI). In this embodiment, the material of the isolation layer 105 is silicon oxide. In other embodiments, the material of the isolation layer may be silicon nitride or other insulating materials such as silicon oxynitride.

The stop layer 370 is used to define a stop position during planarization process of forming the first gate structure 350 and the second gate structure 360, thereby improving the uniformity of the height of the first gate structure 350 and the uniformity of the height of the second gate structure 360.

In this embodiment, the top surfaces of the first gate structure 350 and the second gate structure 360 above the top of the device fin 110 have a recess D; gate dielectric layer 250 is also located within recess D, and gate dielectric layer 250 located within recess D serves as stop layer 370.

The gate dielectric layer 250 is used to achieve electrical isolation between the first gate structure 350 and the device fin 110, and between the second gate structure 360 and the device fin 110.

In this embodiment, the top surfaces of the first gate structure 350 and the second gate structure 360 above the top of the device fin 110 have the recess D, because a barrier layer is further suspended above the top of the device fin 110 in the formation process of the semiconductor structure, and the gate dielectric layer 250 is further formed on the surface of the barrier layer; the process of forming the first gate structure 350 and the second gate structure 360 includes the steps of forming a first gate material layer across the device fin 110 of the first region 100a and a second gate material layer across the device fin 110 of the second region 100b, and removing the first gate material layer and the second gate material layer of the gate dielectric layer 250 above the bottom surface of the barrier layer, and the barrier layer.

The gate dielectric layer 250 is further located in the recess D, and the top surface of the gate dielectric layer 250 located in the recess D is used as the blocking layer 370, so that a stop position for removing the first gate material layer and the second gate material layer can be defined, and further heights of the first gate structure 350 and the second gate structure 360 are defined, which is correspondingly beneficial to precisely controlling the heights of the first gate structure 350 and the second gate structure 360, and improving the height consistency of the first gate structure 350 and the height consistency of the second gate structure 360.

Accordingly, in the present embodiment, the top surfaces of the first gate structure 350 and the second gate structure 360 are flush with the top surface of the stop layer 370.

In the process of forming the semiconductor structure, forming the first gate material layer and the second gate material layer generally includes forming a mask covering layer on the first region 100a or the second region 100b to etch a region exposed by the mask covering layer, where the mask covering layer exposes the second region 100b or the first region 100a, respectively, so as to form the first gate material layer and the second gate material layer with different stack types and/or material types, and in the process of forming the mask covering layer, generally includes a step of etching to remove a covering material layer located in a gate opening of the second region 100b or the first region 100a by an anisotropic etching process, and in the process of performing the anisotropic etching process, a blocking layer is suspended above the top of the device fin 110 at intervals, which can protect the top of the device fin 110, thereby being beneficial to reducing the risk of damaging the film layer (e.g., a gate dielectric layer) located on the top of the device fin 110, and accordingly improving the performance of the first gate structure 350 and the second gate structure 360.

Accordingly, in this embodiment, the material of the stop layer 370 is the same as the material of the gate dielectric layer.

The first gate structure 350 is used to control the turning on and off of the conduction channel of the first device.

In this embodiment, the first gate structure 350 includes: a first work function layer 310 on the gate dielectric layer 250 on the top and sidewalls of the device fin 110 and the sidewalls and bottom of the stop layer 370 of the first region 100 a; the first metal electrode 330 is located on the first work function layer 310 of the sidewall of the device fin 110 of the first region 100a and between the first work function layer 310 located between the top of the device fin 110 and the stop layer 370, and the first metal electrode 340 spans across the device fin 110 of the first region 100 a.

The first work function layer 310 is used to adjust the work function of the first gate structure 350, thereby adjusting the threshold voltage of the first device. The first work function layer 310 may have a single-layer or stacked-layer structure, and the material of the first work function layer 310 includes one or more of titanium aluminide, tantalum carbide, aluminum, titanium carbide, titanium nitride, tantalum silicon nitride, and titanium silicon nitride.

The first metal electrode 330 is used as an external electrode of the first gate structure 350.

In this embodiment, the material of the first metal electrode 330 is W. In other embodiments, the material of the electrode material layer may also be Al, cu, ag, au, pt, ni or Ti, etc. In a specific implementation, the material of the first metal electrode 330 may also be a work function metal material. The work function metal material may be titanium aluminide, tantalum carbide, aluminum, titanium carbide, titanium nitride, tantalum silicon nitride, or titanium silicon nitride.

The second gate structure 360 is used to control the turning on and off of the conduction channel of the second device.

In this embodiment, the first gate structure 350 and the second gate structure 360 are located on the isolation layer 105.

In this embodiment, the second gate structure 360 includes: a second work function layer 320 on the gate dielectric layer 250 on the top and sidewalls of the device fin 110 and the sidewalls and bottom of the stop layer 370 of the second region 100 b; a second metal electrode 340 on the second work function layer 320 on the side wall of the device fin 110 of the second region 100b and between the second work function layer 320 between the top of the device fin 110 and the stop layer 370, the second metal electrode 340 crossing the device fin 110 of the second region 100 b.

The second work function layer 320 is used to adjust the work function of the second gate structure 360 to adjust the threshold voltage of the second device. The second work function layer 320 may have a single-layer or stacked-layer structure, and the material of the second work function layer 320 includes one or more of titanium aluminide, tantalum carbide, aluminum, titanium carbide, titanium nitride, tantalum silicon nitride, and titanium silicon nitride.

The second metal electrode 340 is used as an external electrode of the second gate material layer.

In this embodiment, the material of the second metal electrode 340 is a work function metal material. The work function metal material may be titanium aluminide, tantalum carbide, aluminum, titanium carbide, titanium nitride, tantalum silicon nitride, or titanium silicon nitride. In other embodiments, the material of the second metal electrode may also be W, al, cu, ag, au, pt, ni or Ti.

In this embodiment, the first gate structure 350 and the second gate structure 360 have different stack types and/or material types, so as to meet the requirement of forming different types of gate structures on different regions, so as to implement different device functions.

In this embodiment, the first gate structure 350 and the second gate structure 360 have different stack types and/or material types, which means that the first gate structure 350 and the second gate structure 360 have different stack types, or the first gate structure 350 and the second gate structure 360 have different material types, or the first gate structure 350 and the second gate structure 360 have different stack types and different material types.

More specifically, in this embodiment, the first gate structure 350 and the second gate structure 360 may include different work function layer material types, or may include different numbers of work function layers, or include different work function layer types, or different numbers of work function layers, or different thicknesses of the work function layers, so as to achieve the purpose of adjusting the work functions of the gate structures in different areas, so that the first device and the second device have different work functions, and further, the first device and the second device have different threshold voltages, so as to adjust the threshold voltages of the devices in different areas.

In this embodiment, the materials and/or the number of layers of the first work function layer 310 and the second work function layer 320 are different, so as to adjust the work functions of the first gate structure 350 and the second gate structure 360, and further adjust the threshold voltages of the first device and the second device.

As one example, the first work function layer 310 includes a second work function film 270 and a third work function film 280 on the second work function film 270.

As one example, the second work function layer 320 includes a first work function film 260 and a second work function film 270 on the first work function film 260.

As one example, the material of the first work function film 260 includes titanium aluminide, tantalum carbide, aluminum, titanium carbide, titanium nitride, tantalum silicon nitride, or titanium silicon nitride.

As one example, the material of the second work function film 270 includes titanium aluminide, tantalum carbide, aluminum, titanium carbide, titanium nitride, tantalum silicon nitride, or titanium silicon nitride. In this embodiment, the material of the second work function film 270 is the same as the material of the first work function film 260. In other embodiments, the material of the second work function film may also be different from the material of the first work function film.

The material of the third work function film 280 may be titanium aluminide, tantalum carbide, aluminum, titanium carbide, titanium nitride, tantalum silicon nitride, or titanium silicon nitride.

As an example, the material of the third work function film 280 is the same as that of the second metal electrode 340. In other embodiments, the material of the third work function film may also be different from the material of the second metal electrode.

In this embodiment, the materials and structures of the first gate structure 350 and the second gate structure 360 are merely examples, and the number of layers and materials of the work function layers in the first gate structure 350 and the second gate structure 360 are also merely examples. In a specific embodiment, the structure type, material type of the first gate structure 350 and the second gate structure 360 may be adjusted based on actual process requirements.

In this embodiment, the portion of the first gate structure 350 and the second gate structure 360 on the substrate 100 between the adjacent device fins 110 is used as a first portion (not shown), and the portion located between the top of the device fins 110 and the stop layer 370 is used as a second portion (not shown).

More specifically, the portion of the first gate structure 350 and the second gate structure 360 located on the isolation layer 105 between the device fins 110 serves as a first portion (not labeled) and the portion located above the top of the device fins 110 and between the stop layer 370 serves as a second portion (not labeled).

In this embodiment, the semiconductor structure further includes: the gate sidewall 400 is located on the sidewalls of the first gate structure 350 and the second gate structure 360. The gate sidewall 400 is used to protect sidewalls of the first gate structure 350 and the second gate structure 360, and also used to define a formation location of the source-drain doped region 230 together with the first gate structure 350 and the second gate structure 360.

The material of the gate sidewall 400 may be one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbide or silicon oxycarbonitride, boron nitride and boron carbonitride, and the gate sidewall 400 may have a single-layer structure or a stacked-layer structure.

As an example, the gate sidewall 400 includes: a first side wall 155 located on the side wall of the first portion; the second sidewall 210 is located on the sidewall of the second portion.

In this embodiment, the material of the first sidewall 155 may be one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbide or silicon oxycarbonitride, boron nitride and boron carbonitride. In this embodiment, the first sidewall 155 has a single-layer structure, and the material of the first sidewall 155 is silicon nitride.

In this embodiment, the material of the second sidewall 210 may be one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbide or silicon oxycarbonitride, boron nitride and boron carbonitride. In this embodiment, the second side wall 210 has a single-layer structure, and the material of the second side wall 210 is silicon nitride.

In this embodiment, the gate dielectric layer 250 comprises a high-k gate dielectric layer. High-k gate dielectricThe material of the layer is a high-k dielectric material; the high-k dielectric material refers to a dielectric material with a relative dielectric constant larger than that of silicon oxide. As an example, the material of the high-k gate dielectric layer is hafnium oxide (HfO ₂ )。

In other embodiments, the gate dielectric layer may further include a gate oxide layer and a high-k gate dielectric layer on the gate oxide layer. In still other embodiments, the gate dielectric layer may also include only a gate oxide layer. Wherein, the material of the gate oxide layer comprises one or two of silicon oxide and silicon oxynitride.

In this embodiment, the gate dielectric layer 250 is further disposed between the first gate structure 350 and the gate sidewall 400, and between the second gate structure 360 and the gate sidewall 400.

The source-drain doped region 230 is used to serve as a source or drain of a field effect transistor, and the source-drain doped region 230 is used to provide a carrier source when the field effect transistor is operating.

In this embodiment, the source-drain doped region 230 includes a stress layer doped with ions, and the source-drain doped region 230 is further used to provide stress to the channel, so as to improve the carrier mobility of the channel.

Specifically, when the NMOS transistor is formed, the material of the source-drain doped region 230 is a stress layer doped with N-type ions, the material of the stress layer includes Si or SiC, and the stress layer provides a tensile stress effect for the channel region of the NMOS transistor, so that it is beneficial to improve the carrier mobility of the NMOS transistor, where the N-type ions are P ions, as ions, or Sb ions.

When forming a PMOS transistor, the material of the source-drain doped region 230 is a stress layer doped with P-type ions, where the material of the stress layer includes Si or SiGe, and the stress layer provides a compressive stress to the channel region of the PMOS transistor, so as to facilitate improving carrier mobility of the PMOS transistor, where the P-type ions are B ions, ga ions, or In ions.

As a specific embodiment, the first type MOS transistor is a PMOS transistor, and the second type MOS transistor is an NMOS transistor. Accordingly, the material of the source/drain doped region 230 in the first region 100a is a stress layer doped with N-type ions; the material of the source/drain doped region 230 in the second region 100b is a stress layer doped with P-type ions.

In this embodiment, the semiconductor structure further includes: an interlayer dielectric layer 180 is on the isolation layer 105 on the sides of the first gate structure 350 and the second gate structure 360 and covers the source drain doped regions 230.

The interlayer dielectric layer 180 is used to isolate adjacent first gate structures 350, adjacent second gate structures 360, and thereby electrically isolate adjacent devices.

The interlayer dielectric layer 180 may have a single layer or a stacked structure. The material of the interlayer dielectric layer 180 is an insulating material, such as one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon oxycarbonitride. As an example, the material of the interlayer dielectric layer 180 is silicon oxide.

Correspondingly, the invention further provides a method for forming the semiconductor structure. Fig. 14 to 39 are schematic structural views corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention.

The method for forming the semiconductor structure of the present embodiment will be described in detail below with reference to the accompanying drawings.

Referring to fig. 14 to 17, a substrate is provided, the substrate including a first region 100a and a second region 100b; the base includes a substrate 100 and a device fin 110 that is discrete on the substrate 100.

The substrate is used for providing a process platform for the subsequent process. In this embodiment, the first region 100a is used to form a first device, and the second region 100b is used to form a second device.

In this embodiment, in the step of providing the substrate, the initial sacrificial fin 120 and the initial barrier layer 130 on top of the initial sacrificial fin 120 are formed on top of the device fin 110, the device fin 110 and the initial sacrificial fin 120 and the initial barrier layer 130 are used to form the fin stack 140, and the fin stacks 140 are separated on the substrate 100.

The initial sacrificial fin 120 is used for subsequent sacrificial fin formation. The sacrificial fin is used for defining the heights of a first gate structure and a second gate structure which are formed later.

The sacrificial fin is also removed later, so that the material with etching selectivity to the device fin 110 is selected for the initial sacrificial fin 120, so that the probability of causing erroneous etching to the device fin 110 in the process of removing the sacrificial fin is reduced.

As one example, the material of the initial sacrificial fin 120 is silicon germanium. Silicon germanium is a commonly used semiconductor material and has an etching selectivity with silicon to achieve a high etching selectivity between the sacrificial fin portion and the device fin portion 110, and meanwhile, the method is beneficial to improving process compatibility and reducing process cost.

In other embodiments, the material of the initial sacrificial fin may also be other materials that are etch selective to the material of the device fin, such as: one or more of silicon phosphide, silicon oxycarbide, and hafnium oxide.

The initial barrier layer 130 is used for subsequent barrier layer formation. The barrier layer is used to protect the top of the device fin 110 in the subsequent step of forming the first gate structure in the first region 100a and the second gate structure in the second region 100 b.

For this reason, the material having etching selectivity with the material of the initial sacrificial fin 120 is selected for the initial barrier layer 130, so as to reduce the probability of damaging the subsequent barrier layer in the process of removing the sacrificial fin, so that the barrier layer can be retained, and thus the barrier layer can protect the top of the device fin 110 in the subsequent step of forming the first gate structure and the second gate structure.

As one example, the material of the initial barrier layer 130 includes one or more of silicon, silicon oxide, silicon nitride, and silicon oxynitride. As one embodiment, the material of the initial barrier layer 130 is silicon oxide. The silicon oxide is a common insulating dielectric material, is favorable for improving process compatibility and reducing process cost, and has higher etching selectivity between the silicon oxide and the silicon germanium.

In this embodiment, the step of forming the substrate 100 and the fin stack 140 includes:

as shown in fig. 14 to 15, fig. 14 is a top view, fig. 15 (a) is a sectional view of fig. 14 along the X-X direction, and fig. 15 (b) is a sectional view of fig. 14 along the Y-Y direction, providing an initial laminated structure including: a substrate 100, a semiconductor layer 101 on the substrate 100, a sacrificial fin material layer 102 on the semiconductor layer 101, and a barrier material layer 103 on the sacrificial fin material layer 102; as shown in fig. 16 to 17, fig. 16 is a top view, fig. 17 (a) is a cross-sectional view along the X-X direction of fig. 16, fig. 17 (b) is a cross-sectional view along the Y-Y direction of fig. 16, the barrier material layer 103, the sacrificial fin material layer 102 and the semiconductor layer 101 are patterned, the remaining barrier material layer 103 is used as an initial barrier layer 130, the remaining sacrificial fin material layer 102 is used as an initial sacrificial fin 120, and the remaining semiconductor layer 101 is used as a device fin 110.

In this embodiment, the process of forming the semiconductor layer 101 and the sacrificial fin material layer 102 includes an epitaxial process.

In this embodiment, a deposition process (e.g., a chemical vapor deposition process) is used to form the barrier material layer 103 on the sacrificial fin material layer 102.

Note that, in this embodiment, referring to fig. 16 to 17, the forming method further includes: after the device fin 110 is formed, and before the dummy gate structure is formed, an isolation layer 105 surrounding the device fin 110 is formed on the substrate 100, the top of the isolation layer 105 being lower than the top of the device fin 110.

Specifically, after the fin stack 140 is formed, and before the sacrificial gate is formed across the fin stack 140, an isolation layer 105 is formed on the substrate 100 surrounding the device fin 110.

The isolation layer 105 is used to isolate between adjacent device fins 110, and also to isolate the substrate 100 from a subsequently formed sacrificial gate, and to isolate the substrate 100 from subsequently formed first and second gate structures.

Referring to fig. 18-21, a dummy gate structure 200 is formed on substrate 100 across device fin 110, dummy gate structure 200 including a sacrificial fin 160 on top of device fin 110, a barrier layer 170 on top of sacrificial fin 160, and a sacrificial gate 150 covering the top of barrier layer 170, sidewalls of sacrificial fin 160 and barrier layer 170, and portions of the sidewalls of device fin 110.

The dummy gate structure 200 is used to define the formation location of the source-drain doped region.

Wherein sacrificial gate 150 and sacrificial fin 160 are used to occupy spatial locations for subsequent formation of a first layer of gate material in first region 100a and a second layer of gate material in second region 100 b.

For a description of the material of sacrificial fin 160, reference is made to the foregoing detailed description of initial sacrificial fin 120, which is not repeated here.

In this embodiment, sacrificial gate 150 spans device fin 110, sacrificial fin 160, and barrier 170.

In this embodiment, the material of the sacrificial gate 150 includes polysilicon or amorphous silicon. As an example, the material of the sacrificial gate 150 is polysilicon.

The barrier layer 170 is used for protecting the top of the device fin 110 during the subsequent formation of the first gate material layer and the second gate material layer, so as to reduce the probability of damaging the top of the device fin 110, and further reduce the probability of damaging the film layer located on the top of the device fin 110.

Specifically, the subsequent formation of the first gate material layer and the second gate material layer generally includes a step of forming a mask covering layer on the first region 100a or the second region 100b, so as to etch the exposed region of the mask covering layer, where the mask covering layer exposes the second region 100b or the first region 100a, respectively, so as to form a first gate material layer and a second gate material layer with different stack types and/or material types, where the forming of the mask covering layer generally includes a step of using an anisotropic etching process to etch and remove the covering material layer located in the gate opening of the second region 100b or the first region 100a, where the barrier layer 170 is suspended above the top of the device fin 110 at intervals during the anisotropic etching process, so as to protect the top of the device fin 110, thereby being beneficial to reduce the risk of damaging the film layer located on the top of the device fin 110, and accordingly improving the performance of the first gate material layer or the second gate material layer, and further improving the performance of the semiconductor structure.

In this embodiment, the material of the barrier layer 170 includes one or more of silicon, silicon oxide, silicon nitride, and silicon oxynitride. For a detailed description of the material of the barrier layer 170, please refer to the previous description of the initial barrier layer 130, and the detailed description is omitted herein.

It should be noted that, in the step of forming the barrier layer 170, the thickness of the barrier layer 170 should not be too small or too large. If the thickness of the barrier layer 170 is too small, the barrier layer 170 is easy to be completely consumed in the subsequent process of forming the first gate material layer and the second gate material layer, so that the blocking effect of the barrier layer 170 on the anisotropic etching process is easy to be reduced, and the protection effect of the barrier layer 170 on the device fin 110 is correspondingly easy to be reduced; if the thickness of the barrier layer 170 is too large, the height of the dummy gate structure 200 is easily caused to be too large, and after the first gate material layer and the second gate material layer are formed subsequently, the first gate material layer and the second gate material layer which are higher than the gate dielectric layer on the bottom surface of the barrier layer 170 and the barrier layer 170 are generally removed, and the thickness of the barrier layer 170 is too large, so that the thickness of the removed material is easily caused to be too large, and further the process difficulty, the process time and the manufacturing efficiency are easily increased. For this reason, in the present embodiment, the thickness of the barrier layer 170 is 1nm to 5nm.

Accordingly, in the present embodiment, in the step of forming the initial barrier layer 130 described above, the thickness of the initial barrier layer 130 is 1nm to 5nm.

In this embodiment, the step of forming the dummy gate structure 200 includes:

As shown in fig. 18 to 19, fig. 18 is a top view, fig. 19 (a) is a cross-sectional view along the X-X direction of fig. 18, fig. 19 (b) is a cross-sectional view along the Y-Y direction of fig. 18, a sacrificial gate 150 is formed on the substrate 100 across the fin stack 140, and the sacrificial gate 150 covers a portion of the top and a portion of the sidewalls of the fin stack 140.

The sacrificial gate 150 is used to define subsequent etching locations for the initial barrier 130 and the initial sacrificial fin 120. In this embodiment, a sacrificial gate 150 is formed on the spacer layer 105 and spans the fin stack 140.

In this embodiment, the step of forming the sacrificial gate 150 includes: forming a sacrificial gate material layer (not shown) overlying the spacer layer 105 and the fin stack 140; the sacrificial gate material layer is patterned, leaving the sacrificial gate material layer on portions of the top and portions of the sidewalls of fin stack 140 to serve as sacrificial gate 150.

As shown in fig. 20-21, fig. 20 is a top view, fig. 21 (a) is a cross-sectional view of fig. 20 along the X-X direction, fig. 21 (b) is a cross-sectional view of fig. 20 along the Y-Y direction, initial barrier layer 130 and initial sacrificial fin 120 exposed by sacrificial gate 150 are removed, remaining initial barrier layer 130 is used as barrier layer 170, and remaining initial sacrificial fin 120 is used as sacrificial fin 160.

In this embodiment, an anisotropic etching process is used to remove the initial blocking layer 130 and the initial sacrificial fin 120 exposed by the sacrificial gate 150, which is beneficial to improving the accuracy of pattern transfer. As an example, the anisotropic etching process may be an anisotropic dry etching process.

Referring to fig. 18 to 19 in combination, in this embodiment, the method for forming a semiconductor structure further includes: after forming the sacrificial gate 150, and before removing the initial blocking layer 130 and the initial sacrificial fin 120 exposed by the sacrificial gate 150, a first sidewall 155 is formed on the sidewall of the sacrificial gate 150.

The first sidewall 155 is used to protect the sidewall of the sacrificial gate 150, and is further used to define, together with the sacrificial gate 150, the initial blocking layer 130 exposed by the sacrificial gate 150 and the removed area of the initial sacrificial fin 120, and the first sidewall 155 is further used to define the formation location of the source-drain doped region.

The material of the first sidewall 155 may be one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbide or silicon oxycarbonitride, boron nitride and boron carbonitride, and the first sidewall 155 may have a single-layer structure or a stacked-layer structure. In this embodiment, the first side wall 155 has a single-layer structure, and the material of the first side wall 155 is silicon nitride.

Referring to fig. 22-25, source-drain doped regions 230 are formed in device fin 110 on both sides of dummy gate structure 200, source-drain doped regions 230 exposing sacrificial fin 160 and barrier layer 170.

As an example, in this embodiment, the step of forming the source-drain doped region 230 includes:

as shown in fig. 22 to 23, fig. 22 is a top view, fig. 23 (a) is a cross-sectional view along the X-X direction of fig. 22, fig. 23 (b) is a cross-sectional view along the Y-Y direction of fig. 22, and source-drain recesses 220 are formed in the device fin 110 at both sides of the dummy gate structure 200.

The source drain recesses 220 are used to provide spatial locations for forming source drain doped regions.

Specifically, in this embodiment, after the initial blocking layer 130 and the initial sacrificial fin 120 exposed by the sacrificial gate 150 are removed, the source-drain recess 220 is formed in the device fin 110 exposed by the sacrificial gate 150, so that the device fin 110 can be etched after the initial blocking layer 130 and the initial sacrificial fin 120 exposed by the sacrificial gate 150 are etched, which is beneficial to improving the process integration.

Specifically, an anisotropic etching process is used to etch the device fin 110 exposed by the dummy gate structure 200 to form the source-drain recess 220, which is beneficial to improving the profile quality of the source-drain recess 220. As an example, the anisotropic etching process is an anisotropic dry etching process.

As shown in fig. 24 to 25, fig. 24 is a top view, fig. 25 (a) is a cross-sectional view along the X-X direction of fig. 24, and fig. 25 (b) is a cross-sectional view along the Y-Y direction of fig. 24, and source and drain doped regions 230 are formed in the source and drain recesses 220.

Specifically, in this embodiment, an epitaxial process is used to form the stress layer, and the source-drain doped region 230 is formed by in-situ self-doping ions during the process of forming the stress layer.

It should be noted that, in this embodiment, after the formation of the source-drain recess 220 and before the formation of the source-drain doped region 230 in the source-drain recess 220, the method for forming a semiconductor structure further includes: sidewalls of sacrificial fin 160 and barrier layer 170 are thinned in a direction perpendicular to the extension direction of dummy gate structure 220 and parallel to substrate 100, forming sidewall recesses 225 (shown in fig. 23) in the sidewalls of sacrificial fin 160 and barrier layer 170; a second sidewall 210 is formed within the sidewall recess 225 (as shown in fig. 25).

The sidewall recess 225 is used to provide a spatial location for forming the second sidewall 210.

In this embodiment, the sidewalls of sacrificial fin 160 and barrier layer 170 are etched to form sidewall recesses 225 in a direction perpendicular to the extension direction of dummy gate structure 200 and parallel to substrate 100 using an isotropic etching process. The isotropic etching process may enable etching of sidewalls of sacrificial fin 160 and barrier 170 in a direction perpendicular to the extension direction of dummy gate structure 200 and parallel to substrate 100 to achieve thinning of the sidewalls of sacrificial fin 160 and barrier 170.

Second sidewall 210 is used to protect sidewalls of sacrificial fin 160 and barrier layer 170. After subsequent removal of sacrificial fin 160 to form a gate material layer, second sidewall 210 may also protect sidewalls of the gate material layer.

In addition, in this embodiment, after forming source-drain recess 220 and before forming source-drain doped region 230 in source-drain recess 220, forming second sidewall 210 is also advantageous in preventing sidewalls of sacrificial fin 160 and barrier layer 170 from being exposed to the process environment in which source-drain doped region 230 is formed, thereby preventing formation of source-drain doped region 230 over sacrificial fin 160 and barrier layer 170.

Specifically, in this embodiment, the material of sacrificial fin 160 is a semiconductor material, and the process of forming source-drain doped region 230 includes an epitaxial process, by forming second sidewall 210 before forming source-drain doped region 230, thereby preventing epitaxial growth on the sidewalls of sacrificial fin 160 during the formation of source-drain doped region 230.

The material of the second side wall 210 may be one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbide or silicon oxycarbonitride, boron nitride and boron carbonitride, and the second side wall 210 may have a single-layer structure or a stacked-layer structure. In this embodiment, the second side wall 210 has a single-layer structure, and the material of the second side wall 210 is silicon nitride.

In other embodiments, after the initial barrier layer and the initial sacrificial fin portion exposed by the sacrificial gate are removed and before the source-drain groove is formed, thinning the sidewalls of the sacrificial fin portion and the barrier layer along a direction perpendicular to the dummy gate structure and parallel to the substrate, and forming sidewall grooves on the sidewalls of the sacrificial fin portion and the barrier layer; and forming a second side wall in the side wall groove. Accordingly, the second side wall can also play a role in protecting the side walls of the sacrificial fin portion and the blocking layer in the process of forming the source-drain grooves, and the side walls of the sacrificial fin portion and the blocking layer are prevented from being exposed in the process environment of forming the source-drain grooves.

The second side wall and the first side wall are used for forming a grid side wall.

It should be noted that, in this embodiment, the above process steps for forming the gate sidewall are only taken as an example. In other embodiments, the second sidewall may be formed on the sidewall of the dummy gate structure after removing the initial barrier layer and the initial sacrificial fin exposed by the sacrificial gate and before forming the source-drain recess.

Referring to fig. 26 to 27, fig. 26 is a top view, fig. 27 (a) is a cross-sectional view along the X-X direction of fig. 26, and fig. 27 (b) is a cross-sectional view along the Y-Y direction of fig. 26, in which the method for forming a semiconductor structure further includes: after forming source-drain doped regions 230 and before removing sacrificial gate 150 and sacrificial fin 170, an interlayer dielectric layer 180 is formed on isolation layer 105 on the sides of dummy gate structure 200, covering source-drain doped regions 230.

The interlayer dielectric layer 180 is used to isolate adjacent dummy gate structures 200, thereby achieving electrical isolation between adjacent devices. The interlayer dielectric layer 180 may have a single layer or a stacked structure. The material of the interlayer dielectric layer 180 is an insulating material, such as one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon oxycarbonitride. As an example, the material of the interlayer dielectric layer 180 is silicon oxide.

Referring to fig. 28-29, fig. 28 is a top view, fig. 29 (a) is a cross-sectional view of fig. 28 along the X-X direction, fig. 29 (b) is a cross-sectional view of fig. 28 along the Y-Y direction, sacrificial gate 150 and sacrificial fin 160 are removed, a gate opening 240 exposing barrier layer 170 and device fin 110 is formed, and barrier layer 170 and device fin 110 are suspended in space.

The gate opening 240 is used to provide a spatial location for the subsequent formation of a first layer of gate material in the first region 100a and a second layer of gate material in the second region 100 b.

The blocking layer 170 and the device fin 110 are arranged in a suspended manner at intervals, so that the blocking layer 170 can play a role in blocking an anisotropic etching process in the subsequent anisotropic etching process of forming the first gate material layer and the second gate material layer, thereby protecting the top of the device fin 110, reducing the damage probability of the top of the device fin 110, and correspondingly reducing the damage probability of the film layer at the top of the device fin 110.

In this embodiment, the step of forming the gate opening 240 includes: sacrificial gate 150 is removed to form top opening 41 exposing barrier layer 170 and sacrificial fin 160; exposed sacrificial fin 160 is removed through top opening 41, forming bottom opening 42 between device fin 110 and barrier layer 170, bottom opening 42 and top opening 41 being used to form gate opening 240.

The bottom opening 42 communicates with the top opening 41.

As one example, the sacrificial gate 150 is removed using one or both of an anisotropic etching process and an isotropic etching process. For example: removing part of the thickness of the sacrificial gate 150 by adopting an anisotropic etching process; the remaining sacrificial gate 150 is removed using an isotropic etching process.

As an example, a partial thickness of the sacrificial gate 150 is removed using an anisotropic dry etching process; the remaining sacrificial gate 150 is removed using an isotropic etching process.

In this embodiment, an isotropic etch process is used to remove exposed sacrificial fin 160 through top opening 41. The isotropic etching process has the characteristic of isotropic etching, so that the sidewalls of sacrificial fin 160 exposed by top opening 41 can be etched, and further, the sidewalls of sacrificial fin 160 exposed by top opening 41 are removed, and the probability of residual sacrificial fin 160 is reduced.

As one example, exposed sacrificial fin 160 is removed through top opening 41 using a wet etch process. In this embodiment, the material of sacrificial fin 160 is SiGe and the sidewalls of sacrificial fin 160 exposed by top opening 41 are etched with HCl solution.

Referring to fig. 30 to 31, fig. 30 is a top view, fig. 31 (a) is a cross-sectional view along the X-X direction of fig. 30, fig. 31 (b) is a cross-sectional view along the Y-Y direction of fig. 30, and a gate dielectric layer 250 is formed on top and side walls of the device fin 110 and on the surface of the barrier layer 170 exposed by the gate opening 240.

The gate dielectric layer 250 is used to electrically isolate the subsequently formed first gate material layer from the device fin 110 and the second gate material layer from the device fin 110.

In this embodiment, in the step of forming the gate dielectric layer 250, the gate dielectric layer 250 located at the bottom of the barrier layer 170 is used as the stop layer 370. The stop layer 370 is used for defining a stop position in a planarization process of forming the first gate structure and the second gate structure, so as to improve the height consistency of the first gate structure and the second gate structure and reduce the difficulty of the planarization process of forming the first gate structure and the second gate structure.

In this embodiment, the gate dielectric layer 250 comprises a high-k gate dielectric layer. The material of the high-k gate dielectric layer is a high-k dielectric material; the high-k dielectric material refers to a dielectric material with a relative dielectric constant larger than that of silicon oxide. As an example, the material of the high-k gate dielectric layer is hafnium oxide (HfO ₂ )。

In this embodiment, the process of forming the gate dielectric layer 250 includes an atomic layer deposition process. The atomic layer deposition process has higher step coverage capability, which is beneficial to improving the conformal coverage capability of the gate dielectric layer 250 on the top and the side wall of the device fin 110 exposed by the gate opening 240 and the surface of the barrier layer 170, and is also beneficial to improving the thickness consistency of the gate dielectric layer 250 and forming the gate dielectric layer 250 with smaller thickness to prevent the gate dielectric layer 250 positioned on the top of the device fin 110 and the bottom of the barrier layer 170 from contacting.

Referring to fig. 30 through 35 in combination, a first gate material layer located within the gate opening 240 of the first region 100a and a second gate material layer located within the gate opening 240 of the second region 100b are formed on the gate dielectric layer 250, the first gate material layer and the second gate material layer having different stack types and/or material types.

The forming of the first gate material layer and the second gate material layer generally includes forming a mask covering layer on the first region 100a or the second region 100b, so as to etch a region exposed by the mask covering layer, where the mask covering layer exposes the second region 100b or the first region 100a, respectively, so as to form a first gate material layer and a second gate material layer with different stack types and/or material types, and the forming of the mask covering layer generally includes a step of etching to remove the covering material layer located in the gate opening 240 of the second region 100b or the first region 100a by using an anisotropic etching process, where the blocking layer 170 is suspended above the top of the device fin 110 at intervals during the anisotropic etching process, so that the top of the device fin 110 can be protected, which is beneficial to reducing the risk of damaging the film layer located on the top of the device fin 110, and accordingly improving the performance of the first gate material layer or the second gate material layer, and further improving the performance of the semiconductor structure.

The first gate material layer is used for forming a first gate structure subsequently; the second gate material layer is used for forming a second gate structure later.

In this embodiment, the first gate material layer and the second gate material layer have different stack types and/or material types, so as to meet the requirement of forming different types of gate structures on different regions, so as to implement different device functions.

In this embodiment, the first gate material layer and the second gate material layer have different stack types and/or material types, which means that the first gate material layer and the second gate material layer have different stack types, or the first gate material layer and the second gate material layer have different material types, or the first gate material layer and the second gate material layer have both different stack types and different material types.

More specifically, in this embodiment, the first gate material layer and the second gate material layer may include different work function layer material types, may include work function layers with different layers, or include different work function layer types, or include different layers of work function layers, or different thicknesses of the work function layers, so as to achieve the purpose of adjusting the work functions of the gate structures in different areas, and further enable the first device and the second device to have different threshold voltages, so as to adjust the threshold voltages of the devices in different areas.

In this embodiment, the step of forming the first gate material layer and the second gate material layer includes:

as shown in fig. 30 to 31, a first work function film 260 is formed on the gate dielectric layer 250.

The first work function film 260 located in the second region 100b is used to form a second work function layer later to adjust the work function of the second gate structure.

As shown in fig. 32 to 33, fig. 32 is a top view, fig. 33 (a) is a cross-sectional view along the X-X direction of fig. 32, fig. 33 (b) is a cross-sectional view along the Y-Y direction of fig. 32, and the first work function film 260 located in the first region 100a is removed, exposing the gate dielectric layer 250 of the first region 100 a.

The first work function film 260 located in the first region 100a is removed so that a second work function film is subsequently formed on the gate dielectric layer 260 of the first region 100 b. The second work function film may be different from the first work function film in material and/or thickness.

In this embodiment, the step of removing the first work function film 260 located in the first region 100a includes: forming a mask blanket layer 30 filling the gate opening 240 of the second region 100b, exposing the gate opening 240 of the first region 100 a; the first work function film 260 exposed by the mask cover layer 30 is removed.

The mask cover layer 30 serves as a masking film for etching the first work function film 260.

As an example, the material of the mask cover layer 30 is SOC (spin on carbon).

In this embodiment, the step of forming the mask cover layer 30 includes: forming a layer of capping material (not shown) that fills the gate opening 240; the capping material layer in the first region 100a is removed using an anisotropic etching process, exposing the gate opening 240 of the first region 100a, and the remaining capping material layer is used as a mask to cap layer 30.

In the step of removing the covering material layer located in the first area 100a by using an anisotropic etching process, the barrier layer 170 is suspended above the device fin 110 at intervals, so that the anisotropic etching process can be blocked, and further the top of the device fin 110 is prevented from being etched by the anisotropic etching process, accordingly, the damage probability of the top of the device fin 110 is reduced, and the damage probability of a film layer (for example, the gate dielectric layer 250) located at the top of the device fin 110 is reduced.

In this embodiment, the process of removing the first work function film 260 exposed by the mask cover layer 30 includes isotropic etching process. The isotropic etching process has the characteristic of isotropic etching, and can etch the film material located on the surface of the uneven structure, thereby being beneficial to cleanly removing the first work function film 260 exposed by the mask cover layer 30.

After removing the first work function film 260 exposed by the mask cap layer 30, the mask cap layer 30 is removed to expose the gate opening 240 of the second region 100 b.

As shown in fig. 34 to 35, fig. 34 is a plan view, fig. 35 (a) is a sectional view of fig. 34 along the X-X direction, fig. 35 (b) is a sectional view of fig. 34 along the Y-Y direction, a second work function film 270 is formed on the gate dielectric layer 250 exposed by the gate opening 240 of the first region 100a and on the first work function film 260 exposed by the gate opening 240 of the second region 100b, the second work function film 270 located in the first region 100a is used to form the first work function layer 310, and the first work function film 260 and the second work function film 270 located in the second region 100b are used to form the second work function layer 320.

In this embodiment, the thickness of the first work function layer 310 is different from the thickness of the second work function layer 320, and the types of materials contained in the first work function layer 310 and the second work function layer 320 are different, and the stacked structure is also different, so as to adjust the work functions of the first gate material layer and the second gate material layer.

As shown in fig. 34 to 35, a first metal electrode 330 filling the gate opening 240 of the first region 100a is formed on the first work function layer 310 for constituting a first gate material layer (not shown) with the first work function layer 310 of the first region 100 a; the gate opening 240 of the second region 100a is filled with a second metal electrode 340 for forming a second gate material layer (not shown) with the second work function layer 320.

The first metal electrode 330 is used as an external electrode of the first gate material layer.

Note that, in this embodiment, before forming the first metal electrode 330 that fills the gate opening 240 of the first region 100a on the first work function layer 310, the method further includes: a third work function film 280 is formed on the second work function film 270 exposed from the gate opening 240 of the first region 100a, and the second work function film 270 and the third work function film 280 located in the first region 100a serve to constitute the first work function layer 310.

The third work function film 280 is formed for further adjusting the work function of the first gate material layer to adjust the threshold voltage of the device of the first region 100 a. In other embodiments, the step of forming the third work function film may also be omitted based on actual process requirements.

The above steps of forming the first gate material layer and the second gate material layer are only examples, and the number of layers and materials of the work function layers in the first gate material layer and the second gate material layer are also only examples. In a specific embodiment, the structure type and the material type of the first gate material layer and the second gate material layer may be adjusted based on actual process requirements.

Referring to fig. 36 to 39, in the present embodiment, the forming method further includes: after forming the first and second gate material layers, the first and second gate material layers and the barrier layer 170 are removed above the top surface of the stop layer 370, the remaining first gate material layer is used as the first gate structure 350 and the remaining second gate material layer is used as the second gate structure 360.

The first gate structure 350 is used to control the opening and closing of the conductive channel of the devices of the first region 100 a. The second gate structure 360 is used to control the turning on and off of the conductive channel of the devices of the second region 100 b.

In this embodiment, in the process of forming the first gate material layer and the second gate material layer, the barrier layer 170 is suspended above the top of the device fin 110 at intervals, which can protect the top of the device fin 110, thereby being beneficial to reducing the risk of damaging the film layer at the top of the device fin 110, correspondingly improving the performance of the first gate material layer or the second gate material layer, correspondingly improving the formation quality of the first gate structure 350 and the second gate structure 360, and further improving the performance of the semiconductor structure.

In this embodiment, the stop layer 370 also can serve to define the heights of the first gate structure 350 and the second gate structure 360, which is further beneficial to precisely controlling the heights of the first gate structure 350 and the second gate structure 360 and improving the uniformity of the heights of the first gate structure 350 and the second gate structure 360.

In this embodiment, the process of removing the first gate material layer and the second gate material layer of the gate dielectric layer 250 above the top surface of the stop layer 370, and the barrier layer 170 includes a planarization process. Accordingly, after forming the first gate structure 350 and the second gate structure 360, the top surfaces of the first gate structure 350 and the second gate structure 360 over the top of the device fin 110 have a recess D (as shown at arrow D in fig. 39). Gate dielectric layer 250 is located within recess D and gate dielectric layer 250 located within recess D serves as stop layer 370.

Specifically, along the extension direction of the first gate structure 350 and the second gate structure 360, the top surfaces of the first gate structure 350 and the second gate structure 360 located above the top of the device fin 110 have a recess D.

Accordingly, in this embodiment, the first gate structure 350 includes: a first work function layer 310 on the gate dielectric layer 250 on the top and sidewalls of the device fin 110 and the sidewalls and bottom of the stop layer 370 of the first region 100 a; the first metal electrode 330 is located on the first work function layer 310 of the sidewall of the device fin 110 of the first region 100a and between the first work function layer 310 located between the top of the device fin 110 and the stop layer 370, and the first metal electrode 340 spans the device fin 110 of the first region 100 a.

Accordingly, in this embodiment, the second gate structure 360 includes: a second work function layer 320 on the gate dielectric layer 250 on the top and sidewalls of the device fin 110 and the sidewalls and bottom of the stop layer 370 of the second region 100 b; a second metal electrode 340 is located on the second work function layer 320 on the sidewall of the device fin 110 of the second region 100b and between the second work function layer 320 located between the top of the device fin 110 and the stop layer 370, the second metal electrode 340 crossing the device fin 110 of the second region 100 b.

Wherein the materials and/or the number of layers of the first work function layer 310 and the second work function layer 320 are different, thereby adjusting the work functions of the first gate structure 350 and the second gate structure 360, and thus adjusting the threshold voltages of the first device and the second device.

In this embodiment, the step of removing the first gate material layer and the second gate material layer, which are higher than the top surface of the stop layer 370, and the barrier layer 170 includes:

as shown in fig. 36 to 37, fig. 36 is a top view, fig. 37 (a) is a cross-sectional view along the X-X direction of fig. 36, fig. 37 (b) is a cross-sectional view along the Y-Y direction of fig. 36, and the first planarization process is performed on the first gate material layer and the second gate material layer with the top surface of the barrier layer 170 as a stop position.

In this embodiment, the material of the barrier layer 170 is an insulating dielectric material, the material of the first gate material layer and the material of the second gate material layer are metal materials, and the material difference between the material of the barrier layer 170 and the material of the first gate material layer and the material of the second gate material layer are large, so that the first planarization process is convenient to stop on the top surface of the barrier layer 170, the process difficulty of the first planarization process is easy to reduce, and the stop position of the first planarization process is convenient to define.

As an example, the process of the first planarization process is a chemical mechanical planarization process.

As shown in fig. 38 to 39, fig. 38 is a top view, fig. 39 (a) is a cross-sectional view along the X-X direction of fig. 38, fig. 39 (b) is a cross-sectional view along the Y-Y direction of fig. 38, and the first gate material layer and the second gate material layer and the barrier layer 170 are subjected to a second planarization process with the top surface of the stop layer 370 as a stop position.

The material of the stop layer 370 is greatly different from the materials of the first gate material layer and the second gate material layer, so that the second planarization process is stopped on the top surface of the stop layer 370, and the process difficulty of the second planarization process is reduced.

Specifically, in this embodiment, the gate dielectric layer 250 located on the bottom surface of the barrier layer 170 is used as the stop layer 370, the material of the gate dielectric layer 250 is a dielectric material, and the material of the first gate material layer and the material of the second gate material layer are metal materials, so that the second planarization process is easy to stop on the top surface of the stop layer 370, which is favorable for reducing the process difficulty of the second planarization process, and is convenient for defining the stop position of the second planarization process.

As an example, the process of the second planarization process is a chemical mechanical planarization process.

Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.

Claims

1. A semiconductor structure, comprising:

a substrate comprising a first region and a second region; the base comprises a substrate and a device fin part separated on the substrate;

the stopping layer is positioned above the top of the device fin part and is arranged in suspension at intervals with the top of the device fin part;

a first gate structure located on the substrate of the first region and crossing the device fin of the first region, wherein the first gate structure is filled between the device fin of the first region and the stop layer;

a second gate structure located on the substrate of the second region and crossing the device fin of the second region, wherein the second gate structure is filled between the device fin of the second region and the stop layer;

wherein the first gate structure and the second gate structure have different stack types and/or material types;

The gate dielectric layer is positioned between the first gate structure and the device fin part and between the second gate structure and the device fin part;

and the source-drain doped region is positioned in the fin parts of the devices at two sides of the first grid electrode structure and the second grid electrode structure.

2. The semiconductor structure of claim 1, wherein top surfaces of the first gate structure and the second gate structure above a top of the device fin have recesses; the gate dielectric layer is also positioned in the recess, and the gate dielectric layer positioned in the recess is used as the stop layer.

3. The semiconductor structure of claim 1 or 2, wherein top surfaces of the first gate structure and the second gate structure are flush with a top surface of the stop layer.

4. The semiconductor structure of claim 1, wherein a portion of the first gate structure and the second gate structure on the substrate between adjacent ones of the device fins is to be used as a first portion and a portion between a top of the device fins and a stop layer is to be used as a second portion;

the semiconductor structure further includes: the grid side wall is positioned on the side walls of the first grid structure and the second grid structure; the grid side wall comprises: the first side wall is positioned on the side wall of the first part; and the second side wall is positioned on the side wall of the second part.

5. The semiconductor structure of claim 1, wherein the first gate structure comprises: the first work function layer is positioned on the gate dielectric layer on the top and the side wall of the fin part of the device in the first region and the side wall and the bottom of the stopping layer; a first metal electrode on the first work function layer of the device fin side wall of the first region and between the first work function layer between the top of the device fin and the stop layer, the first metal electrode crossing the device fin of the first region;

the second gate structure includes: the second work function layer is positioned on the gate dielectric layer on the top and the side wall of the fin part of the device in the second region and the side wall and the bottom of the stop layer; a second metal electrode located on the second work function layer of the device fin side wall of the second region and between the second work function layer located between the top of the device fin and the stop layer, the second metal electrode crossing the device fin of the second region;

wherein the materials and/or the layers of the first work function layer and the second work function layer are different.

6. The semiconductor structure of claim 1, wherein the semiconductor structure further comprises: the isolation layer is positioned on the substrate and surrounds the device fin part, and the top of the isolation layer is lower than the top of the device fin part; the interlayer dielectric layer is positioned on the isolation layers at the side parts of the first grid electrode structure and the second grid electrode structure and covers the source-drain doping region;

The first gate structure and the second gate structure are located on the isolation layer.

7. A method of forming a semiconductor structure, comprising:

providing a substrate comprising a first region and a second region; the base comprises a substrate and a device fin part separated on the substrate;

forming a dummy gate structure crossing over the device fin on the substrate, wherein the dummy gate structure comprises a sacrificial fin on the top of the device fin, a barrier layer on the top of the sacrificial fin, and a sacrificial gate covering the top of the barrier layer, the sacrificial fin and the side walls of the barrier layer and the side walls of part of the device fin;

forming source-drain doped regions in the device fin parts at two sides of the pseudo gate structure, wherein the source-drain doped regions expose the sacrificial fin parts and the barrier layer;

removing the sacrificial grid and the sacrificial fin portion to form grid openings exposing the barrier layer and the device fin portion, wherein the barrier layer and the device fin portion are arranged in a suspending mode at intervals;

forming a gate dielectric layer on the top and the side wall of the fin part of the device exposed by the gate opening and on the surface of the barrier layer;

and forming a first gate material layer positioned in the gate opening of the first region and a second gate material layer positioned in the gate opening of the second region on the gate dielectric layer, wherein the first gate material layer and the second gate material layer have different lamination types and/or material types.

8. The method of claim 7, wherein in the step of providing a substrate, an initial sacrificial fin and an initial barrier layer on top of the initial sacrificial fin are formed on top of the device fin, the device fin and initial sacrificial fin and initial barrier layer being used to form a fin stack;

the step of forming the dummy gate structure includes: forming a sacrificial gate on the substrate across the fin stack, the sacrificial gate covering a portion of a top and a portion of a sidewall of the fin stack; and removing the initial blocking layer and the initial sacrificial fin portion exposed by the sacrificial grid electrode, wherein the remaining initial blocking layer is used as the blocking layer, and the remaining initial sacrificial fin portion is used as the sacrificial fin portion.

9. The method of forming a semiconductor structure of claim 8, wherein the step of forming source drain doped regions comprises: after the initial blocking layer and the initial sacrificial fin portion exposed by the sacrificial gate are removed, forming a source drain groove in the device fin portion exposed by the sacrificial gate; and forming the source-drain doped region in the source-drain groove.

10. The method of forming a semiconductor structure of claim 9, wherein after forming the source-drain recesses and before forming the source-drain doped regions in the source-drain recesses; or after removing the initial blocking layer and the initial sacrificial fin exposed by the sacrificial gate and before forming the source-drain groove, the method for forming the semiconductor structure further comprises the following steps:

Thinning the side walls of the sacrificial fin part and the barrier layer along the direction perpendicular to the extending direction of the pseudo gate structure and parallel to the substrate, and forming side wall grooves on the side walls of the sacrificial fin part and the barrier layer; and forming a second side wall in the side wall groove.

11. The method of forming a semiconductor structure of claim 10, further comprising: after the sacrificial gate is formed, and before the initial blocking layer and the initial sacrificial fin exposed by the sacrificial gate are removed, a first side wall is formed on the side wall of the sacrificial gate.

12. The method of forming a semiconductor structure of claim 9, wherein after removing the initial barrier layer and the initial sacrificial fin exposed by the sacrificial gate and prior to forming the source-drain recess, the method further comprises: and forming a grid side wall on the side wall of the pseudo grid structure.

13. The method of forming a semiconductor structure of claim 7, wherein the step of forming a gate opening comprises: removing the sacrificial grid electrode to form a top opening exposing the barrier layer and the sacrificial fin part; and removing the exposed sacrificial fin portion through the top opening to form a bottom opening between the device fin portion and the barrier layer, wherein the bottom opening and the top opening are used for forming the gate opening.

14. The method of forming a semiconductor structure of claim 7, wherein forming the first gate material layer and the second gate material layer comprises: forming a first work function film on the gate dielectric layer;

removing the first work function film positioned in the first region to expose the gate dielectric layer of the first region;

forming a second work function film on the gate dielectric layer exposed by the gate opening of the first region and the first work function film exposed by the gate opening of the second region, wherein the second work function film positioned in the first region is used for forming a first work function layer, and the first work function film and the second work function film positioned in the second region are used for forming a second work function layer;

forming a first metal electrode on the first work function layer, wherein the first metal electrode fills a gate opening of the first region and is used for forming a first gate material layer with the first work function layer of the first region;

and filling a second metal electrode in the gate opening of the second region, and forming a second gate material layer with the second work function layer.

15. The method of forming a semiconductor structure of claim 14, wherein removing the first work function film in the first region comprises: forming a mask covering layer filling the gate opening of the second region to expose the gate opening of the first region;

And removing the first work function film exposed by the mask covering layer.

16. The method of forming a semiconductor structure of claim 15, wherein forming the masking cap comprises: forming a covering material layer filling the gate opening; and removing the covering material layer positioned in the first region by adopting an anisotropic etching process, exposing a gate opening of the first region, and using the remaining covering material layer as the mask covering layer.

17. The method of claim 15, wherein removing the first work function film exposed by the masking cap layer comprises an isotropic etching process.

18. The method of forming a semiconductor structure of claim 7, wherein, in the step of forming the gate dielectric layer, the gate dielectric layer located on the bottom surface of the barrier layer is used as a stop layer; the method for forming the semiconductor structure further comprises the following steps: after the first gate material layer and the second gate material layer are formed, the first gate material layer and the second gate material layer which are higher than the top surface of the stop layer, and the barrier layer are removed, the remaining first gate material layer is used as a first gate structure, and the remaining second gate material layer is used as a second gate structure.

19. The method of forming a semiconductor structure of claim 18, wherein removing the first and second gate material layers above the top surface of the stop layer and the barrier layer comprises: taking the top surface of the barrier layer as a stop position, and carrying out first planarization treatment on the first gate material layer and the second gate material layer; and taking the top surface of the stop layer as a stop position, and carrying out second planarization treatment on the first gate material layer, the second gate material layer and the barrier layer.

20. The method of forming a semiconductor structure of any of claims 7-19, wherein a material of the sacrificial fin comprises one or more of silicon germanium, silicon phosphide, silicon oxycarbide, and hafnium oxide.

21. The method of forming a semiconductor structure of any one of claims 7 to 19, wherein the material of the barrier layer comprises one or more of silicon, silicon oxide, silicon nitride, and silicon oxynitride.

22. The method of forming a semiconductor structure according to any one of claims 7 to 19, wherein in the step of forming the barrier layer, a thickness of the barrier layer is 1nm to 5nm.

23. The method of forming a semiconductor structure of any one of claims 7 to 19, further comprising: after the device fin portion is formed and before the dummy gate structure is formed, forming an isolation layer surrounding the device fin portion on the substrate, wherein the top of the isolation layer is lower than the top of the device fin portion;

and after the source-drain doped region is formed and before the sacrificial grid electrode and the sacrificial fin part are removed, an interlayer dielectric layer is formed on the isolation layer at the side part of the pseudo grid structure to cover the source-drain doped region.