CN115132727A

CN115132727A - Semiconductor structure and forming method thereof

Info

Publication number: CN115132727A
Application number: CN202110333353.3A
Authority: CN
Inventors: 金吉松
Original assignee: Semiconductor Manufacturing International Shanghai Corp; Semiconductor Manufacturing International Beijing Corp
Current assignee: Semiconductor Manufacturing International Shanghai Corp; Semiconductor Manufacturing International Beijing Corp
Priority date: 2021-03-29
Filing date: 2021-03-29
Publication date: 2022-09-30

Abstract

A semiconductor structure and a method of forming the same, the semiconductor structure comprising: the first transistor structure comprises a substrate, a first channel layer, a first gate dielectric layer, a first grid structure and first source-drain doped layers, wherein the first channel layer is positioned on the substrate, the first grid dielectric layer covers the first channel layer, the first grid structure covers the first grid dielectric layer, and the first source-drain doped layers are positioned on two sides of the first grid structure; the bonding layer is positioned on the bonding surface of the first transistor structure; the second transistor structure is positioned on the bonding layer and comprises a second channel layer, a second gate dielectric layer covering the second channel layer, a second gate structure covering the second gate dielectric layer and second source-drain doping layers positioned on two sides of the second gate structure; and the conductive plug penetrates through the second gate dielectric layer and the bonding layer at the bottom of the second gate structure and is electrically connected with the second gate structure and the first gate structure. According to the invention, under the condition that the first gate structure and the second gate structure are not in physical contact, the first gate structure and the second gate structure are electrically connected through the conductive plug, so that the inverter based on the CFET structure is easily obtained.

Description

Semiconductor structure and forming method thereof

Technical Field

Embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular, to a semiconductor structure and a method for forming the same.

Background

In semiconductor manufacturing, integrated circuit feature sizes continue to decrease with the trend toward very large scale integrated circuits. To accommodate the reduction in feature size, the channel length of MOSFETs has also been correspondingly shortened. However, as the channel length of the device is shortened, the distance between the source and the drain of the device is also shortened, so that the controllability of the gate to the channel is deteriorated, the difficulty of the gate voltage to pinch off the channel is increased, and the sub-threshold leakage (SCE), which is a so-called short-channel effect, is more likely to occur.

Therefore, semiconductor processing is gradually beginning to transition from planar MOSFETs to three-dimensional transistors with higher power efficiency in order to better accommodate the reduction in feature size.

Among them, the Complementary Field Effect Transistor (CFET) composed of vertically stacked is a revolutionary three-dimensional transistor. In the CFET structure, the PMOS transistor and the NMOS transistor vertically stacked on each other constitute complementary devices, so that area can be saved, integration density of the transistors can be increased, and thus, power consumption and cost performance benefits can be brought.

Disclosure of Invention

Embodiments of the present invention provide a semiconductor structure and a method for forming the same, which are easy to form a CFET structure-based inverter.

To solve the above problems, an embodiment of the present invention provides a semiconductor structure, including: the first transistor structure comprises a substrate, a first channel layer positioned on the substrate, a first gate dielectric layer conformally covering the first channel layer, a first gate structure covering the first gate dielectric layer, and first source-drain doping layers positioned on the substrate at two sides of the first gate structure, wherein the first source-drain doping layers are in contact with the end part of the first channel layer positioned below the first gate structure, and the first transistor structure is provided with a bonding surface positioned at one side of the first gate structure; the bonding layer is positioned on the bonding surface of the first transistor structure, and the material of the bonding layer is a dielectric material; the second transistor structure is positioned on the bonding layer and comprises a second channel layer, a second gate medium layer covering the second channel layer in a shape-preserving manner, a second gate structure covering the second gate medium layer and second source-drain doping layers positioned on the bonding layer at two sides of the second gate structure, and the second source-drain doping layers are in contact with the end part of the second channel layer positioned below the second gate structure; and the conductive plug penetrates through the second gate dielectric layer and the bonding layer at the bottom of the second gate structure and is electrically connected with the second gate structure and the first gate structure.

Correspondingly, an embodiment of the present invention further provides a method for forming a semiconductor structure, including: forming a first transistor structure, wherein the first transistor structure comprises a first substrate, a first channel layer positioned on the first substrate, a first gate dielectric layer conformally covering the first channel layer, a first gate structure covering the first gate dielectric layer, and first source-drain doping layers positioned on the first substrate at two sides of the first gate structure, the first source-drain doping layers are in contact with the end part of the first channel layer positioned below the first gate structure, and the first transistor structure is provided with a bonding surface positioned at one side of the first gate structure; bonding a second substrate on the bonding surface by using a bonding layer, wherein the material of the bonding layer is a dielectric material; patterning the second substrate to form a second channel layer; forming a dummy gate structure on the bonding layer, wherein the dummy gate structure crosses the second channel layer and covers part of the top and part of the side wall of the second channel layer; forming a second source-drain doping layer in the second channel layer on two sides of the pseudo gate structure, wherein the second source-drain doping layer is in contact with the end part of the second channel layer below the pseudo gate structure; after the second source-drain doping layer is formed, a top interlayer dielectric layer is formed on the bonding layer on the side of the pseudo gate structure, covers the side wall of the pseudo gate structure and exposes the top of the pseudo gate structure; removing the pseudo gate structure, and forming a gate opening in the top interlayer dielectric layer; forming a second gate dielectric layer which conformally covers the bottom and the side wall of the gate opening, wherein the second gate dielectric layer also conformally covers a second channel layer in the gate opening; forming an interconnection opening penetrating through a second gate dielectric layer and a bonding layer at the bottom of the gate opening in the gate opening, wherein the interconnection opening exposes the first gate structure and is communicated with the gate opening; and forming a conductive plug in the interconnection opening, forming a second grid structure in the grid opening, and electrically connecting the second grid structure and the first grid structure through the conductive plug, wherein the second grid structure, the second grid medium layer, the second source-drain doping layer and the second channel layer are used for forming a second transistor structure.

Compared with the prior art, the technical scheme of the embodiment of the invention has the following advantages:

in the semiconductor structure provided by the embodiment of the invention, the first transistor structure and the second transistor structure are bonded through the bonding layer, so that in the manufacturing process of the semiconductor structure, the manufacturing process of the second transistor structure can be independently completed after the manufacturing process of the first transistor structure is completed, the process difficulty for manufacturing the second transistor structure and the influence on the first transistor structure are reduced, in addition, the semiconductor structure further comprises a conductive plug positioned at the bottom of the second gate structure, the conductive plug penetrates through the bonding layer at the bottom of the second gate structure, and the conductive plug is electrically connected with the second gate structure and the first gate structure, so that under the condition that the first gate structure is not in physical contact with the second gate structure, the first gate structure is electrically connected with the second gate structure through the conductive plug arranged between the first transistor structure and the second transistor structure, therefore, the inverter based on the CFET structure is easy to obtain, and the process complexity for forming the semiconductor structure is correspondingly reduced.

In the method for forming a semiconductor structure provided by the embodiment of the invention, after a first transistor structure is formed, a second substrate is bonded on a bonding surface of the first transistor structure by using a bonding layer, the second substrate is patterned to form a second channel layer, a second gate dielectric layer which conformally covers the bottom and the side wall of a gate opening is formed after a dummy gate structure is removed to form a gate opening, then, the second gate dielectric layer penetrating through the bottom of the gate opening and an interconnection opening of the bonding layer are formed in the gate opening, the interconnection opening exposes the first gate structure, the interconnection opening is communicated with the gate opening, a conductive plug is formed in the interconnection opening, a second gate structure is formed in the gate opening, and the second gate structure is electrically connected with the first gate structure through the conductive plug; in the embodiment of the invention, the second substrate is bonded on the bonding surface of the first transistor structure in a bonding mode, namely after the preparation process of the first transistor structure is completed, the preparation process of the second transistor structure is independently completed, so that the process difficulty of preparing the second transistor structure and the influence on the first transistor structure are reduced, in addition, an interconnection opening exposing the first gate structure is formed at the bottom of the gate opening before the second gate structure is formed, correspondingly, the formation of the conductive plug cannot be blocked by the second gate structure, moreover, after the second gate structure is formed in the gate opening, the conductive plug is correspondingly positioned between the first transistor structure and the second transistor structure, and under the condition that the first gate structure is not in physical contact with the second gate structure, the electrical connection between the first gate structure and the second gate structure is realized, therefore, the inverter based on the CFET structure is easy to form, and the process complexity for forming the semiconductor structure is correspondingly reduced.

Drawings

FIG. 1 is a perspective view of a semiconductor structure;

FIG. 2 is a perspective view of another semiconductor structure;

FIGS. 3 and 4 are schematic structural diagrams of an embodiment of a semiconductor structure of the present invention;

fig. 5 to 18 are schematic structural diagrams corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention.

Detailed Description

As is known in the art, a CFET device structure includes a PMOS transistor and an NMOS transistor vertically stacked on each other. However, the current process for manufacturing the inverter based on the CFET structure is difficult.

Now, the reason that the process difficulty of the existing preparation of the inverter based on the CFET structure is large is analyzed by combining a semiconductor structure.

Referring to fig. 1, a perspective view of a semiconductor structure is shown.

The semiconductor structure includes: a first transistor structure 40 including a substrate 41, a first channel layer 42 on the substrate 41, and a first gate structure 43 covering the first channel layer 41; a second transistor structure 50 on the first transistor structure 40, wherein the second transistor structure 50 includes a second channel layer (not shown) suspended above the first transistor structure 40, and a second gate structure 51 covering the second channel layer, the second gate structure 51 is located on the top of the first gate structure 43, and the bottom of the second gate structure 51 is in contact with the top of the first gate structure 43.

The semiconductor structure is a monolithic (monolithic) CFET structure. Specifically, the first transistor structure 40 and the second transistor structure 50 are both fabricated on the same silicon wafer. Also, the bottom of the second gate structure 51 is in contact with the top of the first gate structure 43, and the second gate structure 51 is electrically connected to the first gate structure 43, thereby enabling formation of an inverter. However, this easily results in a complicated process for preparing the monolithic CFET, and the bottom of the second gate structure 51 is in contact with the top of the first gate structure 43, the process for preparing the second transistor structure 50 also has an influence on the first transistor structure 40, for example, the first gate structure 43 is easily influenced during the process of forming the second gate structure 51.

Fig. 2 is a perspective view of another semiconductor structure.

The semiconductor structure includes: a first transistor structure 10 including a substrate 11, a first channel layer 12 on the substrate 11, and a first gate structure 13 crossing the first channel layer 12, the first transistor structure 10 having a bonding surface (not labeled) on one side of the first gate structure 13; a bonding layer 30 on the bonding surface; a second transistor structure 20 on the bonding layer 30, the second transistor structure 20 including a second channel layer 22 and a second gate structure 23 covering the second channel layer 22.

The semiconductor structure is a sequential (sequential) CFET structure. Specifically, the first transistor structure 10 and the second transistor structure 20 are respectively prepared by using separate silicon wafers, and the first transistor structure 10 and the second transistor structure 20 are bonded together by means of bonding. In the semiconductor structure, the bonding layer 30 is arranged between the second transistor structure 20 and the first transistor structure 10, the second gate structure 23 is not in contact with the first gate structure 13, and when an inverter needs to be formed, an interconnection structure needs to be additionally formed to lead out electrical property of the first gate structure 13, so that the first gate structure 13 is electrically connected with the second gate structure 23 through the interconnection line. However, since the second gate structure 23 completely shields the first gate structure 13, it is difficult to electrically extract the first gate structure 13

Therefore, the current process for forming the inverter based on the CFET structure is difficult.

In order to solve the technical problem, in the semiconductor structure provided in the embodiment of the present invention, the first transistor structure and the second transistor structure are bonded through the bonding layer, so that, in the manufacturing process of the semiconductor structure, after the preparation process of the first transistor structure is completed, the preparation process of the second transistor structure can be independently completed, which reduces the process difficulty of preparing the second transistor structure and the influence on the first transistor structure, in addition, the semiconductor structure further includes a conductive plug located at the bottom of the second gate structure, the conductive plug penetrates through the bonding layer at the bottom of the second gate structure, the conductive plug electrically connects the second gate structure and the first gate structure, so that, when the first gate structure and the second gate structure are not in physical contact, through the conductive plug arranged between the first transistor structure and the second transistor structure, and the electrical connection between the first gate structure and the second gate structure is realized, so that the inverter based on the CFET structure is easily obtained, and the process complexity for forming the semiconductor structure is correspondingly reduced.

In order to make the aforementioned objects, features and advantages of the embodiments of the present invention comprehensible, specific embodiments accompanied with figures are described in detail below.

Fig. 3 and 4 are schematic structural diagrams of a semiconductor structure according to an embodiment of the invention. Fig. 3 is a cross-sectional view taken along an extending direction of the first gate structure or the first gate structure, and fig. 4 is a cross-sectional view taken in a direction perpendicular to the extending direction of the first gate structure or the first gate structure.

The semiconductor structure includes: the first transistor structure 400 includes a substrate 410, a first channel layer 470 located on the substrate 410, a first gate dielectric layer 430 conformally covering the first channel layer 470, a first gate structure 460 covering the first gate dielectric layer 430, and first source-drain doping layers 403 (shown in fig. 4) located on the substrate 410 at two sides of the first gate structure 460, where the first source-drain doping layers 403 are in contact with an end portion of the first channel layer 470 located below the first gate structure 460, and the first transistor structure 400 has a bonding surface 401 located at one side of the first gate structure 460; the bonding layer 500 is positioned on the bonding surface 401, and the material of the bonding layer 500 is a dielectric material; a second transistor structure 600, located on the bonding layer 500, where the second transistor structure 600 includes a second channel layer 520, a second gate dielectric layer 610 conformally covering the second channel layer 520, a second gate structure 690 covering the second gate dielectric layer 610, and a second source-drain doping layer 601 (shown in fig. 4) located on the bonding layer 500 at two sides of the second gate structure 690, where the second source-drain doping layer 601 is in contact with an end of the second channel layer 520 located below the second gate structure 690; and a conductive plug 660 penetrating through the second gate dielectric layer 610 and the bonding layer 500 at the bottom of the second gate structure 690, wherein the conductive plug 660 is electrically connected with the second gate structure 690 and the first gate structure 460.

The first transistor structure 400 and the second transistor structure 600 are bonded through the bonding layer 500, so that in the manufacturing process of the semiconductor structure, after the preparation process of the first transistor structure 400 is completed, the preparation process of the second transistor structure 600 can be independently completed, and the difficulty of the process for preparing the second transistor structure 600 and the influence of the process for preparing the second transistor structure 600 on the first transistor structure 400 are reduced; in addition, the semiconductor structure further includes a conductive plug 660 located at the bottom of the second gate structure 690, the conductive plug 660 penetrates through the second gate dielectric layer 610 and the bonding layer 500 at the bottom of the second gate structure 690, and the conductive plug 660 electrically connects the second gate structure 690 and the first gate structure 460, so that, in the case that the first gate structure 460 and the second gate structure 690 are not in physical contact, the electrical connection between the first gate structure 460 and the second gate structure 690 is realized through the conductive plug 660 arranged between the first transistor structure 400 and the second transistor structure 600, thereby easily obtaining an inverter based on a CFET structure, and accordingly, the process complexity for forming the semiconductor structure can be reduced.

The semiconductor structure is a CFET structure and the first transistor structure 400 includes a first transistor, which is a bottom transistor in the CFET structure. The first transistor includes a first channel layer 470, a first gate dielectric layer 430, a first gate structure 460, and a first source-drain doping layer 403, so as to implement a normal function of the first transistor.

In the CFET structure, the PMOS transistor and the NMOS transistor vertically stacked on each other constitute complementary devices, and thus the first transistor may be either an NMOS transistor or a PMOS transistor depending on the channel conductivity type of the first transistor in the first transistor structure 400. As an example, the first transistor in the first transistor structure 400 is an NMOS transistor. The first transistor structure 400 includes a fin field effect transistor (FinFET) or a Gate-All-Around-Gate (GAA) transistor, depending on the type of structure of the first transistor structure 400. In particular, the GAA transistor may be a Horizontal nanosheet (Horizontal Nanosheets) transistor. The embodiment takes the first transistor as a GAA transistor as an example.

The substrate 410 is used to provide a process platform for the formation of semiconductor structures. The base 410 may be a substrate or may include a substrate and a fin protruding from the substrate according to the structure type of the first transistor. As an example, the first transistor is a GAA transistor, and when the base 410 includes a substrate and a fin portion protruding from the substrate, the base 410 further includes an isolation layer (not shown) on the substrate, and the isolation layer covers sidewalls of the fin portion. The isolation layer may be a Shallow Trench Isolation (STI) structure.

In this embodiment, the substrate is made of silicon. In other embodiments, the substrate may also be germanium, silicon carbide, gallium arsenide, indium gallium arsenide, or other materials, and the substrate may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate.

The first channel layer 470 serves to provide a channel of the first transistor.

In the present embodiment, taking the first transistor as a GAA transistor as an example, the first channel layer 470 is located on the substrate 410 and spaced apart from the substrate 410, and the first channel layer 470 includes one or more first sub-channel layers 476 spaced apart from each other. It should be noted that, in the present embodiment, only one first sub-channel layer 476 is illustrated, but the number of the first sub-channel layers 476 is not limited to one. In other embodiments, when the first transistor is a FinFET, the first channel layer is a first fin portion protruding on the substrate.

The material of the first channel layer 470 includes silicon, silicon germanium, or a iii-v semiconductor material. The material of the first channel layer 470 depends on the channel conductivity type and performance requirements of the first transistor. As an example, the material of the first channel layer 470 is silicon.

The first gate structure 460 is a device gate structure for controlling the channel of the first transistor to be turned on or off. In this embodiment, the first gate structure 460 surrounds and covers the first gate dielectric layer 430 on the first channel layer 470. In other embodiments, when the first channel layer is a first fin portion protruding from the substrate, the first gate structure crosses over the first fin portion and covers a portion of the top of the first fin portion and a portion of the first gate dielectric layer on the sidewalls.

In the present embodiment, the first gate structure 460 is a first metal gate structure. The material of the first metal gate structure comprises one or more of TiN, TaN, Ta, Ti, TiAl, W, AL, TiSiN and TiAl. As an example, the first metal gate structure includes a first work function layer 440, and a first gate electrode layer 450 covering the first work function layer 440.

The first work function layer 440 is used to adjust the threshold voltage of the first transistor. When the first transistor is a PMOS transistor, the first work function layer 440 is a P-type work function layer, and the material of the P-type work function layer includes one or more of TiN, TaN, TaSiN, TaAlN and TiAlN; when the first transistor is an NMOS transistor, the first work function layer 440 is an N-type work function layer, and the material of the N-type work function layer includes one or both of TiAl and TiAlC.

The first gate electrode layer 450 is used to electrically conduct the first metal gate structure. The material of the first gate electrode layer 450 includes one or more of TiN, TaN, Ta, Ti, TiAl, W, AL, TiSiN, and TiAlC. As an example, the material of the first gate electrode layer 450 is W.

In this embodiment, the first gate dielectric layer 430 is located between the first gate structure 460 and the first channel layer 470. The first gate dielectric layer 430 serves to isolate the first gate structure 460 from the first channel layer 470.

The material of the first gate dielectric layer 430 comprises HfO ₂ 、ZrO ₂ 、HfSiO、HfSiON、HfTaO、HfTiO、HfZrO、Al ₂ O ₃ 、SiO ₂ And La ₂ O ₃ One or more of (a). In this embodiment, the first gate dielectric layer 430 includes a first gate oxide layer and a first high-k gate dielectric layer covering the first gate oxide layer.

As an example, the material of the first gate oxide layer is silicon oxide.

In this embodiment, the first high-k gate dielectric layer is made of a high-k dielectric material, and the high-k dielectric material is a dielectric material having a relative dielectric constant greater than that of silicon oxide. In particular, the material of the first high-k gate dielectric layer may be selected from HfO ₂ 、ZrO ₂ HfSiO, HfSiON, HfTaO, HfTiO, HfZrO or Al ₂ O ₃ And the like. As an example, the material of the first high-k gate dielectric layer is HfO ₂ 。

It should be noted that the first gate dielectric layer 430 and the first gate structure 460 are formed by a process of forming a high-k gate dielectric layer and then forming a gate electrode layer (high-k metal gate last), and therefore, the first gate dielectric layer 430 is also located between the bottom of the first gate structure 460 and the substrate 110 and extends to cover the sidewall of the first gate structure 460.

It should be further noted that, in other embodiments, the first gate structure may also be a polysilicon gate structure or other types of device gate structures according to process requirements.

The first source-drain doped layer 403 is used as a source or a drain of the first transistor. The conductivity type of the doped ions in the first source-drain doped layer 403 is the same As the channel conductivity type of the first transistor, that is, when the first transistor is an NMOS transistor, the conductivity type of the doped ions in the first source-drain doped layer 403 is N-type, and the N-type ions include one or more of As, P, and Sb; when the first transistor is a PMOS transistor, the conductivity type of the doping ions In the first source-drain doping layer 403 is P-type, and the P-type ions include one or more of B, Ga and In. The detailed description of the first source-drain doping layer 403 is omitted here.

In this embodiment, the first transistor structure 400 further includes: the first gate sidewall spacer 405 covers the sidewall of the first gate structure 460. Specifically, the first gate sidewall spacers 405 cover the first gate dielectric layer 430 on the sidewalls of the first gate structure 460.

The first gate sidewall spacer 405 is used for protecting the sidewalls of the first gate structure 460 and the first gate dielectric layer 430, and is also used for defining the position of the first source-drain doping layer 403.

The first gate sidewall 405 may have a single-layer structure or a stacked-layer structure, and the material of the first gate sidewall 405 includes one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride, and boron carbonitride. As an example, the first gate sidewall spacers 405 have a single-layer structure, and the material of the first gate sidewall spacers 405 is silicon nitride.

As shown in fig. 4, it should be noted that, taking the first transistor as a GAA transistor as an example, the first transistor structure 400 may further include: the first inner sidewall spacer (not labeled) is located between the adjacent first sub-channel layers 476 along the normal direction of the surface of the substrate 410, or located between the first sub-channel layers 476 and the substrate 410, and along the direction perpendicular to the extending direction of the first gate structure 460, the first inner sidewall spacer is located between the sidewall of the first gate dielectric layer 430 and the first source drain doping layer 403.

The first inner sidewall plays a role in isolating the first gate structure 460 from the first source-drain doping layer 403, so as to reduce the parasitic capacitance between the first gate structure 460 and the first source-drain doping layer 403.

The first inner side wall is made of an insulating material and comprises one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride and boron carbonitride. In this embodiment, the first inner sidewall spacer is made of silicon nitride.

In this embodiment, the first transistor structure 400 further includes: and a bottom interlayer dielectric layer 420 on the substrate 410 at the side of the first gate structure 460 and covering the sidewall of the first gate structure 460.

The bottom interlevel dielectric layer 420 serves to isolate adjacent transistors in the first transistor structure 400. The material of the bottom interlayer dielectric layer 420 is an insulating material, and the insulating material includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride and silicon oxycarbonitride. In this embodiment, the bottom interlayer dielectric layer 420 is made of silicon oxide. Accordingly, the first gate dielectric layer 430 is located between the bottom of the first gate structure 460 and the substrate 410, and between the sidewalls of the first gate structure 460 and the bottom interlayer dielectric layer 420.

In this embodiment, the first transistor structure 400 has a bonding surface 401 located at one side of the first gate structure 460. The bonding surface 401 is a front surface of the first transistor structure 400, and in the process of manufacturing the semiconductor structure, the bonding surface 401 is used as a process platform, and the second transistor structure 600 is manufactured above the bonding surface 401.

The bonding layer 500 is located on the bonding surface 401, and a material of the bonding layer 500 is a dielectric material. During the process of manufacturing the second transistor structure 600, a substrate required for forming the second transistor structure 600 is bonded on the bonding surface 401 through the bonding layer 500.

The bonding layer 500 is used to improve the bonding strength between the first transistor structure 400 and the second transistor structure 600, thereby improving the reliability of the semiconductor structure; moreover, the material of the bonding layer 500 is a dielectric material, thereby functioning as an electrical isolation between the second transistor structure 600 and the first transistor structure 400 and making the bonding layer 500 compatible with semiconductor processes; in addition, the bonding layer 500 can also protect the first transistor structure 400 during the process of manufacturing the second transistor structure 600.

The material of the bonding layer 500 includes one or more of silicon oxide, silicon nitride, silicon oxynitride, and carbon-doped silicon oxide. In this embodiment, the material of the bonding layer 500 includes silicon oxide. By adopting the silicon oxide, the bonding can be realized by adopting a fusion bonding (fusion bonding) mode, and the bonding efficiency and the bonding strength can be improved; moreover, it is also beneficial to further improve the electrical isolation effect between the second transistor structure 600 and the first transistor structure 400; in addition, by using silicon oxide, the bonding temperature is made lower, thereby reducing the impact on the performance of the first transistor in the first transistor structure 400. It should be noted that the bonding layer 500 is located on the bonding surface 401, and the bonding layer 500 covers not only the top of the first gate structure 460 but also the top of the bottom interlayer dielectric layer 420.

The second transistor structure 600 is located on the bonding layer 500, and the second transistor structure 600 includes a second transistor, which is a top transistor in a CFET structure. The second transistor includes a second channel layer 520, a second gate dielectric layer 610, a second gate structure 690, and a second source-drain doping layer 601, thereby implementing a normal function of the second transistor.

Thus, the second transistor in the second transistor structure 600 may be an NMOS transistor or a PMOS transistor, and the channel conductivity type of the second transistor is different from the channel conductivity type of the first transistor.

In this embodiment, the first transistor is an NMOS transistor, and thus the second transistor is a PMOS transistor. In other embodiments, when the first transistor is a PMOS transistor, the second transistor is correspondingly an NMOS transistor.

The second transistor structure 600 includes a fin field effect transistor or a GAA transistor, depending on the type of structure of the second transistor structure 600. In particular, the GAA transistor may be a horizontal nanosheet transistor.

The second channel layer 520 is to provide a channel of the second transistor. In this embodiment, taking the second transistor as a GAA transistor as an example, the second channel layer 520 is located on the bonding layer 500 and is spaced apart from the bonding layer 500, and the second channel layer 520 includes one or more second sub-channel layers 526 spaced apart from each other.

Note that only one second sub-channel layer 526 is illustrated in fig. 3, but the number of the second sub-channel layers 526 is not limited to one. In other embodiments, when the second transistor is a FinFET, the second channel layer is a second fin protruding on the bonding layer.

It should be noted that, in the present embodiment, in the process of manufacturing the second transistor structure 600, the substrate bonded on the bonding surface 401 is directly patterned into the second channel layer 520, and therefore, the second transistor structure 600 does not include an additional substrate (e.g., a substrate). Correspondingly, when the second channel layer is a second fin portion protruding from the bonding layer, the second fin portion contacts the bonding layer.

The material of the second channel layer 520 may include silicon, silicon germanium, or a group iii-v semiconductor material. The material of the second channel layer 520 depends on the channel conductivity type and performance requirements of the second transistor. As an example, the material of the second channel layer 520 is silicon.

The second gate structure 690 is a device gate structure for controlling the channel of the second transistor to be turned on or off. In this embodiment, the second gate structure 690 surrounds the second gate dielectric layer 610 on the second channel layer 520. In other embodiments, when the second channel layer is a second fin portion protruding from the bonding layer, the second gate structure crosses over the second fin portion and covers a portion of the top of the second fin portion and a portion of the second gate dielectric layer on the sidewalls.

In this embodiment, the second gate structure 690 is a second metal gate structure, and the material of the second metal gate structure includes one or more of TiN, TaN, Ta, Ti, TiAl, W, AL, TiSiN, and TiAlC. Specifically, the second gate structure 690 includes a second work function layer 670, and a second gate electrode layer 680 overlying the second work function layer 670. For a detailed description of the second work function layer 670 and the second gate electrode layer 680 and the materials thereof, reference may be made to the related description of the first work function layer 440 and the first gate electrode layer 450, respectively, and no further description is provided herein.

In this embodiment, the second gate dielectric layer 610 is located between the second gate structure 690 and the second channel layer 520, and is also located between the second gate structure 690 and the bonding layer 500.

The second gate dielectric layer 610 serves to isolate the second gate structure 690 from the second channel layer 520. The material of the second gate dielectric layer 610 comprises HfO ₂ 、ZrO ₂ 、HfSiO、HfSiON、HfTaO、HfTiO、HfZrO、Al ₂ O ₃ 、SiO ₂ And La ₂ O ₃ One or more of (a).

As an example, the second gate dielectric layer 610 includes a second gate oxide layer and a second high-k gate dielectric layer covering the second gate oxide layer. For a detailed description of the second gate dielectric layer 610, reference may be made to the foregoing description of the first gate dielectric layer 430, and details are not repeated herein.

In this embodiment, the second transistor structure 600 does not include an additional base (e.g., substrate), and thus, the second gate dielectric layer 610 is in contact with the top of the bonding layer 500.

It should be noted that the second gate dielectric layer 610 and the second gate structure 690 are formed by a process of forming a gate electrode layer after forming a high-k gate dielectric layer, and therefore, the second gate dielectric layer 610 also conformally covers the bottom and the sidewall of the second gate structure 690, that is, the second gate dielectric layer 610 is located between the second gate structure 690 and the bonding layer 500 and extends to cover the sidewall of the second gate structure 690.

It should be further noted that, in other embodiments, the second gate structure may also be a polysilicon gate structure or other types of device gate structures according to process requirements.

The second source-drain doped layer 601 is used as a source or a drain of the second transistor. The conductivity type of the dopant ions in the second source-drain doped layer 601 is the same as the channel conductivity type of the second transistor. For a specific description of the second source-drain doping layer 601, reference may be made to the description of the first source-drain doping layer 403, and details are not described herein again in this embodiment.

In this embodiment, the second transistor structure 600 further includes: and a second gate sidewall spacer 605 covering the sidewalls of the second gate structure 690. Specifically, the second gate sidewall spacer 605 covers the second gate dielectric layer 610 on the sidewall of the second gate structure 690.

The second gate sidewall spacer 605 is used for protecting the sidewalls of the second gate structure 690 and the second gate dielectric layer 610, and also for defining the position of the second source-drain doped layer 601.

The second gate sidewall 605 may have a single-layer structure or a stacked-layer structure, and the material of the second gate sidewall 605 includes one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride, and boron carbonitride. As an example, the second gate sidewall spacers 605 have a single-layer structure, and the material of the second gate sidewall spacers 605 is silicon nitride.

As shown in fig. 4, it should be noted that, taking the second transistor as a GAA transistor as an example, the second transistor structure 600 may further include: and a second inner sidewall (not labeled) located between the adjacent second channel layers 520 along a normal direction of the surface of the substrate 410, or located between the second channel layers 520 and the bonding layer 500, and located between the sidewall of the second gate dielectric layer 610 and the second source-drain doping layer 601 along a direction perpendicular to the extending direction of the second gate structure 690.

The second inner sidewall plays a role in isolating the second gate structure 690 from the second source-drain doping layer 601, so as to reduce the parasitic capacitance between the second gate structure 690 and the second source-drain doping layer 601.

The second inner side wall is made of an insulating material, and the second inner side wall is made of one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride and boron carbonitride. In this embodiment, the second inner sidewall is made of silicon nitride.

In this embodiment, the second transistor structure 600 further includes: and a top interlayer dielectric layer 560 on the bonding layer 500 at the side of the second gate structure 690, the top interlayer dielectric layer 560 covering the sidewalls of the second gate structure 690. The top interlevel dielectric layer 560 serves to isolate adjacent transistors in the second transistor structure.

The material of the top interlayer dielectric layer 560 is an insulating material, and the insulating material includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride and silicon oxycarbonitride. In this embodiment, the top interlayer dielectric layer 560 is made of silicon oxide.

The conductive plug 660 electrically connects the second gate structure 690 and the first gate structure 460.

In this embodiment, two ends of the conductive plug 660 are electrically connected to the bottom of the second gate structure 690 and the top of the first gate structure 460 respectively along the stacking direction of the first transistor structure 400 and the second transistor structure 600.

Specifically, two ends of the conductive plug 660 are respectively in contact with the bottom of the second gate structure 690 and the top of the first gate structure 460. The sidewalls of the first gate structure 460 are generally covered by the first gate dielectric layer 430, and the top of the first gate structure 460 is exposed by the first gate dielectric layer 430, so that the conductive plug 660 is located at the top of the first gate structure 460, thereby reducing the process difficulty of forming the conductive plug 660, reducing the influence on the first gate dielectric layer 430, and correspondingly reducing the influence on the performance of the first transistor structure 400.

In other embodiments, depending on the projection relationship of the first gate structure and the second gate structure on the substrate 410, the conductive plug may also be located at one side of the first gate structure, and along the stacking direction of the first transistor structure and the second transistor structure, the conductive plug extends into or through the bottom dielectric layer with a partial thickness, and the conductive plug contacts with the sidewall of the first gate structure. In this case, the first gate dielectric layer covers the sidewall of the first gate structure exposed by the conductive plug.

In this embodiment, the conductive plug 660 and the second gate structure 690 are independent structures, and are electrically connected together. By selecting the independent conductive plug 660, the material of the conductive plug 660 can be flexibly selected according to the performance requirement.

Specifically, the material of the conductive plug 660 includes one or more of W, Co, Ru, TiN, TaN, Ta, Ti, TiAl, W, AL, TiSiN, and TiAlC. The material has better conductivity and higher compatibility with a metal grid structure.

In other embodiments, the conductive plug may also be a unitary structure with the second gate structure, and the conductive plug and the second gate structure are made of the same material. The second gate structure is conductive, and thus, the second gate structure in the bonding layer is used as a conductive plug which can still be electrically connected.

In this embodiment, the conductive plug 660 further extends into the partial thickness of the second gate structure 690 along the stacking direction of the first transistor structure 400 and the second transistor structure 600. Therefore, the second gate structure 690 covers not only the end portion of the conductive plug 660 but also a portion of the sidewall of the conductive plug 660, which is advantageous for reducing the contact resistance between the second gate structure 690 and the conductive plug 660. Furthermore, the conductive plug 660 extends only into a portion of the thickness of the second gate structure 690, which has less impact on the performance of the second gate structure 690.

Fig. 5 to fig. 18 are schematic structural diagrams corresponding to steps of a method for forming a semiconductor structure according to an embodiment of the present invention.

With reference to fig. 5 and 6, fig. 5 is a cross-sectional view along an extending direction of the first gate structure, fig. 6 is a cross-sectional view along a direction perpendicular to the extending direction of the first gate structure, and a first transistor structure 100 is formed, including a first substrate 110, a first channel layer 170 on the first substrate 110, a first gate dielectric layer 130 conformally covering the first channel layer 170, a first gate structure 160 covering the first gate dielectric layer 130, and first source-drain doping layers 103 on the first substrate 110 on both sides of the first gate structure 160, where the first source-drain doping layers 103 are in contact with an end portion of the first channel layer 170 below the first gate structure 160, and the first transistor structure 100 has a bonding surface 101 on one side of the first gate structure 160.

The formation method is used for forming a CFET structure, and the first transistor structure 100 includes a first transistor, which is a bottom transistor in the CFET structure. The first transistor includes a first channel layer 170, a first gate dielectric layer 130, a first gate structure 160, and a first source-drain doping layer 103, so as to implement a normal function of the first transistor.

The first transistor in the first transistor structure 100 may be an NMOS transistor or a PMOS transistor. As an example, the first transistor is an NMOS transistor. The first transistor structure 100 comprises a FinFET or GAA transistor, depending on the type of structure of the first transistor structure 100. In particular, the GAA transistor may be a Horizontal nanosheet (Horizontal Nanosheets) transistor. In this embodiment, the first transistor is a GAA transistor.

The first substrate 110 is used to provide a process platform for the formation of semiconductor structures. The first base 110 may be a substrate, and may also include a substrate and a fin protruding from the substrate according to a structure type of the first transistor. As an example, the first transistor is a GAA transistor, and when the first base 110 includes a substrate and a fin portion protruding from the substrate, the first base 110 further includes an isolation layer (not shown) on the substrate, and the isolation layer covers a sidewall of the fin portion. The isolation layer may be a shallow trench isolation structure. The description of the substrate may refer to the corresponding description in the foregoing embodiments, and the description of this embodiment is not repeated herein.

The first channel layer 170 is to provide a channel of the first transistor. In the present embodiment, the first channel layer 170 is disposed on the substrate 110 and spaced apart from the substrate 110, and the first channel layer 170 includes one or more first sub-channel layers 176 disposed at intervals. It should be noted that, in the present embodiment, only one first sub-channel layer 176 is illustrated, but the number of the first sub-channel layers 176 is not limited to one. In other embodiments, when the first transistor is a FinFET, the first channel layer is a first fin portion protruding from the substrate.

The material of the first channel layer 170 includes silicon, silicon germanium, or a iii-v semiconductor material. The material of the first channel layer 170 depends on the channel conductivity type and performance requirements of the first transistor. As an example, the material of the first channel layer 170 is silicon.

The first gate structure 160 is a device gate structure for controlling the channel of the first transistor to be turned on or off. In this embodiment, the first gate structure 160 circumferentially covers the first gate dielectric layer 130 on the first channel layer 170. In other embodiments, when the first channel layer is a first fin portion protruding from the substrate, the first gate structure crosses over the first fin portion and covers a portion of the top of the first fin portion and a portion of the first gate dielectric layer on the sidewalls.

In this embodiment, the first gate structure 160 is a first metal gate structure. The material of the first metal gate structure comprises one or more of TiN, TaN, Ta, Ti, TiAl, W, AL, TiSiN and TiAlC. As an example, the first metal gate structure includes a first work function layer 140, and a first gate electrode layer 150 overlying the first work function layer 140.

In this embodiment, the first gate dielectric layer 130 is located between the first gate structure 160 and the first channel layer 170. The first gate dielectric layer 130 serves to isolate the first gate structure 160 from the first channel layer 170. Specifically, the first gate dielectric layer 130 includes a first gate oxide layer and a first high-k gate dielectric layer covering the first gate oxide layer.

For specific descriptions of the first gate dielectric layer 130, the first work function layer 140 and the first gate electrode layer 150, reference may be made to the corresponding descriptions in the foregoing embodiments, and details in this embodiment are not repeated herein.

It should be noted that the first gate dielectric layer 130 and the first gate structure 160 are formed by a process of forming a gate electrode layer after forming a high-k gate dielectric layer, and therefore, the first gate dielectric layer 130 also covers the bottom and the side wall of the first gate structure 160.

In this embodiment, the first source-drain doped layer 103 is used as a source or a drain of the first transistor. The conductivity type of the doped ions in the first source-drain doped layer is the same as the conductivity type of the channel of the first transistor.

In this embodiment, the first transistor structure 100 further includes: the first gate sidewall spacers 105 cover sidewalls of the first gate structure 160. Specifically, the first gate sidewall spacers 105 cover the first gate dielectric layer 130 on the sidewalls of the first gate structure 160.

In addition, taking the first transistor as a GAA transistor as an example, the first transistor structure 100 may further include: the first inner sidewall spacer (not shown) is located between the adjacent first sub-channel layers 176 along the normal direction of the surface of the first substrate 110, or located between the first sub-channel layers 176 and the first substrate 110, and is located between the sidewall of the first gate dielectric layer 130 and the first source/drain doping layer 103 along the direction perpendicular to the extending direction of the first gate structure 160.

For specific descriptions of the first source-drain doping layer 103, the first gate sidewall spacer 105 and the first inner sidewall spacer, reference may be made to the corresponding descriptions in the foregoing embodiments, and details are not repeated here.

In this embodiment, the first transistor structure 100 further includes: and a bottom interlayer dielectric layer 120 on the substrate 110 at the side of the first gate structure 160 and covering the sidewall of the first gate structure 160.

The bottom interlevel dielectric layer 120 is used to isolate adjacent transistors in the first transistor structure 100. The material of the bottom interlayer dielectric layer 120 is an insulating material, and the insulating material includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride and silicon oxycarbonitride. In this embodiment, the bottom interlayer dielectric layer 120 is made of silicon oxide.

In this embodiment, the first transistor structure 100 has a bonding face 101. The bonding surface 101 is a front surface of the first transistor structure 100, and then a second transistor structure is prepared above the bonding surface 101 by using the bonding surface 101 as a process platform, so as to form a sequential CFET structure.

With continued reference to fig. 5 and 6, a second substrate 205 is bonded on the bonding surface 101 by using a bonding layer 200, and a material of the bonding layer 200 is a dielectric material.

The second substrate 205 is used to form a second channel layer in a second transistor structure.

A second transistor structure is subsequently formed on bonding layer 200, the second transistor structure including a second transistor, the second transistor being a top transistor in a CFET structure. The second transistor in the second transistor structure may be an NMOS transistor or a PMOS transistor, and a channel conductivity type of the second transistor is different from a channel conductivity type of the first transistor. In this embodiment, the first transistor is an NMOS transistor, and thus the second transistor is a PMOS transistor. In other embodiments, when the first transistor is a PMOS transistor, the second transistor is correspondingly an NMOS transistor.

In this embodiment, the second substrate 205 is bonded on the bonding surface 101 in a bonding manner, that is, after the fabrication process of the first transistor structure 100 is completed, the fabrication process of the second transistor structure is completed independently, so that the process difficulty of subsequently fabricating the second transistor structure and the influence of the process of fabricating the second transistor structure on the first transistor structure 100 are reduced.

The bonding layer 200 is used for improving the bonding strength between the first transistor structure 400 and the second substrate 205, so that the reliability of the semiconductor structure is improved; moreover, the material of the bonding layer 200 is a dielectric material, so as to perform an electrical isolation function between the first transistor structure 200 and a subsequently formed second transistor structure, and make the bonding layer 200 compatible with a semiconductor process; in addition, the bonding layer 200 can also protect the first transistor structure 200 during the subsequent process of manufacturing the second transistor structure.

The material of the bonding layer 200 includes one or more of silicon oxide, silicon nitride, silicon oxynitride, and carbon-doped silicon oxide. In this embodiment, the material of the bonding layer 200 includes silicon oxide. By adopting the silicon oxide, the bonding can be realized by adopting a fusion bonding mode, and the bonding efficiency and the bonding strength can be improved; moreover, the electrical isolation effect of the bonding layer 200 can be further improved; furthermore, by using silicon oxide, the bonding temperature is made lower, thereby reducing the impact on the performance of the first transistor in the first transistor structure 200.

In this embodiment, the bonding layer 200 is located between the second substrate 205 and the first transistor structure 100, and the bonding layer 200 covers the top of the first gate structure 160 and the top of the bottom interlayer dielectric layer 120.

As an example, with the bonding surface 101 of the first transistor structure 100 as the first bonding surface 101, the second substrate 205 includes a second bonding surface (not labeled), and the step of bonding the second substrate 205 on the bonding surface 101 by using the bonding layer 200 includes: forming a first sub-bonding layer (not labeled) on the first bonding surface 101, and forming a second sub-bonding layer (not labeled) on the second bonding surface; the first sub-bonding layer and the second sub-bonding layer are oppositely arranged and bonded, and the second substrate 205 is bonded on the bonding surface 101. Accordingly, the first sub-bonding layer and the second sub-bonding layer constitute the bonding layer 200 of the stacked structure. In this embodiment, the materials of the first sub-bonding layer and the second sub-bonding layer are both silicon oxide, so that silicon oxide-silicon oxide fusion bonding is realized.

In other embodiments, the second substrate may be bonded to the bonding surface through the bonding layer after the bonding layer is formed on only one of the first bonding surface and the second bonding surface.

In the present embodiment, the bonding layer 200 is formed by a deposition process (e.g., a chemical vapor deposition process).

In this embodiment, taking the example that the second transistor to be formed subsequently is a GAA transistor, in the step of bonding the second substrate 205 on the bonding surface 101 by using the bonding layer 200, the second substrate 205 includes one or more stacked channel material stacks 206, the channel material stack 206 includes a sacrificial material layer 215 and a channel material layer 225 on the sacrificial material layer 215, and in the same channel material stack 206, the sacrificial material layer 215 is closer to the bonding layer 200 than the channel material layer 225.

The sacrificial material layer 21 is used in preparation for the subsequent formation of a sacrificial layer, and the channel material layer 225 is used in preparation for the subsequent formation of a second channel layer. In this embodiment, only one channel material stack 206 is illustrated. The number of channel material stacks 206 is not limited to one.

Specifically, taking the example that the second substrate 205 includes one channel material stack 206, the step of forming the second substrate 205 and the second sub-bonding layer includes: providing an initial substrate of the same material as the channel material layer 225; forming a sacrificial material layer 215 on the channel material layer 225, the sacrificial material layer 215 and the channel material layer 225 forming a channel material stack 206; after forming the stack 206 of channel material, a second sub-bonding layer is formed on the layer 215 of sacrificial material.

In this embodiment, after the second base 205 is bonded to the bonding surface 101 by using the bonding layer 200, the initial substrate is thinned until the remaining initial substrate reaches a target thickness, where the target thickness of the remaining initial substrate is equal to the target thickness of the channel material layer 225.

Accordingly, when the second substrate 205 includes a plurality of stacked channel material stacks 206, after forming the first channel material stack 206, before forming the second sub-bonding layer, the method further includes: alternately forming a channel material layer 225 and a sacrificial material layer 215 on the channel material layer 225 on the first channel material stack 206 until the total number of channel material stacks 206 reaches a target number.

Therefore, in the present embodiment, after the second transistor structure is formed subsequently, the second transistor structure does not include an additional substrate (e.g., a substrate).

The material of the channel material layer 225 includes silicon, silicon germanium, or a group iii-v semiconductor material. The material of the channel material layer 225 depends on the channel conductivity type and performance requirements of the second transistor. As an example, the material of the channel material layer 225 is silicon.

The sacrificial material layer 215 is selected to have an etching selectivity with respect to the channel material layer 225 according to the material of the channel material layer 225. In this embodiment, the channel material layer 225 is made of silicon, and thus the sacrificial material layer 215 is made of silicon germanium. The silicon germanium and the silicon have a high etching selectivity ratio, so that the sacrificial material layer 215 is easy to remove in the subsequent process, and the damage of the process for removing the sacrificial material layer 215 to the channel material layer 225 is reduced.

In other embodiments, when the second transistor to be formed subsequently is a FinFET, the second substrate is a fin material layer in the step of bonding the second substrate on the bonding surface by using the bonding layer. Correspondingly, the initial substrate comprises a material layer which is the same as the fin material layer, and after bonding, the initial substrate is thinned until the target thickness of the fin material layer is reached.

Referring to fig. 7, fig. 7 is a cross-sectional view based on fig. 5, and the second substrate 205 (shown in fig. 5) is patterned to form a second channel layer 220.

The second channel layer 220 is for providing a channel of the second transistor. As an example, the material of the second channel layer 220 is silicon.

Specifically, in the step of patterning the second substrate 205, the channel material stack 206 is patterned into one or more stacked channel stacks 227 protruding on the bonding layer 200, the channel stacks 227 include a sacrificial layer 210 and a sub-channel layer 226 on the sacrificial layer 210, and the one or more sub-channel layers 226 constitute the second channel layer 220.

It should be noted that the first channel layer 170 includes one or more first sub-channel layers 176 disposed at intervals, and therefore, in the step of patterning the second substrate 205, the sub-channel layer 226 in the channel stack 227 is defined as the second sub-channel layer 226, and the one or more second sub-channel layers 226 constitute the second channel layer 220.

In other embodiments, when the second substrate is a fin material layer, in the step of patterning the second substrate, the second channel layer is a fin (specifically, a second fin) protruding from the bonding layer.

With combined reference to fig. 8 and 9, fig. 8 is a cross-sectional view based on fig. 7, and fig. 9 is a cross-sectional view based on fig. 8 in a direction perpendicular to an extending direction of the first gate structure or the dummy gate structure, a dummy gate structure 250 is formed on the bonding layer 200, the dummy gate structure 250 crossing the second channel layer 220 and covering a portion of the top and a portion of the sidewall of the second channel layer 220.

The dummy gate structure 250 is used to occupy a spatial location for the subsequent formation of a second gate structure. Specifically, the dummy gate structure 250 crosses the channel stack 227 and covers a portion of the top and a portion of the sidewalls of the channel stack 227.

In this embodiment, the dummy gate structure 250 includes a dummy gate oxide layer 230 covering the channel stack 227, and a dummy gate layer 240 covering the dummy gate oxide layer 230. As an example, the material of the dummy gate oxide layer 230 is silicon oxide or silicon oxynitride, and the material of the dummy gate layer 240 is polysilicon, amorphous silicon, or amorphous carbon.

In other embodiments, when the second channel layer is a second fin portion protruding from the bonding layer, the dummy gate structure crosses over the second fin portion and covers a portion of the top and a portion of the sidewall of the second fin portion.

With continuing reference to fig. 8 and 9, after forming the dummy gate structure 250, further comprising: forming a second gate sidewall 205 on the sidewall of the dummy gate structure 250; after the second gate sidewall 205 is formed, a second source-drain doping layer 201 is formed in the second channel layer 220 on both sides of the dummy gate structure 250, and the second source-drain doping layer 201 is in contact with the end portion of the second channel layer 220 located below the dummy gate structure 250.

The conductivity type of the doped ions in the second source-drain doped layer 201 is the same as the channel conductivity type of the second transistor. Specifically, after a groove (not shown) is formed in the second channel layer 220 on both sides of the dummy gate structure 250, an epitaxial process is used to form a second source-drain doping layer 201 in the groove.

After forming the recess and before forming the second source/drain doping layer 201, the method further includes: transversely etching the sacrificial layer 210 with the exposed part of the width of the groove to form a groove communicated with the groove; a second inner sidewall (not labeled) is formed in the trench.

For specific descriptions of the second gate sidewall spacers 205, the second source-drain doping layer 201, and the second inner sidewall spacers, reference may be made to the corresponding descriptions in the foregoing embodiments, and details are not repeated here.

With continued reference to fig. 8 and 9, after the second source-drain doping layer 201 is formed, a top interlayer dielectric layer 260 is formed on the bonding layer 200 at the side of the dummy gate structure 250, and the top interlayer dielectric layer 260 covers the side wall of the dummy gate structure 250 and exposes the top of the dummy gate structure 250.

The top interlevel dielectric layer 260 serves to isolate adjacent transistors in a subsequent second transistor structure and also serves to provide a process foundation for the subsequent formation of an interconnect opening and a second gate structure.

The material of the top interlayer dielectric layer 260 is an insulating material, and the insulating material includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride and silicon oxycarbonitride. In this embodiment, the top interlayer dielectric layer 260 is made of silicon oxide.

Referring to fig. 10, fig. 10 is a cross-sectional view based on fig. 8, in which the dummy gate structure 250 (shown in fig. 6) is removed and a gate opening 270 is formed in the top interlayer dielectric layer 260.

The gate opening 270 serves to provide a spatial location for the subsequent formation of a second gate structure and also serves to provide a process foundation for the subsequent formation of an interconnect opening.

In this embodiment, after forming the gate opening 270, the method further includes: the sacrificial layer 210 exposed by the gate opening 270 is removed to form a through trench 280 communicating with the gate opening 270.

The through-trenches 280 also serve to provide spatial location for the subsequent formation of a second gate structure.

Referring to fig. 11, a second gate dielectric layer 310 is formed conformally covering the bottom and sidewalls of the gate opening 270, the second gate dielectric layer 310 also conformally covering the second channel layer 220 in the gate opening 270.

In this embodiment, the second gate dielectric layer 310 is used to isolate the second gate structure and the second channel layer 220, which are formed subsequently.

In this embodiment, the second gate dielectric layer 310 comprises a high-k gate dielectric layer. Specifically, the second gate dielectric layer 310 includes a gate oxide layer and a high-k gate dielectric layer covering the gate oxide layer. Wherein the gate oxide layer conformally covers the respective surfaces of the second channel layer 220; the high-k gate dielectric layer conformally covers the gate oxide layer and also conformally covers the bottom and sidewalls of the gate opening 270. For a detailed description of the second gate dielectric layer 310, reference may be made to the foregoing description of the first gate dielectric layer 130, and details are not repeated herein.

Note that the second gate dielectric layer 310 also covers the top of the top interlayer dielectric layer 260.

Referring to fig. 12, after forming the second gate dielectric layer 310, the method further includes: forming a cap layer (not shown) conformally covering the second gate dielectric layer 310 and a sacrificial layer 320 conformally covering the cap layer; after the sacrificial layer 320 is formed, an annealing process 330 is performed on the second gate dielectric layer 310.

When a second work function layer is subsequently formed in the gate opening 270, the cap layer is used for protecting the high-k gate dielectric layer in the second gate dielectric layer 310, so as to prevent metal ions in the second work function layer from diffusing into the high-k gate dielectric layer; the cap layer can also prevent oxygen ions in the high-k gate dielectric layer from diffusing into the second work function layer, so that the problem of increasing the content of oxygen vacancies in the high-k gate dielectric layer is avoided. In this embodiment, the capping layer is made of TiN. In other embodiments, the material of the cap layer may also be TiSiN or TaN.

The sacrificial layer 320 is used to improve the electrical performance stability of the subsequently formed second transistor. In this embodiment, the material of the sacrificial layer 320 is amorphous silicon (a-Si).

The annealing process 330 is used to improve the quality of the second gate dielectric layer 310. The annealing process 330 may include one or both of a spike annealing process and a laser annealing process.

Referring to fig. 13 to 14, in the gate opening 270, an interconnect opening 350 (shown in fig. 11) is formed through the second gate dielectric layer 310 and the bonding layer 200 at the bottom of the gate opening 270, the interconnect opening 350 exposes the first gate structure 160, and the interconnect opening 350 communicates with the gate opening 270.

Interconnect opening 350 is used to provide a spatial location for the subsequent formation of a conductive plug. At this time, the second gate structure is not formed in the gate opening 270, the formation of the conductive plug is not blocked by the second gate structure, and the conductive plug is correspondingly located between the first transistor structure 100 and the second transistor structure after the second gate structure is formed in the gate opening 270, and the conductive plug realizes the electrical connection between the first gate structure and the second gate structure under the condition that the first gate structure 160 and the second gate structure are not in physical contact, so that the inverter based on the CFET structure is easily formed.

In this embodiment, after the second gate dielectric layer 310 is formed, the interconnect opening 350 is formed, so as to prevent the second gate dielectric layer 310 from being formed in the interconnect opening 350, and accordingly, after a conductive plug is formed in the interconnect opening 350, the second gate dielectric layer 310 does not exist between the conductive plug and the first gate structure 160, and the conductive plug can be electrically connected to the first gate structure 160. Furthermore, after the sacrificial layer 320 is formed, the interconnect opening 350 is formed, so that the sacrificial layer 320 protects the second gate dielectric layer 310 during the process of forming the interconnect opening 350, and the probability of damaging the second gate dielectric layer 310 is reduced. Furthermore, after the annealing 330 is performed on the second gate dielectric layer 310, the interconnect opening 350 is formed, and when the annealing 330 is performed, the bonding surface 101 of the first transistor structure 100 is completely covered by the bonding layer 200, so as to reduce the influence of the annealing 330 on the first transistor structure 100 (especially the first gate structure 160).

Specifically, the step of forming the interconnect opening 350 includes: as shown in fig. 13, the gate opening 270 is filled with a protection layer 330; forming a mask layer 340 on the top of the protection layer 330, wherein a mask opening 345 is formed in the mask layer 340, and the mask opening 345 exposes a part of the top of the protection layer 330 on the side of the second channel layer 220; as shown in fig. 11, the mask layer 340 is used as a mask, and the protective layer 330, the second gate dielectric layer 310 and the bonding layer 200 are sequentially etched along the mask opening 345 to form an interconnect opening 350 penetrating through the second gate dielectric layer 310 and the bonding layer 200.

In this embodiment, the material of the protection layer 330 includes an organic material. The mask opening 345 is typically formed by a photolithography process, and the organic material is compatible with the photolithography process. Moreover, the filling performance of the organic material is better. In addition, the organic material is a material which is easy to remove, and the process for removing the organic material has less damage to other film layers. As an example, the protective layer 330 is formed using a spin-on process. Correspondingly, the protection layer 330 also covers the top of the top interlayer dielectric layer 260.

The material of the protection layer 330 includes a BARC (bottom-antireflective coating) material, an ODL (organic dielectric layer) material, a DARC (dielectric-antireflective coating) material, a spin-on carbon (SOC) material, a DUO (Deep UV Light Absorbing Oxide) material, or an APF (Advanced Patterning Film) material. As an example, the material of the protection layer 330 is an SOC material. The SOC material has good filling properties.

In this embodiment, after the protective layer 330 is etched and before the second gate dielectric layer 310 is etched, the sacrificial layer 320 is also etched correspondingly.

In this embodiment, a dry etching process (e.g., an anisotropic dry etching process) is adopted to sequentially etch the protection layer 330, the sacrificial layer 320, the second gate dielectric layer 310 and the bonding layer 200 along the mask opening 345. The dry etching process has anisotropic etching characteristics, and is easy to obtain a better etching profile of the interconnect opening 350. In addition, in the present embodiment, the material of the bonding layer 200 is a dielectric material, and the dielectric material is an inorganic material, so that a better etching profile can be easily obtained in the etching process.

In this embodiment, after forming the interconnect opening 350, the method further includes: the masking layer 340 and the protection layer 330 are removed. The masking layer 340 and the protective layer 330 are removed to expose the gate opening 270 and the through trench 280 in preparation for the subsequent formation of the conductive plug and the second gate structure.

In this embodiment, after the mask layer 340 and the protection layer 330 are removed, the sacrificial layer 320 is remained.

Referring collectively to fig. 15-16, a conductive plug 360 is formed in the interconnect opening 350.

The conductive plug 360 is used to electrically connect the first gate structure 160 and a second gate structure subsequently formed in the gate opening 270.

In this embodiment, after the conductive plug 360 is formed in the interconnect opening 350, a second gate structure is formed in the gate opening, and the conductive plug 360 and the second gate structure are independent structures and are electrically connected together. By forming the conductive plug 360 separately, the material of the conductive plug 360 can be flexibly selected according to performance requirements. Specifically, the material of the conductive plug 360 includes one or more of W, Co, Ru, TiN, TaN, Ta, Ti, TiAl, W, AL, TiSiN, and TiAlC. The material has better conductivity and higher compatibility with a metal gate structure.

Specifically, the step of forming the conductive plug 360 in the interconnect opening 350 includes: as shown in fig. 15, a conductive material 365 is filled into the interconnect opening 350, the conductive material 365 also being formed in the gate opening 270 and the through trench 280; as shown in fig. 16, the conductive material 365 in the gate opening 270 and the through trench 280 is removed by means of back etching, and the remaining conductive material 365 in the interconnect opening 350 remains as a conductive plug 360.

In this embodiment, according to the material and process requirements of the conductive plug 360, the process of filling the conductive material 365 into the interconnect opening 350 includes one or more of a physical vapor deposition process, a chemical vapor deposition process, and an atomic layer deposition process, so as to obtain a better filling effect.

In this embodiment, the conductive material 365 is formed by a deposition process, the conductive material 365 also covers the top of the top interlayer dielectric layer 260, and accordingly, the conductive material 365 on the top of the top interlayer dielectric layer 260 is also removed in the back etching process. In other embodiments, the conductive material may also be selectively formed in the gate openings, the through trenches, and the interconnect openings, depending on the chosen process.

In this embodiment, the conductive material 365 is etched back by one or both of a dry etching process and a wet etching process.

In this embodiment, after the conductive plug 360 is formed, the top of the conductive plug 360 is flush with the top of the sacrificial layer 320 at the bottom of the gate opening 270. Accordingly, during the etching back of the conductive material 365, the top of the sacrificial layer 320 at the bottom of the gate opening 270 can be used as an etching stop position, thereby facilitating precise control of the etching back amount of the conductive material 365. Moreover, in the process of etching back the conductive material 365, the sacrificial layer 320 can also protect the second gate dielectric layer 310, and the probability of damaging the second gate dielectric layer 310 is reduced.

Therefore, referring to fig. 17, after forming the conductive plug 360, further includes: the sacrificial layer 320 is removed.

The sacrificial layer 320 is a film layer that is not intended to remain in the second gate structure, and the sacrificial layer 320 is removed in preparation for the subsequent formation of the second gate structure.

In this embodiment, after removing the sacrificial layer 320, the top of the second gate dielectric layer 310 at the bottom of the gate opening 270 is lower than the top of the conductive plug 360, so that when the second gate structure is formed subsequently, the second gate structure covers not only the end of the conductive plug 360 but also a part of the sidewall of the conductive plug 360, which is beneficial to reducing the contact resistance between the conductive plug 360 and the second gate structure.

Referring to fig. 18, after forming the conductive plug 360, a second gate structure 390 is formed in the gate opening 270, and the second gate structure 390 is electrically connected to the first gate structure 160 through the conductive plug 360, wherein the second gate structure 390, the second gate dielectric layer 310, the second source-drain doping layer 201 (as shown in fig. 9), and the second channel layer 220 are used to form a second transistor structure.

The second gate structure 390 is a device gate structure for controlling the channel of the second transistor to be turned on or off. In this embodiment, the second gate structure 390 surrounds and covers the second gate dielectric layer 310 on the second channel layer 220. In other embodiments, when the second channel layer is a second fin portion, the second gate structure crosses over the second fin portion and covers a portion of the top and a portion of the sidewall of the second fin portion.

In this embodiment, the second gate structure 390 is a second metal gate structure, and the material of the second metal gate structure includes one or more of TiN, TaN, Ta, Ti, TiAl, W, AL, TiSiN, and TiAlC. Specifically, the second gate structure 390 includes a second work function layer 370, and a second gate electrode layer 380 covering the second work function layer 370. For a detailed description of the second work function layer 370 and the second gate electrode layer 380, reference may be made to the foregoing description of the first work function layer 140 and the first gate electrode layer 150, respectively, and no further description is provided herein.

Specifically, the second gate structure 390 is formed in the gate opening 270 by a deposition step and a planarization step, which are sequentially performed. During the planarization process, the second gate dielectric layer 310 on top of the top interlayer dielectric layer 260 is also removed.

It should be noted that, in the present embodiment, in different steps, the conductive plug and the second gate structure are sequentially formed. In other embodiments, the conductive plug and the second gate structure may be formed in the same step. In the step of forming the second gate structure in the gate opening, the second gate structure is further formed in the interconnect opening, the second gate structure located in the interconnect opening serves as a conductive plug, and accordingly the second gate structure and the conductive plug are of an integral structure, and the film structure and the material of the second gate structure and the film structure of the conductive plug are the same.

Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims

1. A semiconductor structure, comprising:

the first transistor structure comprises a substrate, a first channel layer positioned on the substrate, a first gate dielectric layer conformally covering the first channel layer, a first gate structure covering the first gate dielectric layer, and first source-drain doping layers positioned on the substrate at two sides of the first gate structure, wherein the first source-drain doping layers are in contact with the end part of the first channel layer positioned below the first gate structure, and the first transistor structure is provided with a bonding surface positioned at one side of the first gate structure;

the bonding layer is positioned on the bonding surface of the first transistor structure, and the material of the bonding layer is a dielectric material;

the second transistor structure is positioned on the bonding layer and comprises a second channel layer, a second gate medium layer covering the second channel layer in a shape-preserving manner, a second gate structure covering the second gate medium layer and second source-drain doping layers positioned on the bonding layer at two sides of the second gate structure, and the second source-drain doping layers are in contact with the end part of the second channel layer positioned below the second gate structure;

and the conductive plug penetrates through the second gate dielectric layer and the bonding layer at the bottom of the second gate structure and is electrically connected with the second gate structure and the first gate structure.

2. The semiconductor structure of claim 1, wherein, along a stacking direction of the first and second transistor structures, two ends of the conductive plug are electrically connected with a bottom of the second gate structure and a top of the first gate structure, respectively.

3. The semiconductor structure of claim 1, wherein the conductive plug and the second gate structure are a unitary structure.

4. The semiconductor structure of claim 1, wherein a material of the conductive plug comprises one or more of W, Co, Ru, TiN, TaN, Ta, Ti, TiAl, W, AL, TiSiN, and TiAlC.

5. The semiconductor structure of claim 1, wherein the first channel layer is a first fin raised above the substrate; the first grid electrode structure crosses the first fin part and covers the first grid dielectric layer on the partial top and partial side wall of the first fin part;

or the first channel layer is positioned on the substrate and is arranged at intervals with the substrate, and the first channel layer comprises one or more first sub-channel layers arranged at intervals; the first gate structure covers the first gate medium layer on the first channel layer in a surrounding mode.

6. The semiconductor structure of claim 1, wherein the second channel layer is a second fin raised above the bonding layer; the second gate structure crosses over the second fin portion and covers part of the top of the second fin portion and part of the second gate dielectric layer on the side wall;

or the second channel layer is located on the bonding layer and is arranged at an interval with the bonding layer, and the second channel layer comprises one or more second sub-channel layers arranged at intervals; the second gate structure covers the second gate medium layer on the second channel layer in a surrounding mode.

7. The semiconductor structure of claim 1, wherein the first gate structure comprises a first metal gate structure and the second gate structure comprises a second metal gate structure.

8. The semiconductor structure of claim 1, wherein the conductive plug also extends into a partial thickness of the second gate structure in a stacking direction of the first and second transistor structures.

9. The semiconductor structure of claim 1, wherein the first transistor structure comprises an NMOS transistor, and the second transistor structure comprises a PMOS transistor;

alternatively, the first transistor structure comprises a PMOS transistor and the second transistor structure comprises an NMOS transistor.

10. The semiconductor structure of claim 1, wherein a material of the first channel layer comprises silicon, silicon germanium, or a group iii-v semiconductor material; the material of the second channel layer includes silicon, silicon germanium, or a group III-V semiconductor material.

11. The semiconductor structure of claim 1, wherein a material of the bonding layer comprises one or more of silicon oxide, silicon nitride, silicon oxynitride, carbon-doped silicon oxide.

12. Such asThe semiconductor structure of claim 1, wherein the material of the first gate dielectric layer comprises HfO ₂ 、ZrO ₂ 、HfSiO、HfSiON、HfTaO、HfTiO、HfZrO、Al ₂ O ₃ 、SiO ₂ And La ₂ O ₃ One or more of; the material of the second gate dielectric layer comprises HfO ₂ 、ZrO ₂ 、HfSiO、HfSiON、HfTaO、HfTiO、HfZrO、Al ₂ O ₃ 、SiO ₂ And La ₂ O ₃ One or more of (a).

13. The semiconductor structure of claim 7, wherein a material of the first metal gate structure comprises one or more of TiN, TaN, Ta, Ti, TiAl, W, AL, TiSiN, and TiAlC; the material of the second metal gate structure comprises one or more of TiN, TaN, Ta, Ti, TiAl, W, AL, TiSiN and TiAl.

14. A method of forming a semiconductor structure, comprising:

forming a first transistor structure, wherein the first transistor structure comprises a first substrate, a first channel layer positioned on the first substrate, a first gate dielectric layer conformally covering the first channel layer, a first gate structure covering the first gate dielectric layer, and first source-drain doping layers positioned on the first substrate at two sides of the first gate structure, the first source-drain doping layers are in contact with the end part of the first channel layer positioned below the first gate structure, and the first transistor structure is provided with a bonding surface positioned at one side of the first gate structure;

bonding a second substrate on the bonding surface by using a bonding layer, wherein the material of the bonding layer is a dielectric material;

patterning the second substrate to form a second channel layer;

forming a dummy gate structure on the bonding layer, wherein the dummy gate structure crosses the second channel layer and covers part of the top and part of the side wall of the second channel layer;

forming second source-drain doping layers in second channel layers on two sides of the pseudo gate structure, wherein the second source-drain doping layers are in contact with the end part of the second channel layer below the pseudo gate structure;

after the second source-drain doping layer is formed, a top interlayer dielectric layer is formed on the bonding layer on the side of the pseudo gate structure, covers the side wall of the pseudo gate structure and exposes the top of the pseudo gate structure;

removing the pseudo gate structure, and forming a gate opening in the top interlayer dielectric layer;

forming a second gate dielectric layer which conformally covers the bottom and the side wall of the gate opening, wherein the second gate dielectric layer also conformally covers a second channel layer in the gate opening;

forming an interconnection opening penetrating through the second gate dielectric layer and the bonding layer at the bottom of the gate opening in the gate opening, wherein the interconnection opening exposes the first gate structure and is communicated with the gate opening;

and forming a conductive plug in the interconnection opening, forming a second grid structure in the grid opening, and realizing the electric connection between the second grid structure and the first grid structure through the conductive plug, wherein the second grid structure, the second grid medium layer, the second source-drain doping layer and the second channel layer are used for forming a second transistor structure.

15. The method of forming a semiconductor structure of claim 14, wherein a second gate structure is formed in the gate opening after forming a conductive plug in the interconnect opening.

16. The method of forming a semiconductor structure of claim 15, wherein the step of forming a conductive plug in the interconnect opening comprises: filling the interconnect opening with a conductive material, the conductive material also being formed in the gate opening;

and removing the conductive material in the gate opening by means of back etching, and reserving the residual conductive material in the interconnection opening as a conductive plug.

17. The method of forming a semiconductor structure of claim 14, wherein in the step of forming a second gate structure in the gate opening, the second gate structure is also formed in the interconnect opening, the second gate structure located in the interconnect opening acting as a conductive plug.

18. The method of forming a semiconductor structure of claim 14, wherein forming the interconnect opening comprises: filling a protective layer in the gate opening; forming a mask layer on the top of the protection layer, wherein a mask opening is formed in the mask layer, and the mask opening exposes part of the top of the protection layer on the side part of the second channel layer; taking the mask layer as a mask, and sequentially etching the protective layer, the second gate dielectric layer and the bonding layer along the mask opening to form an interconnection opening penetrating through the second gate dielectric layer and the bonding layer;

before forming the conductive plug and the second gate structure, the forming method further includes: and removing the mask layer and the protective layer.

19. The method of claim 18, wherein in the step of filling the gate opening with a protective layer, a material of the protective layer comprises an organic material.

20. The method of forming a semiconductor structure of claim 14, wherein in the step of forming the second gate dielectric layer, the second gate dielectric layer comprises a high-k gate dielectric layer;

after the second gate dielectric layer is formed and before the interconnection opening is formed, the method further includes: forming a sacrificial layer which conformally covers the second gate dielectric layer; after the sacrificial layer is formed, annealing the second gate dielectric layer;

before forming the second gate structure, further comprising: and removing the sacrificial layer.

21. The method of forming a semiconductor structure of claim 20, wherein a second gate structure is formed in the gate opening after forming a conductive plug in the interconnect opening;

in the step of forming the conductive plug, the top of the conductive plug is flush with the top of the sacrificial layer at the bottom of the gate opening;

after forming the conductive plug, removing the sacrificial layer before forming the second gate structure.

22. The method of forming a semiconductor structure of claim 14, wherein in the step of bonding a second substrate on the bonding face using a bonding layer, the second substrate is a layer of fin material;

in the step of patterning the second substrate, the second channel layer is a fin portion protruding from the bonding layer;

in the step of forming the dummy gate structure, the dummy gate structure crosses the fin part and covers part of the top and part of the side wall of the fin part;

alternatively, the first and second electrodes may be,

in the step of bonding a second substrate on the bonding face by means of a bonding layer, the second substrate comprises one or more stacked stacks of channel material, the stacks of channel material comprise a layer of sacrificial material and a layer of channel material on the layer of sacrificial material, and in the same stack of channel material, the layer of sacrificial material is closer to the bonding layer than the layer of channel material;

in the step of patterning the second substrate, patterning the channel material stack into one or more stacked channel stacks protruding above the bonding layer, the channel stack including a sacrificial layer and sub-channel layers on the sacrificial layer, the one or more sub-channel layers constituting the second channel layer;

in the step of forming the dummy gate structure, the dummy gate structure crosses the channel lamination and covers partial top and partial side wall of the channel lamination;

after the gate opening is formed and before the second gate dielectric layer is formed, the method further includes: removing the sacrificial layer exposed from the gate opening;

in the step of forming the second gate structure, the second gate structure covers the second gate dielectric layer on the second channel layer in a surrounding manner.

23. The method of forming a semiconductor structure of claim 16, wherein the process of filling the interconnect opening with a conductive material comprises one or more of a physical vapor deposition process, a chemical vapor deposition process, and an atomic layer deposition process.

24. The method of forming a semiconductor structure of claim 16, wherein the process of etching back the conductive material comprises one or both of a dry etch process and a wet etch process.