CN115249705A - Semiconductor structure and forming method thereof - Google Patents

Semiconductor structure and forming method thereof Download PDF

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Publication number
CN115249705A
CN115249705A CN202110465076.1A CN202110465076A CN115249705A CN 115249705 A CN115249705 A CN 115249705A CN 202110465076 A CN202110465076 A CN 202110465076A CN 115249705 A CN115249705 A CN 115249705A
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layer
channel
substrate
gate
device region
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金吉松
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0924—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823821—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823878—Complementary field-effect transistors, e.g. CMOS isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

A semiconductor structure and a forming method thereof are provided, wherein the forming method comprises the following steps: providing a substrate, wherein the substrate comprises a first device area and a second device area which are adjacent, a channel structure is formed on the substrate, the channel structure comprises one or more stacked channel laminates, the channel laminates comprise a first sacrificial layer and a channel layer positioned on the first sacrificial layer, a partition wall is formed on the substrate between the adjacent channel structures at the junction of the first device area and the second device area, a pseudo gate structure is further formed on the substrate, source and drain doped layers are formed on the substrate at two sides of the pseudo gate structure, and the adjacent source and drain doped layers are isolated through the partition wall; forming an interlayer dielectric layer on the substrate, and exposing the top of the pseudo gate structure; removing the dummy gate structure to form a gate opening; removing the isolation wall exposed from the gate opening; removing the first sacrificial layer exposed by the gate opening; and removing the isolation wall and the first sacrificial layer exposed by the gate opening to form a gate structure surrounding and covering the channel layer. The gate structure circumferentially covers the channel layer, increasing the area in the channel layer for acting as a channel.

Description

Semiconductor structure and forming method thereof
Technical Field
Embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular, to a semiconductor structure and a method for forming the same.
Background
With the rapid development of semiconductor manufacturing technology and the development of semiconductor devices toward higher element density and higher integration, the trend of semiconductor process nodes following moore's law is decreasing. Transistors are currently being widely used as the most basic semiconductor devices, and therefore, as the element density and integration of semiconductor devices increase, the channel length of transistors has to be continuously shortened in order to accommodate the reduction of process nodes.
In order to better accommodate the scaling requirements of device dimensions, semiconductor processes are gradually starting to transition from planar transistors to three-dimensional transistors with higher power efficiency, such as Gate-all-around (GAA) transistors and forkgate (forkheet) transistors. The cross-gate transistor can reduce the cell area as a whole, but the performance of the cross-gate transistor still needs to be improved.
Disclosure of Invention
Embodiments of the present invention provide a semiconductor structure and a method for forming the same, which improve the performance of the semiconductor structure.
To solve the above problem, an embodiment of the present invention provides a semiconductor structure, including: the device comprises a substrate, a first electrode and a second electrode, wherein the substrate comprises a first device area and a second device area which are adjacent; a channel layer structure suspended over the substrate along a normal to the substrate surface, the channel layer structure comprising one or more spaced channel layers; the grid structure is positioned on the substrate and crosses the channel layer structure, and comprises a grid medium layer surrounding the channel layer along the extension direction of the grid structure and a grid electrode layer positioned on the grid medium layer; the grid side wall is positioned on the side wall of the grid structure; the source-drain doping layer is positioned on the substrate at two sides of the grid structure and is contacted with the end part of the channel layer structure; and the isolation wall is protruded on the substrate between the adjacent source-drain doping layers at the junction of the first device area and the second device area, and is in contact with the gate structure.
Correspondingly, an embodiment of the present invention further provides a method for forming a semiconductor structure, including: providing a substrate, wherein the substrate comprises a first device region and a second device region which are adjacent, a channel structure is formed on the substrate, the channel structure comprises one or more stacked channel lamination layers, each channel lamination layer comprises a first sacrificial layer and a channel layer positioned on the first sacrificial layer, the extending direction of the channel structure is vertical to the arrangement direction of the first device region and the second device region, a separation wall covering the side wall of the channel structure is formed on the substrate between the adjacent channel structures at the junction of the first device region and the second device region, a pseudo gate structure crossing the channel structure and the separation wall is further formed on the substrate, the pseudo gate structure covers partial side wall and partial top of the channel structure and partial top of the separation wall, source and drain doping layers are further formed on the substrate at two sides of the pseudo gate structure, the source and drain doping layers are in contact with the end part of the channel structure below the pseudo gate structure, and the adjacent channel doping layers are separated by the separation wall at the junction of the first device region and the second device region; forming an interlayer dielectric layer on the substrate to cover the source-drain doping layer, wherein the interlayer dielectric layer also covers the side wall of the pseudo gate structure and exposes the top of the pseudo gate structure; removing the pseudo gate structure, and forming a gate opening in the interlayer dielectric layer, wherein the gate opening exposes the isolation wall; removing the isolation wall exposed from the gate opening; removing the first sacrificial layer exposed from the gate opening to form a through groove communicated with the gate opening and expose the channel layer; and after the isolation wall and the first sacrificial layer exposed by the gate opening are removed, forming a gate structure crossing the channel layer in the gate opening and the through groove, wherein the gate structure covers the channel layer in a surrounding manner.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following advantages:
the semiconductor structure provided by the embodiment of the invention comprises a separation wall, wherein the separation wall is raised on a substrate between adjacent source-drain doping layers at the junction of a first device area and a second device area, and the separation wall is in contact with a grid structure; in the embodiment of the invention, the isolation wall isolates the source-drain doping layers of the first device region and the second device region, so that the source-drain doping layers of the first device region and the second device region are close to each other as much as possible under the condition of better ensuring the isolation effect on adjacent devices, and the distance between adjacent channel layer structures of the first device region and the second device region is favorably reduced, so that a device with a tighter size and a smaller size is formed.
In the forming method provided by the embodiment of the invention, at the junction of the first device area and the second device area, a separation wall covering the side wall of the channel structure is formed between the adjacent channel structures, and at the junction of the first device area and the second device area, the adjacent source-drain doped layers are separated by the separation wall, then the pseudo gate structure is removed, a gate opening is formed in the interlayer dielectric layer, the gate opening exposes the separation wall, and the separation wall exposed by the gate opening is removed; in the embodiment of the invention, at the junction of the first device region and the second device region, a separation wall covering the side wall of the channel structure is formed between the adjacent channel structures, and the adjacent source-drain doping layers are separated by the separation wall, so that the source-drain doping layers of the adjacent first device region and the adjacent second device region are as close as possible under the condition of better ensuring the separation effect on the adjacent devices, the distance between the adjacent channel structures of the first device region and the second device region is favorably reduced, and a device with a tighter size is formed.
Drawings
Fig. 1 to 4 are schematic structural diagrams corresponding to steps in a method for forming a semiconductor structure;
FIGS. 5-7 are schematic structural diagrams illustrating a semiconductor structure according to an embodiment of the present invention;
fig. 8 to 19 are schematic structural diagrams corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention.
Detailed Description
The performance of semiconductor structures currently needs to be improved. The reason why the performance of the semiconductor structure needs to be improved is analyzed in combination with a method for forming the semiconductor structure.
Fig. 1 to 4 are schematic structural diagrams corresponding to steps in a method for forming a semiconductor structure.
Referring to fig. 1 to fig. 3 in combination, fig. 1 is a perspective view, fig. 2 is a cross-sectional view based on an AA direction of fig. 1, fig. 3 is a cross-sectional view based on a BB direction, a substrate 10 is provided, a channel structure 20 is formed on the substrate 10, the channel structure 20 includes one or more channel stacks 21, wherein the channel stack 21 includes a sacrificial layer 22 and a channel layer 23 located on the sacrificial layer 22, the substrate includes a first device region 10N and a second device region 10P which are adjacent to each other, a partition wall 41 protruding from the substrate 10 is formed between the adjacent channel structures 20 at a boundary between the first device region 10N and the second device region 10P, the partition wall 41 covers opposite sidewalls of the channel structure 20, and the partition wall 41 further extends to the substrate 10 on two sides of the dummy gate structure 61 along an extending direction of the channel structure 20.
With continuing reference to fig. 1 to 3, forming a dummy gate structure 61 on the substrate 10, wherein the dummy gate structure 61 crosses over the trench structure 20 and the isolation wall 41, and the dummy gate structure 61 covers a part of the sidewall of the trench structure 20 and a part of the top of the trench structure 20 and the isolation wall 41; and forming source-drain doping layers 50 in the channel structures 20 at two sides of the pseudo gate structure 61.
Referring to fig. 4, fig. 4 is a cross-sectional view based on fig. 3, in which the dummy gate structure 61 is removed to expose the sacrificial layer 22; removing the exposed sacrificial layer 22; after removing the exposed sacrificial layer 22, a metal gate structure 60 covering the top, bottom and partial sidewalls of the channel layer 23 is formed at the positions of the dummy gate structure 40 and the sacrificial layer 22.
At present, in order to make the distance between adjacent channel structures 20 smaller at the junction between the first device region 10N and the second device region 10P, a partition wall 41 covering the sidewall of the channel structure 20 is formed at the junction between the first device region 10N and the second device region 10P, and the partition wall 41 ensures the isolation effect on adjacent devices under the condition that the source-drain doping layers 50 adjacent to the first device region 10N and the second device region 10P are as close as possible.
However, the partition wall 41 covers the sidewall of the channel layer 23 at the boundary between the first device region 10N and the second device region 10P, so after the metal gate structure 60 is formed, the metal gate structure 60 is difficult to completely cover the opposite sidewalls of the channel layer 23, that is, the metal gate structure 60 only covers the top and bottom of the channel layer 23 and the sidewall facing away from the partition wall 41 under the shielding of the partition wall 41, the sidewall of the channel layer 23 contacting the partition wall 41 is difficult to cover by the metal gate structure 60, and since the portion of the channel layer 23 covered by the metal gate structure 60 is used as a channel, the area of the channel layer 23 used as a channel is reduced, and thus the operating current of the semiconductor structure is difficult to increase, and it is difficult to improve the performance of the semiconductor structure.
In order to solve the technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate, wherein the substrate comprises a first device area and a second device area which are adjacent, a channel structure is formed on the substrate, the channel structure comprises one or more stacked channel laminates, each channel laminate comprises a first sacrificial layer and a channel layer positioned on the first sacrificial layer, the extending direction of the channel structure is vertical to the arrangement direction of the first device area and the second device area, an isolation wall covering the side wall of the channel structure is formed on the substrate between the adjacent channel structures at the junction of the first device area and the second device area, a pseudo gate structure crossing the channel structure and the isolation wall is further formed on the substrate, the pseudo gate structure covers part of the side wall and part of the top of the channel structure and part of the top of the isolation wall, source and drain doping layers are further formed on the substrate at two sides of the pseudo gate structure, the source and drain doping layers are in contact with the end part of the channel structure below the pseudo gate structure, and the adjacent source and drain doping layers are isolated from the junction of the first device area and the second device area through the isolation wall; forming an interlayer dielectric layer on the substrate to cover the source-drain doping layer, wherein the interlayer dielectric layer also covers the side wall of the pseudo gate structure and exposes the top of the pseudo gate structure; removing the pseudo gate structure, and forming a gate opening in the interlayer dielectric layer, wherein the gate opening exposes the isolation wall; removing the isolation wall exposed from the gate opening; removing the first sacrificial layer exposed from the gate opening to form a through groove communicated with the gate opening and expose the channel layer; and after the isolation wall and the first sacrificial layer exposed by the gate opening are removed, forming a gate structure crossing the channel layer in the gate opening and the through groove, wherein the gate structure covers the channel layer in a surrounding manner.
In the forming method provided by the embodiment of the invention, at the junction of the first device region and the second device region, a separation wall covering the side wall of the channel structure is formed between the adjacent channel structures, and the adjacent source/drain doping layers are separated by the separation wall, so that under the condition of better ensuring the separation effect on the adjacent devices, the source/drain doping layers of the adjacent first device region and the adjacent second device region are as close as possible, which is favorable for reducing the distance between the adjacent channel structures of the first device region and the second device region, thereby forming a device with a tighter size.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 5 to 7 are schematic structural diagrams of a semiconductor structure according to an embodiment of the present invention, wherein fig. 5 is a perspective view, fig. 6 is a cross-sectional view of fig. 5 taken along the AA direction, and fig. 7 is a cross-sectional view of fig. 5 taken along the BB direction.
The semiconductor structure includes: a substrate 101, wherein the substrate 101 comprises a first device region 101N and a second device region 101P which are adjacent to each other; a channel layer structure 201 suspended over the substrate 101, the channel layer structure 201 comprising one or more spaced apart channel layers 231 along a normal direction of a surface of the substrate 101; a gate structure 601 located on the substrate 101 and crossing the channel layer structure 231, wherein the gate structure 601 includes a gate dielectric layer 641 surrounding the channel layer 231 along an extending direction of the gate structure 601, and a gate electrode layer (not shown) located on the gate dielectric layer 641; a gate sidewall 631 located on a sidewall of the gate structure 601; the source-drain doping layer 501 is located on the substrate on two sides of the gate structure 601, and the source-drain doping layer 501 is in contact with the end portion of the channel layer structure 201; the isolation wall 411 protrudes from the substrate 101 between the adjacent source/drain doping layers 501 at the junction of the first device region 101N and the second device region 101P, and the isolation wall 411 is in contact with the gate structure 601.
In the embodiment of the present invention, the isolation wall 411 isolates the source-drain doping layers 501 of the first device region 101N and the second device region 101P, so that under the condition of better ensuring the isolation effect on adjacent devices, the source-drain doping layers 501 adjacent to the first device region 101N and the second device region 101P are as close as possible, which is beneficial to reducing the distance between the adjacent channel layer structures 201 of the first device region 101N and the second device region 101P, thereby forming a device with a tighter and smaller size, and meanwhile, the isolation wall 411 is only located between the adjacent source-drain doping layers 501 at the junction between the first device region 101N and the second device region 101P, but not located between the adjacent channel layer structures 201 below the gate structure 601, so that the gate structure 601 surrounds and covers each surface of the channel layer 231, thereby increasing the area used as a channel in the channel layer 231 while forming a device with a smaller size, further increasing the working current of the semiconductor structure, and being beneficial to improving the performance of the semiconductor structure.
In addition, in this embodiment, the isolation wall 411 is in contact with the gate structure 601, so that the adjacent source/drain doping layer 501 near the junction of the first device region 101P and the second device region 101N can be better isolated.
The substrate 101 provides a process operation basis for the formation process of the semiconductor structure. The semiconductor structure includes a gate-all-around (GAA) transistor and a forkgate (Forksheet) transistor.
The substrate 101 includes a semiconductor substrate (not shown).
In this embodiment, the semiconductor substrate is made of silicon, in other embodiments, the semiconductor substrate may also be made of other materials such as germanium, silicon germanium, gallium nitride, silicon carbide, gallium arsenide, or indium gallium arsenide, and the semiconductor substrate may also be a silicon-on-insulator semiconductor substrate or another type of semiconductor substrate such as a germanium-on-insulator semiconductor substrate. The material of the semiconductor substrate may be a material suitable for process requirements or easy integration.
It should be noted that the substrate 101 may further include: a fin (not labeled) discrete on the semiconductor substrate.
In this embodiment, the substrate 101 further includes an isolation layer 111 located in the substrate 101 and surrounding the fin portion, and the isolation layer 111 exposes a top surface of the fin portion. The isolation layer 111 is used to achieve isolation between different devices, for example, in a CMOS fabrication process, the isolation layer 111 is typically formed between an NMOS transistor and a PMOS transistor.
The material of the isolation layer 111 includes one or more of silicon oxide, carbon-doped silicon oxide, silicon oxynitride, silicon nitride, boron-doped silicon oxide, and phosphorus-doped silicon oxide. In this embodiment, taking the semiconductor structure as a cross-gate transistor as an example, the substrate 101 includes a first device region 101N and a second device region 101P which are adjacent to each other, the first device region 101N is used for forming a first device, and the second device region 101P is used for forming a second device.
In this embodiment, the first device region 101N includes an NMOS region, the second device region 101P includes a PMOS region, the NMOS region is used to form an NMOS transistor, and the PMOS region is used to form a PMOS transistor.
With the shrinking feature size of devices, the use of the cross-type gate transistors allows for smaller spacing between adjacent NMOS and PMOS transistors, thereby allowing for better area scalability.
The channel layer structure 201 includes one or more longitudinally spaced channel layers 231, the channel layers 231 being for serving as channels of a semiconductor structure. Wherein, the longitudinal direction refers to a normal direction of the surface of the substrate 101.
In this embodiment, the material of the channel layer 231 includes silicon, germanium, silicon germanium, or a iii-v semiconductor material. As an example, the material of the channel layer 231 is silicon. In other embodiments, the material of the channel layer is determined according to the type and performance of the transistor.
It should be noted that, in this embodiment, the material of the channel layer 231 and the substrate 101 are the same, and in other embodiments, the material of the channel layer and the substrate may also be different.
In this embodiment, the gate structure 601 is used to control the on/off of the channel of the transistor.
In this embodiment, the gate structure 601 includes a gate dielectric layer 641 surrounding the channel layer 231 along an extending direction of the gate structure 601.
In this embodiment, the gate dielectric layer 641 conformally covers the sidewall, the top, and the bottom of the channel layer 231, and the gate structure 601 circumferentially covers the gate dielectric layer 641, so that the gate structure 601 conformally covers the sidewall, the top, and the bottom of the channel layer 231.
It should be noted that, the top, the bottom, and the sidewalls of the channel layer 231 covered by the gate structure 601 are used as channels, in this embodiment, the gate structure 601 covers the top, the opposing sidewalls, and the bottom of the channel layer 231, so that the top, the bottom, and the sidewalls of the channel layer 231 can be used as channels, the area of the channel layer 231 used as a channel is increased, and the operating current of the semiconductor structure is increased.
The gate dielectric layer 641 is used for isolating the gate structure 601 from the channel layer 231.
The gate dielectric layer 641 comprises HfO 2 、ZrO 2 、HfSiO、HfSiON、HfTaO、HfTiO、HfZrO、Al 2 O 3 、SiO 2 And La 2 O 3 One or more of (a). In this embodiment, the gate dielectric layer 620 includes a high-k dielectric material. Wherein, the high-k dielectric material is a dielectric material with a relative dielectric constant larger than that of silicon oxide. Specifically, the material of the high-k gate dielectric layer comprises HfO 2 、ZrO 2 HfSiO, hfSiON, hfTaO, hfTiO, hfZrO or Al 2 O 3 And the like.
In this embodiment, the gate structure 601 includes a metal gate structure.
In this embodiment, the metal gate structure includes a work function layer (not labeled) and a gate electrode layer (not labeled) on the work function layer.
The work function layer is used for adjusting the threshold voltage of the transistor. For the PMOS transistor, the work function layer is a P-type work function layer, and the material of the P-type work function layer comprises one or more of TiN, taN, taSiN, taAlN and TiAlN; for an NMOS transistor, the work function layer is an N-type work function layer, and the material of the N-type work function layer comprises one or two of TiAl and TiAl C.
The gate electrode layer is used for leading out the electrical property of the metal gate structure. In this embodiment, the material of the gate electrode layer includes one or more of TiN, taN, ta, ti, tiAl, W, AL, tiSiN, and TiAlC.
In other embodiments, the gate structure may also be a polysilicon gate structure according to process requirements.
The gate sidewall 631 is used for protecting the sidewall of the gate structure 601.
The gate sidewall 631 may have a single-layer structure or a stacked-layer structure, and the material of the gate sidewall 631 may include one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride, and boron carbonitride. In this embodiment, the gate sidewall 631 has a single-layer structure, and the gate sidewall 631 is made of silicon nitride.
The source-drain doping layer 501 is used as a source region or a drain region of a transistor, and the doping type of the source-drain doping layer 501 is the same as the channel conductivity type of the corresponding transistor.
Specifically, when the substrate 101 is used to form an NMOS transistor, the doping ions in the source-drain doping layer 501 are N-type ions, and the N-type ions include P ions, as ions, or Sb ions; when the substrate 101 is used for forming a PMOS transistor, the doped ions In the source-drain doped layer 501 are P-type ions, and the P-type ions include B ions, ga ions, or In ions.
In this embodiment, the semiconductor structure further includes: and an inner sidewall (not shown) located between the adjacent channel layers 231 along a normal direction of the surface of the substrate 101, and located between the sidewall of the gate structure 601 and the source/drain doping layer 501 along a direction perpendicular to the extending direction of the gate structure 601.
The inner sidewall has the function of isolating the gate structure 601 from the source-drain doped layer 501, so that the parasitic capacitance between the gate structure 601 and the source-drain doped layer 501 is reduced.
The inner side wall is made of an insulating material. In this embodiment, the material of the inner sidewall includes silicon oxide.
The isolation wall 411 is used for isolating the adjacent source/drain doping layers 501 close to the junction of the first device region 101N and the second device region 101P, so that the source/drain doping layers 501 adjacent to the first device region 101N and the second device region 101P are as close as possible under the condition of better ensuring the isolation effect on the adjacent devices, which is beneficial to reducing the distance between the adjacent channel layer structures 201 of the first device region 101N and the second device region 101P, thereby forming a device with a tighter size and a smaller size.
In this embodiment, the top of the isolation wall 411 is higher than or flush with the top of the channel layer structure 201, so as to improve the isolation effect on the adjacent source-drain doped layer 501. As shown in fig. 6, the top of the isolation wall 410 is shown to be higher than the top of the channel layer structure 201.
In this embodiment, at the junction between the first device region 101N and the second device region 101P, the source-drain doping layer 501 adjacent to the first device region 101N and the source-drain doping layer 501 adjacent to the second device region 101P are respectively in contact with the isolation wall 411.
In the direction perpendicular to the extending direction of the channel layer structure 201, the source/drain doping layer 501 grows to the isolation wall 411 at most in an epitaxial manner, so that the source/drain doping layer 501 of the first device region 101N and the source/drain doping layer 501 of the second device region 101P which are adjacent to each other are respectively in contact with the isolation wall 411, and the size of the source/drain doping layer 501 can be maximized as much as possible in the direction perpendicular to the extending direction of the channel layer structure 201, thereby improving the performance of the semiconductor structure.
It should be noted that the step of forming the partition wall 411 includes: forming a channel structure material layer on the substrate 101 of the first device region 101N and the second device region 101P; removing the channel structure material layer at the junction of the first device region 101N and the second device region 101P to form a groove, and reserving the remaining channel structure material layer as a channel structure 201, wherein the groove isolates the channel structure 201 of the first device region 101N from the channel structure 201 of the second device region 101P; filling the groove to form an initial isolation wall; forming a pseudo gate structure covering the top of the initial isolation wall part and a gate side wall of the pseudo gate structure; removing the dummy gate structure to form a gate opening surrounded by the gate side wall; and removing the initial isolation wall exposed by the gate opening, and reserving the residual initial isolation wall as the isolation wall.
Therefore, in this embodiment, the isolation wall 411 is in contact with the gate structure 601, and the isolation wall 411 penetrates through the gate sidewall 631 along the extending direction of the channel layer structure 201.
In this embodiment, the material of the isolation wall 411 includes silicon oxide, silicon nitride, silicon oxynitride, or carbon-doped silicon oxide.
The silicon oxide, the silicon nitride, the silicon oxynitride or the carbon-doped silicon oxide has good insulation, so that a good isolation effect can be achieved between the adjacent source/drain doping layers 501 at the junction of the first device region 101N and the second device region 101P.
Fig. 8 to 19 are schematic structural diagrams corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention.
With reference to fig. 8 to 10, where fig. 8 is a perspective view, fig. 9 is a sectional view of fig. 8 based on an AA direction, fig. 10 is a sectional view of fig. 8 based on a BB direction, a substrate 100 is provided, which includes a first device region 100N and a second device region 100P that are adjacent to each other, a channel structure 200 is formed on the substrate 100, the channel structure 200 includes one or more stacked channel stacks 210, the channel stack 210 includes a first sacrificial layer 220 and a channel layer 230 on the first sacrificial layer 220, an extending direction of the channel structure 200 is perpendicular to an arrangement direction of the first device region 100N and the second device region 100P, a separation wall 410 covering a sidewall of the channel structure 200 is formed on the substrate 100 between adjacent channel structures 200 at a boundary between the first device region 100N and the second device region 100P, a source-drain structure 610 crossing the channel structure 200 and the separation wall 410 is further formed on the substrate 100, the dummy structure 610 covers a portion of the sidewall and a top portion of the channel structure 200, and a top portion of the drain structure 500 is in contact with the second device region 100N, and the dummy gate structure 500 is further formed on both sides of the substrate 100, and the substrate 100, the dummy doped layer, the source-drain structure 500 is in contact with the source-drain structure 500, and the drain structure 500.
The substrate 100 provides a process operation basis for the formation process of the semiconductor structure. The semiconductor structure includes a gate-all-around (GAA) transistor and a forkgate (Forksheet) transistor.
The substrate 100 includes a semiconductor substrate (not shown).
In this embodiment, the semiconductor substrate is made of silicon, in other embodiments, the semiconductor substrate may also be made of other materials such as germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, and the semiconductor substrate may also be a silicon-on-insulator semiconductor substrate or another type of semiconductor substrate such as a germanium-on-insulator semiconductor substrate. The material of the semiconductor substrate may be a material suitable for process requirements or easy integration.
It should be noted that the substrate 100 may further include: fins (not labeled) are discrete on the semiconductor substrate.
In this embodiment, the substrate 100 further includes an isolation layer 110 located in the substrate 100 and surrounding the fin portion, and the isolation layer 110 exposes the top surface of the fin portion. The isolation layer 110 is used to isolate different devices, for example, in a CMOS fabrication process, the isolation layer 110 is typically formed between an NMOS transistor and a PMOS transistor.
The material of the isolation layer 110 includes one or more of silicon oxide, carbon-doped silicon oxide, silicon oxynitride, silicon nitride, boron-doped silicon oxide, and phosphorus-doped silicon oxide. In this embodiment, taking the semiconductor structure as a cross-gate transistor as an example, the substrate 100 includes a first device region 100N and a second device region 100P that are adjacent to each other, the first device region 100N is used for forming a first device, and the second device region 100P is used for forming a second device.
In this embodiment, the first device region 100N includes an NMOS region, and the second device region 100P includes a PMOS region, the NMOS region is used to form an NMOS transistor, and the PMOS region is used to form a PMOS transistor, so as to form a cross-gate transistor.
With the continuous shrinking of the device feature size, the fork-type gate transistors can allow smaller spacing between adjacent NMOS transistors and PMOS transistors, thereby achieving better area scalability.
The channel layer 230 in the channel structure 200 is used as a channel of a transistor, and the first sacrificial layer 220 is used for providing a process foundation for a subsequent suspension of the channel layer 230, and also for occupying a spatial position for a subsequently formed gate structure. In the subsequent process, the first sacrificial layer 220 is removed, such that the channel layer 230 is suspended, and gate structures are formed between the channel layer 230 and the substrate 100 and between adjacent channel layers 230, such that the gate structures surround and cover the channel layer 230.
The top and the sidewall of the channel layer 230 covered by the gate structure are used as a channel, and in this embodiment, the top, the bottom and the sidewall of the channel layer 230 can be used as a channel, so that the area of the channel layer 230 used as a channel is increased, and the operating current of the semiconductor structure is increased.
In this embodiment, the material of the channel layer 230 includes silicon, germanium, silicon germanium, or a iii-v semiconductor material. As an example, the material of the channel layer 230 is silicon. In other embodiments, the material of the channel layer is determined according to the type and performance of the transistor.
It should be noted that, in this embodiment, the material of the channel layer 230 is the same as that of the substrate 100, and in other embodiments, the material of the channel layer may be different from that of the substrate.
In this embodiment, the material of the first sacrificial layer 220 includes silicon, germanium or silicon germanium, and an etching selection ratio is provided between the materials of the channel layer 230 and the first sacrificial layer 220, which is beneficial to removing the first sacrificial layer 220 subsequently.
In this embodiment, the channel layer 230 is made of silicon, and therefore, the first sacrificial layer 220 is made of silicon germanium.
The silicon germanium and the silicon can form a larger etching selection ratio, which is beneficial to removing the first sacrificial layer 220 subsequently and reducing the damage to the channel layer 230.
In other embodiments, a material suitable for the channel layer with an etching selectivity ratio may be selected according to the material of the channel layer, so as to reduce damage to the channel layer when the first sacrificial layer is removed later.
In this embodiment, in the step of providing the substrate 100, the channel structure 200 further includes a second sacrificial layer 240 on the topmost channel stack 210.
The second sacrificial layer 240 is used to occupy a space position for increasing the height of the formed gate structure, and meanwhile, the isolation wall 410 below the dummy gate structure 610 is removed later, and the second sacrificial layer 240 is also used to protect the top of the topmost channel layer 230.
In this embodiment, in the step of forming the channel structure 200, the first sacrificial layer 220 and the second sacrificial layer 240 are made of the same material, which is favorable for simplifying the forming process, and the subsequent step of removing a part of the first sacrificial layer 220 and the second sacrificial layer 240 is also required, which is favorable for removing the first sacrificial layer 220 and the second sacrificial layer 240 in the same step, so that the removing process is simplified.
Specifically, the material of the second sacrificial layer 240 includes silicon germanium.
The silicon germanium and the silicon can form a larger etching selection ratio, which is beneficial to removing the second sacrificial layer 240 subsequently and reducing the damage to the channel layer 230.
The isolation wall 410 is used for isolating the junction between the first device region 100N and the second device region 100P from the adjacent source-drain doping layer 500.
In this embodiment, the top of the isolation wall 410 is higher than or flush with the top of the channel structure 200, so as to improve the isolation effect on the adjacent source-drain doped layers 500. As shown in fig. 10, the case where the top of the partition wall 410 is flush with the top of the channel structure 200 is shown.
It should be noted that the step of forming the partition wall 410 includes: forming a channel structure material layer on the substrate 100 of the first and second device regions 100N and 100P; removing the channel structure material layer at the junction of the first device region 100N and the second device region 100P to form a groove, and reserving the remaining channel structure material layer as a channel structure 200, wherein the groove isolates the channel structure 200 of the first device region 100N from the channel structure 200 of the second device region 100P; the grooves are filled with a partition wall 410.
Therefore, in this embodiment, at the junction between the first device region 100N and the second device region 100P and on the substrate 100 between the adjacent channel structures 200, the isolation wall 410 covers the side wall of the channel structure 200, and compared with a scheme in which the channel structures are formed separately in the first device region and the second device region, this embodiment is favorable for reducing the distance between the adjacent channel structures 200, and the source-drain doping layer 500 is in contact with the end portion of the channel structure 200 below the dummy gate structure 610, and the source-drain doping layer 500 is isolated by the isolation wall 410, so that the source-drain doping layer 500 adjacent to the first device region 100N and the second device region 100P can be made as close as possible under the condition of better ensuring the isolation effect on the adjacent devices, and is favorable for reducing the distance between the adjacent channel structures 200 between the first device region 100N and the second device region 100P, thereby forming a tighter device with a smaller size.
In this embodiment, the material of the isolation wall 410 includes silicon oxide, silicon nitride, silicon oxynitride, or carbon-doped silicon oxide.
The silicon oxide, the silicon nitride, the silicon oxynitride or the carbon-doped silicon oxide have good insulativity, so that a good isolation effect can be achieved between the adjacent source-drain doping layers 500 at the junction of the first device area 100N and the second device area 100P.
The dummy gate structure 610 occupies a space for a gate structure formed in a subsequent process.
In this embodiment, the dummy gate structure 610 may be a single-layer structure or a stacked-layer structure, and the material of the dummy gate structure 610 includes one or both of amorphous silicon and polysilicon. In other embodiments, the material of the dummy gate structure may also be silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon nitride, silicon oxycarbonitride, or amorphous carbon.
In this embodiment, the dummy gate structure 610 is a single-layer structure, and the material of the dummy gate structure 610 is amorphous silicon. The amorphous silicon does not have a crystal orientation, so that the uniformity of the etching rate and the uniformity of the etching effect of the amorphous silicon are better, and the subsequent removal effect of the dummy gate structure 610 is improved.
It should be noted that, according to process requirements, a dummy gate oxide layer (not shown) may be further formed between the dummy gate structure 610 and the channel structure 200. Wherein, the material of the pseudo gate oxide layer can be silicon oxide.
In this embodiment, a gate sidewall 630 is further formed on the sidewall of the dummy gate structure 610.
The gate sidewall spacers 630 are used to subsequently protect sidewalls of the gate structure.
The gate sidewall 630 may have a single-layer structure or a stacked-layer structure, and the material of the gate sidewall 630 includes one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride, and boron carbonitride. In this embodiment, the gate sidewall 630 has a single-layer structure, and the material of the gate sidewall 630 is silicon nitride.
The source-drain doping layer 500 is used as a source region or a drain region of a transistor, and the doping type of the source-drain doping layer 500 is the same as the channel conductivity type of the corresponding transistor.
Specifically, when the substrate 100 is used to form an NMOS transistor, the doped ions in the source-drain doped layer 500 are N-type ions, and the N-type ions include P ions, as ions, or Sb ions; when the substrate 100 is used to form a PMOS transistor, the doped ions In the source-drain doped layer 500 are P-type ions, and the P-type ions include B ions, ga ions, or In ions.
The adjacent source/drain doping layers 500 close to the junction of the first device region 100N and the second device region 100P are isolated by the isolation wall 410, so that the isolation effect between the adjacent source/drain doping layers 500 is better ensured.
It should be noted that, in this embodiment, the source/drain doping layer 500 is formed at the end portion of the channel structure 200 below the dummy gate structure 610 through an epitaxial growth process, so that the source/drain doping layer 500 is in contact with the isolation wall 410, and the size of the source/drain doping layer 500 can be maximized as much as possible in the direction perpendicular to the extending direction of the channel structure 200, thereby improving the performance of the semiconductor structure.
With reference to fig. 11 and 12, where fig. 11 is a perspective view, and fig. 12 is a cross-sectional view of fig. 11 based on an AA direction, an interlayer dielectric layer 300 covering the source-drain doping layer 500 is formed on the substrate 100, and the interlayer dielectric layer 300 further covers a sidewall of the dummy gate structure 610 and exposes a top of the dummy gate structure 610.
The interlayer dielectric layer 300 is used for isolating adjacent devices, the interlayer dielectric layer 300 is further used for providing a process foundation for the subsequent removal of the dummy gate structure 610 to form a gate opening, and the interlayer dielectric layer 300 is exposed out of the top of the dummy gate structure 610 and is used for preparing for the subsequent removal of the dummy gate structure 610.
In this embodiment, the interlayer dielectric layer 300 is formed by a chemical vapor deposition process, the interlayer dielectric layer 300 covers the source-drain doping layer 500 and the dummy gate structure 610, and then the interlayer dielectric layer 300 is planarized by a chemical mechanical polishing process to remove a part of the thickness of the interlayer dielectric layer 300 and expose the top of the dummy gate structure 610.
The interlayer dielectric layer 300 is made of an insulating material and includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride and silicon oxycarbonitride.
It should be noted that fig. 11 illustrates the source-drain doping layer 500 and the isolation wall 410, and in an actual process, the interlayer dielectric layer 300 covers the source-drain doping layer 500 and the isolation wall 410.
Referring to fig. 13 and 14 in combination, where fig. 13 is a perspective view, and fig. 14 is a cross-sectional view of fig. 13 based on the BB direction, the dummy gate structure 610 is removed, a gate opening 620 is formed in the interlayer dielectric layer 300, and the gate opening 620 exposes the isolation wall 410.
Specifically, the dummy gate structure 610 and the dummy gate oxide layer are sequentially removed.
The gate opening 620 provides a spatial location for a subsequent formation of a gate structure, and at the same time, the gate opening 620 exposes the isolation wall 410 in preparation for a subsequent removal of the isolation wall 410, and the gate opening 620 also exposes the first sacrificial layer 220 and the second sacrificial layer 240 in preparation for a subsequent removal of the first sacrificial layer 220 and the second sacrificial layer 240.
Referring to fig. 15, fig. 15 is a cross-sectional view based on fig. 14, in which the isolation wall 410 exposed by the gate opening 620 is removed.
As the feature size of the integrated circuit is continuously reduced, adjacent devices are closer to each other, in the embodiment of the present invention, at the junction between the first device region 100N and the second device region 100P, a separation wall 410 covering the sidewall of the channel structure 200 is formed between adjacent channel structures 200, and adjacent source-drain doping layers 500 are separated by the separation wall 410, so that under the condition of better ensuring the separation effect on adjacent devices, the source-drain doping layers 500 adjacent to the first device region 100N and the second device region 100P are as close as possible, which is favorable for reducing the distance between the adjacent channel structures 200 of the first device region 100N and the second device region 100P, thereby forming a more compact device with a smaller size, and in the embodiment of the present invention, after forming the gate opening 620, the separation wall 410 between the adjacent channel structures 200 exposed by the gate opening 620 is removed, so that under the condition of retaining the separation wall 410 between the adjacent source-drain doping layers 500, the sidewall of the first device region 100N and the sidewall of the second device region 100P is also covered by the gate structure 230, thereby being favorable for increasing the size of the semiconductor channel layer 230 and the semiconductor channel structures 230, thereby increasing the performance of the semiconductor channel layer 230.
In this embodiment, the isolation wall 410 is etched and removed by a maskless etching method.
Since the first sacrificial layer 220 and the second sacrificial layer 240 can protect the channel layer 230, the isolation wall 410 can be etched and removed by a maskless etching method.
By using a maskless etching method, the isolation wall 410 can be removed with good position accuracy, so as to avoid the problem of alignment error caused by the existing photolithography process. The maskless etching process comprises one or two of a dry etching process and a wet etching process.
It should be noted that, in other implementations, according to process requirements, a photomask may also be used to define the area to be etched in the isolation wall.
Referring to fig. 16, fig. 16 is a cross-sectional view based on fig. 15, in which the first sacrificial layer 220 exposed by the gate opening 620 is removed, and a through groove 250 communicating with the gate opening 620 is formed to expose the channel layer 230.
The through-trench 250 is used to provide a space for a subsequently formed gate structure, and the through-trench 250 exposes the top, bottom, and sidewalls of the channel layer 230, so that the subsequently formed gate structure covers the channel layer 230 in a surrounding manner.
In this embodiment, the first sacrificial layer 220 is removed by a wet etching process. The wet etching process has relatively low cost and simple operation steps, can realize a large etching selection ratio, and is favorable for reducing damage to the channel layer 230 in the process of removing the first sacrificial layer 220.
In this embodiment, in the process of removing the first sacrificial layer 220 exposed by the gate opening 620, the second sacrificial layer 240 exposed by the gate opening 620 is also removed.
The second sacrificial layer 240 is removed to expose the top of the topmost channel layer 230, so that a subsequently formed gate structure covers the channel layer 230 in a surrounding manner, and in this embodiment, the second sacrificial layer 240 and the first sacrificial layer 220 are made of the same material, which is beneficial to removing the second sacrificial layer 240 and the first sacrificial layer 220 together.
In this embodiment, after the isolation wall 410 exposed by the gate opening 620 is removed, the first sacrificial layer 220 exposed by the gate opening 620 is removed.
After the isolation wall 410 exposed by the gate opening 620 is removed, the first sacrificial layer 220 exposed by the gate opening 620 is removed, so that during the process of removing the isolation wall 410, the first sacrificial layer 220 and the second sacrificial layer 240, in particular the second sacrificial layer 240, can protect the channel layer 230, and the second sacrificial layer 240 is located on the topmost channel stack 210, and during the process of removing the isolation wall 410, can protect the topmost channel layer 230 well.
It should be noted that, the end of the channel layer 230 is in contact with the source-drain doping layer 500, and after the first sacrificial layer 220 and the second sacrificial layer 240 are removed, the channel layer 230 is suspended above the substrate 100 at intervals.
Referring to fig. 17 to 19 in combination, in which fig. 17 is a perspective view, fig. 18 is a cross-sectional view of fig. 17 based on an AA direction, and fig. 19 is a cross-sectional view of fig. 17 based on a BB direction, after removing the isolation wall 410 and the first sacrificial layer 220 exposed by the gate opening 620, a gate structure 600 surrounding and covering the channel layer 230 is formed in the gate opening 620 and the through trench 250.
The gate structure 600 is used to control the channel of the transistor to be turned on or off.
Since the isolation wall 410 in the gate opening 620 is removed, the gate structure 600 surrounds and covers the gate dielectric layer 640, the gate dielectric layer 640 surrounds and covers the channel layer 230, and the gate structure 600 surrounds and covers the channel layer 230, the top, the bottom and the sidewall of the channel layer 230 can be used as a channel, the area of the channel layer 230 used as a channel is increased, and the operating current of the semiconductor structure is increased.
In this embodiment, the gate structure 600 includes a gate dielectric layer 640 surrounding the channel layer 230 along the extending direction of the gate structure 600.
The gate dielectric layer 640 is used to isolate the gate structure 600 from the channel layer 230.
The material of the gate dielectric layer 640 comprises HfO 2 、ZrO 2 、HfSiO、HfSiON、HfTaO、HfTiO、HfZrO、Al 2 O 3 、SiO 2 And La 2 O 3 One or more of (a). In this embodiment, the gate dielectric layer 640 includes a high-k gate dielectric layer, and the material of the high-k gate dielectric layer includes a high-k dielectric material. Wherein, the high-k dielectric material is a dielectric material with a relative dielectric constant larger than that of silicon oxide. Specifically, the material of the high-k gate dielectric layer comprises HfO 2 、ZrO 2 HfSiO, hfSiON, hfTaO, hfTiO, hfZrO or Al 2 O 3 And the like.
It should be noted that the gate dielectric layer 640 may further include a gate oxide layer located between the channel layer 230 and the high-k gate dielectric layer. As an example, the material of the gate oxide layer may be SiO 2 。
In this embodiment, the gate structure 600 includes a metal gate structure.
In this embodiment, the metal gate structure includes a work function layer (not shown) and a gate electrode layer (not shown) on the work function layer.
The work function layer is used to adjust the threshold voltage of the formed transistor. The material of the work function layer comprises one or more of TiAl, mo, moN, alN, tiN, taN, taSiN, taAlN, tiAlN and TiAlC. When a PMOS transistor is formed, the work function layer is a P-type work function layer, and the material of the P-type work function layer comprises one or more of TiN, taN, taSiN, taAlN and TiAlN; when an NMOS transistor is formed, the work function layer is an N-type work function layer, and the material of the N-type work function layer comprises one or two of TiAl and TiAl C.
The gate electrode layer is used for leading out the electrical property of the metal gate structure. In this embodiment, the gate electrode layer is made of one or more of TiN, taN, ta, ti, tiAl, W, AL, tiSiN, and TiAlC.
In other embodiments, the gate structure may also be a polysilicon gate structure according to process requirements.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims (19)

1. A semiconductor structure, comprising:
the device comprises a substrate, a first electrode and a second electrode, wherein the substrate comprises a first device area and a second device area which are adjacent;
a channel layer structure suspended over the substrate along a normal to the substrate surface, the channel layer structure comprising one or more spaced channel layers;
the grid structure is positioned on the substrate and crosses the channel layer structure, and comprises a grid medium layer surrounding the channel layer along the extension direction of the grid structure and a grid electrode layer positioned on the grid medium layer;
the grid side wall is positioned on the side wall of the grid structure;
the source-drain doping layer is positioned on the substrate on two sides of the grid structure and is contacted with the end part of the channel layer structure below the grid structure;
and the isolation wall is protruded on the substrate between the adjacent source-drain doping layers at the junction of the first device area and the second device area, and is in contact with the gate structure.
2. The semiconductor structure of claim 1, wherein at a junction of the first device region and the second device region, a source-drain doping layer of the first device region and a source-drain doping layer of the second device region adjacent to each other are respectively in contact with the isolation wall.
3. The semiconductor structure of claim 1, further comprising: and the inner side wall is positioned between the adjacent channel layers along the normal direction of the surface of the substrate and is vertical to the extending direction of the grid structure, and the inner side wall is positioned between the side wall of the grid structure and the source drain doping layer.
4. The semiconductor structure of claim 1, wherein the substrate comprises a semiconductor substrate, a fin portion separated from the semiconductor substrate, and an isolation layer surrounding the fin portion, wherein the isolation layer exposes a top surface of the fin portion.
5. The semiconductor structure of claim 4, wherein the material of the semiconductor substrate comprises one or more of silicon, silicon germanium, gallium nitride, and silicon carbide.
6. The semiconductor structure of claim 4, in which a material of the isolation layer comprises one or more of silicon oxide, carbon-doped silicon oxide, silicon oxynitride, silicon nitride, boron-doped silicon oxide, and phosphorus-doped silicon oxide.
7. The semiconductor structure of claim 1, wherein the isolation wall extends through the gate sidewall along an extension direction of the channel layer structure.
8. The semiconductor structure of claim 1, wherein the first device region comprises an NMOS region and the second device region comprises a PMOS region.
9. The semiconductor structure of claim 1, wherein the material of the isolation wall comprises silicon oxide, silicon nitride, silicon oxynitride, or carbon-doped silicon oxide.
10. The semiconductor structure of claim 1, wherein a material of the gate electrode layer comprises one or more of TiN, taN, ta, ti, tiAl, W, AL, tiSiN, and TiAlC.
11. The semiconductor structure of claim 1, wherein the material of the gate dielectric layer comprises HfO 2 、ZrO 2 、HfSiO、HfSiON、HfTaO、HfTiO、HfZrO、Al 2 O 3 、SiO 2 And La 2 O 3 One or more of (a).
12. A method of forming a semiconductor structure, comprising:
providing a substrate, wherein the substrate comprises a first device region and a second device region which are adjacent, a channel structure is formed on the substrate, the channel structure comprises one or more stacked channel lamination layers, each channel lamination layer comprises a first sacrificial layer and a channel layer positioned on the first sacrificial layer, the extending direction of the channel structure is vertical to the arrangement direction of the first device region and the second device region, a separation wall covering the side wall of the channel structure is formed on the substrate between the adjacent channel structures at the junction of the first device region and the second device region, a pseudo gate structure crossing the channel structure and the separation wall is further formed on the substrate, the pseudo gate structure covers partial side wall and partial top of the channel structure and partial top of the separation wall, source and drain doping layers are further formed on the substrate at two sides of the pseudo gate structure, the source and drain doping layers are in contact with the end part of the channel structure below the pseudo gate structure, and the adjacent channel doping layers are separated by the separation wall at the junction of the first device region and the second device region;
forming an interlayer dielectric layer covering the source-drain doping layer on the substrate, wherein the interlayer dielectric layer also covers the side wall of the pseudo gate structure and exposes the top of the pseudo gate structure;
removing the pseudo gate structure, and forming a gate opening in the interlayer dielectric layer, wherein the gate opening exposes the isolation wall;
removing the isolation wall exposed from the gate opening;
removing the first sacrificial layer exposed from the gate opening to form a through groove communicated with the gate opening and expose the channel layer;
and after the isolation wall and the first sacrificial layer exposed by the gate opening are removed, forming a gate structure crossing the channel layer in the gate opening and the through groove, wherein the gate structure covers the channel layer in a surrounding manner.
13. The method of forming a semiconductor structure of claim 12, wherein in the step of providing a substrate, the channel structure further comprises a second sacrificial layer located on a topmost of the channel stacks;
and in the process of removing the first sacrificial layer exposed by the gate opening, the second sacrificial layer exposed by the gate opening is also removed.
14. The method for forming a semiconductor structure according to claim 12 or 13, wherein after removing the isolation wall exposed by the gate opening, the first sacrificial layer exposed by the gate opening is removed.
15. The method of forming a semiconductor structure of claim 12, wherein the first device region comprises an NMOS region and the second device region comprises a PMOS region.
16. The method for forming a semiconductor structure according to claim 12, wherein the isolation wall is etched and removed by a maskless etching method.
17. The method of claim 12, wherein in the step of providing the substrate, the material of the channel layer comprises silicon, germanium, silicon germanium or a group iii-v semiconductor material, the material of the first sacrificial layer comprises silicon, germanium or silicon germanium, and the channel layer and the first sacrificial layer have an etching selectivity between the materials.
18. The method for forming a semiconductor structure according to claim 13, wherein in the step of forming the channel structure, the first sacrificial layer and the second sacrificial layer are made of the same material.
19. The method of forming a semiconductor structure of claim 12, wherein in the step of forming the gate structure, the gate structure comprises a metal gate structure.
CN202110465076.1A 2021-04-28 2021-04-28 Semiconductor structure and forming method thereof Pending CN115249705A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116504616A (en) * 2023-06-29 2023-07-28 北京北方华创微电子装备有限公司 Method for manufacturing semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116504616A (en) * 2023-06-29 2023-07-28 北京北方华创微电子装备有限公司 Method for manufacturing semiconductor device
CN116504616B (en) * 2023-06-29 2023-11-14 北京北方华创微电子装备有限公司 Method for manufacturing semiconductor device

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