CN110690286B - Semiconductor structure and forming method thereof - Google Patents

Semiconductor structure and forming method thereof Download PDF

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Publication number
CN110690286B
CN110690286B CN201810742340.XA CN201810742340A CN110690286B CN 110690286 B CN110690286 B CN 110690286B CN 201810742340 A CN201810742340 A CN 201810742340A CN 110690286 B CN110690286 B CN 110690286B
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layer
channel
work function
forming
gate
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CN110690286A (en
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王楠
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/1037—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure and non-planar channel
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

The invention provides a semiconductor structure and a forming method thereof, wherein the forming method of the semiconductor structure comprises the following steps: providing a substrate, wherein the substrate comprises a substrate, a fin part protruding out of the substrate and one or more channel laminated layers positioned on the fin part, and the channel laminated layer adjacent to the fin part is a bottom channel laminated layer; forming a pseudo gate layer on the fin portion, wherein the pseudo gate layer crosses the channel lamination layer, and the pseudo gate layer covers part of the top wall and part of the side wall of the channel lamination layer; forming source and drain doping layers which are in contact with the fin parts in the channel laminated layers on the two sides of the pseudo gate layer; removing the pseudo gate layer to form a gate opening; removing the sacrificial layer in the bottom channel lamination to form a first channel communicated with the grid opening; forming a first work function layer in the first channel to cover at least a bottom surface of the first channel; and forming a second work function layer on the first work function layer and the exposed inner wall of the first channel of the first work function layer, wherein the second work function layer also covers the bottom surface and the side wall of the gate opening.

Description

Semiconductor structure and forming method thereof
Technical Field
The present invention relates to the field of semiconductor technologies, and in particular, to a semiconductor structure and a method for forming the same.
Background
In semiconductor manufacturing, integrated circuit feature sizes continue to decrease with the trend toward very large scale integrated circuits. To accommodate the reduction in feature size, the channel length of a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) is also being shortened accordingly. However, as the channel length of the device is shortened, the distance between the source and the drain of the device is also shortened, so that the controllability of the gate to the channel is deteriorated, and the difficulty of pinching off (ping off) the channel by the gate voltage is increased, so that a sub-threshold leakage (SCE), i.e., a so-called short-channel effect (SCE), is more likely to occur.
Therefore, in order to better accommodate the scaling requirements of device dimensions, semiconductor processes are gradually starting to transition from planar transistors to more power efficient three-dimensional transistors, such as Gate-all-around (GAA) transistors. In the fully-surrounded metal gate transistor, the gate surrounds the region where the channel is located from the periphery, and compared with a planar transistor, the fully-surrounded metal gate transistor has stronger control capability on the channel by the gate, and can better inhibit a short-channel effect.
The full-gate nanowire can be obtained by adding only two process modules in the existing replacement gate fin field effect transistor (FinTET) process flow, wherein the two process modules are as follows:
one is to grow a layer of Silicon on bulk Silicon (bulk Silicon) or SOI wafer, which avoids leakage of bulk Silicon material. Second, selectively remove the silicon germanium on the replaceable metal gate loop, and then use HKMG (high-k insulating layer + metal gate) to stack the surrounding silicon channel to form the all-around metal gate transistor.
Disclosure of Invention
The invention provides a semiconductor structure and a forming method thereof, which can reduce the electric leakage problem generated by a parasitic MOS.
In order to solve the above problems, the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate, wherein the substrate comprises a substrate, a discrete fin portion protruding out of the substrate and one or more channel lamination layers positioned on the fin portion, the channel lamination layers comprise a sacrificial layer and a channel layer positioned on the sacrificial layer, and the channel lamination layer adjacent to the fin portion is a bottom channel lamination layer; forming a pseudo gate layer on the fin portion, wherein the pseudo gate layer crosses the channel lamination layer, and the pseudo gate layer covers part of the top wall and part of the side wall of the channel lamination layer; forming source-drain doped layers which are in contact with the fin parts in the channel laminated layers on the two sides of the pseudo-gate layer; removing the pseudo gate layer to form a gate opening; removing the sacrificial layer in the bottom channel lamination layer to form a first channel communicated with the grid opening; forming a first work function layer in the first channel at least covering a bottom surface of the first channel; and forming a second work function layer on the first work function layer and the inner wall of the first channel exposed from the first work function layer, wherein the second work function layer also covers the bottom surface and the side wall of the grid opening.
Accordingly, the present invention also provides a semiconductor structure comprising: a substrate; a plurality of discrete fin portions on the substrate; the two source drain doping layers are separated on the fin part; the channel layer is arranged between the source-drain doping layers and is in contact with the source-drain doping layers, the channel layer is suspended above the fin portion, and the channel layer adjacent to the fin portion is a bottom channel layer; the bottom channel layer, the fin portion and the source drain doping layer form a first channel in a surrounding mode; a gate opening is formed on the bottom channel layer; a first work function layer at least covering the bottom surface of the first channel; the second work function layer covers the first work function layer and the inner wall of the first channel exposed by the first work function layer, and is also positioned on the bottom and the side wall of the grid opening; a metal gate structure in the first channel and gate opening and surrounding the bottom channel layer.
Compared with the prior art, the technical scheme of the invention has the following advantages:
according to the invention, a channel lamination is formed on a fin part, the channel lamination comprises a sacrificial layer and a channel layer positioned on the sacrificial layer, a pseudo gate layer is formed on the fin part, the pseudo gate layer crosses the channel lamination, the pseudo gate layer covers part of the top wall and part of the side wall of the channel lamination, then the pseudo gate layer is removed, a gate opening is formed, the sacrificial layer at the bottom is removed, a first channel is formed, and the gate opening is communicated with the first channel; forming a first work function layer covering the bottom surface of the first channel, forming a second work function layer at least covering the first work function layer in the bottom surface of the first channel and the exposed inner wall of the first channel of the first work function layer after forming the first work function layer, and covering the bottom surface and the side wall of the gate opening with the second work function layer; the bottom parasitic MOS can be controlled to be in a high threshold voltage depletion state through the first work function layer, the problem of electric leakage is solved, and in addition, the transistor can work at a proper voltage through the arrangement of the second work function layer, so that the performance of the device is improved.
Further, when the channel lamination layers are multiple, the channel lamination layers are mutually overlapped in the direction perpendicular to the fin portion, the bottom sacrificial layer in the bottom channel lamination layer is removed to form the first work function layer covering the bottom surface of the first channel, the top sacrificial layer in the top channel lamination layer is removed to form a second channel, the second channel is communicated with the grid opening, the second channel is formed by surrounding the top channel layer and the source-drain doping layer or the top channel layer, the bottom channel layer and the source-drain doping layer, the inner wall of the second channel and the bottom surface and the side wall of the grid opening are covered with the second work function layer, the second work function layer covers the first work function layer and the inner wall of the first channel exposed by the first work function layer, when the channel lamination layers are multiple, the bottom parasitic MOS is controlled to be in a high-threshold voltage depletion state through the first work function layer, the leakage problem is reduced, and in addition, the transistor can work at a proper voltage performance by the arrangement of the second work function layer, and the transistor device is improved.
Drawings
FIG. 1 is a schematic diagram of a semiconductor structure;
fig. 2 to 16 are schematic structural views corresponding to steps in a first embodiment of a method for forming a semiconductor structure according to the present invention;
fig. 17 to 21 are schematic structural diagrams corresponding to respective steps in a second embodiment of a method for forming a semiconductor structure according to the present invention.
Detailed Description
The reason for the leakage problem caused by the parasitic Metal Oxide Semiconductor (MOS) existing at the bottom of the semiconductor structure is analyzed in combination with a forming method of the semiconductor structure.
Referring to fig. 1, a schematic diagram of a semiconductor structure is shown. A bottom parasitic MOS5 is formed in a region surrounded by the channel layer 1, the fin portion 2, and the source-drain doping layer 3, and the bottom parasitic MOS5 easily forms a channel at a low voltage, thereby causing a leakage problem.
In addition, the bottom parasitic MOS5 is wrapped by a high-dielectric-constant gate dielectric layer 4 (high-k, HK), and the HK process adopts a gate dielectric material with a higher dielectric constant, so that the parasitic gate capacitance is easily increased, and the characteristics of the MOS transistor under high frequency can be influenced by the large parasitic capacitance.
In order to solve the technical problem, the invention provides a method for forming a semiconductor structure, which comprises the steps of providing a substrate, wherein the substrate comprises a substrate, a fin part protruding out of the substrate and one or more channel lamination layers positioned on the fin part, each channel lamination layer comprises a sacrificial layer and a channel layer positioned on the sacrificial layer, and the channel lamination layer adjacent to the fin part is a bottom channel lamination layer; forming a pseudo gate layer on the fin portion, wherein the pseudo gate layer crosses the channel lamination layer, and the pseudo gate layer covers part of the top wall and part of the side wall of the channel lamination layer; forming source-drain doped layers which are in contact with the fin parts in the channel laminated layers on the two sides of the pseudo-gate layer; removing the pseudo gate layer to form a gate opening; removing the sacrificial layer in the bottom channel lamination layer to form a first channel communicated with the grid opening; forming a first work function layer in the first channel at least covering a bottom surface of the first channel; and forming a second work function layer on the first work function layer and the inner wall of the first channel exposed from the first work function layer, wherein the second work function layer also covers the bottom surface and the side wall of the grid opening.
According to the invention, a channel lamination is formed on a fin part, the channel lamination comprises a sacrificial layer and a channel layer positioned on the sacrificial layer, a pseudo gate layer is formed on the fin part, the pseudo gate layer crosses the channel lamination, the pseudo gate layer covers part of the top wall and part of the side wall of the channel lamination, then the pseudo gate layer is removed, a gate opening is formed, the sacrificial layer at the bottom is removed, a first channel is formed, and the gate opening is communicated with the first channel; forming a first work function layer covering the bottom surface of the first channel, forming a second work function layer at least covering the first work function layer in the bottom surface of the first channel and the exposed inner wall of the first channel of the first work function layer after forming the first work function layer, and covering the bottom surface and the side wall of the gate opening with the second work function layer; the bottom parasitic MOS can be controlled to be in a high threshold voltage depletion state through the first work function layer, the problem of electric leakage is reduced, in addition, the transistor can work at proper voltage through the arrangement of the second work function layer, and the performance of the device is improved.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 2 to 16 are schematic structural diagrams corresponding to steps in the first embodiment of the method for forming a semiconductor structure according to the present invention.
Referring to fig. 2, a substrate is provided, and the substrate includes a substrate 100, a fin 101 protruding from the substrate 100, and a channel stack located on the fin 101, where the channel stack includes a sacrificial layer and a channel layer located on the sacrificial layer, and the channel stack adjacent to the fin 101 is a bottom channel stack 102.
The substrate 100 is used to provide a process platform for the subsequent formation of fully-enclosed metal gate transistors. Specifically, the all-around metal gate transistor may be a PMOS transistor or an NMOS transistor.
In this embodiment, the substrate 100 is a silicon substrate, in other embodiments, the substrate may also be other materials such as germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, and the substrate may also be another type of substrate such as a silicon-on-insulator substrate or a germanium-on-insulator substrate. The material of the substrate may be a material suitable for process requirements or easy integration.
In this embodiment, after the forming the channel stack, an isolation structure 108 is formed on the substrate 100 exposed by the channel stack, where the isolation structure 108 at least exposes a sidewall of the fin 101.
In this embodiment, a channel stack is formed on the fin 101, and the channel stack is adjacent to the fin 101, that is, the channel stack is a bottom channel stack 102, and the bottom channel stack 102 includes a bottom sacrificial layer 1021 and a bottom channel layer 1022 located on the bottom sacrificial layer 1021. In other embodiments, the number of the channel stacks may also be multiple according to actual process requirements, where the channel stack adjacent to the fin is a bottom channel stack, and the remaining channel stacks are top channel stacks.
The channel lamination is used for providing a process foundation for forming a suspended channel layer subsequently. Specifically, in this embodiment, the bottom channel stack 102 is used to provide a process foundation for the subsequent formation of the suspended bottom channel layer. The bottom sacrificial layer 1021 is used for supporting the bottom channel layer 1022, so as to provide a process foundation for realizing the spaced suspension setting of the bottom channel layer 1022 subsequently, and also be used for occupying a space position for a metal gate structure formed subsequently, and forming a channel completely surrounding a metal gate transistor and located in the bottom channel layer 1022 and the fin 101.
With continued reference to fig. 2, a dummy gate layer is formed across the channel stack, with the dummy gate layer 103 covering a portion of the top wall and a portion of the sidewalls of the channel stack.
In this embodiment, the dummy gate layer 103 is formed on the fin 101.
In this embodiment, the Dummy Gate layer 103 is used as a part of a Dummy Gate material structure (Dummy Gate), and the Dummy Gate material structure is a stacked structure, so before forming the Dummy Gate layer 103, the method further includes: and forming a pseudo gate oxide material layer which conformally covers the channel laminated layer, wherein the pseudo gate oxide material layer and the pseudo gate layer 103 form a pseudo gate material structure. In other embodiments, the dummy gate material structure may also be a single-layer structure, that is, the dummy gate material structure only includes the dummy gate layer.
Specifically, the step of forming the dummy gate material structure includes: after forming a pseudo gate oxide material layer conformally covering the bottom channel lamination layer 102, forming a pseudo gate material layer crossing the bottom channel lamination layer 102 on the pseudo gate oxide material layer; forming a gate mask layer 105 on the surface of the pseudo gate material layer; and etching the pseudo gate material layer by taking the gate mask layer 105 as a mask to form a pseudo gate layer 103, wherein the pseudo gate layer 103 covers part of the top and part of the side wall of the bottom channel lamination layer 102.
In this embodiment, the material of the dummy gate layer 103 is polysilicon. In other embodiments, the material of the dummy gate layer may also be silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, or amorphous carbon.
In this embodiment, the material of the dummy gate oxide layer is silicon oxide. In other embodiments, the material of the dummy gate oxide material layer may also be silicon oxynitride.
It should also be noted that as the device size decreases, the distance (Head to Head, HTH) between the ends of adjacent channel stacks decreases along the extension direction of the channel stacks. In the process of forming the dummy gate structure, a mask gate structure (not shown) is further formed on the isolation structure 108, so that in the subsequent process of sequentially etching the bottom channel stack 102 on both sides of the dummy gate layer 103 and part of the fin 101 below the bottom channel stack 102 to form a top through groove and a bottom groove respectively, over-etching of the isolation structure 108 by the etching process is reduced, and thus the problem that the appearances of the top through groove and the bottom groove are changed due to loss of the isolation structure 108 is avoided. Specifically, the top of the mask gate structure is flush with the top of the dummy gate structure, and the mask gate structure can be used as a Single Diffusion Break (SDB) structure.
It should be noted that after the dummy gate layer 103 is formed, the gate mask layer 105 on the top of the dummy gate layer 103 is remained. The gate mask layer 105 is made of silicon nitride, and the gate mask layer 105 is used for protecting the top of the dummy gate layer 103 in the subsequent process.
With continuing reference to fig. 2, after forming the dummy gate layer 103, further comprising: and forming a side wall 106 on the side wall of the pseudo gate layer 103. The sidewall spacers 106 may be used as an etching mask for a subsequent etching process to define a formation region of a subsequent source-drain doping layer.
Specifically, the step of forming the sidewall spacers 106 includes: forming a side wall film which conformally covers the side wall of the pseudo gate layer 103, the side wall and the top of the gate mask layer 105, the surface of the pseudo gate oxide material layer and the surface of the isolation structure 108; and removing the side wall films on the top of the gate mask layer 105, the surface of the pseudo gate oxide material layer and the surface of the isolation structure 108 by using a maskless etching process, and keeping the side wall film on the side wall of the pseudo gate layer 103 as the side wall 106.
In this embodiment, the sidewall spacers 106 are made of silicon nitride. In other embodiments, the material of the sidewall spacer may be one or more of silicon oxide, silicon carbide, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride, and boron carbonitride. In this embodiment, the sidewall 106 has a single-layer structure. In other embodiments, the sidewall spacer may have a stacked structure. In this embodiment, the thickness of the sidewall 106 is 2nm to 8nm according to actual process requirements. The thickness of the sidewall 106 refers to: the dimension of the side wall 106 in a direction perpendicular to the side wall of the side wall 106.
Referring to fig. 3, source-drain doping layers 107 in contact with the fin 101 are formed in the bottom channel stack 102 on both sides of the dummy gate layer 103.
In this embodiment, the source/drain doping layer 107 is formed by epitaxy, and the step of forming the source/drain doping layer 107 in contact with the fin 101 in the bottom channel stack on both sides of the dummy gate layer 103 includes: and sequentially etching the bottom channel lamination 102 and part of the fin part 101 on two sides of the pseudo gate layer 103, forming a top through groove (not shown in the figure) in the bottom channel lamination 102, and forming a bottom groove (not shown in the figure) communicated with the top through groove on the fin part 101.
In this embodiment, a top through groove is formed in the bottom channel stack 102, the top through groove and the bottom groove are used to provide a spatial position for the subsequent formation of a source/drain doping layer, and in other embodiments, a top through hole is formed in the bottom channel stack.
In this embodiment, before etching the bottom channel stack 102 and the fin 101 on both sides of the dummy gate layer 103, the method further includes: a pattern layer (not shown) is formed on the surface of the fin 101, the surface of the isolation structure 108, and a part of the surface of the bottom channel stack 102, and the pattern layer plays a role of protecting the fin 101 and the isolation structure 108, and may also cover an area where the bottom channel stack 102 is not desired to be etched. The material of the pattern layer is a photoresist material. And after the top through groove and the bottom groove are formed, removing the pattern layer by adopting a wet photoresist removing or ashing process.
It should be noted that the sidewall 106 is formed on the sidewall of the dummy gate layer 103, so that in the process of etching the bottom channel stack 102 and the fin 101 below the bottom channel stack 102, the sidewall 106 is used as an etching mask, so that the top through groove formed by etching is arranged at an interval from the dummy gate layer 103, and thus the source-drain doped layer 107 formed in the top through groove is arranged at an interval from the dummy gate layer 103.
It should be noted that, in this embodiment, after the side wall 106 is formed, the method further includes removing, by etching, the pseudo gate oxide layer exposed by the side wall 106, and reserving the pseudo gate oxide layer covered by the pseudo gate layer 103 and the side wall 106 as the pseudo gate oxide layer 104 to expose the channel stacks 102 on both sides of the pseudo gate layer 103, which is convenient for performing subsequent process steps.
In this embodiment, the bottom channel stack 102 on both sides of the dummy gate layer 103 and a portion of the fin 101 below the bottom channel stack 102 are etched by using an anisotropic etching process, so as to improve the topography quality of the top through groove and the bottom groove. Specifically, the anisotropic etching process may be a reactive ion etching process.
Referring to fig. 4, the dummy gate oxide layer 104 and the dummy gate layer 103 form a dummy gate structure, and the dummy gate structure is used for occupying a spatial position for the metal gate structure formed subsequently. Therefore, after the source-drain doping layer 107 is formed, the method further includes: forming an anti-etching layer 115 which conformally covers the isolation structure 108, the source drain doping layer 107 and the side wall; after the anti-etching layer 115 is formed, an interlayer dielectric material layer which is filled and covers the pseudo gate layer 103 is formed; and removing the interlayer dielectric material layer higher than the dummy gate layer 103 to form an interlayer dielectric layer 109.
Specifically, the step of forming the interlayer dielectric layer 109 includes: forming an interlayer dielectric material layer on the substrate 100, the anti-etching layer 115 and the dummy gate layer 103 exposed by the dummy gate layer 103, wherein the interlayer dielectric material layer covers the top of the dummy gate layer 103; and performing planarization treatment on the interlayer dielectric material layer, and removing the interlayer dielectric material layer higher than the top of the dummy gate layer 103, wherein the residual interlayer dielectric material layer after the planarization treatment is used as the interlayer dielectric layer 109.
The interlayer dielectric layer 109 is used for realizing electrical isolation between adjacent semiconductor structures, and the interlayer dielectric layer 109 is also used for defining the size and position of a metal gate structure formed subsequently. The interlayer dielectric layer 109 is made of an insulating material. In this embodiment, the interlayer dielectric layer 109 is made of silicon oxide. In other embodiments, the interlayer dielectric layer may also be made of other dielectric materials such as silicon nitride or silicon oxynitride.
In this embodiment, a gate mask layer 105 is formed on the dummy gate layer 103, so that the interlayer dielectric material layer also covers the top of the gate mask layer 105 (as shown in fig. 3), and thus the gate mask layer 105 is also removed in the process of forming the interlayer dielectric layer 109.
Referring to fig. 5 to 6, fig. 5 is a cross-sectional view of the dummy gate layer 103 removed, and fig. 6 is an omitted view of a cross-section along direction AA in fig. 5. It should be noted that fig. 6 does not show all the structures in fig. 5 in order to more clearly and concisely show the position relationship between the bottom channel stack 102 and the gate opening 110 after the dummy gate layer 103 is removed.
Removing the pseudo gate layer 103 to form a gate opening; removing the bottom sacrificial layer in the bottom channel stack to form a first channel in communication with the gate opening.
Referring to fig. 6, after removing the dummy gate layer 103, a gate opening 110 exposing a portion of the top surface of the fin 101 and a portion of the top surface and sidewalls of the bottom channel stack 102 is formed, where the bottom channel stack 102 protrudes from the fin 101, and the gate opening 110 exposes the sidewalls of the bottom sacrificial layer 1021.
In this embodiment, the gate opening 110 exposes a portion of the top surface of the fin and a portion of the top surface and sidewalls of the bottom channel layer.
In this embodiment, the process of removing the dummy gate layer 103 is a dry etching process, and in other embodiments, a wet etching process or a process combining a wet method and a dry method may also be adopted.
It should be noted that the step of removing the dummy gate layer 103 further includes removing the dummy gate oxide layer 104 covered by the dummy gate layer 103 to form a residual dummy gate oxide layer 122, and this step provides a process basis for the subsequent formation of the metal gate structure.
Referring to fig. 7 and 8, fig. 7 is a schematic cross-sectional structure diagram of the bottom channel stack 102 with the bottom sacrificial layer 1021 (as shown in fig. 5) removed, and fig. 8 is an omitted cross-sectional view in the BB direction of fig. 7, i.e., some structures are not drawn to better show the positional relationship between the bottom channel layer 1022 and the first channel 111 and the gate opening 110.
By removing the bottom sacrificial layer 1021 exposed from the gate opening 110 (as shown in fig. 5), a first channel 111 communicating with the gate opening 110 is formed below the bottom channel layer 1022, and the first channel 111 is surrounded by the bottom channel layer 1022, the source-drain doping layer 107, and the fin 101.
It should be noted that, because the bottom sacrificial layer 1021 (as shown in fig. 5) is removed after the formation of the source/drain doping layer 107, after the removal of the bottom sacrificial layer 1021, two ends of the bottom channel layer 1022 are connected to the source/drain doping layer 107, and the bottom channel layer 1022 is suspended in the gate opening 110. Thereby providing a foundation for a subsequently formed metal gate structure to surround the bottom channel layer 1022.
In this embodiment, the bottom channel stack 102 is located on the fin 101, so after removing the bottom sacrificial layer 1021 (as shown in fig. 5), the bottom channel layer 1022 is suspended on the fin 101, and the first channel 111 between the bottom channel layer 1022 and the fin 101 exposes a portion of the top surface of the fin 101.
In this embodiment, the material of the bottom sacrificial layer 1021 and the material of the bottom channel layer 1022 and the fin 101 have a larger etching selection ratio, and in the process of removing the gate opening 110 to expose the sidewall of the bottom sacrificial layer 1021, the etching rate of the wet etching process on the bottom sacrificial layer 1021 is greater than the etching rates on the bottom channel layer 1022 and the fin 101, and the bottom sacrificial layer 1021 exposed by the gate opening 110 is removed by the wet etching, so that the damage of the removal process on the bottom channel layer 1022 and the fin 101 by the bottom sacrificial layer 1021 can be reduced, and the yield of the formed all-around metal gate transistor is improved and the electrical performance is improved.
In this embodiment, the transistor is a PMOS transistor, the material of the fin portion 101 and the bottom channel layer 1022 is Si, and the material of the bottom sacrificial layer 1021 is SiGe, so the etching solution adopted in the wet etching process is a tetramethylammonium hydroxide solution, and the difference between the etching rate of the tetramethylammonium hydroxide solution to the Si material and the etching rate to the SiGe material is large, so that the remaining bottom sacrificial layer 1021 is removed by using the tetramethylammonium hydroxide solution, and the probability of damage to the bottom channel layer 1022 and the fin portion 101 can be effectively reduced. The volume percentage concentration of the tetramethylammonium hydroxide solution is 10% to 80%, so that effective etching of the remaining bottom sacrificial layer 1021 can be achieved, and the probability of loss of the bottom channel layer 1022 and the fin 101 is significantly reduced.
In other embodiments, the all-around metal gate transistor is an NMOS transistor, the material of the bottom channel layer 1022 and the fin 101 is Si, and the material of the bottom sacrificial layer 1021 is SiGe.
Referring to fig. 9 to 14, a first work function layer 112 is formed in the first channel 111 to cover at least a bottom surface of the first channel.
Referring to fig. 9 to 10, fig. 9 is a cross-sectional view of the first work-function material layer 113 covering the bottom and the sidewall of the gate opening 110 and the inner wall of the first channel 111, and fig. 10 is a cross-sectional view of fig. 9 along a CC direction cut line with an omitted illustration, i.e., some structures are not drawn for better illustrating the positional relationship between the bottom channel layer 1022, the first work-function material layer 113, and the first channel 111 and the gate opening 110.
The step of forming a first work function layer 112 in the first channel 111 to cover at least the bottom surface of the first channel 111 includes: a first work function material layer 113 is formed on an inner wall of the first channel 111 and a bottom surface and a sidewall of the gate opening 110.
In this embodiment, the forming process of the first work function material layer 113 is Atomic Layer Deposition (ALD), and in other embodiments, the forming process of the first work function material layer may also be Physical Vapor Deposition (PVD).
Specifically, before forming the first work function material layer 113 on the inner wall of the first channel 111 and the bottom surface and the side wall of the gate opening 110, forming a gate dielectric material layer 114 on the inner wall of the first channel 111 and the bottom surface and the side wall of the gate opening 110 is further included.
The gate dielectric material layer 114 is used to achieve electrical isolation between the subsequently formed metal gate structure 118 and the channel. Since the channel of the all-around metal gate transistor is located in the bottom channel layer 1022 and the fin 101, the gate dielectric material layer 114 covers the surfaces of the bottom channel layer 1022 exposed by the gate opening 110 and also covers a portion of the top of the fin 101.
It should be noted that the gate dielectric material layer 114 also covers the top surface of the interlayer dielectric layer 109.
The material of the gate dielectric material layer 114 is a high-k dielectric material. Wherein, the high-k dielectric material is a dielectric material with a relative dielectric constant larger than that of silicon oxide. In this embodiment, the gate dielectric material layer 114 is made of HfO 2 . In other embodiments, the material of the gate dielectric material layer 114 may also be selected from ZrO 2 HfSiO, hfSiON, hfTaO, hfTiO, hfZrO or Al 2 O 3 One or more of them.
Referring to fig. 11, after forming the first work function material layer 113, an organic layer (not shown) is formed to fill the first channel 111 and the gate opening 110;
specifically, the step of forming an organic layer filling and covering the first channel 111 and the gate opening 110 includes forming an organic material layer filling and covering the channel 111 and the gate opening 110, and performing planarization processing on the organic material layer to obtain the organic layer.
Specifically, the material of the organic layer is a high molecular organic polymer.
Referring to fig. 12, the organic layer in the gate opening 110 and a part of the organic layer in the first channel 111 are etched to form a remaining organic layer 119 covering at least the bottom of the first channel 111.
In this embodiment, the process of removing the organic layer in the gate opening 110 and the organic layer with a partial thickness in the first channel 111 by etching is wet etching.
Referring to fig. 13 to 14, the first work function material layer 113 not covered by the remaining organic layer 119 is removed; the remaining organic layer 119 is removed to form the first work function layer 112 covering the bottom surface of the first channel 111.
Specifically, the process of removing the first work function material layer 113 not covered by the remaining organic layer is a wet etching process; the remaining organic layer 119 is removed, and the process of forming the first work function layer 112 covering the bottom surface of the first channel 111 is a wet etching process. In other embodiments, a combination of wet and dry processes may be used to remove the remaining organic layer.
Referring to fig. 15 to 16, a second work function layer 116 is formed on the first work function layer 112 and the exposed inner wall of the first channel 111 of the first work function layer 112, and the second work function layer 116 further covers the bottom surface and the sidewall of the gate opening 110.
Specifically, the step of forming the second work function layer 116 on the first work function layer 112 and the inner wall of the first channel 111 exposed by the first work function layer 112, and the step of forming the second work function layer 116 to cover the bottom surface and the sidewall of the gate opening 110 further includes:
a second work function material layer 117 is formed on the first work function layer 112 and the inner wall of the first channel 111 exposed by the first work function layer 112, and the second work function material layer 117 also covers the bottom surface and the sidewall of the gate opening 110 and the top surface of the interlayer dielectric layer 109. After forming the second work function material layer 117, forming a metal gate material in the gate opening 110 and the first channel 111 to fill and cover the gate opening 110 and the first channel 111; and removing the metal gate material and the second work function material layer 117 on the interlayer dielectric layer 109 to obtain a second work function layer 116 and a metal gate structure 118 completely surrounding the bottom channel layer 1022.
It should be noted that, when the metal gate material and the second work function material layer 117 on the interlayer dielectric layer 109 are removed, the gate dielectric material layer 114 formed on the interlayer dielectric layer 109 is also removed, so as to obtain the gate dielectric layer 120.
In this embodiment, the forming process of the second work function material layer 117 is Atomic Layer Deposition (ALD), and in other embodiments, the forming process of the second work function material layer may also be Physical Vapor Deposition (PVD).
In this embodiment, the metal gate structure 118 serves as an electrode for making electrical connection to an external circuit. In this embodiment, the material of the metal gate structure 118 is magnesium-tungsten alloy, and in other embodiments, the material of the metal gate structure may also be Al, cu, ag, au, pt, ni, ti, or the like.
In this embodiment, the thickness of the first work function layer 112 is 5 to 10 nm, and the thickness of the second work function layer 116 is 5 to 10 nm.
In this embodiment, the all-around metal gate transistor is a PMOS transistor, the all-around metal gate transistor adopts a Si channel technology, and accordingly, the fin portion 101 and the bottom channel layer 1022 are both made of silicon. The first work function layer 112 uses a metal material with a lower work function than the second work function layer 116 to control the bottom parasitic MOS in a high threshold voltage depletion state, thereby reducing leakage and parasitic capacitance, and the second work function layer sets the GAA channel to operate at a suitable threshold voltage.
The metal work functions of the first work function layer 112 and the second work function layer 116 are in a range of 4.8 to 5.1 ev, the work function of the first work function layer 112 is lower than that of the second work function layer 116, and the first work function layer 112 and the second work function layer 116 may be made of titanium nitride, tantalum nitride, titanium carbide, tantalum silicon nitride, titanium silicon nitride, or tantalum carbide.
The mole volume percentage of nitrogen ions in the first work function layer 112 and the mole volume percentage of nitrogen ions in the second work function layer 116 are both 3% to 30%, and wherein more tantalum or titanium ion-containing compound is added to the first work function layer 112 than to the second work function layer 116, the mole volume percentage of tantalum or titanium ions in the compound being 60% to 95%.
In other embodiments, the all-around metal gate transistor is an NMOS transistor, the all-around metal gate transistor adopts a Si channel technology, and accordingly, the fin portion and the bottom channel layer are both made of Si. The first work function layer controls the bottom parasitic MOS to be in a high threshold voltage depletion state by using a metal material with a work function higher than that of the second work function layer, so that electric leakage and parasitic capacitance are reduced, and the second work function layer sets the GAA channel to work under a proper threshold voltage.
The metal work functions of the first work function layer and the second work function layer are in the range of 4.1 to 4.4 electron volts, and the work function of the first work function layer is higher than that of the second work function layer. The first work function layer and the second work function layer can be made of titanium aluminide, tantalum carbide, aluminum or titanium carbide.
The mol volume percentage of aluminum ions in the first work function layer and the second work function layer is 3-30%, and the second work function layer is doped with more compounds containing nitrogen, fluorine, carbon, arsenic or lanthanum ions than the first work function layer, and the mol volume percentage of the nitrogen, fluorine, carbon, arsenic or lanthanum ions in the compounds is 3-30%.
Fig. 17 to 21 are schematic structural diagrams corresponding to steps in the second embodiment of the method for forming a semiconductor structure according to the present invention.
The same parts of this embodiment as the previous embodiment are not repeated, and the differences from the previous embodiment are: the channel lamination is a plurality of. Specifically, the channel stack located at the bottommost portion is a bottom channel stack, and the channel stack located above the bottom channel stack is a top channel stack. The bottom channel stack includes a bottom sacrificial layer and a bottom channel layer 2021 on the bottom sacrificial layer, the top channel stack includes a top channel layer 2022 and a top sacrificial layer under the top channel layer 2022;
referring to fig. 17 to 18, fig. 17 is a schematic cross-sectional structure view after removing the bottom sacrificial layer and the top bottom sacrificial layer, and fig. 18 is a cross-sectional omitted view of fig. 17 along direction DD. It should be noted that all the structures in fig. 17 are not shown in fig. 18 in order to more clearly and concisely show the positional relationship between the bottom channel layer 2021 and the top channel layer 2022 and the first channel 211, the second channel 221 and the gate opening 210.
The gate opening 210 exposes a portion of the top surface and sidewalls of the top channel layer, a portion of the top surface of the fin, and a portion of the sidewalls of the bottom channel layer.
Removing the bottom sacrificial layer in the bottom channel stack, forming a first channel 211 in communication with the gate opening 210 comprises: removing the bottom sacrificial layer in the bottom channel lamination layer to form a first channel 211 surrounded by the bottom channel layer 2021, the source-drain doping layer 207 and the fin 201, wherein the first channel 211 is communicated with the gate opening 210; and removing the top sacrificial layer in the top channel lamination layer to form a second channel 221, where the second channel 221 is defined by the top channel layer 2022 and the source/drain doping layer 207, or a second channel 221 surrounded by the top channel layer 2022, the bottom channel layer 2021, and the source/drain doping layer 207, and the second channel 221 is also communicated with the gate opening 210. The bottom channel layer 2021 and the top channel layer 2022 are suspended, thereby providing a foundation for a subsequently formed all-around metal gate structure to surround the bottom channel layer 2021 and the top channel layer 2022.
It should be noted that, because the bottom sacrificial layer and the top sacrificial layer are removed after the source/drain doping layer 207 (as shown in fig. 17) is formed, after the bottom sacrificial layer and the top sacrificial layer are removed, two ends of the bottom channel layer 2021 and the top channel layer 2022 are connected to the source/drain doping layer 207, so that the bottom channel layer 2021 and the top channel layer 2022 are suspended in the gate opening 210, and the bottom of the first channel 211 between the bottom channel layer 2021 and the fin 201 exposes a portion of the top surface of the fin 201.
After the source-drain doping layer 207 is formed, the method further includes: forming an anti-etching layer 215 which conformally covers the isolation structure 208, the source-drain doping layer 207 and the side wall 206; after the anti-etching layer 215 is formed, an interlayer dielectric material layer which is filled and covers the pseudo gate layer is formed; and removing the interlayer dielectric material layer higher than the dummy gate layer to form an interlayer dielectric layer 209.
It should be noted that in the step of removing the dummy gate layer by etching, the dummy gate oxide layer below the dummy gate layer is removed, and a residual dummy gate oxide layer 222 is formed between the top channel layer 2022 and the sidewall 206.
Referring to fig. 19 to 20, a first work function layer 212 is formed in the first channel 211 to cover at least a bottom surface of the first channel.
Referring to fig. 19, the step of forming a first work function layer 212 in the first channel 211 to cover at least the bottom surface of the first channel includes: forming a first work function material layer 213 on the inner walls of the first channel 211 and the second channel 221 and the bottom surface and the side wall of the gate opening 210, wherein the first work function layer also covers the top surface of the interlayer dielectric layer 209; after forming the first work function material layer 213, forming an organic layer filling and covering the first channel 211, the second channel 221 and the gate opening 210; etching to remove a part of the organic layer (not shown in the figure) with a thickness in the gate opening 210, the second channel 221, and the first channel 211, so as to obtain a remaining organic layer (not shown in the figure) at least covering the bottom of the first channel 211; removing the first work function material layer 213 not covered by the remaining organic layer results in a first work function layer 212 covering at least the bottom surface of the first channel.
In the present embodiment, the formation process of the first work function material layer 213 is Atomic Layer Deposition (ALD), and in other embodiments, the formation process of the first work function material layer may also be Physical Vapor Deposition (PVD).
Before forming the first work function material layer 213 on the inner wall of the first channel 211 and the bottom and the side wall of the gate opening 210, a gate dielectric material layer 214 is formed on the inner walls of the first channel 211 and the second channel 221 and the bottom and the side wall of the gate opening 210.
In this embodiment, the wet etching is a process of etching to remove a part of the organic layer with a thickness in the gate opening 210, the second channel 221, and the first channel 211, and obtaining a remaining organic layer at least covering the bottom of the first channel 211. In other embodiments, a combination of wet and dry processes may be used to remove the organic layer.
In this embodiment, the process of removing the first work function material layer 213 not covered by the remaining organic layer is a wet etching process.
Referring to fig. 20, the remaining organic layer is removed to form the first work function layer 212 covering the bottom surface of the first channel 211.
In this embodiment, the step of removing the remaining organic layer to form the first work function layer 212 covering the bottom surface of the first channel 211 includes: and removing the residual organic layer by using a wet etching process to form the first work function layer 212 covering the bottom surface of the first channel 211. In other embodiments, a combination of wet and dry processes may be used to remove the remaining organic layer.
Referring to fig. 21, in the present embodiment, a second work function layer 216 is formed on the first work function layer 212 and the exposed inner wall of the first channel 211 of the first work function layer 212, the second work function layer 216 further covers the bottom surface and the sidewall of the gate opening 210, and the second work function layer 216 further covers the inner wall of the second channel.
Specifically, the step of forming the second work function layer 216 on the first work function layer 212 and the inner wall of the first channel 211 exposed by the first work function layer 212, wherein the second work function layer 216 further covers the bottom surface and the sidewall of the gate opening 210, and the step of covering the inner wall of the second channel with the second work function layer 216 further includes:
a second work function material layer is formed on the first work function layer 212 and the exposed inner wall of the first channel 211 of the first work function layer 212, and the second work function material layer also covers the bottom surface and the sidewall of the gate opening 210, and also covers the inner wall of the second channel 221 and the top surface of the interlayer dielectric layer 209. After the second work function material layer is formed, a metal gate material fully surrounding the bottom channel layer 2021 and the top channel layer 2022 is formed in the gate opening 210, the first channel 211 and the second channel 221, and the metal gate material and the second work function material layer on the interlayer dielectric layer 209 are removed, so that a second work function layer 216 and a metal gate structure are obtained.
It should be noted that, when the metal gate material and the second work function material on the interlayer dielectric layer 209 are removed, the gate dielectric material layer 214 formed on the interlayer dielectric layer 209 is also removed, so as to obtain the gate dielectric layer 220.
In this embodiment, the materials of the top channel layer 2022 and the bottom channel layer 2021 are the same, and are specifically described in the first embodiment, which is not repeated herein.
In this embodiment, the work function relationship between the first work function layer 212 and the second work function layer 216, and the material between the first work function layer 212 and the second work function layer 216 are specifically selected as described in the first embodiment, and are not described herein again.
In this embodiment, the process and materials for removing the top sacrificial layer and the bottom sacrificial layer used in the step of removing the bottom sacrificial layer in the bottom channel stack and forming the first channel 211 communicated with the gate opening 210 are as described in the first embodiment, and are not described herein again. The materials of the top sacrificial layer and the bottom sacrificial layer are the same, which is specifically described in the first embodiment and will not be described herein again.
Correspondingly, the invention further provides a semiconductor structure, and referring to fig. 16, a schematic cross-sectional structure diagram of a first embodiment of the semiconductor structure of the invention is shown.
The semiconductor structure includes: a substrate 100; a plurality of discrete fins 101 on the substrate 100; two source-drain doping layers 107 which are separated on the fin portion 101; one or more spaced channel layers located between the source-drain doping layers 107 and contacting the source-drain doping layers 107, wherein the channel layers are suspended above the fin 101, and the channel layer adjacent to the fin 101 is a bottom channel layer 1022; the bottom channel layer 1022, the fin 101 and the source-drain doping layer 107 enclose a first channel 111; a gate opening 110 is formed on the bottom channel layer 1022; a first work function layer 112 covering at least a bottom surface of the first channel 111; a second work function layer 116 covering the first work function layer 112 and the inner wall of the first channel 111 exposed by the first work function layer 112, and further located on the bottom and the sidewall of the gate opening 110; a metal gate structure 118 located in the first channel 111 and the gate opening 110 and surrounding the underlying channel layer 1022.
The substrate 100 is used for providing a process platform for subsequently forming a fully-enclosed metal gate transistor. The all-around metal gate transistor can be either a PMOS transistor or an NMOS transistor.
In this embodiment, the substrate 100 is a silicon substrate, in other embodiments, the substrate may also be other materials such as germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, and the substrate may also be another type of substrate such as a silicon-on-insulator substrate or a germanium-on-insulator substrate. The material of the substrate may be a material suitable for process requirements or easy integration.
In this embodiment, the number of the channel layers is one, that is, the channel layer is a bottom channel layer 1022, the bottom channel layer 1022 is located on the fin portion 101 and is arranged at an interval with the fin portion 101, the bottom channel layer 1022, the fin portion 101 and the source drain doping layer 107 surround to form a first channel 111, a part of a metal gate structure 118 which covers the bottom channel layer 1022 in a fully surrounding manner is formed in the first channel 111, and the metal gate structure 118 is used for controlling conduction and disconnection of the fully surrounding metal gate transistor channel. In other embodiments, the plurality of channel layers, the channel layer adjacent to the fin is a bottom channel layer, and the remaining channel layers are top channel layers.
The channel of the all-around metal gate transistor is located within the fin 101 and the bottom channel layer 1022. When the fully-surrounded metal gate transistor is a PMOS, a Si channel technology is adopted, and accordingly, the fin portion 101 and the bottom channel layer 1022 are both made of silicon. When the fully-surrounded metal gate transistor is an NMOS, a Si channel technology is adopted, and accordingly, the fin 101 and the bottom channel layer 1022 are made of silicon.
The gate opening exposes a portion of the top surface of the fin 101 and a portion of the top surface and sidewalls of the bottom channel layer 1022.
It should be noted that a gate dielectric layer 120 is formed on the inner wall of the first channel 111 and the bottom surface and the side wall of the gate opening, and the first work function layer 112 is formed on the gate dielectric layer 120 on the bottom surface of the first channel 111. In the first channel 111, the second work function layer 116 is formed on the first work function layer 112 and on the gate dielectric layer 120 exposed from the first work function layer 112; in the gate opening, the gate dielectric layer 120 covers the bottom surface and the sidewall of the gate opening, and the second work function layer 116 covers the gate dielectric layer 120.
The gate dielectric layer 120 is used to electrically isolate the metal gate structure 118 from the channel. Since the channel of the all-around metal gate transistor is located in the bottom channel layer 1022 and the fin 101, the gate dielectric layer 120 covers the upper surface, the lower surface, and the side surfaces of the bottom channel layer 1022, and also covers part of the top and part of the sidewall of the fin 101.
The gate dielectric layer 120 is made of a high-k dielectricA material. Wherein, the high-k dielectric material is a dielectric material with a relative dielectric constant larger than that of silicon oxide. In this embodiment, the gate dielectric layer 120 is made of HfO 2 . In other embodiments, the material of the gate dielectric layer may also be ZrO 2 HfSiO, hfSiON, hfTaO, hfTiO, hfZrO or Al 2 O 3 One or more of them.
The metal gate structure 118 serves as an electrode for making electrical connection to an external circuit. In this embodiment, the material of the metal gate structure 118 is magnesium-tungsten alloy, and in other embodiments, the material of the metal gate structure may also be Al, cu, ag, au, pt, ni, ti, or the like.
In addition, the semiconductor structure further includes: and a sidewall 106 covering the sidewall of the metal gate structure 118, a portion of the top surface of the fin 101, and the top and the sidewall of the bottom channel layer 1022 exposed by the metal gate structure 118.
The sidewall spacers 106 are used to define the region of the source-drain doped layer 107.
Specifically, in the process of forming the top through groove for accommodating the source/drain doping layer 107, the sidewall 106 is used as a part of an etching mask, so that the source/drain doping layer 107 formed in the top through groove and the metal gate structure 118 are arranged at an interval.
In this embodiment, the sidewall spacers 106 are made of silicon nitride. In other embodiments, the material of the sidewall spacer may be one or more of silicon oxide, silicon carbide, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride, and boron carbonitride. In this embodiment, the sidewall 106 has a single-layer structure. In other embodiments, the sidewall spacer may have a stacked structure. In this embodiment, the thickness of the sidewall 106 is 2nm to 8nm according to actual process requirements. The thickness of the sidewall 106 refers to: the dimension of the side wall 106 in a direction perpendicular to the side wall of the side wall 106.
In this embodiment, the semiconductor further includes: conformally covering the isolation structure 108, the source-drain doping layer 107 and the anti-etching layer 115 of the sidewall spacer 106, and forming, filling and covering an interlayer dielectric layer 109 on the metal gate structure 118 and the anti-etching layer 115 exposed by the sidewall spacer 106.
The material of the etch-resistant layer 115 is silicon nitride.
The interlayer dielectric layer 109 is used for realizing electrical isolation between adjacent semiconductor structures, and the interlayer dielectric layer 109 is also used for defining the size and the position of a metal gate structure 118 formed subsequently. The interlayer dielectric layer 109 is made of an insulating material. In this embodiment, the interlayer dielectric layer 109 is made of silicon oxide. In other embodiments, the interlayer dielectric layer may also be made of other dielectric materials such as silicon nitride or silicon oxynitride.
In this embodiment, in the process of forming the semiconductor structure, the metal gate structure 118 is formed by a process of forming a metal gate (high-K metal gate) after forming a high-K gate dielectric layer, so that before the metal gate structure 118 is formed, the position of the metal gate structure 118 is occupied by a dummy gate structure crossing the top and the sidewall of the bottom channel layer 1022 structure and a bottom sacrificial layer between the bottom channel layer 1022 and the fin 101.
In this embodiment, the adopted dummy gate structure is a stacked structure, and includes a dummy gate oxide layer covering the bottom channel layer and a dummy gate layer on the dummy gate oxide layer. In the process of removing a part of the dummy gate structure to form the metal gate structure 118, the remaining dummy gate oxide layer 122 between the sidewall 206 and the bottom channel layer 1022 is retained under the protection of the sidewall 206, so that the semiconductor structure further includes: a remaining dummy gate oxide layer 122 between the sidewall spacers 106 and the bottom channel layer 1022.
In other embodiments, when the adopted dummy gate structure is a single-layer structure, that is, when the dummy gate structure only includes a dummy gate layer, the semiconductor structure may further not include the remaining dummy gate oxide layer.
In this embodiment, the material of the remaining dummy gate oxide layer 122 is silicon oxide. In other embodiments, the material of the remaining dummy gate oxide layer 122 may also be silicon oxynitride.
The source drain doped layer 107 is used as a source region and a drain region of the formed all-around metal gate transistor.
In this embodiment, the top of the source-drain doping layer 107 is higher than the top of the bottom channel layer 1022, and the source-drain doping layer 107 also covers a part of the sidewall 106. In other embodiments, the top of the source-drain doping layer 107 may be flush with the top of the bottom channel layer according to actual process requirements.
In this embodiment, the all-around metal gate transistor is a PMOS transistor, the first work function layer 112 uses a metal material with a lower work function than the second work function layer 116 to control the bottom parasitic MOS to be in a high threshold voltage depletion state, so as to reduce leakage and parasitic capacitance, and the second work function layer 116 sets the GAA channel to operate at a suitable threshold voltage.
The metal work functions of the first work function layer 112 and the second work function layer 116 are in a range of 4.8 to 5.1 ev, the work function of the first work function layer 112 is lower than that of the second work function layer 116, and the first work function layer 112 and the second work function layer 116 may be made of titanium nitride, tantalum nitride, titanium carbide, tantalum silicon nitride, titanium silicon nitride, or tantalum carbide.
The mole volume percentage of nitrogen ions in the first work function layer 112 and the mole volume percentage of nitrogen ions in the second work function layer 116 are both 3% to 30%, and wherein more tantalum or titanium ion-containing compound is added to the first work function layer 112 than to the second work function layer 116, the mole volume percentage of tantalum or titanium ions in the compound being 60% to 95%.
In other embodiments, the all-around metal gate transistor is an NMOS transistor, the all-around metal gate transistor adopts a Si channel technology, and accordingly, the fin portion and the bottom channel layer are both made of silicon. The first work function layer controls the bottom parasitic MOS to be in a high threshold voltage depletion state by using a metal material with a work function higher than that of the second work function layer, so that electric leakage and parasitic capacitance are reduced, and the second work function layer sets the GAA channel to work under a proper threshold voltage.
The metal work functions of the first work function layer and the second work function layer are 4.1 to 4.4 electron volts, and the work function of the first work function layer is higher than that of the second work function layer. The first work function layer and the second work function layer can be made of titanium aluminide, tantalum carbide, aluminum or titanium carbide.
The mol volume percentage of aluminum ions in the first work function layer and the second work function layer is 3-30%, and the second work function layer is doped with more compounds containing nitrogen, fluorine, carbon, arsenic or lanthanum ions than the first work function layer, and the mol volume percentage of the nitrogen, fluorine, carbon, arsenic or lanthanum ions in the compounds is 3-30%.
Referring to fig. 21, a schematic diagram of a second embodiment of the semiconductor structure of the present invention is shown.
Referring to fig. 21, the same parts of this embodiment as those of the first embodiment are not repeated, and the differences from the first embodiment are: the number of the channel layers is multiple.
The semiconductor structure includes a bottom channel layer 2021 adjacent to the fin 201 and a top channel layer 2022 suspended on the bottom channel layer 2021; the top channel layer 2022 and the source drain doping layer 207, or the top channel layer 2022, the bottom channel layer 2021 and the source drain doping layer 207 enclose a second channel 221; the second work function layer 216 also covers the inner wall of the second channel 221; the metal gate structure 218 is also located in the second channel 221.
The channel of the all-around metal gate transistor is located within the fin 201, the bottom channel layer 2021, and the top channel layer 2022. When the fully-surrounded metal gate transistor is a PMOS, a Si channel technology is adopted, and accordingly, the fin 201, the bottom channel layer 2021, and the top channel layer 2022 are made of silicon. When the fully-surrounded metal gate transistor is an NMOS, a Si channel technology is adopted, and accordingly, the fin 201, the bottom channel layer 2021, and the top channel layer 2022 are made of silicon.
It should be noted that a gate dielectric layer 220 is formed on the inner walls of the first channel 211 and the second channel 221 and the bottom surface and the side wall of the gate opening, and the first work function layer 212 is formed on the gate dielectric layer 220 on the bottom surface of the first channel 211. In the first channel 211, the second work function layer 216 is formed on the first work function layer 212 and on the exposed gate dielectric layer 220 of the first work function layer 212; in the second channel 221, the gate dielectric layer 220 is formed on an inner wall of the second channel 221, and the second work function layer 216 is formed on the gate dielectric layer 220; in the gate opening, the gate dielectric layer 220 covers the gate opening, and the second work function layer covers the gate dielectric layer 220.
The gate dielectric layer 220 is used to electrically isolate the metal gate structure 218 from the channel. Since the channel of the all-around metal gate transistor is located in the bottom channel layer 2021, the top channel layer 2022 and the fin 201, the gate dielectric layer 220 covers the upper surface, the lower surface and the side surfaces of the bottom channel layer 2021 and the top channel layer 2022, and also covers a part of the top and a part of the sidewall of the fin 201.
In this embodiment, the all-around metal gate transistor is a PMOS transistor, the all-around metal gate transistor adopts a Si channel technology, and accordingly, the fin portion 201, the top channel layer 2022, and the bottom channel layer 2021 are made of silicon. When the fully-surrounded metal gate transistor is an NMOS, a Si channel technology is adopted, and accordingly, the top channel layer 2022, the bottom channel layer 2021, and the fin 201 are made of silicon.
It should be noted that the semiconductor structure further includes: a sidewall 206 covering the sidewall of the metal gate structure 218, a portion of the top surface of the fin 201, a portion of the top channel layer 2022 exposed by the metal gate structure 218, and a portion of the sidewalls of the top channel layer 2022 and the bottom channel layer 2021.
The sidewall spacers 206 are used to define the region of the source-drain doping layer 207.
Specifically, in the process of forming the top through-trench for accommodating the source/drain doping layer 207, the sidewall 206 is used as a part of an etching mask, so that the source/drain doping layer 207 formed in the top through-trench and the metal gate structure 218 are arranged at an interval.
In this embodiment, the semiconductor further includes: and conformally covering the isolation structure 208, the source/drain doping layer 207 and the etch-resistant layer 215 of the sidewall spacer 206, and forming, filling and covering an interlayer dielectric layer 209 on the metal gate structure 218 and the etch-resistant layer 215 exposed by the sidewall spacer 206.
In this embodiment, in the process of forming the semiconductor structure, the metal gate structure 218 is formed by a process of forming a metal gate (high K gate metal gate last) after forming a high K gate dielectric layer, so that before forming the metal gate structure 218, the position of the metal gate structure 218 is occupied by a dummy gate structure crossing the top of the top channel layer 2022 and sidewalls of the bottom channel layer 2021 and the top channel layer 2022, a bottom sacrificial layer between the bottom channel layer 2021 and the fin 201, and a top sacrificial layer between the top channel layer 2022 and the bottom channel layer 2021, or a sacrificial layer between the top channel layer 2022 and the top channel layer 2022.
In this embodiment, the adopted dummy gate structure is a stacked structure, and includes a dummy gate oxide layer covering the top channel layer 2022 and a dummy gate layer on the dummy gate oxide layer. In the process of removing a part of the dummy gate structure to form the metal gate structure 218, the remaining dummy gate oxide layer 222 between the sidewall 206 and the top channel layer 2022 is retained under the protection of the sidewall 206, so that the semiconductor structure further includes: a residual dummy gate oxide layer 222 between the sidewall spacers 206 and the bottom channel layer 2021.
In other embodiments, when the adopted dummy gate structure is a single-layer structure, that is, when the dummy gate structure only includes a dummy gate layer, the semiconductor structure may further not include the remaining dummy gate oxide layer.
In this embodiment, the remaining dummy gate oxide layer 222 is made of silicon oxide. In other embodiments, the material of the remaining dummy gate oxide layer 222 may also be silicon oxynitride.
The source-drain doped layer 207 is used as a source region and a drain region of the formed all-around metal gate transistor.
In this embodiment, the top of the source/drain doping layer 207 is higher than the top of the top channel layer 2022, and the source/drain doping layer 207 also covers a part of the sidewall 206. In other embodiments, the top of the source/drain doping layer 207 may also be flush with the top of the top channel layer according to actual process requirements.
In this embodiment, the all-around metal gate transistor is a PMOS transistor, the all-around metal gate transistor adopts a Si channel technology, and accordingly, the fin portion 201, the top channel layer 2022, and the bottom channel layer 2021 are made of silicon. The first work function layer 212 controls the bottom parasitic MOS to be in a high threshold voltage depletion state by using a metal material with a lower work function than the second work function layer 216, so as to reduce leakage and parasitic capacitance, and the second work function layer 216 sets the GAA channel to operate at a proper threshold voltage.
The metal work functions of the first work function layer 212 and the second work function layer 216 are 4.8 to 5.1 ev, the work function of the first work function layer 212 is lower than that of the second work function layer 216, and the first work function layer 212 and the second work function layer 216 may be made of titanium nitride, tantalum nitride, titanium carbide, tantalum silicon nitride, titanium silicon nitride or tantalum carbide.
The mole volume percent of nitrogen ions in both the first work function layer 212 and the second work function layer 216 is between 3% and 30%, and wherein more tantalum or titanium ion containing compounds are added to the first work function layer 212 than to the second work function layer 216, the mole volume percent of tantalum or titanium ions in the compounds being between 60% and 95%.
In other embodiments, the all-around metal gate transistor is an NMOS transistor, the all-around metal gate transistor adopts a Si channel technology, and accordingly, the fin portion, the top channel layer, and the bottom channel layer are made of silicon. The first work function layer controls the bottom parasitic MOS to be in a high threshold voltage depletion state by using a metal material with a work function higher than that of the second work function layer, so that electric leakage and parasitic capacitance are reduced, and the second work function layer sets the GAA channel to work under a proper threshold voltage.
The metal work functions of the first work function layer and the second work function layer are in the range of 4.1 to 4.4 electron volts, and the work function of the first work function layer is higher than that of the second work function layer. The first work function layer and the second work function layer can be made of titanium aluminide, tantalum carbide, aluminum or titanium carbide.
The mol volume percentage of aluminum ions in the first work function layer and the second work function layer is 3-30%, and the second work function layer is doped with more compounds containing nitrogen, fluorine, carbon, arsenic or lanthanum ions than the first work function layer, and the mol volume percentage of the nitrogen, fluorine, carbon, arsenic or lanthanum ions in the compounds is 3-30%.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims (16)

1. A method of forming a semiconductor structure, comprising:
providing a substrate, wherein the substrate comprises a substrate, a discrete fin portion protruding out of the substrate and one or more channel lamination layers positioned on the fin portion, the channel lamination layers comprise a sacrificial layer and a channel layer positioned on the sacrificial layer, and the channel lamination layer adjacent to the fin portion is a bottom channel lamination layer;
forming a pseudo gate layer on the fin portion, wherein the pseudo gate layer crosses the channel lamination layer, and the pseudo gate layer covers part of the top wall and part of the side wall of the channel lamination layer;
forming source and drain doping layers which are in contact with the fin portion in the channel laminated layers on the two sides of the pseudo gate layer;
removing the pseudo gate layer to form a gate opening;
removing the sacrificial layer in the bottom channel lamination layer to form a first channel communicated with the grid opening;
forming a first work function layer in the first channel at least covering a bottom surface of the first channel;
forming a second work function layer on the first work function layer and the exposed inner wall of the first channel of the first work function layer, wherein the second work function layer also covers the bottom surface and the side wall of the gate opening;
when the semiconductor structure is a PMOS, the work function of the first work function layer is lower than that of the second work function layer; when the semiconductor structure is an NMOS, the work function in the first work function layer is higher than that of the second work function layer.
2. The method of forming of claim 1, wherein the channel stack is one, being the bottom channel stack, the bottom channel stack including a bottom sacrificial layer and a bottom channel layer on the bottom sacrificial layer;
removing the sacrificial layer in the bottom channel stack to form a first channel in communication with the gate opening, comprising: and removing the bottom sacrificial layer in the bottom channel lamination layer to form a first channel surrounded by the bottom channel layer, the source-drain doping layer and the fin portion.
3. The method of forming as claimed in claim 2, wherein the step of forming a first work function layer in the first via covering at least a bottom surface of the first via comprises:
forming a first work function material layer on the inner wall of the first channel and the bottom surface and the side wall of the gate opening;
after forming the first work function material layer, forming an organic layer which is filled and covers the first channel and the gate opening;
etching to remove the organic layer in the gate opening and a part of the organic layer with the thickness in the first channel, and forming a residual organic layer at least covering the bottom of the first channel;
removing the first work function material layer not covered by the remaining organic layer;
and removing the residual organic layer to form the first work function layer covering the bottom surface of the first channel.
4. The forming method of claim 2, further comprising: after forming the second work function layer, forming a metal gate structure in the gate opening and the first channel all around the bottom channel layer.
5. The method of forming of claim 1, wherein the channel stack is plural, wherein the channel stack at a bottommost is a bottom channel stack and above the bottom channel stack is a top channel stack; the bottom channel stack includes a bottom sacrificial layer and a bottom channel layer on the bottom sacrificial layer; the top channel stack comprises a top sacrificial layer and a top channel layer on the top sacrificial layer; removing the sacrificial layer in the bottom channel stack to form a first channel in communication with the gate opening, comprising: removing the bottom sacrificial layer in the bottom channel lamination layer to form a first channel surrounded by the bottom channel layer, the source drain doping layer and the fin portion; and removing the top sacrificial layer in the top channel lamination layer to form a second channel, wherein the second channel is formed by the top channel layer and the source-drain doping layer, or is formed by the top channel layer, the bottom channel layer and the source-drain doping layer in a surrounding manner, and the second channel is communicated with the grid opening.
6. The method of forming as claimed in claim 5, wherein the step of forming a first work function layer in the first via covering at least a bottom surface of the first via comprises:
forming a first work function material layer on the inner walls of the first channel and the second channel and the bottom surface and the side walls of the gate opening;
after the first work function material layer is formed, an organic layer which is filled and covers the first channel, the second channel and the grid opening is formed;
etching to remove the gate opening, the second channel and part of the organic layer with the thickness in the first channel to obtain a residual organic layer at least covering the bottom of the first channel;
removing the first work function material layer not covered by the remaining organic layer;
and removing the residual organic layer to form the first work function layer covering the bottom surface of the first channel.
7. The forming method of claim 5, wherein in the step of forming the second work function layer, the second work function layer further covers an inner wall of the second channel.
8. The method of forming as claimed in claim 5, further comprising: after forming the second work function layer, forming a metal gate structure completely surrounding the top and bottom channel layers in the gate opening, the first channel, and the second channel.
9. The forming method according to claim 3 or 6, wherein a material of the organic layer is a high molecular organic polymer.
10. The method of forming of claim 1, wherein the semiconductor structure is a PMOS, and the material of the first and second work function layers is titanium nitride, tantalum nitride, titanium carbide, tantalum silicon nitride, titanium silicon nitride, or tantalum carbide.
11. The method of forming of claim 1, wherein the semiconductor structure is an NMOS and the material of the first and second work function layers is titanium aluminide, tantalum carbide, aluminum, or titanium carbide.
12. A semiconductor structure, comprising:
a substrate;
a plurality of discrete fin portions on the substrate;
the two source drain doping layers are separated on the fin part;
the channel layer is arranged between the source-drain doped layers and is in contact with the source-drain doped layers, the channel layer is suspended above the fin portion, and the channel layer adjacent to the fin portion is a bottom channel layer; the bottom channel layer, the fin portion and the source drain doping layer form a first channel in a surrounding mode; a grid opening is formed on the bottom channel layer;
a first work function layer at least covering the bottom surface of the first channel;
the second work function layer covers the first work function layer and the inner wall of the first channel exposed by the first work function layer, and is also positioned on the bottom and the side wall of the grid opening; a metal gate structure in the first channel and gate opening and surrounding the bottom channel layer;
when the semiconductor structure is a PMOS, the work function of the first work function layer is lower than that of the second work function layer; when the semiconductor structure is an NMOS, the work function in the first work function layer is higher than that of the second work function layer.
13. The semiconductor structure of claim 12, wherein the number of the channel layers is one, the channel layer being the bottom channel layer.
14. The semiconductor structure of claim 12, wherein the number of channel layers is a plurality including, a bottom channel layer adjacent to the fin and a top channel layer suspended above the bottom channel layer; the top channel layer and the source-drain doping layer, or the top channel layer, the bottom channel layer and the source-drain doping layer enclose a second channel;
the second work function layer also covers the inner wall of the second channel;
the metal gate structure is also located in the second channel.
15. The semiconductor structure of claim 12, wherein the semiconductor structure is a PMOS and the material of the first and second work function layers is titanium nitride, tantalum nitride, titanium carbide, tantalum silicon nitride, titanium silicon nitride, or tantalum carbide.
16. The semiconductor structure of claim 12, wherein the semiconductor structure is an NMOS and the material of the first and second work function layers is titanium aluminide, tantalum carbide, aluminum, or titanium carbide.
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CN103515425A (en) * 2012-06-27 2014-01-15 三星电子株式会社 Semiconductor device, transistor and integrated circuit device
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