CN113838803B - Semiconductor structure and forming method thereof - Google Patents
Semiconductor structure and forming method thereof Download PDFInfo
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- CN113838803B CN113838803B CN202010584728.9A CN202010584728A CN113838803B CN 113838803 B CN113838803 B CN 113838803B CN 202010584728 A CN202010584728 A CN 202010584728A CN 113838803 B CN113838803 B CN 113838803B
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- 238000000034 method Methods 0.000 title claims abstract description 117
- 239000004065 semiconductor Substances 0.000 title claims abstract description 96
- 239000000463 material Substances 0.000 claims description 125
- 239000000758 substrate Substances 0.000 claims description 101
- 230000008569 process Effects 0.000 claims description 79
- 238000005530 etching Methods 0.000 claims description 27
- 239000003989 dielectric material Substances 0.000 claims description 25
- 238000002955 isolation Methods 0.000 claims description 22
- 238000001039 wet etching Methods 0.000 claims description 16
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims description 10
- 229910052799 carbon Inorganic materials 0.000 claims description 10
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 9
- 229910052760 oxygen Inorganic materials 0.000 claims description 9
- 239000001301 oxygen Substances 0.000 claims description 9
- 238000000231 atomic layer deposition Methods 0.000 claims description 7
- 230000000873 masking effect Effects 0.000 claims description 4
- 229920002120 photoresistant polymer Polymers 0.000 claims description 3
- 102100022717 Atypical chemokine receptor 1 Human genes 0.000 claims 1
- 101000678879 Homo sapiens Atypical chemokine receptor 1 Proteins 0.000 claims 1
- 238000005229 chemical vapour deposition Methods 0.000 claims 1
- 238000003475 lamination Methods 0.000 claims 1
- 230000004044 response Effects 0.000 abstract description 5
- 239000010410 layer Substances 0.000 description 389
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 18
- 229910052710 silicon Inorganic materials 0.000 description 18
- 239000010703 silicon Substances 0.000 description 18
- 239000011229 interlayer Substances 0.000 description 16
- 230000015572 biosynthetic process Effects 0.000 description 15
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 10
- 229910052814 silicon oxide Inorganic materials 0.000 description 10
- 230000009286 beneficial effect Effects 0.000 description 7
- 230000001808 coupling effect Effects 0.000 description 6
- 229910052732 germanium Inorganic materials 0.000 description 6
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 6
- 230000003071 parasitic effect Effects 0.000 description 6
- 229910010271 silicon carbide Inorganic materials 0.000 description 6
- 230000000694 effects Effects 0.000 description 5
- 229910052751 metal Inorganic materials 0.000 description 5
- 239000002184 metal Substances 0.000 description 5
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 4
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 4
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 description 4
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 4
- KXNLCSXBJCPWGL-UHFFFAOYSA-N [Ga].[As].[In] Chemical compound [Ga].[As].[In] KXNLCSXBJCPWGL-UHFFFAOYSA-N 0.000 description 4
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 4
- 238000001312 dry etching Methods 0.000 description 4
- 239000012212 insulator Substances 0.000 description 4
- 229910044991 metal oxide Inorganic materials 0.000 description 4
- 150000004706 metal oxides Chemical class 0.000 description 4
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 238000000059 patterning Methods 0.000 description 3
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 2
- 229910052582 BN Inorganic materials 0.000 description 2
- PZNSFCLAULLKQX-UHFFFAOYSA-N Boron nitride Chemical compound N#B PZNSFCLAULLKQX-UHFFFAOYSA-N 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 229910001080 W alloy Inorganic materials 0.000 description 2
- PPWPWBNSKBDSPK-UHFFFAOYSA-N [B].[C] Chemical compound [B].[C] PPWPWBNSKBDSPK-UHFFFAOYSA-N 0.000 description 2
- NTCVORQAIAUAJB-UHFFFAOYSA-N [Mg].[W] Chemical compound [Mg].[W] NTCVORQAIAUAJB-UHFFFAOYSA-N 0.000 description 2
- 239000006117 anti-reflective coating Substances 0.000 description 2
- 239000000969 carrier Substances 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 239000011810 insulating material Substances 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000011368 organic material Substances 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- -1 silicon carbide nitride Chemical class 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 238000004528 spin coating Methods 0.000 description 2
- WGTYBPLFGIVFAS-UHFFFAOYSA-M tetramethylammonium hydroxide Chemical compound [OH-].C[N+](C)(C)C WGTYBPLFGIVFAS-UHFFFAOYSA-M 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 229910021529 ammonia Inorganic materials 0.000 description 1
- 229910003481 amorphous carbon Inorganic materials 0.000 description 1
- 238000004380 ashing Methods 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 238000001035 drying Methods 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 239000002070 nanowire Substances 0.000 description 1
- 239000002243 precursor Substances 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
- 238000006557 surface reaction Methods 0.000 description 1
- 239000000725 suspension Substances 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
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-
- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823412—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823431—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
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- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823821—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
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- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/0886—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
- H01L27/0924—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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Abstract
A semiconductor structure and a method for forming the same, the method for forming the same includes: after the groove is formed, the sacrificial layer exposed by the groove is transversely etched to form a first groove, the sacrificial layer exposed by the first groove in the second area is transversely etched to form a second groove, the transverse size of the sacrificial layer below the gate structure in the second area is smaller than that of the sacrificial layer below the gate structure in the first area, the dummy gate structure and the sacrificial layer are removed, after the gate structure is formed, the transverse size of the gate structure in the second area, which is in contact with the channel layer, is smaller, and the transverse size of the gate structure in the first area, which is in contact with the channel layer, is larger. When the semiconductor structure works, the transverse dimension of a channel in the first area is larger than that of a channel in the second area, the on-state current and the power consumption of a transistor formed in the first area are small, the leakage current probability is small, the on-state current of a transistor formed in the second area is large, and the response speed is high.
Description
Technical Field
Embodiments of the present disclosure relate to semiconductor manufacturing, and more particularly, to a semiconductor structure and a method for forming the same.
Background
In semiconductor manufacturing, with the trend of very large scale integrated circuits, the feature size of integrated circuits is continuously reduced, and in order to adapt to smaller feature sizes, the channel length of Metal-Oxide-semiconductor field effect transistors (MOSFETs) is also continuously shortened. However, as the channel length of the device is shortened, the distance between the source and the drain of the device is also shortened, so that the control capability of the gate structure on the channel is further and further reduced, and the difficulty of pinching off the channel by the gate voltage is further and further increased, so that the phenomenon of subthreshold leakage (subthreshold leakage), namely the so-called short channel effect (SCE: short-CHANNEL EFFECTS), is more likely to occur.
Accordingly, to better accommodate the demand for device scaling, semiconductor processes are increasingly beginning to transition from planar transistors to three-dimensional transistors with higher power, such as Gate-all-around (GAA) transistors. In the fully-enclosed metal gate transistor, the gate encloses the region where the channel is located from the periphery, and compared with a planar transistor, the gate of the fully-enclosed metal gate transistor has stronger control capability on the channel and can better inhibit the short channel effect.
The full gate nanowire can be obtained by adding only two process modules in the existing process flow of the replacement gate fin field effect transistor (FinTET), wherein the two process modules are as follows: firstly, a layer of Silicon is grown on bulk Silicon (bulk Silicon) or SOI wafer, so that the leakage of bulk Silicon materials can be avoided. Second, the sige is selectively removed on a replaceable metal gate loop, and then a HKMG (high-k insulating layer + metal gate) stack is used to surround the silicon channel to form a fully enclosed metal gate transistor.
Disclosure of Invention
The embodiment of the invention solves the problem of providing a semiconductor structure and a forming method thereof, and optimizes the electrical performance of the semiconductor structure.
In order to solve the above problems, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate, wherein the substrate comprises a substrate, a channel stack layer separated on the substrate and a pseudo gate structure crossing the channel stack layer, the pseudo gate structure covers partial top wall and partial side wall of the channel stack layer, the channel stack layer comprises sacrificial layers and channel layers which are alternately stacked, and the bottommost part of the channel stack layer is the sacrificial layer; etching the channel laminated layers on two sides of the pseudo gate structure, and forming a groove in the channel laminated layers; forming a first groove by transversely etching the sacrificial layer exposed by the groove by taking the extending direction parallel to the surface of the substrate and perpendicular to the dummy gate structure as a transverse direction; transversely etching the sacrificial layer exposed out of the first groove in the second area to form a second groove; forming a side wall material layer in the first groove and the second groove; removing the pseudo gate structure after the side wall material layer is formed, and forming a gate opening; after forming the grid electrode opening, removing the sacrificial layer to form a channel; a gate structure is formed in the channel and gate opening.
Correspondingly, the embodiment of the invention also provides a semiconductor structure, which comprises: a substrate comprising a first region and a second region; the source-drain doped layer is separated on the substrate; a plurality of channel layers which are suspended on the substrate at intervals in the normal direction of the surface of the substrate and are positioned between the source-drain doped layers; a gate structure surrounding the channel layer so as to be parallel to a substrate surface and perpendicular to an extension direction of the gate structure; the first side wall layer is positioned between the source-drain doped layer and the grid structure in the first region; the second side wall layer is positioned between the source-drain doping layer and the grid structure in the second region, and the transverse dimension of the second side wall layer is larger than that of the first side wall layer.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following advantages:
In the method for forming a semiconductor structure provided by the embodiment of the invention, the substrate comprises a first region and a second region, in the step of providing the substrate, the substrate comprises a substrate and a channel stack layer positioned on the substrate, grooves are formed in the channel stack layer at two sides of the pseudo gate structure, correspondingly, the transverse dimension of the channel stack layer between the grooves of the first region is the same as the transverse dimension of the channel stack layer between the grooves of the second region, after the grooves are formed in the channel stack layer at two sides of the pseudo gate structure, the sacrificial layer exposed by the grooves is etched transversely, a first groove is formed, the sacrificial layer exposed by the first groove in the second region is etched transversely, a second groove is formed, the transverse dimension of the second groove is larger than that of the first groove, the lateral dimension of the side wall material layer formed in the second groove is larger than that of the side wall material layer formed in the first groove, the lateral dimension of the sacrificial layer below the gate structure in the second area is smaller than that of the sacrificial layer below the gate structure in the first area, the dummy gate structure and the sacrificial layer are removed, after the gate structure is formed, the lateral dimension of the gate structure in the second area, which is in contact with the channel layer, is smaller, the lateral dimension of the gate structure in the first area, which is in contact with the channel layer, is larger, the lateral dimension of the channel in the first area, which is larger than that of the channel in the second area, is correspondingly, when the semiconductor structure is in operation, the on-state current of the transistor formed in the first area is small, the power consumption is small, the leakage current probability is small, the on-state current of the transistor formed in the second area is large, the response speed is high.
Drawings
FIGS. 1-3 are schematic diagrams illustrating key steps in a method for forming a semiconductor structure;
fig. 4 to 13 are schematic structural views corresponding to steps in the first embodiment of the method for forming a semiconductor structure according to the embodiment of the present invention;
fig. 14 is a schematic structural view of a second embodiment of a semiconductor structure according to an embodiment of the present invention.
Detailed Description
As can be seen from the background art, the devices formed at present still have the problem of poor performance. The reason for the poor performance of the device is analyzed by combining a forming method of a semiconductor structure.
Referring to fig. 1-3, a schematic structure diagram of key steps in a method for forming a semiconductor structure is shown.
As shown in fig. 1, the base comprises a first region I and a second region II, comprising a substrate 1 and a channel stack 2 on the substrate 1, the channel stack 2 comprising a sacrificial layer 21 and a channel layer 22 on the sacrificial layer 21; a dummy gate structure 4 located on the channel stack 2, wherein the dummy gate structure 4 covers a part of top wall and a part of side wall of the channel stack 2 so as to be parallel to the surface of the substrate 1 and perpendicular to the extending direction of the dummy gate structure 4; the source-drain doped layers 3 are positioned in the channel stack layers 2 at two sides of the pseudo gate structure 4; the inner side wall layer 7 is positioned between the sacrificial layer 21 and the source-drain doped layer 3; and the interlayer dielectric layer 6 is positioned on the side part of the pseudo gate structure 4, and the top surface of the interlayer dielectric layer 6 is flush with the top surface of the pseudo gate structure 4.
As shown in fig. 2, the dummy gate structure 4 is removed to form a gate opening 5; after forming the gate opening 5, the sacrificial layer 21 is removed, forming a first channel 8 surrounded by the substrate 1, the channel layer 22 and the inner sidewall layer 7, and a second channel 9 surrounded by the channel layer 22 and the inner sidewall layer 7.
As shown in fig. 3, a gate structure 10 is formed in the gate opening 5, the first channel 8 and the second channel 9.
Semiconductor structures are increasingly integrated, and semiconductor processes are gradually transitioning from planar transistors to three-dimensional transistors with higher efficiency, such as Gate-all-around (GAA) transistors, where the gates of the Gate-all-around transistors have greater channel control capability and can better suppress short channel effects. Typically, the dummy gate structures 4 in the first device region I and the second device region II are formed by a self-aligned dual patterning process (SADP), and the lateral dimensions of the dummy gate structures 4 in the respective first device region I and the dummy gate structures 4 in the second device region II are the same. With the need for semiconductor structures, the channels in the first device region I and the second device region II need to be different lengths to meet different process requirements.
In order to solve the technical problem, in the method for forming a semiconductor structure provided by the embodiment of the present invention, the substrate includes a first region and a second region, in the step of providing the substrate, the substrate includes a substrate and a channel stack layer located on the substrate, trenches are formed in the channel stack layer on both sides of the dummy gate structure, and accordingly, a lateral dimension of the channel stack layer between the trenches of the first region is the same as a lateral dimension of the channel stack layer between the trenches of the second region, after forming the trenches in the channel stack layer on both sides of the dummy gate structure, the sacrificial layer exposed by the trenches is laterally etched to form a first recess, the sacrificial layer exposed by the first recess in the second region is laterally etched to form a second recess, and a lateral dimension of the second recess is greater than a lateral dimension of the first recess, the lateral dimension of the side wall material layer formed in the second groove is larger than that of the side wall material layer formed in the first groove, the lateral dimension of the sacrificial layer below the gate structure in the second area is smaller than that of the sacrificial layer below the gate structure in the first area, the dummy gate structure and the sacrificial layer are removed, after the gate structure is formed, the lateral dimension of the gate structure in the second area, which is in contact with the channel layer, is smaller, the lateral dimension of the gate structure in the first area, which is in contact with the channel layer, is larger, the lateral dimension of the channel in the first area, which is larger than that of the channel in the second area, is correspondingly, when the semiconductor structure is in operation, the on-state current of the transistor formed in the first area is small, the power consumption is small, the leakage current probability is small, the on-state current of the transistor formed in the second area is large, the response speed is high.
In order to make the above objects, features and advantages of the embodiments of the present invention more comprehensible, a detailed description of specific embodiments of the present invention is provided below with reference to the accompanying drawings.
Fig. 4 to 13 are schematic structural views corresponding to each step in an embodiment of a method for forming a semiconductor structure according to the present invention.
Referring to fig. 4 and 5, fig. 5 is a cross-sectional view of fig. 4 in the AA direction, providing a base including a first region and a second region, the base including a substrate 100, a channel stack layer separated on the substrate 100, and a dummy gate structure 103 crossing the channel stack layer, the dummy gate structure 103 covering a portion of a top wall and a portion of a side wall of the channel stack layer, the channel stack layer including a sacrificial layer 101 and a channel layer 102 alternately stacked, and a bottommost portion of the channel stack layer being the sacrificial layer 101.
In this embodiment, the method for forming a semiconductor structure is used to form a semiconductor structure in which a channel length of a transistor formed in a first region is longer than a channel length of a transistor formed in a second region.
The substrate 100 is used to provide a process platform for the subsequent formation of semiconductor structures.
In this embodiment, the substrate 100 is a silicon substrate. In other embodiments, the substrate may be made of other materials such as germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, and the substrate may be made of other types of substrates such as silicon on insulator substrates or germanium on insulator substrates.
The channel stack is used to provide a process basis for the subsequent formation of the dangling set of channel layers 102. The sacrificial layer 101 is used for supporting the channel layer 102, providing process conditions for the space suspension arrangement of the subsequent channel layer 102, and occupying space positions for the subsequently formed gate structure.
In this embodiment, the difficulty of etching the channel layer 102 is greater than that of etching the sacrificial layer 101, and the channel layer 102 is not easily damaged when the sacrificial layer 101 is removed later.
In this embodiment, the material of the channel layer 102 is silicon; the material of the sacrificial layer 101 is silicon germanium. In other embodiments, the material of the channel layer may be germanium, silicon carbide, gallium arsenide, indium gallium arsenide, or other materials, and the material of the sacrificial layer may be silicon.
In this embodiment, the topmost film layer in the channel stack is the sacrificial layer 101. In other embodiments, the topmost film layer in the channel stack is a channel layer.
The dummy gate structure 103 occupies a space for a gate structure to be formed in a subsequent process.
In this embodiment, the dummy gate structure 103 includes a dummy gate oxide layer (not shown) conformally covering a portion of the top surface and a portion of the sidewalls of the channel stack, and a dummy gate layer (not shown) on the dummy gate oxide layer.
In this embodiment, the material of the dummy gate oxide layer 1031 is silicon oxide. In other embodiments, the material of the dummy gate oxide layer may also be silicon oxynitride.
In this embodiment, the material of the dummy gate layer 1032 is polysilicon. In other embodiments, the material of the dummy gate layer may also be amorphous carbon.
The step of forming the dummy gate structure 103 includes: forming a dummy gate oxide material layer (not shown) covering the channel stack and a dummy gate material layer (not shown) on the dummy gate oxide layer; forming a gate mask layer 104 on the dummy gate material layer; the dummy gate material layer and the dummy gate oxide material layer are etched with the gate mask layer 104 as a mask, the remaining dummy gate oxide material layer serves as the dummy gate oxide layer 1031, and the remaining dummy gate material layer serves as the dummy gate layer 1032.
It should be noted that, in this embodiment, the extension direction parallel to the surface of the substrate 100 and perpendicular to the dummy gate structure 103 is the transverse direction, and the transverse dimensions of the dummy gate structures in the first area and the second area are the same, which simplifies the forming process of the dummy gate structure 103 and is beneficial to improving the forming efficiency of the dummy gate structure 103.
In the step of providing the substrate, a gate sidewall layer 105 is formed on the sidewall of the dummy gate structure 103.
The gate sidewall layer 105 is used to define a formation position of a source-drain doped layer to be formed later, and is also used to protect the sidewall of the dummy gate structure 103 from being damaged during the formation process of the subsequent semiconductor structure.
The materials of the gate sidewall layer 105 include: one or more of silicon nitride, silicon oxynitride, silicon carbide nitride, boron nitride silicon and boron carbon nitride silicon.
Note that in this embodiment, both the first region and the second region may be used to form NMOS (NEGATIVE CHANNEL METAL Oxide Semiconductor) or PMOS (Positive CHANNEL METAL Oxide Semiconductor). In other embodiments, one of the first region and the second region may be an NMOS, and one may be a PMOS.
It should be further noted that, the bottommost end of the channel stack is the sacrificial layer 101, and the bottommost sacrificial layer 101 is removed later to form a channel, the channel is prepared for forming the gate structure later, the bottommost channel layer 102 of the channel stack can be surrounded by the gate structure, and accordingly, the bottommost channel layer 102 is easy to be depleted when the semiconductor structure works, which is beneficial to improving the electrical performance of the semiconductor structure.
In this embodiment, in the step of providing the substrate, the topmost layer of the channel stack is the sacrificial layer 101. In other embodiments, in the step of providing a substrate, a topmost layer of the channel stack is a channel layer.
It should also be noted that, in the step of providing a substrate, the substrate further includes: a fin 112 protruding on the substrate 100, the fin 112 being located between the substrate 100 and the channel stack; an isolation layer 113 located on the substrate 100 where the fin 112 is exposed; the dummy gate structure 103 is located on the isolation layer 113.
The fin 112 protrudes above the substrate 100, and the side of the fin 112 provides a process space for the isolation layer 113.
In this embodiment, the fin 112 is made of the same material as the substrate 100. In other embodiments, the fin may also be of a different material than the substrate.
The isolation layer 113 electrically isolates the gate structure formed by the subsequent replacement dummy gate structure 113 from the substrate 100, and the isolation layer 113 is used to further electrically isolate the fins 112 from each other.
In this embodiment, the material of the isolation layer 113 is a dielectric material. Specifically, the material of the isolation layer 113 includes silicon oxide, which is a dielectric material with common process and low cost, and has high process compatibility, so that the process difficulty and the process cost for forming the isolation layer 113 are reduced.
In this embodiment, the dummy gate structure 103 is located on the isolation layer 113, and the dummy gate structure 103 spans across the fin 112 and covers a portion of the top wall and a portion of the side wall of the fin 112.
Referring to fig. 6, the channel stack on both sides of the dummy gate structure 103 is etched, forming a trench 106 in the channel stack.
The trench 106 provides for the subsequent formation of a sidewall material layer, and the trench 106 also provides process space for the subsequent formation of a source-drain doped layer.
In this embodiment, the channel stacks on both sides of the dummy gate structure 103 are etched by using the gate mask layer 104 as a mask and using a dry etching process to form the trench 106. The dry etching process has anisotropic etching characteristics and good etching profile control, is favorable for enabling the shape of the groove 106 to meet the process requirements, and can take the top of the fin portion 112 as an etching stop position in the process of forming the groove 106 by adopting the dry etching process, so that damage to other film structures can be reduced. Moreover, by changing the etching gas, the sacrificial layer 101 and the channel layer 102 can be etched in the same etching apparatus, which is advantageous in improving the formation rate of the trench 106.
In other embodiments, a wet etching process or an etching process combining a dry process and a wet process may be further used to etch the channel stack on both sides of the dummy gate structure to form the trench.
Referring to fig. 7, the sacrificial layer 101 exposed by the trench 106 is etched laterally with a direction parallel to the surface of the substrate 100 and perpendicular to the extension direction of the dummy gate structure 103 as a lateral direction, so as to form a first recess 107.
The first grooves 107 of the first region I provide a process space for the subsequent formation of the sidewall material layer, the first grooves 107 in the first region I are used for defining the length of the channel region in the subsequent first region I, and the first grooves 107 of the second region II provide for the subsequent further etching to form second grooves.
In this embodiment, the sacrificial layer 101 exposed by the trench 106 is etched laterally by a wet etching process to form the first recess. The wet etching process is isotropic etching, has higher etching rate, and is simple to operate and low in process cost. In other embodiments, the first groove may be formed by laterally etching the sacrificial layer exposed by the trench using an isotropic dry etching process.
In this embodiment, the material of the sacrificial layer 101 is silicon germanium, and correspondingly, in the process of laterally etching the sacrificial layer 101 exposed by the trench 106 by using a wet etching process, the wet etching solution used includes HCl solution.
Referring to fig. 8, the sacrificial layer 101 exposed by the first recess 107 in the second region II is laterally etched to form a second recess 108.
The substrate comprises a first region I and a second region II, in the step of providing the substrate, the substrate comprises a substrate 100 and channel stacks positioned on the substrate 100, grooves 106 are formed in the channel stacks at two sides of the pseudo gate structure 103, the lateral dimensions of the channel stacks between the grooves 106 of the first region I are the same as the lateral dimensions of the channel stacks between the grooves of the second region II, after the grooves 106 are formed in the channel stacks at two sides of the pseudo gate structure 103, the sacrificial layer 101 exposed by the grooves 106 is laterally etched to form a first groove 107, the sacrificial layer 101 exposed by the first groove 107 in the second region II is laterally etched to form a second groove 108, the lateral dimensions of the second groove 108 are larger than those of the first groove 107, the lateral dimension of the sidewall material layer subsequently formed in the second recess 108 is greater than the lateral dimension of the sidewall material layer formed in the first recess 107, and accordingly, the lateral dimension of the sacrificial layer 101 under the gate structure in the second region II is smaller than the lateral dimension of the sacrificial layer 101 under the gate structure in the first region I, the dummy gate structure 103 and the sacrificial layer 101 are removed, after the gate structure is formed, the lateral dimension of the gate structure in the first region I in contact with the channel layer 102 is greater, the lateral dimension of the gate structure in the second region II in contact with the channel layer 102 is smaller, and accordingly, the lateral dimension of the channel in the first region I is greater than the lateral dimension of the channel in the second region II when the semiconductor structure is in operation, the on-current of the transistor formed in the first region I is small, the power consumption is small, the leakage current probability is small, the on-current of the transistor formed in the second region II is large, the response speed is high.
The second recess 108 in the second region II provides a process space for the subsequent formation of the sidewall material layer, and the second recess 108 in the second region II is used to define the length of the channel region in the subsequent second region II.
The second recess 108 provides a process space for the subsequent formation of a sidewall material layer.
The step of forming the second recess 108 includes: forming a shielding layer 109 covering the first groove 107 of the first region I and exposing the first groove 107 of the second region II; and using the shielding layer 109 as a mask, and laterally etching the sacrificial layer 101 exposed by the first groove 107 in the second region II to form the second groove 108.
The shielding layer 109 is made of a material that is easy to remove, and damage to the formed film layer can be reduced when the shielding layer 109 is removed later.
The material of the shielding layer 109 is an organic material. Specifically, the materials of the shielding layer 109 include: one or more of BARC (bottom anti-REFLECTIVE COATING ) material, SOC (spin on carbon) material, ODL (organic DIELECTRIC LAYER) material, photoresist, DARC (DIELECTRIC ANTI-REFLECTIVE COATING ) material, DUO material, or APF (ADVANCED PATTERNING FILM, advanced patterning film) material. In this embodiment, the material of the shielding layer 109 includes photoresist.
The step of forming the shielding layer 109 includes: forming a shielding material layer (not shown in the figure) covering the first region I and the second region II; the layer of masking material is patterned, with the remaining layer of masking material acting as masking layer 109.
In this embodiment, the shielding material layer is formed by a spin-coating process. The spin coating process has the advantages of mild process conditions, simple operation and the like, and has remarkable convenient effects of reducing pollution, saving energy, improving cost performance and the like.
In this embodiment, the second recess 108 is formed by using the shielding layer 109 as a mask and performing a wet etching process to laterally etch the sacrificial layer 101 exposed by the first recess 107 in the second region II. The wet etching process is isotropic etching, has higher etching rate, and is simple to operate and low in process cost.
In this embodiment, the material of the sacrificial layer 101 is silicon germanium, and correspondingly, in the process of laterally removing the sacrificial layer 101 with the width of the exposed portion of the sidewall of the trench 106 by using a wet etching process, the wet etching solution used includes HCl solution.
In the step of forming the second groove 108, the lateral dimension of the second groove 108 is preferably not too large or too small as compared with the lateral dimension of the first groove 107. If the lateral dimension of the second recess 108 is too large compared to the lateral dimension of the first recess 107, and correspondingly, the lateral dimension of the sacrificial layer 101 remaining in the second region II is too small, the lateral dimension of the channel formed by subsequently removing the sacrificial layer 101 in the second region II is too small, and the lateral dimension of the gate structure formed in the second device region II is subsequently too small, so that the control capability of the gate structure in the second device region II on the channel is poor during the operation of the semiconductor structure, resulting in poor performance of the second device region II. If the lateral dimension of the second recess 108 is too small compared with the lateral dimension of the first recess 107, the lateral dimension of the sacrificial layer 101 in the corresponding second device region II is different from the lateral dimension of the sacrificial layer 101 in the first device region I, the lateral dimension of the sacrificial layer 101 in the second device region II is too large, after the sacrificial layer 101 in the second device region II is subsequently removed, the lateral dimension of a channel formed is too large, and then the lateral dimension of a gate structure formed in the channel of the second device region II is too large. In this embodiment, in the step of forming the second groove 108, the lateral dimension of the second groove 108 is 1 nm to 5 nm larger than the lateral dimension of the first groove 107.
The method for forming the semiconductor structure further comprises the following steps: after the second recess 108 is formed, the shielding layer 109 is removed.
In this embodiment, the material of the shielding layer 109 is an organic material, and accordingly, an ashing process is used to remove the shielding layer 109.
Referring to fig. 9, a sidewall material layer is formed in the first recess 107 and the second recess 108.
And subsequently removing the dummy gate structure 103, forming a gate opening, removing the sacrificial layer 101, forming a channel, and forming a gate structure in the channel and the gate opening, wherein the lateral dimension of the first groove 107 is smaller than the lateral dimension of the second groove 108, so that the lateral dimension of the side wall material layer formed in the first groove 107 is smaller than the lateral dimension of the side wall material layer formed in the second groove 108, and accordingly, the lateral dimension of the channel of the second device region II is smaller than the lateral dimension of the channel of the first device region I, and the lateral dimension of the gate structure of the second device region II is smaller than the lateral dimension of the gate structure of the first device region I.
The side wall material layer is used for reducing the capacitive coupling effect between the source-drain doped layer and the gate structure which are formed later, so that parasitic capacitance is reduced, and the electrical property of the transistor structure is improved.
In this embodiment, the sidewall material layer located in the first groove 107 is used as a first sidewall layer 110, and the sidewall material layer located in the second groove 108 is used as a second sidewall layer 111.
In this embodiment, the material of the sidewall material layer is a low K dielectric material. A low-k dielectric material (low-k dielectric material refers to a dielectric material having a relative dielectric constant of 2.6 or more and 3.9 or less). The low-K dielectric material has excellent insulating property. The electric coupling effect between the gate structure and the source-drain doped layer which are subsequently formed on the two sides of the side wall material layer can be reduced, parasitic capacitance is further reduced, and the electric performance of the transistor structure is improved.
Specifically, the material of the side wall material layer includes: siON, siBCN, siCN carbon doped SiN or oxygen doped SiN. In this embodiment, the material of the sidewall material layer includes SiN doped with carbon or SiN doped with oxygen.
The forming method of the side wall material layer comprises the following steps: forming a side wall material film (not shown in the figure) which conformally covers the dummy gate structure 103, the trench 106, the first groove 107 and the second groove 108; and removing the sidewall material films at the bottom of the groove 106 and on the side wall of the pseudo gate structure 103, and taking the remaining sidewall material films in the first groove 107 and the second groove 108 as sidewall material layers.
In this embodiment, an atomic layer deposition (Atomic Layer Deposition, ALD) process is used to form the sidewall material film. An atomic layer deposition process refers to a deposition process in which a vapor precursor is alternately pulsed into a reaction chamber, chemisorbed on a substrate to be deposited, and a surface reaction occurs. Through an atomic layer deposition process, the sidewall material film is formed on the surfaces of the dummy gate structure 103, the trench 106, the first groove 107 and the second groove 108 in an atomic layer manner, so that uniformity of deposition rate, thickness uniformity of the sidewall material film and structural uniformity in the sidewall material film are improved, and the sidewall material film has good covering capability; in addition, the process temperature of the atomic layer deposition process is generally lower, so that the Thermal Budget (Thermal Budget) is also reduced, and the probability of performance shift of the semiconductor structure is reduced.
The method for forming the semiconductor structure further comprises the following steps: after the sidewall material layer is formed, a source-drain doped layer 114 is formed in the trench 106.
The source drain doped layer 114 is used to provide stress to the channel during operation of the semiconductor structure, and to enhance the mobility of carriers in the channel.
When the regions are used to form an NMOS, the source drain doped layer 114 is used to act as the source and drain of the NMOS. During operation of the semiconductor structure, the source-drain doped layer 114 applies a tensile stress to the channel under the gate structure, which may increase the electron mobility rate.
When the regions are used to form a PMOS, the source drain doped layer 114 is used as the source and drain of the PMOS. In operation of the semiconductor structure, the source drain doped layer 114 applies compressive stress to the channel under the gate structure, which can improve hole mobility.
The method for forming the semiconductor structure further comprises the following steps: after the source-drain doped layer 114 is formed, an interlayer dielectric layer 115 is formed on the substrate 100 at the side portion of the dummy gate structure 103, and the top surface of the interlayer dielectric layer 115 is lower than or flush with the top surface of the dummy gate structure 103.
Interlayer dielectric layer 115 is used to electrically isolate adjacent devices.
In this embodiment, the material of the interlayer dielectric layer 115 is an insulating material. The material of the interlayer dielectric layer 115 specifically includes silicon oxide. Silicon oxide is a dielectric material with common process and low cost, and has high process compatibility, which is beneficial to reducing the process difficulty and the process cost for forming the interlayer dielectric layer 115.
In the process of forming the interlayer dielectric layer 115, the gate mask layer 114 is removed.
Referring to fig. 11, the dummy gate structure 103 is removed to form a gate opening 116.
The gate opening 116 provides process space for the subsequent formation of a gate structure.
In this embodiment, a wet etching process is used to remove the dummy gate structure 103. The wet etching process has higher etching rate, simple operation and low process cost.
In this embodiment, the dummy gate structure 103 includes a dummy gate oxide 1031 and a dummy gate 1032. The material of the dummy gate oxide layer 1031 is silicon oxide, and the material of the dummy gate layer 1032 is polysilicon. Specifically, in the step of removing the dummy gate structure 103, an etching solution is used that includes ammonia and tetramethylammonium hydroxide solution.
In this embodiment, the gate opening 116 exposes the topmost sacrificial layer 101.
Referring to fig. 12, after the gate opening 116 is formed, the sacrificial layer 101 is removed to form a channel 117.
The channel 117 and gate opening 116 together provide process space for the subsequent formation of a gate structure.
In this embodiment, a wet etching process is used to remove the sacrificial layer 101. The wet etching process has higher etching rate, simple operation and low process cost.
Specifically, the material of the sacrificial layer 101 is silicon germanium. Correspondingly, in the process of removing the sacrificial layer 101 by the wet etching process, the etching solution adopted is HCl solution.
Specifically, in the first region I, the bottommost channel 117 is surrounded by the fin 112, the first sidewall layer 110 and the channel layer 102, the topmost channel layer 117 is surrounded by the channel layer and the first sidewall layer 110 and is communicated with the gate opening 116, and the remaining channel layers 117 are surrounded by the channel layer 102 and the first sidewall layer 110.
In the second region II, the bottom-most channel 117 is surrounded by the fin 112, the second sidewall 111 and the channel layer 102, the top-most channel 117 is surrounded by the channel layer and the second sidewall 111 and is communicated with the gate opening 116, and the remaining channel 117 is surrounded by the channel layer 102 and the second sidewall 111.
In this embodiment, the topmost layer in the channel stack is the sacrificial layer 101. After the sacrificial layer 101 is correspondingly removed, the exposed lateral dimension of the top surface of the channel layer 102 at the top in the second region II is equal to the exposed lateral dimension of the rest of the channel layers 102 in the second region II, and after the gate structure is subsequently formed, the channel lengths of the channel layers 102 in the second region II are the same when the semiconductor structure is in operation, which is beneficial to improving the uniformity of the device performance.
In other embodiments, the topmost layer of the channel stack is a channel layer.
The lateral contact size of the gate structure and the top surface of the topmost channel layer is a first size, and the lateral contact size of the gate structure and the bottommost channel layer is a second size.
When the lateral dimension of the second side wall layer is equal to the lateral dimension of the grid side wall layer, the first dimension is equal to the second dimension, and after a grid structure is formed subsequently, when the semiconductor structure works, the channel lengths of all the channel layers in the second region II are the same, so that uniformity of device performance is improved.
When the lateral dimension of the second side wall layer is larger than the lateral dimension of the grid side wall layer, the first dimension is smaller than the second dimension, and after a grid structure is formed subsequently, when the semiconductor structure works, the channel length of the topmost channel layer in the second region is different from the channel length of the bottom, so that the starting voltage of the channel at the top is different from the starting voltage of the channel at the bottom.
When the lateral dimension of the second side wall layer is smaller than that of the grid side wall layer, the first dimension is larger than the second dimension, and after a grid structure is formed subsequently, when the semiconductor structure works, the channel length of the topmost channel layer in the second region is different from that of the bottom channel layer, so that the starting voltage of the top channel is different from that of the bottom channel.
Referring to fig. 13, a gate structure 118 is formed in the channel 117 and the gate opening 116.
The gate structure 118 is used to control the opening and closing of the channel during operation of the semiconductor structure.
In this embodiment, the material of the gate structure 118 is magnesium-tungsten alloy. In other embodiments, the material of the gate structure may be W, al, cu, ag, au, pt, ni or Ti.
The method for forming the semiconductor structure further comprises the following steps: a gate dielectric layer (not shown) is formed in the channel 117 and gate opening 116 prior to forming the gate structure 118.
The gate dielectric layer is used to electrically isolate gate structure 118 from fin 112. The gate dielectric layer is made of a high-k dielectric material. The high-k dielectric material refers to a dielectric material with a relative dielectric constant larger than that of silicon oxide.
In this embodiment, the gate dielectric layer is made of HfO 2. In other embodiments, the material of the gate dielectric layer may be one or more selected from ZrO 2, hfSiO, hfSiON, hfTaO, hfTiO, hfZrO, or Al 2O3.
Correspondingly, the embodiment of the invention also provides a semiconductor structure. Referring to fig. 13, a schematic structure diagram of an embodiment of the semiconductor structure of the present invention is shown.
The semiconductor structure includes: a substrate 100, the substrate 100 comprising a first region I and a second region II; a source drain doped layer 114, which is separated on the substrate 100; a plurality of channel layers 102 suspended on the substrate 100 at intervals in a direction normal to the surface of the substrate 100, and the plurality of channel layers 102 are located between the source-drain doped layers 114; a gate structure 118 surrounding the channel layer 102 so as to be parallel to the surface of the substrate 100 and perpendicular to the extending direction of the gate structure 118; a first sidewall layer 110 located between the source/drain doped layer 114 and the gate structure 118 in the first region I; the second sidewall layer 111 is located between the source-drain doped layer 114 and the gate structure 118 in the second region II, and the lateral dimension of the second sidewall layer 111 is greater than the lateral dimension of the first sidewall layer 110.
In the semiconductor structure provided in the embodiment of the present invention, in the step of forming the semiconductor structure, the forming position of the gate structure 118 is occupied by a dummy gate structure, in the step of forming the dummy gate structure, generally, the lateral dimensions of the dummy gate structures in the first region I and the second region II are the same, the source-drain doped layers 114 are formed on both sides of the dummy gate structure, and the interval between the source-drain doped layers 114 on both sides of the dummy gate structure in the corresponding first region I is equal to the interval between the source-drain doped layers 114 in the second region II, that is, the lateral dimension of the channel layer 102 between the source-drain doped layers 114 in the first region I is equal to the lateral dimension between the channel layers 102 between the source-drain doped layers 114 in the second region II. The first sidewall layer 110 is located between the source-drain doped layer 114 and the gate structure 118 in the first region I, the second sidewall layer 111 is located between the source-drain doped layer 114 and the gate structure 118 in the second region II, the lateral dimension of the second sidewall layer 111 is larger than that of the first sidewall layer 110, the lateral dimension of the gate structure 118 in the second region II in contact with the channel layer 102 is smaller, the lateral dimension of the gate structure 118 in the first region I in contact with the channel layer 102 is larger, and accordingly, when the semiconductor structure is in operation, the lateral dimension of the channel in the first region I is larger than that of the channel in the second region II, the on-current and the power consumption of the transistor formed in the first region I are small, the leakage current probability is smaller, the on-current of the transistor formed in the second region II is large, and the response speed is fast.
It should be noted that, in this embodiment, the first region I and the second region II may be used to form an NMOS (NEGATIVE CHANNEL METAL Oxide Semiconductor) or a PMOS (Positive CHANNEL METAL Oxide Semiconductor). In other embodiments, one of the first region and the second region may be an NMOS, and one may be a PMOS.
The substrate 100 is used to provide a process platform for the subsequent formation of semiconductor structures.
In this embodiment, the substrate 100 is a silicon substrate. In other embodiments, the substrate may be made of other materials such as germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, and the substrate may be made of other types of substrates such as silicon on insulator substrates or germanium on insulator substrates.
It should be noted that the semiconductor structure further includes: and the fin 112 is located between the substrate 100 and the plurality of channel layers 102.
The sides of the fin 112 provide process space for the isolation layer 113.
In this embodiment, the fin 112 is made of the same material as the substrate 100. In other embodiments, the fin may also be of a different material than the substrate.
The semiconductor structure further includes: and the isolation layer 113 is positioned on the substrate 100 at the side part of the fin 112, and the isolation layer 113 covers part of the side wall of the fin 112.
The isolation layer 113 electrically isolates the gate structure 118 from the substrate 100. Furthermore, the isolation layer 113 also serves to electrically isolate the individual fins 112 from each other.
In this embodiment, the material of the isolation layer 113 is a dielectric material. Specifically, the material of the isolation layer 113 includes silicon oxide, which is a dielectric material with common process and low cost, and has high process compatibility, so that the process difficulty and the process cost for forming the isolation layer 113 are reduced.
The channel layer 102 serves as a channel when the semiconductor structure is in operation.
In this embodiment, the material of the channel layer 102 is silicon. In other embodiments, the material of the channel layer may be germanium, silicon carbide, gallium arsenide, indium gallium arsenide, or other materials.
A plurality of channel layers 102 are suspended on the substrate 100 at intervals in the direction of the surface normal of the substrate 100.
The gate structure 118 is used to control the opening and closing of the channel during operation of the semiconductor structure.
In this embodiment, the material of the gate structure 118 is magnesium-tungsten alloy. In other embodiments, the material of the gate structure may be W, al, cu, ag, au, pt, ni or Ti.
In this embodiment, the gate structure 118 is on the isolation layer 113, and the gate structure 118 spans across the fin 112 and covers a portion of the top wall and a portion of the side wall of the fin 112.
It should be noted that the gate structure 118 can completely surround the bottommost channel layer 102, and accordingly, the bottommost channel layer 102 is easy to be depleted when the semiconductor structure is in operation, which is beneficial to improving the electrical performance of the semiconductor structure.
The source drain doped layer 114 is used to provide stress to the channel during operation of the semiconductor structure, and to enhance the mobility of carriers in the channel.
When the regions are used to form an NMOS, the source drain doped layer 114 is used to act as the source and drain of the NMOS. During operation of the semiconductor structure, the source drain doped layer 114 applies a tensile stress to the channel under the gate structure 118, which may increase the electron mobility rate.
When the regions are used to form a PMOS, the source drain doped layer 114 is used as the source and drain of the PMOS. In operation of the semiconductor structure, the source drain doped layer 114 applies compressive stress to the channel under the gate structure 118, which can improve hole mobility.
The method for forming the semiconductor structure further comprises the following steps: a gate dielectric layer is formed in the channel 117 and gate opening 116 prior to forming the gate structure 118.
The gate dielectric layer is used to electrically isolate gate structure 118 from fin 112. The gate dielectric layer is made of a high-k dielectric material. The high-k dielectric material refers to a dielectric material with a relative dielectric constant larger than that of silicon oxide.
In this embodiment, the gate dielectric layer is made of HfO 2. In other embodiments, the material of the gate dielectric layer may be one or more selected from ZrO 2, hfSiO, hfSiON, hfTaO, hfTiO, hfZrO, or Al 2O3.
In the first region I, the first sidewall layer 110 is used to define the length of the channel region in the subsequent first region I, and the first sidewall layer 110 is further used to reduce the capacitive coupling effect between the source-drain doped layer 114 and the gate structure 118, thereby reducing the parasitic capacitance and improving the electrical performance of the transistor structure.
In this embodiment, the material of the first sidewall layer 110 is a low-K dielectric material. A low-k dielectric material (low-k dielectric material refers to a dielectric material having a relative dielectric constant of 2.6 or more and 3.9 or less). The low-K dielectric material has excellent insulating property. The electrical coupling effect between the gate structure 118 and the source-drain doped layer on both sides of the first sidewall layer 110 can be reduced, thereby reducing parasitic capacitance and improving the electrical performance of the transistor structure.
Specifically, the materials of the first sidewall layer 110 include: siON, siBCN, siCN carbon doped SiN or oxygen doped SiN. In this embodiment, the material of the first sidewall layer 110 includes SiN doped with carbon or SiN doped with oxygen.
In this embodiment, in the first region I, the first sidewall layer 110 is further located on the topmost channel layer 102.
In the second region II, the second sidewall layer 111 is used to define the length of the channel region in the subsequent second region II, and the second sidewall layer 111 is used to reduce the capacitive coupling effect between the source-drain doped layer 114 and the gate structure 118, thereby reducing the parasitic capacitance and improving the electrical performance of the transistor structure.
In this embodiment, the material of the second sidewall layer 111 is a low K dielectric material. The low-k dielectric material has excellent insulating property. The electrical coupling effect between the gate structure 118 and the source-drain doped layer formed on two sides of the second side wall layer 111 can be reduced, so that parasitic capacitance is reduced, and the electrical performance of the transistor structure is improved.
Specifically, the materials of the second sidewall layer 111 include: siON, siBCN, siCN carbon doped SiN or oxygen doped SiN. In this embodiment, the material of the second sidewall layer 111 includes SiN doped with carbon or SiN doped with oxygen.
In the step of forming the second sidewall layer 111, the lateral dimension of the second sidewall layer 111 is preferably not larger than or smaller than the lateral dimension of the first sidewall layer 110. If the lateral dimension of the second sidewall layer 111 is too large compared to the lateral dimension of the first sidewall layer 110, and correspondingly, the lateral dimension of the gate structure 118 between the second sidewall layers 111 in the second region II is too small, and when the semiconductor structure is in operation, the gate structure 118 in the second device region II has poor control capability on the channel, resulting in poor performance of the second device region II. If the lateral dimension of the second sidewall layer 111 is too small compared to the lateral dimension of the first sidewall layer 110, the lateral dimension of the gate structure 118 between the second sidewall layers 111 in the second device region II is correspondingly small compared to the lateral dimension of the gate structure 118 between the first sidewall layers 110 in the first device region I, that is, the lateral dimension of the gate structure 118 between the second sidewall layers 111 in the second device region II is too large, and when the semiconductor structure works, the channel length in the second device region II is small, resulting in larger on-current, larger power consumption and larger leakage probability of the second transistor formed in the second device region. In this embodiment, in the step of forming the second sidewall layer 111, the lateral dimension of the second sidewall layer 111 is 1 nm to 5 nm larger than the lateral dimension of the first sidewall layer 110.
The second sidewall layer 111 is located on the topmost channel layer 102, between the channel layers 102, and between the channel layers 102 and the substrate 100.
Specifically, the space between the channel layer 102 and the substrate 100 refers to the space between the channel layer 102 and the fin 112.
In this embodiment, in the second region II, the lateral contact dimension between the gate structure 118 and the top surface of the topmost channel layer 102 is a first dimension, the lateral contact dimension between the gate structure 118 and the bottommost channel layer 102 is a second dimension, and the first dimension is equal to the second dimension.
The lateral dimension of the top surface of the channel layer 102 in the second region II, which is exposed at the top, is equal to the lateral dimension of any one surface of the remaining channel layers 102 in the second region II, and the areas of the corresponding channel layers 102 in the second region II covered by the gate structure are the same.
The semiconductor structure further includes: an interlayer dielectric layer 115 is located on the substrate 100 at a side portion of the gate structure 118, and a top surface of the interlayer dielectric layer 115 is flush with a top surface of the gate structure 118.
Interlayer dielectric layer 115 is used to electrically isolate adjacent devices.
In this embodiment, the material of the interlayer dielectric layer 115 is an insulating material. The material of the interlayer dielectric layer 115 specifically includes silicon oxide. Silicon oxide is a dielectric material with common process and low cost, and has high process compatibility, which is beneficial to reducing the process difficulty and the process cost for forming the interlayer dielectric layer 115.
It should be noted that the semiconductor structure further includes: and a gate sidewall layer 105 positioned between the gate structure 118 and the interlayer dielectric layer 115.
During the formation of the semiconductor structure, the gate sidewall layer 105 is used to define a formation location of the gate structure 118.
The materials of the gate sidewall layer 105 include: one or more of silicon nitride, silicon oxynitride, silicon carbide nitride, boron nitride silicon and boron carbon nitride silicon.
The second sidewall layer 111 located on the topmost channel layer 102 is formed between the topmost channel layer 102 and the gate sidewall layer 105.
Correspondingly, the embodiment of the invention also provides a second semiconductor structure. Referring to fig. 14, the present embodiment is the same as the first embodiment, and the difference is that:
The second sidewall layer 211 is located between the channel layers 202 and the substrate 200.
Specifically, the space between the channel layer 202 and the substrate 200 refers to the space between the channel layer 202 and the fin 212.
The gate structure 218 has a first dimension in lateral contact with the top surface of the topmost channel layer 202 and the gate structure 218 has a second dimension in lateral contact with the bottommost channel layer 202.
When the lateral dimension of the second sidewall layer 211 is equal to the lateral dimension of the gate sidewall layer 205, the first dimension is equal to the second dimension, and after the gate structure 218 is subsequently formed, the channel lengths of the channel layers 202 in the second region II are the same when the semiconductor structure is in operation, which is beneficial to improving uniformity of device performance.
When the lateral dimension of the second sidewall layer 211 is greater than the lateral dimension of the gate sidewall layer 205, the first dimension is smaller than the second dimension, and after the gate structure 218 is formed subsequently, when the semiconductor structure is operated, the channel length of the topmost channel layer 202 in the second region is different from the channel length of the bottom, so that the turn-on voltage of the top channel is different from the turn-on voltage of the bottom channel.
When the lateral dimension of the second sidewall layer 211 is smaller than the lateral dimension of the gate sidewall layer 205, the first dimension is larger than the second dimension, and after the gate structure 218 is formed subsequently, when the semiconductor structure is operated, the channel length of the topmost channel layer 202 in the second region is different from the channel length of the bottom, so that the turn-on voltage of the channel at the top is different from the turn-on voltage of the channel at the bottom.
It should be noted that, when the first dimension and the second dimension are different, the difference between the first dimension and the second dimension is equal to twice the difference between the lateral dimension of the second sidewall layer 211 and the first sidewall layer.
The semiconductor structure may be formed by the forming method of the foregoing embodiment, or may be formed by other forming methods. For a specific description of the semiconductor structure of the present embodiment, reference may be made to the corresponding description in the foregoing embodiment, which is not repeated here.
Although the embodiments of the present invention are disclosed above, the embodiments of the present invention are not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the embodiments of the invention, and the scope of the embodiments of the invention should be pointed out in the appended claims.
Claims (19)
1. A method of forming a semiconductor structure, comprising:
Providing a substrate, wherein the substrate comprises a substrate, a channel stack layer separated on the substrate and a pseudo gate structure crossing the channel stack layer, the pseudo gate structure covers partial top wall and partial side wall of the channel stack layer, the channel stack layer comprises sacrificial layers and channel layers which are alternately stacked, and the bottommost part of the channel stack layer is the sacrificial layer;
Etching the channel laminated layers on two sides of the pseudo gate structure, and forming a groove in the channel laminated layers;
Forming a first groove by transversely etching the sacrificial layer exposed by the groove by taking the extending direction parallel to the surface of the substrate and perpendicular to the dummy gate structure as a transverse direction;
Performing lateral etching on the sacrificial layer exposed out of the first groove in the second area to form a second groove, wherein the lateral end face of the second groove is positioned below the pseudo gate structure;
forming a side wall material layer in the first groove and the second groove, wherein the side wall material layer in the second groove is used as a second side wall layer;
removing the pseudo gate structure after the side wall material layer is formed, and forming a gate opening; after the grid electrode opening is formed, removing the sacrificial layer to form a channel, wherein the topmost second side wall layer exposes the bottom of the grid electrode opening;
forming a gate structure in the channel and gate opening;
The method for forming the semiconductor structure further comprises the following steps: forming a source-drain doped layer in the groove after forming the side wall material layer; the lateral dimension of the channel layer between the source and drain doped layers in the first region is equal to the lateral dimension between the channel layers between the source and drain doped layers in the second region.
2. The method of forming a semiconductor structure of claim 1, wherein in the step of forming the second recess, a lateral dimension of the second recess is 1 nm to 5 nm greater than a lateral dimension of the first recess.
3. The method of claim 1, wherein the first recess is formed by laterally etching the sacrificial layer exposed by the trench using a wet etching process.
4. The method of claim 1, wherein the sacrificial layer exposed by the first recess in the second region is laterally etched using a wet etching process to form a second recess.
5. The method of forming a semiconductor structure of claim 1, wherein the step of forming the second recess comprises:
Forming a shielding layer covering a first groove of the first region and exposing the first groove of the second region;
using the shielding layer as a mask to transversely etch the sacrificial layer exposed out of the first groove in the second area to form a second groove;
the method for forming the semiconductor structure further comprises the following steps: and removing the shielding layer after the second groove is formed.
6. The method of claim 5, wherein the material of the masking layer comprises one or more of BARC material, SOC material, ODL material, photoresist, DARC material, DUO material, or APF material.
7. The method of claim 1, wherein the sidewall material layer is a low K dielectric material.
8. The method of forming a semiconductor structure of claim 7, wherein the material of the sidewall material layer comprises: siON, siBCN, siCN carbon doped SiN or oxygen doped SiN.
9. The method for forming a semiconductor structure according to claim 1, wherein the method for forming a sidewall material layer comprises: forming a side wall material film which conformally covers the pseudo gate structure, the groove, the first groove and the second groove; and removing the side wall material films at the bottom and the side wall of the groove and the side wall of the pseudo gate structure, and taking the remaining side wall material films in the first groove and the second groove as the side wall material layers.
10. The method of claim 9, wherein the sidewall material film is formed by an atomic layer deposition process or a chemical vapor deposition process.
11. The method of forming a semiconductor structure of claim 1, wherein in the step of providing a substrate, a topmost layer of the channel stack is a sacrificial layer;
or the topmost layer of the channel stack is a channel layer.
12. The method of forming a semiconductor structure of claim 1, wherein in the step of providing a substrate, the substrate further comprises: the fin part is raised on the substrate and is positioned between the substrate and the channel lamination layer;
the isolation layer is positioned on the substrate exposed out of the fin part and covers part of the side wall of the fin part;
The dummy gate structure is located on the isolation layer, stretches across the fin portion and covers part of the top wall and part of the side wall of the fin portion.
13. A semiconductor structure, comprising:
a substrate comprising a first region and a second region;
The source-drain doped layer is separated on the substrate;
A plurality of channel layers suspended on the substrate at intervals in a direction normal to the surface of the substrate, the plurality of channel layers being located between the source-drain doped layers, a lateral dimension of the channel layers between the source-drain doped layers in the first region being equal to a lateral dimension between the channel layers between the source-drain doped layers in the second region;
a gate structure surrounding the channel layer so as to be parallel to a substrate surface and perpendicular to an extension direction of the gate structure;
the first side wall layer is positioned between the source-drain doped layer and the grid structure in the first region;
The second side wall layer is positioned between the source-drain doping layer and the grid structure in the second region, the transverse size of the second side wall layer is larger than that of the first side wall layer, and the transverse end face of the second side wall is positioned right below the grid structure.
14. The semiconductor structure of claim 13, wherein a lateral dimension of the second sidewall layer is 1 nm to 5 nm greater than a lateral dimension of the first sidewall layer.
15. The semiconductor structure of claim 13, wherein the material of the second sidewall layer comprises: siON, siBCN, siCN carbon doped SiN or oxygen doped SiN.
16. The semiconductor structure of claim 13, wherein the material of the first sidewall layer comprises: siON, siBCN, siCN carbon doped SiN or oxygen doped SiN.
17. The semiconductor structure of claim 13, wherein in the second region, the second sidewall layer is located on top of the channel layer, between the channel layers, and between the channel layer and the substrate.
18. The semiconductor structure of claim 13, wherein the second sidewall layer is located between the channel layers and the substrate.
19. The semiconductor structure of claim 13, wherein the semiconductor structure further comprises: a fin located between the substrate and the plurality of channel layers;
The isolation layer is positioned on the substrate at the side part of the fin part and covers part of the side wall of the fin part;
And the grid structure stretches across the fin part and covers part of the top wall and part of the side wall of the fin part on the isolation layer.
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