CN114551356A - Semiconductor structure, forming method thereof and SRAM device - Google Patents

Semiconductor structure, forming method thereof and SRAM device Download PDF

Info

Publication number
CN114551356A
CN114551356A CN202011340562.2A CN202011340562A CN114551356A CN 114551356 A CN114551356 A CN 114551356A CN 202011340562 A CN202011340562 A CN 202011340562A CN 114551356 A CN114551356 A CN 114551356A
Authority
CN
China
Prior art keywords
channel
layer
region
layers
semiconductor structure
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202011340562.2A
Other languages
Chinese (zh)
Inventor
王楠
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
Original Assignee
Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Semiconductor Manufacturing International Shanghai Corp, Semiconductor Manufacturing International Beijing Corp filed Critical Semiconductor Manufacturing International Shanghai Corp
Priority to CN202011340562.2A priority Critical patent/CN114551356A/en
Publication of CN114551356A publication Critical patent/CN114551356A/en
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823821—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0924—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B10/00—Static random access memory [SRAM] devices
    • H10B10/12—Static random access memory [SRAM] devices comprising a MOSFET load element

Abstract

A semiconductor structure, a forming method thereof and an SRAM device are provided, wherein the forming method comprises the following steps: providing a substrate, wherein the substrate comprises a substrate, a plurality of channel lamination layers separated on the substrate and a pseudo gate structure crossing the channel lamination layers, the pseudo gate structure covers partial top walls and partial side walls of the channel lamination layers, and the channel lamination layers comprise sacrificial layers and channel layers positioned on the sacrificial layers; forming an interlayer dielectric layer which covers the side wall of the pseudo gate structure and exposes the top of the pseudo gate structure; removing the pseudo gate structure, and forming a gate opening in the interlayer dielectric layer; removing the one or more channel layers on top of the channel stack; removing the sacrificial layer to form a channel; a gate structure is formed in the gate opening and the channel. According to the embodiment of the invention, one or more channel layers on the top of the channel lamination are removed, so that the number of the channel layers in the semiconductor structure is reduced, and further, when the semiconductor structure works, the whole conduction current of the channel of the semiconductor structure is reduced, so that the semiconductor structure can meet the process requirements.

Description

Semiconductor structure, forming method thereof and SRAM (static random Access memory) device
Technical Field
The embodiment of the invention relates to the field of semiconductor manufacturing, in particular to a semiconductor structure, a forming method of the semiconductor structure and an SRAM device.
Background
In Semiconductor manufacturing, with the trend of ultra-large scale integrated circuits, the feature size of the integrated circuit is continuously reduced, and in order to adapt to smaller feature sizes, the channel length of a Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) is also continuously shortened correspondingly. However, as the channel length of the device is shortened, the distance between the source and the drain of the device is also shortened, so the controllability of the gate structure to the channel is deteriorated, and the difficulty of the gate voltage to pinch off the channel is increased, so that the sub-threshold leakage (SCE) phenomenon, i.e. the so-called short-channel effect (SCE), is more likely to occur.
Therefore, in order to better accommodate the scaling requirements of device dimensions, semiconductor processes are gradually starting to transition from planar transistors to more power efficient three-dimensional transistors, such as Gate-all-around (GAA) transistors. In the fully-surrounded metal gate transistor, the gate surrounds the region where the channel is located from the periphery, and compared with a planar transistor, the fully-surrounded metal gate transistor has stronger control capability on the channel by the gate, and can better inhibit a short-channel effect.
The gate structures in the all-around gate transistor are generally formed by a self-aligned dual patterning process (SADP) or a self-aligned quad patterning process (SAQP), and in an extending direction perpendicular to the gate structures, the lateral dimensions of the gate structures are the same, and the lengths of channels below the corresponding gate structures are the same.
Disclosure of Invention
Embodiments of the present invention provide a semiconductor structure, a method for forming the same, and an SRAM device, where the overall on-current of a channel of the semiconductor structure is reduced, so that the semiconductor structure can meet process requirements.
To solve the above problems, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate, wherein the substrate comprises a substrate, a plurality of channel lamination layers separated from the substrate and a pseudo gate structure crossing the plurality of channel lamination layers, the pseudo gate structure covers partial top walls and partial side walls of the channel lamination layers, and the channel lamination layers comprise sacrificial layers and channel layers located on the sacrificial layers; forming an interlayer dielectric layer which covers the side wall of the pseudo gate structure and exposes the top of the pseudo gate structure; removing the pseudo gate structure, and forming a gate opening in the interlayer dielectric layer; removing one or more of the channel layers atop the channel stack; removing the sacrificial layer between the remaining channel layers to form a channel after removing one or more of the channel layers on the top of the channel stack; and forming a gate structure in the gate opening and the channel.
Correspondingly, an embodiment of the present invention further provides a semiconductor structure, including: a substrate comprising a first region and a second region; the plurality of channel layers are suspended on the substrate at intervals in the normal direction of the surface of the substrate, and the number of the channel layers in the second area is less than that of the channel layers in the first area; a gate structure surrounding the channel layer; the grid side wall layer is positioned on the side wall which is higher than the channel layer and close to the top of the grid structure; one or more end channel layers between the gate sidewall layer and the topmost channel layer of the second region.
Correspondingly, an embodiment of the present invention further provides an SRAM device, including a semiconductor structure, where the semiconductor structure includes: a substrate comprising a first region and a second region; the plurality of channel layers are suspended on the substrate at intervals in the normal direction of the surface of the substrate, and the number of the channel layers in the second area is less than that of the channel layers in the first area; a gate structure surrounding the channel layer; the grid side wall layer is positioned on the side wall of the grid structure at the top of the channel layer; one or more end channel layers between the gate sidewall layer and the topmost channel layer of the second region; the method comprises the following steps: the first region includes a pull-down transistor; the second region includes a pass gate transistor or a pull-up transistor.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following advantages:
in the method for forming the semiconductor structure provided by the embodiment of the invention, the dummy gate structure is removed, the gate opening is formed in the interlayer dielectric layer, the gate opening exposes a plurality of channel laminations, and one or more channel layers at the top of the channel laminations are removed, so that the number of the channel layers in the semiconductor structure is reduced, and when the semiconductor structure works, the whole conduction current of the channel of the semiconductor structure is reduced, so that the semiconductor structure can meet the process requirement; in addition, the sacrificial layer between the rest channel layers is removed to form a channel, a gate structure is formed in the gate opening and the channel, the forming space of the gate structure is larger, the number of the channel layers which need to be controlled by the gate structure is reduced, correspondingly, when the semiconductor structure works, the control capability of the gate structure on the rest channel layers is enhanced, the probability of channel leakage current is favorably reduced, and the electrical performance of the semiconductor structure is improved.
In the SRAM device provided in the embodiment of the present invention, the first region includes a pull-down transistor; the second area comprises transmission gate transistors or pull-up transistors, the number of the channel layers of the pull-down transistors is more than that of the channel layers of the transmission gate transistors or the pull-up transistors, and when a corresponding SRAM device works, the conduction current of the pull-down transistors is larger than that of the transmission gate transistors or the pull-up transistors, so that when the SRAM device works, the stability of the SRAM device is high and the SRAM device is not easily interfered. Specifically, the conduction current of the pull-down transistor is larger than that of the transmission gate transistor, so that the reading stability of the SRAM device is improved; the conducting current of the pull-down transistor is larger than that of the pull-up transistor, so that the writing speed of the SRAM device is improved.
Drawings
Fig. 1 to 3 are schematic structural diagrams of key steps in a method for forming a semiconductor structure;
FIGS. 4 and 5 are schematic structural views of key steps in another method of forming a semiconductor structure;
fig. 6 to 19 are schematic structural diagrams corresponding to steps in a method for forming a semiconductor structure according to an embodiment of the invention.
Detailed Description
As can be seen from the background art, the performance of the devices formed at present is still not good. The reason for the poor performance of the device is analyzed in combination with a method for forming a semiconductor structure.
Referring to fig. 1 to fig. 3, schematic structural diagrams of key steps in a method for forming a semiconductor structure are shown.
As shown in fig. 1, providing a base, the base including a first device region I and a second device region II, the base including a substrate 1 and a channel stack 2 on the substrate 1, the channel stack 2 including a sacrificial layer 21 and a channel layer 22 on the sacrificial layer 21; the pseudo gate structure 4 spans the channel stack 2, and the pseudo gate structure 4 covers part of the top wall and part of the side wall of the channel stack 2, and the extending direction which is parallel to the surface of the substrate 1 and vertical to the pseudo gate structure 4 is transverse; the source-drain doping layer 30 is positioned in the channel laminated layer 2 on two sides of the pseudo gate structure 4; the inner side wall layer 7 is positioned between the sacrificial layer 21 and the source drain doping layer 30; and the interlayer dielectric layer 6 is positioned on the side part of the dummy gate structure 4, and the top surface of the interlayer dielectric layer 6 is flush with the top surface of the dummy gate structure 4.
As shown in fig. 2, removing the dummy gate structure 4 to form a gate opening 5; after the gate opening 5 is formed, the sacrificial layer 21 is removed, and a first channel 8 surrounded by the substrate 1, the channel layer 22, and the inner sidewall layer 7, and a second channel 9 surrounded by the channel layer 22 and the inner sidewall layer 7 are formed.
As shown in fig. 3, a gate structure 10 is formed in the gate opening 5, the first channel 8 and the second channel 9.
Semiconductor technology gradually starts to transition from a planar transistor to a three-dimensional transistor with higher efficiency, such as a Gate-all-around (GAA) transistor, and the Gate of the GAA transistor has stronger channel control capability, so that short channel effect can be better suppressed. Usually, the dummy gate structures 4 in the first device region I and the second device region II are formed by a self-aligned dual patterning process (SADP), the lateral dimensions of the dummy gate structures 4 in the first device region I and the dummy gate structures 4 in the second device region II are the same, the lateral dimension of the channel layer 22 in the first device region I is the same as the lateral dimension of the channel layer 22 in the second device region II, and when the semiconductor structure operates, the total sum of the on-currents in the channels of the first device region I is the same as the total sum of the on-currents in the channels of the second device region II, which cannot meet the requirement that the total on-currents in the channels of the first device region I and the second device region II are inconsistent, that is, the requirement that the semiconductor structure has diversified electrical properties.
Referring to fig. 4 and 5, the structure of a key step in another method for forming a semiconductor structure is schematically illustrated.
The forming method of the semiconductor structure is different from the forming method of the former semiconductor structure in that:
as shown in fig. 4, the number of channel stacks 20 of the first region I is greater than the number of channel stacks 20 of the second region II.
As shown in fig. 5, source-drain doped layers 30 are formed in the channel stack 20 on both sides of the dummy gate structure 40.
The number of the channel stacks 20 of the first region I is greater than that of the channel stacks 20 of the second region II, so that after the dummy gate structure 40 is replaced with the gate structure, the number of the channel layers 22 of the first region I is greater than that of the channel layers of the second region II, and when the semiconductor structure operates, the total current of the channels of the first region I is greater than that of the channels of the second region II.
The step of forming the source drain doping layer 30 includes: grooves (not shown in the figure) are formed in the channel laminated layer 20 at two sides of the dummy gate structure 40, the depth of the groove in the first region I is greater than that of the groove in the second region II, a selective epitaxial growth process (SEG) is usually adopted to form a source-drain doped layer 30 in the groove, the side wall and the bottom surface of the groove provide an interface for selective epitaxial growth, accordingly, the thickness of the source-drain doped layer 30 of the dummy gate structure 40 in the first region I is greater than that of the source-drain doped layer 30 formed at two sides of the dummy gate structure 40, the stress of the source-drain doped layer 30 of the first region I to the groove is greater than that of the source-drain doped layer 30 of the second region II to the groove, and the uniformity of the semiconductor structure is different.
In order to solve the technical problem, in the method for forming the semiconductor structure provided by the embodiment of the invention, the dummy gate structure is removed, the gate opening is formed in the interlayer dielectric layer, the gate opening exposes a plurality of channel stacks, and one or more channel layers on the top of the channel stacks are removed, so that the number of the channel layers in the semiconductor structure is reduced, and when the semiconductor structure works, the whole on-state current of the channel of the semiconductor structure is reduced, so that the semiconductor structure can meet the process requirement; in addition, the sacrificial layer between the rest channel layers is removed to form a channel, a gate structure is formed in the gate opening and the channel, the forming space of the gate structure is larger, the number of the channel layers which need to be controlled by the gate structure is reduced, correspondingly, when the semiconductor structure works, the control capability of the gate structure on the rest channel layers is enhanced, the probability of channel leakage current is favorably reduced, and the electrical performance of the semiconductor structure is improved.
In the SRAM device provided in the embodiment of the present invention, the first region includes a pull-down transistor; the second region comprises transmission gate transistors or pull-up transistors, the number of the channel layers of the pull-down transistors is more than that of the channel layers of the transmission gate transistors or the pull-up transistors, and when the corresponding SRAM device works, the conducting current of the pull-down transistors is larger than that of the transmission gate transistors or the pull-up transistors, so that when the SRAM device works, the stability of the SRAM device is high, and the SRAM device is not easily interfered. Specifically, the conduction current of the pull-down transistor is larger than that of the transmission gate transistor, so that the reading stability of the SRAM device is improved; the conducting current of the pull-down transistor is larger than that of the pull-up transistor, so that the writing speed of the SRAM device is improved.
In order to make the aforementioned objects, features and advantages of the embodiments of the present invention comprehensible, specific embodiments accompanied with figures are described in detail below.
Fig. 6 to 19 are schematic structural diagrams corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention.
Referring to fig. 6 and 7, fig. 7 is a cross-sectional view of fig. 6 in the direction AA, and provides a base including a substrate 100, a plurality of channel stacks 300 separated from the substrate 100, and a dummy gate structure 103 crossing the plurality of channel stacks 300, where the dummy gate structure 103 covers a part of the top wall and a part of the sidewall of the channel stack 300, and the channel stack 300 includes a sacrificial layer 101 and a channel layer 102 on the sacrificial layer 101.
The substrate 100 is used to provide a process platform for subsequently forming semiconductor structures.
In this embodiment, the substrate 100 is a silicon substrate. In other embodiments, the material of the substrate may also be other materials such as germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, and the substrate may also be another type of substrate such as a silicon-on-insulator substrate or a germanium-on-insulator substrate.
In this embodiment, in the step of providing a substrate, the substrate includes a first region I and a second region II.
In this embodiment, the first region I is used to form an nmos (negative Channel Metal Oxide semiconductor), such as a Pull-down transistor (PD), and the second region II is used to form a pmos (positive Channel Metal Oxide semiconductor), such as a transfer gate transistor (PG) or a Pull-up transistor (PU).
In the present embodiment, the method for forming a semiconductor structure is used to form a semiconductor structure in which the total on-current of channels of transistors formed in the first region I is greater than the total on-current of transistors formed in the second region II, that is, the number of channel layers 102 formed in the first region I is greater than the number of channel layers 102 formed in the second region II.
Channel stack 300 is used to provide a process foundation for the subsequent formation of suspended channel layer 102. The sacrificial layer 101 is used to support the channel layer 102, provide process conditions for the spacer-floating arrangement of the subsequent channel layer 102, and also occupy space for the subsequently formed gate structure.
In this embodiment, the difficulty of etching the channel layer 102 is greater than the difficulty of etching the sacrificial layer 101, and the channel layer 102 is not easily damaged when the sacrificial layer 101 is subsequently removed.
Specifically, the material of the channel layer 102 includes: one or more of silicon, germanium, silicon carbide, gallium arsenide, and indium gallium. In this embodiment, the material of the channel layer 102 is silicon.
Specifically, the material of the sacrificial layer 101 includes one or both of silicon germanium and silicon. In this embodiment, the sacrificial layer 101 is made of silicon germanium.
The dummy gate structure 103 occupies a space for forming a gate structure in a subsequent process.
In this embodiment, the lateral dimension of the dummy gate structure 103 in the second region II is smaller than the lateral dimension of the dummy gate structure 103 in the first region I, source-drain doping layers are subsequently formed in the channel lamination layers on both sides of the dummy gate structure 103, and the channel layer between the source-drain doping layers serves as a channel when the semiconductor structure operates, so that the lateral dimension of the channel in the semiconductor structure is limited by the lateral dimension of the dummy gate structure 103. The dummy gate structure 103 is replaced by a gate structure, and the lateral dimension of the gate structure in the second region II is smaller than that of the gate structure in the first region I. The lateral dimension of the channel layer 102 under the gate structure of the corresponding second region II is smaller than the lateral dimension of the channel layer 102 under the gate structure of the first region I, and when the semiconductor structure is in operation, the on-current of the channel in the second region II is smaller than the on-current of the channel in the first region I.
In the step of providing the base, the ratio of the lateral dimension of the dummy gate structure 103 in the second region II to the lateral dimension of the dummy gate structure 103 in the first region I is not too large or too small, taking the extending direction parallel to the surface of the substrate 100 and perpendicular to the dummy gate structure 103 as the lateral direction. Generally, the semiconductor structure is used for forming an SRAM device, specifically, the first region I is used for forming a pull-down transistor, and the second region II is used for forming a pass-gate transistor or a pull-up transistor, if the ratio is too large, when the semiconductor structure is in operation, the conduction current of the channel in the second region II is caused to be approximately the same as the conduction current in the first region I, and the reading stability and the writing rate of the SRAM device cannot be significantly improved. If the ratio is too small, the on-current of the channel in the second region II is too small compared to the on-current in the first region I during operation of the semiconductor structure, i.e., the on-current of the pass-gate transistor is too small, which may limit the read and write rates of the SRAM device. In this embodiment, in the step of providing the base, the extending direction parallel to the surface of the substrate 100 and perpendicular to the dummy gate structure 103 is a lateral direction, and the lateral dimension of the dummy gate structure 103 in the second region II is 55% to 95% of the lateral dimension of the dummy gate structure 103 in the first region I.
In this embodiment, the dummy gate structure 103 includes a dummy gate oxide 1031 conformally covering a portion of the top surface and a portion of the sidewalls of the channel stack and a dummy gate layer 1032 located on the dummy gate oxide 1031.
In this embodiment, the material of the dummy gate oxide 1031 is silicon oxide. In other embodiments, the material of the dummy gate oxide layer may also be silicon oxynitride.
In this embodiment, the material of the dummy gate layer 1032 is polysilicon. In other embodiments, the material of the dummy gate layer may also be amorphous carbon.
The step of forming the dummy gate structure 103 includes: forming a dummy gate oxide material layer (not shown) covering the channel stack and a dummy gate material layer (not shown) on the dummy gate oxide layer; forming a gate mask layer 104 on the dummy gate material layer; and etching the pseudo gate oxide material layer and the pseudo gate oxide material layer by taking the gate mask layer 104 as a mask, wherein the residual pseudo gate oxide material layer is taken as the pseudo gate oxide 1031, and the residual pseudo gate material layer is taken as the pseudo gate layer 1032.
It should be noted that, taking the extending direction parallel to the surface of the substrate 100 and perpendicular to the dummy gate structure 103 as a lateral direction, in this embodiment, the dummy gate structure 103 in the first region I and the second region II is formed by a self-aligned dual patterning process (SADP) or a self-aligned quadruple patterning process (SAQP), and the lateral dimensions of the dummy gate structure 103 in the first region I and the second region II are the same, which simplifies the forming process of the dummy gate structure 103 and is beneficial to improving the forming efficiency of the dummy gate structure 103.
In the step of providing the substrate, a gate sidewall layer 105 is formed on the sidewall of the dummy gate structure 103.
The gate sidewall layer 105 is used for defining a formation position of a source-drain doping layer formed subsequently, and is also used for protecting a sidewall of the dummy gate structure 103 from being damaged in a formation process of a subsequent semiconductor structure.
The material of the gate sidewall layer 105 includes: one or more of silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, boron nitride boron silicon nitride, and boron nitride silicon carbide.
It should be further noted that in the step of providing a substrate, the substrate further includes: a fin 112 protruding from the substrate 100, wherein the fin 112 is located between the substrate 100 and the channel stack; an isolation layer 113 on the substrate 100 where the fin 112 is exposed. The dummy gate structure 103 is located on the isolation layer 113.
The fin 112 protrudes from the substrate 100, and the side of the fin 112 provides a process space for the isolation layer 113.
In this embodiment, the material of the fin portion 112 is the same as that of the substrate 100. In other embodiments, the material of the fin may also be different from the material of the substrate.
The isolation layer 113 electrically isolates a gate structure formed by the replacement dummy gate structure 113 from the substrate 100, and the isolation layer 113 is used for further electrically isolating the fins 112.
In this embodiment, the isolation layer 113 is made of a dielectric material. Specifically, the isolation layer 113 includes silicon oxide, which is a dielectric material with a common process and a low cost, and has a high process compatibility, thereby facilitating reduction of process difficulty and process cost for forming the isolation layer 113.
Correspondingly, the dummy gate structure 103 is located on the isolation layer 113, and the dummy gate structure 103 crosses over the fin portion 112 and covers a part of the top wall and a part of the sidewall of the fin portion 112.
Referring to fig. 8 and 9, an interlayer dielectric layer 115 (shown in fig. 9) covering the sidewalls of the dummy gate structure 103 and exposing the top of the dummy gate structure 103 is formed.
Interlevel dielectric layer 115 is used to electrically isolate adjacent devices. In addition, the interlayer dielectric layer 115 provides a process space for the subsequent formation of a gate opening.
In this embodiment, the interlayer dielectric layer 115 is made of an insulating material. Specifically, the material of the interlayer dielectric layer 115 includes silicon oxide.
It should be noted that, in the process of forming the interlayer dielectric layer 115, the gate mask layer 104 is removed.
As shown in fig. 8, the method for forming the semiconductor structure further includes: after providing a substrate, before forming the interlayer dielectric layer 115, etching the channel stack 300 on both sides of the dummy gate structure 103, and forming a trench 106 in the channel stack 300.
The trench 106 provides a process space for the subsequent formation of a source-drain doped layer.
In this embodiment, the gate mask layer 104 is used as a mask, and a dry etching process is used to etch the channel stack 300 on both sides of the dummy gate structure 103, so as to form the trench 106. The dry etching process has anisotropic etching characteristics and good etching profile controllability, is beneficial to enabling the appearance of the groove 106 to meet the process requirements, and can reduce the damage to other film layer structures by taking the top of the fin portion 112 as an etching stop position in the process of forming the groove 106 by adopting the dry etching process. Moreover, by replacing the etching gas, the sacrificial layer 101 and the channel layer 102 can be etched in the same etching apparatus, which is beneficial to increasing the formation rate of the trench 106.
In other embodiments, a wet etching process or a dry and wet combined etching process may be used to etch the channel stack layers on both sides of the dummy gate structure to form a trench.
It should be noted that the lateral dimensions of the dummy gate structures 103 in the first region I and the second region II are the same, and correspondingly, after the trenches are formed, the lateral dimensions of the channel layers at the bottoms of the gate structures in the first region I and the second region II are the same.
It should be noted that, in this embodiment, the first region I and the second region II share the source-drain doping layer, and the types of the doping ions of the corresponding source-drain doping layers are the same. In other embodiments, the source drain doping layers of the first region and the second region are independent from each other, and the types of the doped ions of the source drain doping layers may be different.
It should be noted that, source-drain doping layers are formed in the trench 106 subsequently, and when the semiconductor structure operates, the channel layer between the source-drain doping layers serves as a channel, so that the lateral dimension of the dummy gate structure 103 defines the lateral dimension of the channel in the semiconductor structure, and therefore the lateral dimension of the channel layer 102 in the second region II is 55% to 95% of the lateral dimension of the channel layer 102 in the first region I.
And subsequently, the dummy gate structure 103 is replaced by a gate structure, the lateral dimension of the channel layer 102 in the second region II is smaller than that of the channel layer 102 under the gate structure in the first region I, and when the semiconductor structure works, the on-state current of the channel in the second region II is smaller than that of the channel in the first region I.
The method for forming the semiconductor structure further comprises the following steps: after the trench 106 is formed and before the source-drain doping layer is formed, the sacrificial layer 101 exposed out of the trench 106 is laterally etched to form a sidewall groove (not shown in the figure); an inner sidewall layer 110 is formed in the sidewall recess.
The sidewall recesses of the first region I provide a process space for forming the inner sidewall layer 110.
In this embodiment, the sacrificial layer 101 exposed by the trench 106 is laterally etched by using a wet etching process to form the sidewall recess. The wet etching process is isotropic etching, has high etching rate, and is simple to operate and low in process cost. In other embodiments, the sacrificial layer exposed by the trench may be laterally etched by an isotropic dry etching process to form the sidewall recess.
In this embodiment, the sacrificial layer 101 is made of silicon germanium, and correspondingly, in the process of laterally etching the sacrificial layer 101 exposed by the trench 106 by using a wet etching process, the wet etching solution used in the process includes an HCl solution.
The inner sidewall layer 110 is used for reducing the capacitance coupling effect between the source-drain doping layer and the gate structure formed subsequently, so as to reduce the parasitic capacitance and improve the electrical performance of the transistor structure.
In this embodiment, the material of the inner sidewall layer 110 is a low-K dielectric material. A low-k dielectric material (a low-k dielectric material refers to a dielectric material having a relative dielectric constant of 2.6 or more and 3.9 or less). The low-K dielectric material has excellent insulating property, reduces the electrical coupling effect between the gate structure and the source-drain doping layer which are formed at two sides of the inner side wall layer 110 subsequently, further reduces the parasitic capacitance and improves the electrical property of the transistor structure.
Specifically, the material of the inner side wall layer 110 includes: SiON, SiBCN, SiCN, carbon doped SiN or oxygen doped SiN. In this embodiment, the material of the inner sidewall layer 110 includes carbon-doped SiN or oxygen-doped SiN.
The forming method of the inner side wall layer 110 includes: forming a side wall material film (not shown in the figure) which conformally covers the dummy gate structure 103, the trench 106 and the side wall groove; and removing the side wall material film at the bottom of the groove 106 and on the side wall of the pseudo gate structure 103, and using the remaining side wall material layer positioned in the side wall groove as an inner side wall layer 110.
In this embodiment, the sidewall material film is formed by an Atomic Layer Deposition (ALD) process. The atomic layer deposition process refers to a deposition process in which a vapor phase precursor is alternately pulsed into a reaction chamber to chemisorb and cause a surface reaction on a substrate to be deposited. Through an atomic layer deposition process, the side wall material film is formed on the surfaces of the pseudo gate structure 103, the groove 106 and the side wall groove in an atomic layer mode, so that the uniformity of the deposition rate, the thickness uniformity of the side wall material film and the structural uniformity in the side wall material film are improved, and the side wall material film has good covering capability; in addition, the process temperature of the atomic layer deposition process is generally lower, so that the Thermal Budget (Thermal Budget) is favorably reduced, and the probability of performance deviation of the semiconductor structure is reduced.
As shown in fig. 9, a source-drain doped layer 114 is formed in the trench 106.
When the semiconductor structure is in operation, the source-drain doped layer 114 is used to provide stress to the channel, thereby increasing the mobility rate of carriers in the channel.
In this embodiment, the first region I is used to form an NMOS, and the source-drain doped layer 114 is used as a source and a drain of the NMOS. When the semiconductor structure works, the source-drain doped layer 114 applies tensile stress to a channel below the gate structure, and the channel is stretched to improve the migration rate of electrons. The material of the source-drain doped layer 114 of the first region I includes: silicon carbide or silicon phosphide doped with N-type ions. The N-type ions include one or more of P, As and Sb.
The second region II is used to form a PMOS, and the source-drain doped layer 114 of the second region II is used to serve as a source and a drain of the PMOS. When the semiconductor structure works, the source-drain doped layers apply compressive stress to the channel below the gate structure, and the compressed channel can improve the mobility of holes. The material of the source-drain doped layer 114 of the second region II includes: silicon germanium doped with P-type ions. The P-type ions include one or more of B, Ga and In.
Referring to fig. 10 to 12, fig. 11 is a cross-sectional view at BB of fig. 10, and fig. 12 is a cross-sectional view at CC of fig. 10, wherein the dummy gate structure 103 is removed, and a gate opening 116 is formed in the interlayer dielectric layer 115.
The gate opening 116 provides a process space for the subsequent formation of a gate structure.
In this embodiment, the dummy gate structure 103 is removed by a wet etching process. The wet etching process has the advantages of high etching rate, simple operation and low process cost.
In this embodiment, the dummy gate structure 103 includes a dummy gate oxide 1031 and a dummy gate layer 1032. The material of the dummy gate oxide 1031 is silicon oxide, and the material of the dummy gate layer 1032 is polysilicon. Specifically, in the step of removing the dummy gate structure 103, the etching solution used includes ammonia water and a tetramethylammonium hydroxide solution.
It should be noted that the lateral dimension of the gate opening 116 of the second region II is smaller than the lateral dimension of the gate opening 116 of the first region I. Accordingly, the lateral dimension of the gate structure of the gate opening 116 subsequently formed in the second region II is smaller than the lateral dimension of the gate structure of the gate opening 116 in the first region I.
Referring to fig. 13-15, fig. 15 is a cross-sectional view at CC of fig. 14, with one or more of the channel layers 102 on top of the channel stack 300 removed.
In the embodiment of the present invention, one or more of the channel layers 102 on the top of the channel stack 300 are removed, so that the number of the channel layers 102 in the semiconductor structure is reduced, and further, when the semiconductor structure works, the overall on-state current of the channel of the semiconductor structure is reduced, so that the semiconductor structure can meet the process requirements. Subsequently, the sacrificial layer 101 between the remaining channel layers 102 is removed to form a channel, a gate structure is formed in the gate opening and the channel, the forming space of the gate structure is larger, the number of the channel layers 102 to be controlled by the gate structure is reduced, and when the semiconductor structure works, the control capability of the gate structure on the remaining channel layers 102 is enhanced, which is beneficial to reducing the probability of channel leakage current and improving the electrical performance of the semiconductor structure.
In the step of removing one or more of the channel layers 102 on top of the channel stack 300, one or more of the channel layers 102 of the second region II are removed. Accordingly, the number of channel layers 102 remaining in the second region II is less than the number of channel layers 102 in the first region I, so that the overall on-current of the channel of the second region II is less than the overall on-current of the channel of the first region I.
It should be noted that after removing one or more of the channel layers 102 on the top of the channel stack 300, the remaining channel layers 102 on the bottom of the gate sidewall layer 105 are used as end channel layers 119.
In this embodiment, the step of removing one or more of the channel layers 102 in the second region II includes: forming a mask layer 109 covering the first region I and exposing the second region II; and removing one or more channel layers 102 in the second region II by using the mask layer 109 as a mask.
The mask layer 109 is a material that is easy to remove, and damage to the formed film layer can be reduced when the mask layer 109 is subsequently removed.
In this embodiment, the material of the mask layer 109 includes: a layer of organic material (not shown), an anti-reflective coating (not shown) on the layer of organic material, and a photoresist layer (not shown) on the anti-reflective coating.
The organic material layer includes: one or more of a SOC (spin on carbon) material, an ODL (organic dielectric layer) material, a DUO material, or an APF (Advanced Patterning Film) material.
The anti-reflective coating includes: a BARC (bottom-reflective coating) material or a DARC (dielectric anti-reflective coating) material.
In this embodiment, the mask layer 109 is used as a mask, and a wet etching process is used to remove one of the channel layers 102 on the top of the channel stack 300. The wet etching process is isotropic etching, has high etching rate, and is simple to operate and low in process cost.
In this embodiment, the channel layer 101 is made of silicon, and correspondingly, in the process of laterally removing the channel layer 101 with the width of the exposed portion of the sidewall of the trench 106 by using a wet etching process, the wet etching solution used in the process includes a tetramethylammonium hydroxide solution.
It should be noted that, in the process of removing one of the channel layers 102 on the top of the channel stack 300 in the second region II by using a wet etching process, the top surface and the sidewall of the top channel layer 102 are exposed in the gate opening 116, the sidewall of the remaining channel layer 102 is exposed in the gate opening 116, and after removing the top one of the channel layers 102, the sidewall of the remaining channel layer 102 in the second region II is slightly damaged.
In other embodiments, the mask layer may be a mask, and the one or more channel layers on the top of the channel stack may be removed by using a dry etching process. In the process of the dry etching process, in the process of etching a plurality of channel layers, the channel layers and the sacrificial layers can be etched in the same etching equipment by replacing etching gas, so that the process steps are simplified. The dry etching process has anisotropic etching characteristics, the side walls of the rest channel layers are not easily damaged in the process of removing the one or more channel layers on the top of the channel lamination in the second region, the improvement of the morphology quality of the rest channel layers in the second region is facilitated, and the migration rate of carriers in the channel in the second region is high when the semiconductor structure works.
Specifically, in the process of removing one or more channel layers on the top of the channel stack by using a dry etching process, the adopted etching gas comprises CF4、CHF3Or C2F6And the like.
In other embodiments, the method of forming a semiconductor structure further comprises: and after the mask layer is formed, forming a shielding layer exposing one or more channel layers in the second region before removing the one or more channel layers on the top of the channel lamination in the second region.
The shielding layer covers the channel layer to be retained in the second region, exposing the channel layer to be removed. In the process of removing the one or more channel layers on the top of the channel lamination in the second region, the channel layer to be reserved is not easy to be damaged, the appearance quality of the residual channel layer in the second region is improved, and when the semiconductor structure works, the migration rate of carriers in the channel in the second region is high.
The blocking layer includes an organic material layer.
In other embodiments, the barrier layer is removed after removing one or more of the channel layers on top of the channel stack.
The method for forming the semiconductor structure further comprises the following steps: after removing one or more of the channel layers 101 on top of the channel stack 300, the mask layer 109 is removed.
In this embodiment, the mask layer 109 is removed by an ashing process. After removing one or more of the channel layers 101 on the top of the channel stack 300, organic materials in the mask layer 109 may be prevented from contaminating a machine, and preparation may be made for subsequent removal of the sacrificial layer 102.
Referring to fig. 16, after removing one or more of the channel layers 102 on top of the channel stack 300, the sacrificial layer 101 between the remaining channel layers 102 is removed to form a via 117.
The channel 117 and the gate opening 116 together provide a process space for the subsequent formation of a gate structure.
In this embodiment, the sacrificial layer 101 is removed by a wet etching process. The wet etching process has the advantages of high etching rate, simple operation and low process cost.
Specifically, the material of the sacrificial layer 101 is silicon germanium. Correspondingly, in the process of removing the sacrificial layer 101 by using the wet etching process, the adopted etching solution is an HCl solution.
Note that in the step of removing the sacrificial layer 101 between the remaining channel layers 102 and forming the channel 117, the sacrificial layer 101 on the top of the remaining channel layers 102 is removed.
Referring to fig. 17-19, fig. 18 is a cross-sectional view at DD of fig. 17, and fig. 19 is a cross-sectional view at EE of fig. 17, with a gate structure 118 formed in the gate opening 116 and the channel 117.
The gate structure 118 is used to control the opening and closing of the channel during operation of the semiconductor structure.
The number of the channel layers 102 in the second region II is less than that of the channel layers 102 in the first region I, so that when the semiconductor structure works, the overall on-current of the channel of the second region II is less than that of the channel of the first region I, so that the semiconductor structure can meet the process requirements; in addition, the number of the channel layers 102 in the second region II, which need to be controlled by the gate structure 118, is reduced, so that when the semiconductor structure operates, the control capability of the gate structure 118 on the remaining channel layers 102 is enhanced, which is beneficial to reducing the probability of channel leakage and improving the electrical performance of the semiconductor structure.
The gate structure 118 includes a work function layer and a gate layer over the work function layer.
Specifically, the material of the work function layer in the NMOS includes one or more of titanium aluminide, tantalum carbide, and titanium carbide. The material of the work function layer in the PMOS includes one or more of titanium nitride, tantalum nitride, titanium carbide, tantalum silicon nitride, titanium silicon nitride, and tantalum carbide.
Specifically, the material of the gate layer comprises one or more of magnesium-tungsten alloy, tungsten, copper, nickel and titanium. In this embodiment, the gate layer is made of a magnesium-tungsten alloy.
In this embodiment, the lateral dimension of the dummy gate structure 103 of the second region II is smaller than the lateral dimension of the dummy gate structure 103 of the first region I, and accordingly, the lateral dimension of the gate structure 118 of the second region II is smaller than the lateral dimension of the gate structure 118 of the first region I, and since the lateral dimension of the channel layer 102 under the gate structure 118 of the second region II is smaller than the lateral dimension of the channel layer 102 under the gate structure 118 of the first region I, when the semiconductor structure operates, the on-current of the channel in the second region II is smaller than the on-current of the channel in the first region I.
In this embodiment, the lateral dimension of the gate structure 118 in the second region II is 55% to 95% of the lateral dimension of the gate structure 118 in the first region I, taking the extending direction parallel to the surface of the substrate 100 and perpendicular to the gate structure 118 as the lateral direction.
The method for forming the semiconductor structure further comprises the following steps: a gate dielectric layer (not shown) is formed in the channel 117 and gate opening 116 before the gate structure 118 is formed.
The gate dielectric layer is used to achieve electrical isolation between the gate structure 118 and the fin 112. The gate dielectric layer is made of a high-k dielectric material. Wherein, the high-k dielectric material is a dielectric material with a relative dielectric constant larger than that of silicon oxide.
In this embodiment, the gate dielectric layer is made of HfO2. In other embodiments, the material of the gate dielectric layer may also be selected from ZrO2HfSiO, HfSiON, HfTaO, HfTiO, HfZrO or Al2O3One or more of them.
Correspondingly, the embodiment of the invention also provides a semiconductor structure. Referring to fig. 17 to 19, fig. 18 is a cross-sectional view at DD of fig. 17, and fig. 19 is a cross-sectional view at EE of fig. 17, which illustrate a schematic structural diagram of an embodiment of a semiconductor structure according to the present invention.
The semiconductor structure includes: a substrate 100, the substrate 100 comprising a first region I and a second region II; a plurality of channel layers 102, which are suspended on the substrate 100 at intervals in the normal direction of the surface of the substrate 100, and the number of the channel layers 102 in a second area II is less than that of the channel layers 102 in a first area I; a gate structure 118 surrounding the channel layer 102; a gate sidewall layer 105 on sidewalls above the channel layer 102 near the top of the gate structure 118; one or more end channel layers 119 between the gate sidewall layer 105 and the topmost channel layer 102 of the second region II.
In the semiconductor structure provided in the embodiment of the present invention, the number of the channel layers 102 in the second region II is less than the number of the channel layers 102 in the first region I, so that when the semiconductor structure operates, the overall on-current of the channel in the second region II is less than the overall on-current of the channel in the first region I, so that the semiconductor structure can meet the process requirement; in addition, the number of the channel layers 102 in the second region II, which need to be controlled by the gate structure 118, is reduced, so that when the semiconductor structure operates, the control capability of the gate structure 118 on the channel layer 102 in the second region II is stronger than that on the channel layer 102 in the first region I, which is beneficial to reducing the probability of channel leakage in the second region II and improving the electrical performance of the semiconductor structure.
The substrate 100 is used to provide a process platform for forming semiconductor structures.
In this embodiment, the substrate 100 is a silicon substrate. In other embodiments, the material of the substrate may also be other materials such as germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, and the substrate may also be another type of substrate such as a silicon-on-insulator substrate or a germanium-on-insulator substrate.
In this embodiment, the first region I is used to form an nmos (negative Channel Metal Oxide semiconductor), such as a Pull-down transistor (PD), and the second region II is used to form a pmos (positive Channel Metal Oxide semiconductor), such as a transfer gate transistor (PG) or a Pull-up transistor (PU).
Specifically, the material of the channel layer 102 includes: one or more of silicon, germanium, silicon carbide, gallium arsenide, and indium gallium. In this embodiment, the material of the channel layer 102 is silicon.
In this embodiment, the lateral dimension of the channel layer 102 in the second region II is smaller than the lateral dimension of the channel layer 102 under the gate structure 118 in the first region I. Correspondingly, when the semiconductor structure works, the conduction current of the channel in the second area II is smaller than that of the channel in the first area I.
In the step of providing the substrate, a ratio of a lateral dimension of the channel layer 102 in the second region II to a lateral dimension of the channel layer 102 in the first region I is preferably neither too large nor too small, with the lateral dimension being parallel to the surface of the substrate 100 and perpendicular to the extending direction of the gate structure 118 as the lateral direction. Generally, the semiconductor structure is used for forming an SRAM device, specifically, the first region I is used for forming a pull-down transistor, and the second region II is used for forming a pass-gate transistor or a pull-up transistor, if the ratio is too large, when the semiconductor structure is in operation, the conduction current of the channel in the second region II is caused to be approximately the same as the conduction current in the first region I, and the reading stability and the writing rate of the SRAM device cannot be significantly improved. If the ratio is too small, the on-current of the channel in the second region II is too small compared to the on-current in the first region I during operation of the semiconductor structure, i.e., the on-current of the pass-gate transistor is too small, which may limit the read and write rates of the SRAM device. In this embodiment, in the step of providing the substrate, the lateral dimension of the channel layer 102 in the second region II is 55% to 95% of the lateral dimension of the channel layer 102 in the first region I, with the extending direction parallel to the surface of the substrate 100 and perpendicular to the gate structure 118 as the lateral direction.
It should be further noted that the semiconductor structure further includes: a fin 112 protruding from the substrate 100, wherein the fin 112 is located between the substrate 100 and the channel stack; an isolation layer 113 on the substrate 100 where the fin portion 112 is exposed; the gate structure 118 is located on the isolation layer 113, and the gate structure 118 crosses over the fin 112 and covers a portion of the top wall and a portion of the sidewall of the fin 112.
The fin 112 protrudes from the substrate 100, and the side of the fin 112 provides a process space for the isolation layer 113.
In this embodiment, the material of the fin portion 112 is the same as that of the substrate 100. In other embodiments, the material of the fin may also be different from the material of the substrate.
The isolation layer 113 electrically isolates the gate structure 118 from the substrate 100, and the isolation layer 113 is used to further electrically isolate the fins 112 from each other.
In this embodiment, the isolation layer 113 is made of a dielectric material. Specifically, the isolation layer 113 includes silicon oxide, which is a dielectric material with a common process and a low cost, and has a high process compatibility, thereby facilitating reduction of process difficulty and process cost for forming the isolation layer 113.
The gate structure 118 is used to control the opening and closing of the channel during operation of the semiconductor structure.
The gate structure 118 includes a work function layer and a gate layer over the work function layer.
Specifically, the material of the work function layer in the NMOS includes one or more of titanium aluminide, tantalum carbide, and titanium carbide. The material of the work function layer in the PMOS includes one or more of titanium nitride, tantalum nitride, titanium carbide, tantalum silicon nitride, titanium silicon nitride, and tantalum carbide.
Specifically, the material of the gate layer comprises one or more of magnesium-tungsten alloy, tungsten, copper, nickel and titanium. In this embodiment, the gate layer is made of a magnesium-tungsten alloy.
In this embodiment, the gate structure 118 completely surrounds the channel layer 102. The lateral dimension of the channel layer 102 of the second region II is smaller than the lateral dimension of the channel layer 102 of the first region I, the lateral dimension of the gate structure 118 of the corresponding second region II is smaller than the lateral dimension of the gate structure 118 of the first region I, and the on-current of the channel in the second region II is smaller than the on-current of the channel in the first region I when the semiconductor structure is in operation.
In this embodiment, the lateral dimension of the gate structure 118 in the second region II is 55% to 95% of the lateral dimension of the gate structure 118 in the first region I, taking the extending direction parallel to the surface of the substrate 100 and perpendicular to the gate structure 118 as the lateral direction.
The gate sidewall layer 105 serves to protect the sidewalls of the gate structure 118 from damage during the formation of the semiconductor structure.
The material of the gate sidewall layer 105 includes: one or more of silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, boron nitride boron silicon nitride, and boron nitride silicon carbide.
The semiconductor structure further includes: and the source-drain doping layer 114 is separated on the substrate 100, and is parallel to the surface of the substrate 100, and the extending direction of the gate structure 118 is a transverse direction, and the source-drain doping layer 114 is positioned at two transverse ends of the channel layer 102.
When the semiconductor structure operates, the source-drain doping layer 114 is used for providing stress for a channel in the channel layer 102, and increasing the migration rate of carriers in the channel.
In this embodiment, the first region I is used to form an NMOS, and the source-drain doped layer 114 is used as a source and a drain of the NMOS. When the semiconductor structure works, the source-drain doped layer 114 applies tensile stress to a channel below the gate structure, and the channel is stretched to improve the migration rate of electrons. The material of the source-drain doped layer 114 of the first region I includes: silicon carbide or silicon phosphide doped with N-type ions. The N-type ions include one or more of P, As and Sb.
The second region II is used to form a PMOS, and the source-drain doped layer 114 of the second region II is used to serve as a source and a drain of the PMOS. When the semiconductor structure works, the source-drain doped layers apply compressive stress to the channel below the gate structure, and the compressed channel can improve the mobility of holes. The material of the source-drain doped layer 114 of the second region II includes: silicon germanium doped with P-type ions. The P-type ions include one or more of B, Ga and In.
In this embodiment, the source-drain doping layers 114 in the first region I and the second region II are formed simultaneously, the formation conditions of the source-drain doping layers 114 in the first region I and the second region II are the same, and correspondingly, the thickness of the source-drain doping layer 114 in the first region I is equal to the thickness of the source-drain doping layer 114 in the second region II.
The semiconductor structure further includes: and an interlayer dielectric layer 115 covering the sidewall of the gate structure 118 and exposing the top of the gate structure.
Interlevel dielectric layer 115 is used to electrically isolate adjacent devices. The interlayer dielectric layer 115 is made of an insulating material. Specifically, the material of the interlayer dielectric layer 115 includes silicon oxide. Silicon oxide is a dielectric material with common process and low cost, has high process compatibility, and is beneficial to reducing the process difficulty and the process cost for forming the interlayer dielectric layer 115.
One or more end channel layers 119 between the gate sidewall layer 105 and the topmost channel layer 102 of the second region II. In the present embodiment, only one end channel layer 119 is illustrated.
In the forming process of the semiconductor structure, a plurality of channel layers 102 with the same number are arranged in a first area I and a second area II, one or more channel layers 102 exposed from the grid side wall layer 105 of the second area II are etched, one or more end channel layers 119 are formed under the grid side wall layer 105, the number of the channel layers 102 of the corresponding second area II is less than that of the channel layers 102 of the first area I, and the conduction current of the second area is less than that of the first area when the semiconductor structure works.
The semiconductor structure further includes: and the inner sidewall layer 110 is positioned between the source-drain doped layer 114 and the gate structure 118.
The inner sidewall layer 110 is used to reduce the capacitive coupling effect between the source-drain doped layer 114 and the gate structure 118, thereby reducing the parasitic capacitance and improving the electrical performance of the transistor structure.
Accordingly, the inner sidewall layer 110 is also located between the end channel layers 119, or between the end channel layers 119 and the channel layer 102, or between the channel layers 102.
In this embodiment, the material of the inner sidewall layer 110 is a low-K dielectric material. A low-k dielectric material (a low-k dielectric material refers to a dielectric material having a relative dielectric constant of 2.6 or more and 3.9 or less). The low-K dielectric material has excellent insulating property. The capacitive coupling effect between the source-drain doped layer 114 and the gate structure 118 can be reduced, thereby reducing the parasitic capacitance and improving the electrical performance of the transistor structure.
Specifically, the material of the inner side wall layer 110 includes: SiON, SiBCN, SiCN, carbon doped SiN, or oxygen doped SiN. In this embodiment, the material of the inner sidewall layer 110 includes carbon-doped SiN or oxygen-doped SiN.
Correspondingly, the embodiment of the invention also provides an SRAM device. A schematic structural diagram of an embodiment of an SRAM device of the present invention is shown.
The SRAM device comprises the semiconductor structure described in the preamble, the semiconductor structure comprising: a substrate comprising a first region and a second region; the plurality of channel layers are suspended on the substrate at intervals in the normal direction of the surface of the substrate, and the number of the channel layers in the second area is less than that of the channel layers in the first area; a gate structure surrounding the channel layer; the grid side wall layer is positioned on the side wall of the grid structure at the top of the channel layer; one or more end channel layers between the gate sidewall layer and the topmost channel layer of the second region.
The first region I includes a Pull-down transistor (PD); the second region II includes a Pass-gate transistor (PG) or a Pull-down transistor (PD).
The number of the channel layers 102 of the pull-down transistors is more than that of the channel layers 102 of the transmission gate transistors or the pull-up transistors, and when the corresponding SRAM device works, the conduction current of the pull-down transistors is larger than that of the transmission gate transistors or the pull-up transistors, so that when the SRAM device works, the stability of the SRAM device is high and is not easily interfered, and particularly, the conduction current of the pull-down transistors is larger than that of the transmission gate transistors, so that the reading stability of the SRAM device is improved; the conduction current of the pull-down transistor is larger than that of the pull-up transistor, so that the write-in speed of the SRAM device is improved.
In this embodiment, the SRAM device is a six-transistor static random access memory (six-transistor SRAM, 6T-SRAM).
Specifically, in the present embodiment, the number of the channel layers 102 of the pull-down transistor is three; the number of the channel layers of the pass gate transistor is two, the number of the channel layers 102 of the pull-up transistor is one, or the number of the channel layers 102 of the pass gate transistor is one, and the number of the channel layers 102 of the pull-up transistor is two.
In this embodiment, the lateral dimension of the channel layer 102 in the second region II is smaller than the lateral dimension of the channel layer 102 in the first region I. Correspondingly, when the semiconductor structure works, the conduction current of the channel in the second area II is smaller than that of the channel in the first area I.
In the step of providing the substrate, a ratio of a lateral dimension of the channel layer 102 in the second region II to a lateral dimension of the channel layer 102 in the first region I is preferably neither too large nor too small, with the lateral dimension being parallel to the surface of the substrate 100 and perpendicular to the extending direction of the gate structure 118 as the lateral direction. Generally, the semiconductor structure is used for forming an SRAM device, specifically, the first region I is used for forming a pull-down transistor, and the second region II is used for forming a pass-gate transistor or a pull-up transistor, if the ratio is too large, when the semiconductor structure is in operation, the conduction current of the channel in the second region II is caused to be approximately the same as the conduction current in the first region I, and the reading stability and the writing rate of the SRAM device cannot be significantly improved. If the ratio is too small, the on-current of the channel in the second region II is too small compared to the on-current in the first region I during operation of the semiconductor structure, i.e., the on-current of the pass-gate transistor is too small, which may limit the read and write rates of the SRAM device. In this embodiment, in the step of providing the substrate, the lateral dimension of the channel layer 102 in the second region II is 55% to 95% of the lateral dimension of the channel layer 102 in the first region I, with the extending direction parallel to the surface of the substrate 100 and perpendicular to the gate structure 118 as the lateral direction.
In this embodiment, the lateral dimension of the gate structure 118 in the second region II is 55% to 95% of the lateral dimension of the gate structure 118 in the first region I, taking the extending direction parallel to the surface of the substrate 100 and perpendicular to the gate structure 118 as the lateral direction. Specific advantages refer to the statements in the semiconductor structure, which are not repeated here.
The semiconductor structure may be formed by the formation method of the foregoing embodiment, or may be formed by other formation methods. For a detailed description of the semiconductor structure of this embodiment, reference may be made to the corresponding description in the foregoing embodiments, and details of this embodiment are not repeated herein.
Although the embodiments of the present invention are disclosed above, the embodiments of the present invention are not limited thereto. Various changes and modifications may be effected therein by one of ordinary skill in the pertinent art without departing from the scope or spirit of the present embodiments, and it is intended that the scope of the present embodiments be defined by the appended claims.

Claims (28)

1. A method of forming a semiconductor structure, comprising:
providing a substrate, wherein the substrate comprises a substrate, a plurality of channel lamination layers separated from the substrate and a pseudo gate structure crossing the plurality of channel lamination layers, the pseudo gate structure covers partial top walls and partial side walls of the channel lamination layers, and the channel lamination layers comprise sacrificial layers and channel layers located on the sacrificial layers;
forming an interlayer dielectric layer which covers the side wall of the pseudo gate structure and exposes the top of the pseudo gate structure;
removing the pseudo gate structure, and forming a gate opening in the interlayer dielectric layer;
removing one or more of the channel layers atop the channel stack;
removing the sacrificial layer between the remaining channel layers to form a channel after removing one or more of the channel layers on the top of the channel stack;
and forming a gate structure in the gate opening and the channel.
2. The method of forming a semiconductor structure of claim 1, wherein in the step of providing a substrate, the substrate comprises a first region and a second region;
in the step of removing the one or more channel layers on top of the channel stack, the one or more channel layers of the second region are removed.
3. The method for forming a semiconductor structure according to claim 2, wherein in the step of providing a base, a lateral dimension of the dummy gate structure of the second region is 55% to 95% of a lateral dimension of the dummy gate structure of the first region, with a lateral direction being parallel to the surface of the substrate and perpendicular to an extending direction of the dummy gate structure.
4. The method of forming a semiconductor structure of claim 2, wherein removing one or more of the channel layers of the second region comprises: forming a mask layer covering the first area and exposing the second area; removing one or more channel layers in the second area by taking the mask layer as a mask;
the method for forming the semiconductor structure further comprises the following steps: and removing the mask layer after removing one or more channel layers on the top of the channel lamination.
5. The method of forming a semiconductor structure of claim 4, wherein the mask layer comprises: the organic light-emitting diode comprises an organic material layer, an anti-reflection coating layer and a photoresist layer, wherein the anti-reflection coating layer is positioned on the organic material layer, and the photoresist layer is positioned on the anti-reflection coating layer.
6. The method of forming a semiconductor structure of claim 4, wherein the method of forming a semiconductor structure comprises: after the mask layer is formed, before the one or more channel layers on the top of the channel lamination in the second area are removed, a shielding layer exposing the one or more channel layers is formed in the second area;
the method for forming the semiconductor structure further comprises the following steps: removing the barrier layer after removing the one or more channel layers on top of the channel stack.
7. The method of forming a semiconductor structure of claim 6, wherein the masking layer comprises: and an organic material layer.
8. The method of forming a semiconductor structure of claim 1, wherein a wet etch process is used to remove one of the channel layers on top of the channel stack.
9. The method of forming a semiconductor structure of claim 8, wherein the wet etching solution comprises a tetramethylammonium hydroxide solution.
10. The method of forming a semiconductor structure of claim 1, wherein the one or more channel layers on top of the channel stack are removed using a dry etch process.
11. The method of forming a semiconductor structure of claim 2, further comprising: after providing a substrate and before forming the interlayer dielectric layer, etching the channel laminated layers on two sides of the pseudo gate structure, and forming a groove in the channel laminated layers;
and forming a source drain doping layer in the groove.
12. The method for forming a semiconductor structure according to claim 11, wherein a direction parallel to the surface of the substrate and perpendicular to an extending direction of the dummy gate structure is a lateral direction;
the method for forming the semiconductor structure further comprises the following steps: after the groove is formed and before the source drain doping layer is formed, the sacrificial layer exposed out of the groove is transversely etched to form a side wall groove; and forming an inner side wall layer in the side wall groove.
13. The method for forming a semiconductor structure according to claim 11, wherein in the step of forming the trench, a lateral dimension of the channel layer of the second region is 55% to 95% of a lateral dimension of the channel layer of the first region, in a lateral direction parallel to the surface of the substrate and perpendicular to an extending direction of the dummy gate structure.
14. The method of forming a semiconductor structure of claim 11, wherein in the step of providing a substrate, the substrate further comprises: a fin located between the substrate and the channel stack;
the isolation layer is positioned on the substrate with the exposed fin part and covers part of the side wall of the fin part;
the dummy gate structure is located on the isolation layer, crosses the fin portion, and covers part of the top wall and part of the side wall of the fin portion.
15. A semiconductor structure, comprising:
a substrate comprising a first region and a second region;
the plurality of channel layers are suspended on the substrate at intervals in the normal direction of the surface of the substrate, and the number of the channel layers in the second area is less than that of the channel layers in the first area;
a gate structure surrounding the channel layer;
the grid side wall layer is positioned on the side wall which is higher than the channel layer and close to the top of the grid structure;
one or more end channel layers between the gate sidewall layer and the topmost channel layer of the second region.
16. The semiconductor structure of claim 15, wherein the semiconductor structure further comprises: and the source and drain doping layers are separated on the substrate, are parallel to the surface of the substrate and are transverse to the extending direction of the grid structure, and are positioned at two transverse ends of the channel layer.
17. The semiconductor structure of claim 16, wherein the semiconductor structure further comprises: and the inner side wall layer is positioned between the source-drain doped layer and the grid structure and between the end channel layers, or between the end channel layers and the channel layers, or between the channel layers.
18. The semiconductor structure of claim 16, wherein a thickness of the source drain doped layer in the first region is equal to a thickness of the source drain doped layer in the second region.
19. The semiconductor structure of claim 16, wherein the first region is an NMOS, and wherein the materials of the source-drain doped layers of the first region comprise: silicon carbide or silicon phosphide doped with N-type ions, the N-type ions comprising one or more of P, As and Sb;
the second region is a PMOS, and the material of the source-drain doping layer of the second region comprises: silicon germanium doped with P-type ions including one or more of B, Ga and In.
20. The semiconductor structure of claim 15, wherein the semiconductor structure further comprises: a fin portion between the substrate and the plurality of channel layers;
the isolation layer is positioned on the substrate on the side part of the fin part and covers part of the side wall of the fin part;
the grid electrode structure is located on the isolation layer, stretches across the fin portion and covers part of the top wall and part of the side wall of the fin portion.
21. The semiconductor structure of claim 15, wherein a material of the channel layer comprises: one or more of silicon, germanium, silicon carbide, gallium arsenide, and indium gallium.
22. The semiconductor structure of claim 15, wherein the gate structure comprises a work function layer and a gate layer located on the work function layer;
the first region is an NMOS, and the material of the work function layer in the NMOS comprises one or more of titanium aluminide, tantalum carbide and titanium carbide; the second region is a PMOS, and the material of the work function layer in the PMOS comprises one or more of titanium nitride, tantalum nitride, titanium carbide, tantalum silicon nitride, titanium silicon nitride and tantalum carbide;
the material of the gate layer comprises one or more of magnesium-tungsten alloy, tungsten, copper, nickel and titanium.
23. The semiconductor structure of claim 15, wherein the gate structure is laterally oriented parallel to the substrate surface and perpendicular to the direction of extension of the gate structure;
the lateral dimension of the channel layer of the second region is 55% to 95% of the lateral dimension of the channel layer of the first region.
24. The semiconductor structure of claim 15, wherein the gate structure is laterally oriented parallel to the substrate surface and perpendicular to the gate structure;
the lateral dimension of the gate structure of the second region is 55% to 95% of the lateral dimension of the gate structure of the first region.
25. An SRAM device comprising a semiconductor structure, the semiconductor structure comprising:
a substrate comprising a first region and a second region;
the plurality of channel layers are suspended on the substrate at intervals in the normal direction of the surface of the substrate, and the number of the channel layers in the second area is less than that of the channel layers in the first area;
a gate structure surrounding the channel layer;
the grid side wall layer is positioned on the side wall of the grid structure at the top of the channel layer;
one or more end channel layers between the gate sidewall layer and the topmost channel layer of the second region;
it is characterized by comprising:
the first region includes a pull-down transistor;
the second region includes a pass gate transistor or a pull-up transistor.
26. The SRAM device of claim 25, wherein the number of the channel layers of the pull-down transistor is three, the number of the channel layers of the pass-gate transistor is two, and the number of the channel layers of the pull-up transistor is one;
alternatively, the first and second electrodes may be,
the number of the channel layers of the pull-down transistor is three, the number of the channel layers of the transmission gate transistor is one, and the number of the channel layers of the pull-up transistor is two.
27. The SRAM device of claim 25, wherein lateral is taken parallel to the substrate surface and perpendicular to an extension direction of the gate structure;
the lateral dimension of the channel layer of the second region is 55% to 95% of the dimension of the first region.
28. The SRAM device of claim 25, wherein lateral is taken parallel to the substrate surface and perpendicular to an extension direction of the gate structure;
the lateral dimension of the gate structure of the second region is 55% to 95% of the lateral dimension of the gate structure of the first region.
CN202011340562.2A 2020-11-25 2020-11-25 Semiconductor structure, forming method thereof and SRAM device Pending CN114551356A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202011340562.2A CN114551356A (en) 2020-11-25 2020-11-25 Semiconductor structure, forming method thereof and SRAM device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202011340562.2A CN114551356A (en) 2020-11-25 2020-11-25 Semiconductor structure, forming method thereof and SRAM device

Publications (1)

Publication Number Publication Date
CN114551356A true CN114551356A (en) 2022-05-27

Family

ID=81659247

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202011340562.2A Pending CN114551356A (en) 2020-11-25 2020-11-25 Semiconductor structure, forming method thereof and SRAM device

Country Status (1)

Country Link
CN (1) CN114551356A (en)

Similar Documents

Publication Publication Date Title
CN110277316B (en) Semiconductor structure and forming method thereof
CN106373924B (en) Method for forming semiconductor structure
CN112309861B (en) Semiconductor structure, forming method thereof and transistor
CN113809010B (en) Semiconductor structure and forming method thereof
CN110581173A (en) Semiconductor structure and forming method thereof
CN110854194B (en) Semiconductor structure and forming method thereof
CN113539969B (en) Semiconductor structure and forming method thereof
CN113809011B (en) Semiconductor structure and forming method thereof
CN112309845B (en) Semiconductor structure and forming method thereof
CN111490092B (en) Semiconductor structure and forming method thereof
CN114551356A (en) Semiconductor structure, forming method thereof and SRAM device
CN113838803B (en) Semiconductor structure and forming method thereof
CN114068706B (en) Semiconductor structure and forming method thereof
CN110690286B (en) Semiconductor structure and forming method thereof
CN111627854B (en) Semiconductor structure and forming method thereof
US20220052185A1 (en) Semiconductor structure and method for forming the same
CN112951725B (en) Semiconductor structure and forming method thereof
CN114068700B (en) Semiconductor structure and forming method thereof
CN113838806B (en) Semiconductor structure and forming method thereof
CN112310198B (en) Semiconductor structure and forming method thereof
CN110875390B (en) Semiconductor structure and forming method thereof
CN113838803A (en) Semiconductor structure and forming method thereof
CN114664734A (en) Semiconductor structure and forming method thereof
WO2022193085A1 (en) Semiconductor structure and method for forming same
CN113808947A (en) Semiconductor structure and forming method thereof

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination