CN116031280A

CN116031280A - Semiconductor structure and forming method thereof

Info

Publication number: CN116031280A
Application number: CN202111254216.7A
Authority: CN
Inventors: 武咏琴; 卜伟海
Original assignee: North Ic Technology Innovation Center Beijing Co ltd
Current assignee: North Ic Technology Innovation Center Beijing Co ltd
Priority date: 2021-10-27
Filing date: 2021-10-27
Publication date: 2023-04-28

Abstract

A semiconductor structure and a method of forming the same, wherein the semiconductor structure comprises: a substrate; a plurality of protruding parts protruding from the substrate; the isolation layer is positioned on the protruding part and comprises a first area and second areas positioned on two sides of the first area along the extending direction of the protruding part; a filling layer located on the first region of the isolation layer; the channel structure layer is arranged above the filling layer and is suspended from the filling layer, and comprises one or more channel layers which are arranged at intervals in sequence, and the channel layers are stacked along the direction vertical to the surface of the substrate; the insulating layer is positioned on the substrate and surrounds the bulge, the isolation layer and the filling layer, and covers the side walls of the isolation layer and the filling layer and exposes the channel structure layer; and the gate structure is positioned on the insulating layer, spans the channel structure layer and surrounds the channel layer, and is also positioned on top of the filling layer and spans the filling layer. The embodiment of the invention can reduce the leakage current of the device and improve the performance of the semiconductor structure.

Description

Semiconductor structure and forming method thereof

Technical Field

Embodiments of the present disclosure relate to semiconductor manufacturing, and more particularly, to a semiconductor structure and a method for forming the same.

Background

With the rapid development of semiconductor manufacturing technology, semiconductor devices are being developed toward higher element density and higher integration, and the development trend of semiconductor process nodes following moore's law is continuously decreasing. Transistors are currently being widely used as the most basic semiconductor devices, and therefore, as the element density and integration level of the semiconductor devices are improved, the channel length of the transistors has to be continuously shortened in order to accommodate the reduction of process nodes.

To better accommodate the demand for device scaling, semiconductor processes are increasingly beginning to transition from planar transistors to three-dimensional transistors with higher power, such as Gate-all-around (GAA) transistors. In the fully-enclosed gate transistor, the gate encloses the region where the channel is located from the periphery, and compared with a planar transistor, the gate of the fully-enclosed gate transistor has stronger control capability on the channel and can better inhibit the short channel effect.

However, the performance of the fully-surrounding gate transistor is still to be improved.

Disclosure of Invention

The embodiment of the invention solves the problem of providing a semiconductor structure and a forming method thereof, which can reduce leakage current of a device and improve the performance of the semiconductor structure.

To solve the above problems, an embodiment of the present invention provides a semiconductor structure, including: a substrate; a plurality of protruding portions protruding from the substrate; the isolation layer is positioned on the protruding part and comprises a first area and second areas positioned on two sides of the first area along the extending direction of the protruding part; a fill layer located on the first region of the isolation layer; the channel structure layer is positioned above the filling layer and is suspended in the air at intervals with the filling layer, and comprises one or more channel layers which are sequentially arranged at intervals, and the channel layers are stacked along the direction vertical to the surface of the substrate; an insulating layer on the substrate and surrounding the protrusion, the isolation layer and the filling layer, the insulating layer covering sidewalls of the isolation layer and the filling layer and exposing the channel structure layer; a gate structure on the insulating layer and crossing the channel structure layer and surrounding the channel layer, the gate structure also being on top of and crossing the fill layer; the source-drain doping layers are positioned on the filling layers at two sides of the grid structure and are in contact with the end parts of each channel layer in the channel structure layer along the extending direction.

Correspondingly, the embodiment of the invention also provides a method for forming the semiconductor structure, which comprises the following steps: providing a substrate, wherein the substrate comprises a substrate and a plurality of protruding parts protruding out of the substrate, a sacrificial layer, an etching stop layer and a laminated structure are sequentially formed on the protruding parts, the etching stop layer is made of a semiconductor material, the laminated structure comprises one or a plurality of channel laminated layers which are sequentially stacked from bottom to top, and each channel laminated layer comprises a space occupying layer and a channel layer positioned on the space occupying layer; forming an insulating layer surrounding the bump, the sacrificial layer, and the etch stop layer on the substrate; forming a dummy gate structure on the insulating layer across the stacked structure; forming grooves in the laminated structures at two sides of the pseudo gate structure, wherein the bottoms of the grooves expose the etching stop layer; forming a protection side wall on the side wall of the groove, wherein the protection side wall covers part of the top surface of the etching stop layer; removing the etching stop layer exposed by the protection side wall, and exposing the top surface of the sacrificial layer; removing the sacrificial layer, and forming a channel between the etching stop layer and the protruding part and below the groove, wherein the channel is surrounded by the insulating layer, the protruding part and the etching stop layer; forming an isolation layer within the channel; removing the protection side wall on the side wall of the channel layer, exposing the side wall of the channel layer and the etching stop layers on two sides of the pseudo gate structure; forming source-drain doped layers on the etching stop layers at two sides of the pseudo gate structure, wherein the source-drain doped layers are in contact with the end parts of the channel layer along the extending direction; removing the etching stop layer to form a groove, wherein the groove is surrounded by the isolation layer, the insulating layer, the laminated structure and source-drain doping layers positioned on two sides of the laminated structure, and the laminated structure and the source-drain doping layers are suspended on the isolation layer; forming a filling layer in the groove; removing the dummy gate structure after the filling layer is formed, forming a gate opening, and exposing the laminated structure; removing the occupying layer through the grid opening to form a through groove, wherein the through groove is surrounded by adjacent channel layers or is surrounded by the channel layers and the filling layer; and filling a gate structure in the gate opening and the through groove, wherein the gate structure surrounds the channel layer, and the gate structure is also positioned on the top of the filling layer and spans the filling layer.

Compared with the prior art, the technical scheme of the embodiment of the invention has the following advantages:

according to the semiconductor structure provided by the embodiment of the invention, the isolation layer and the filling layer are sequentially arranged on the bulge, the channel structure layer is arranged above the filling layer in a suspending manner at intervals, the grid structure is positioned at the top of the filling layer and spans across the filling layer, the source-drain doping layers are positioned on the filling layer at two sides of the grid structure, accordingly, the isolation between the source-drain doping layers and the bulge and the isolation between the grid structure and the bulge are realized through the isolation layer and the filling layer, parasitic devices are formed by the source-drain doping layers, the grid structure and the bulge below the grid structure, and further, leakage channels generated in the bulge are eliminated, leakage current of the devices is reduced, and the performance of the semiconductor structure is improved.

In the method for forming the semiconductor structure provided by the embodiment of the invention, the sacrificial layer is removed, and a channel is formed; forming an isolation layer within the channel; removing the etching stop layer after the source-drain doped layer is formed, and forming a groove; and forming a filling layer in the trench. Therefore, after the grid structure is formed, the isolation between the source and drain doping layer and the protruding part and the isolation between the grid structure and the protruding part are realized through the isolation layer and the filling layer, so that parasitic devices formed by the source and drain doping layer, the grid structure and the protruding part below the source and drain doping layer and the grid structure are prevented, leakage channels generated in the protruding part are eliminated, and leakage current of the devices is reduced; in addition, after forming the groove, a protection side wall is formed on the side wall of the groove, the protection side wall covers part of the top surface of the etching stop layer, after forming the channel, the protection side wall on the side wall of the channel layer is removed, the etching stop layers on two sides of the pseudo gate structure are correspondingly exposed, the etching stop layers are made of semiconductor materials, the process of forming the source/drain doping layers generally comprises an epitaxial process, in the step of forming the source/drain doping layers, besides taking the channel layer as a growth basis of the epitaxial process, the source/drain doping layers can be formed by adopting the etching stop layers as a growth basis, a process platform for carrying out the epitaxial process is increased, and the epitaxial quality of the source/drain doping layers is further improved. In summary, the embodiment of the invention improves the performance of the semiconductor structure.

Drawings

Fig. 1 to 6 are schematic structural views corresponding to steps in a method for forming a semiconductor structure;

FIGS. 7-8 are schematic diagrams illustrating an embodiment of a semiconductor structure according to the present invention;

fig. 9 to 31 are schematic structural views corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention.

Detailed Description

As known from the background art, the performance of the current semiconductor structure needs to be improved. The reason why the performance of a semiconductor structure is to be improved is analyzed by combining a method for forming the semiconductor structure. Fig. 1 to 6 are schematic structural diagrams corresponding to steps in a method for forming a semiconductor structure. Specifically, fig. 1 to 6 show schematic sectional structures along the extending direction of the channel layer.

Referring to fig. 1, a base is provided, comprising a substrate (not shown) and a plurality of protrusions 1 protruding from the substrate 1, a stack structure 6 is formed on the protrusions 1, the stack structure 6 comprises one or more channel stacks 2, the channel stacks 2 comprise a placeholder layer 12 and a channel layer 3 located on the placeholder layer 12.

With continued reference to fig. 1, an insulating layer (not shown) surrounding the protruding portion 1 is formed on the substrate, the insulating layer exposing the laminated structure 6.

With continued reference to fig. 1, a dummy gate structure 5 is formed on the insulating layer across the stack 6.

Referring to fig. 2, gate side walls 4 are formed on the side walls of the two sides of the dummy gate structure 5; a groove 8 is formed in the stacked structure 6 at both sides of the gate sidewall 4.

Referring to fig. 3, the part of the thickness occupying layer 12 exposed from the side wall of the groove 8 is removed along the extending direction of the channel layer 3 to form an inner groove (not shown); the inner trench (not shown) is filled with the inner sidewall 14.

Referring to fig. 4, a source-drain doped layer 15 is formed in the recess 8, and the source-drain doped layer 15 is located on the protruding portion 1.

With continued reference to fig. 4, an interlayer dielectric layer 19 is formed on the insulating layers on both sides of the dummy gate structure 5 to cover the source-drain doped layer 15.

Referring to fig. 5, the dummy gate structure 5 is removed to form a gate opening 16 exposing the stacked structure and the insulating layer; the gate opening 16 is used to remove the placeholder layer 12, so as to form a through groove 17, wherein the through groove 17 is surrounded by adjacent channel layers or is surrounded by the channel layer 3 and the protruding portion 1.

Referring to fig. 6, a gate structure 18 is filled in the gate opening 16 and the through trench 17, and the gate structure 18 surrounds the channel layer 3.

The semiconductor structure is a fully-surrounding gate transistor, wherein the source-drain doped layer 15 and the protruding portion 1, and the gate structure 18 and the protruding portion 1 are in contact with each other, the source-drain doped layer 15 and the gate structure 18 and the protruding portion 1 below the same easily form a parasitic device, and a leakage channel is easily generated in the protruding portion 1, so that leakage current of the semiconductor structure is too large, and device performance is poor.

A method for reducing leakage current is to arrange isolation layers between a protruding part and a source-drain doping layer and between the protruding part and a grid structure, so that isolation between the source-drain doping layer and the protruding part and isolation between the grid structure and the protruding part are realized through the isolation layers. However, in the method, in the process of forming the source-drain doped layer, the isolation layer is arranged on the protruding portion, so that the source-drain doped layer can be formed only by taking the end part of the channel layer along the extending direction as the growth basis of the epitaxial process, the area of the epitaxial basis of the epitaxial process for forming the source-drain doped layer is small, the process platform is insufficient when the epitaxial process is performed, and the formation quality of the source-drain doped layer is further reduced. In particular, the cross-sectional area of the channel layer is smaller, which is easy to further reduce the formation quality of the source-drain doped layer, resulting in poor performance of the semiconductor structure.

In order to solve the technical problems, the embodiment of the invention provides a semiconductor structure, wherein the isolation layer and the filling layer are sequentially arranged on the protruding portion, a channel structure layer is arranged above the filling layer in a suspending manner at intervals, the grid structure is positioned at the top of the filling layer and spans across the filling layer, the source-drain doping layers are positioned on the filling layer at two sides of the grid structure, accordingly, isolation between the source-drain doping layers and the protruding portion and isolation between the grid structure and the protruding portion are realized through the isolation layer and the filling layer, parasitic devices are prevented from being formed in the source-drain doping layers, the grid structure and the protruding portion below the source-drain doping layers, leakage channels generated in the protruding portion are eliminated, leakage current of the devices is reduced, and performance of the semiconductor structure is improved.

In order to solve the technical problem, the embodiment of the invention also provides a method for forming a semiconductor structure, which comprises the steps of removing the sacrificial layer and forming a channel; forming an isolation layer within the channel; removing the etching stop layer after the source-drain doped layer is formed, and forming a groove; and forming a filling layer in the trench. Therefore, after the grid structure is formed, the isolation between the source and drain doping layer and the protruding part and the isolation between the grid structure and the protruding part are realized through the isolation layer and the filling layer, so that parasitic devices formed by the source and drain doping layer, the grid structure and the protruding part below the source and drain doping layer and the grid structure are prevented, leakage channels generated in the protruding part are eliminated, and leakage current of the devices is reduced; in addition, after forming the groove, a protection side wall is formed on the side wall of the groove, the protection side wall covers part of the top surface of the etching stop layer, after forming the channel, the protection side wall on the side wall of the channel layer is removed, the etching stop layers on two sides of the pseudo gate structure are correspondingly exposed, the etching stop layers are made of semiconductor materials, the process of forming the source/drain doping layers generally comprises an epitaxial process, in the step of forming the source/drain doping layers, besides taking the channel layer as a growth basis of the epitaxial process, the source/drain doping layers can be formed by using the etching stop layers as a growth basis, the process platform for carrying out the epitaxial process is increased, and the epitaxial quality of the source/drain doping layers is further improved. In summary, the embodiment of the invention improves the performance of the semiconductor structure.

In order that the above objects, features and advantages of embodiments of the invention may be readily understood, a more particular description of the invention will be rendered by reference to specific embodiments thereof which are illustrated in the appended drawings.

Referring to fig. 7-8, schematic structural diagrams of an embodiment of the semiconductor structure of the present invention are shown. Fig. 7 is a perspective view, and fig. 8 is a sectional view of fig. 7 taken along the X-X direction.

As shown in fig. 7 and 8, the semiconductor structure includes: a substrate 800; a plurality of protrusions 810 protruding from the substrate 800; the isolation layer 820 is located on the protruding portion 810, and along the extending direction of the protruding portion 810, the isolation layer 820 includes a first area i and second areas ii located on two sides of the first area i; a fill layer 900 on the first region i of the isolation layer 820; the channel structure layer 850 is located above the filling layer 900 and is suspended from the filling layer 900 at intervals, the channel structure layer 850 includes one or more channel layers 860 sequentially arranged at intervals, and the channel layers 860 are stacked along a direction perpendicular to the surface of the substrate 800; an insulating layer 870 on the substrate 800 and surrounding the protrusion 810, the isolation layer 820 and the filling layer 900, the insulating layer 870 covering sidewalls of the isolation layer 820 and the filling layer 900 and exposing the channel structure layer 850; a gate structure 830 on the insulating layer 870 and crossing the channel structure layer 850 and surrounding the channel layer 860, the gate structure 830 also being on top of the fill layer 900 and crossing the fill layer 900; and a source/drain doped layer 840 on the filling layer 900 at both sides of the gate structure 830 and contacting with an end of each channel layer 860 of the channel structure layer 850 along the extending direction.

The substrate 800 is used to provide a process platform for the formation of semiconductor structures.

In this embodiment, a semiconductor structure is taken as an example of a fully-enclosed Gate (GAA) transistor. In other embodiments, the semiconductor structure may also be a fork gate transistor (fork gate) or a Complementary Field Effect Transistor (CFET) or other type of transistor.

In this embodiment, the substrate 800 is a silicon substrate, that is, the material of the substrate 800 is monocrystalline silicon. In other embodiments, the substrate material may be one or more of germanium, silicon carbide, gallium nitride, gallium arsenide, and indium gallium arsenide, and the substrate may be a silicon-on-insulator substrate or a germanium-on-insulator substrate, among other types of substrates.

The boss 810 protrudes above the substrate 800 so that an insulating layer can be located on the substrate 800 and surround the boss 810. The raised portions 810 also serve to provide support for the channel structure layer and the gate structure 830.

In this embodiment, the protruding portion 810 and the substrate 800 are in an integral structure, and the material of the protruding portion 810 and the material of the substrate 800 are the same, and are both silicon. In other embodiments, the material of the protrusions may be different from the material of the substrate, and the material of the protrusions may be other suitable materials, such as: germanium, silicon carbide, gallium nitride, gallium arsenide, and indium gallium.

The isolation layer 820 is used to realize the isolation between the source-drain doped layer 840 and the protruding portion 810, and the isolation between the gate structure 830 and the protruding portion 810, which is beneficial to preventing the parasitic devices formed by the source-drain doped layer 840, the gate structure 830 and the protruding portion 810 below the source-drain doped layer 840 and the gate structure 830, and further is beneficial to eliminating the leakage channel generated in the protruding portion 810, reducing the leakage current of the devices, and improving the performance of the semiconductor structure.

For this purpose, the material of the isolation layer 820 is an insulating material.

Specifically, the material of the isolation layer 820 includes one or more of silicon oxide, silicon oxynitride, silicon nitride, silicon carbide, silicon carbonitride oxide, boron nitride, and boron carbonitride. As an example, the material of the isolation layer 820 is silicon oxide.

In this embodiment, the isolation layer 820 includes a first region i and second regions ii located on both sides of the first region i; the first region i is located below the gate structure 830 and the source-drain doped layer 840, and the second region ii is located at two sides of the gate structure 830 and the source-drain doped layer 840.

Accordingly, in this embodiment, the isolation layer 820 includes: a first isolation layer 821 on the first region i; and a second isolation layer 822 on the second region ii.

The first isolation layer 821 is used to isolate the gate structure 830 from the protruding portion 810 and the source/drain doped layer 840 from the protruding portion 810, and the second isolation layer 822 is used to further isolate the source/drain doped layer 840 from the protruding portion 810.

In this embodiment, the materials of the first isolation layer 821 and the second isolation layer 822 are the same, and are both silicon oxide. In other embodiments, the materials of the first and second barrier layers may also be different.

In this embodiment, the first isolation layer 821 is flush with the top surface of the second isolation layer 822, so that isolation between the source-drain doped layer 840 and the raised portion 810, and isolation between the gate structure 830 and the raised portion 810 are achieved, and the channel layer 860 is exposed, which is advantageous for forming the source-drain doped layer 840 on the exposed end portion of the channel layer 860 through an epitaxial process.

In other embodiments, the top surface of the second isolation layer may also be lower than the top surface of the first isolation layer.

In this embodiment, the isolation layer 820 includes a first isolation layer 821 and a second isolation layer 822 is described as an example. In other embodiments, the isolation layer may also be an integrated structure based on actual process requirements, and the isolation layer may also achieve isolation between the gate structure and the protruding portion, and between the source/drain doped layer and the protruding portion.

In this embodiment, the filling layer 900 is located on the first area i of the isolation layer 820, so that the filling layer 900 and the first isolation layer 821 together make the space between the channel structure layer 850 and the protruding portion 810 suspended.

The gate structure 830 is located on top of the filling layer 900 and spans the filling layer 900, and the source-drain doped layer 840 is located on the filling layer 900 at two sides of the gate structure 830, and accordingly, isolation between the gate structure 830 and the protruding portion 810 and isolation between the source-drain doped layer 840 and the protruding portion 810 are achieved through the filling layer 900 and the isolation layer 820.

For this purpose, the material of the filling layer 900 is an insulating material.

Specifically, the material of the filling layer 900 includes one or more of silicon oxide, silicon oxynitride, silicon nitride, silicon carbide, silicon carbonitride oxide, boron nitride, and boron carbonitride. As an example, the material of the filling layer 900 is silicon oxide. The extending direction of the channel layer 860 is transverse, and the lateral width of the filling layer 900 between the source-drain doped layer 840 and the isolation layer 820 is not too small or too large. If the lateral width of the filling layer 900 between the source-drain doped layer 840 and the isolation layer 820 is too small, the space of the source-drain doped layer 840 is correspondingly reduced, thereby reducing the quality of the source-drain doped layer 840; if the lateral width of the filling layer 900 between the source-drain doped layer 840 and the isolation layer 820 is too large, the space of the source-drain doped layer 840 formed on the filling layer 900 is too large, thereby reducing the formation space of the interlayer dielectric layer 910 and correspondingly reducing the isolation effect of adjacent devices. For this reason, in the present embodiment, the lateral width of the filling layer 900 between the source/drain doped layer 840 and the isolation layer 820 is 5nm to 10nm.

The channel structure layer 850 is used to provide a conductive channel of a field effect transistor. In particular, the channel layer 860 is used to provide the conductive channel.

As an example, the channel structure layer 850 extends in the lateral direction. The stacking direction of the channel layer 860 is perpendicular to the surface of the substrate 800.

In this embodiment, the channel layer 860 is made of Si, which is beneficial to improving the performance of the NMOS transistor. In other embodiments, when the semiconductor structure is a PMOS transistor, siGe channel technology may be used to enhance the performance of the PMOS transistor, and the material of the channel layer is SiGe. In other embodiments, the material of the channel layer may also be one or more of germanium, silicon carbide, gallium nitride, gallium arsenide, and indium gallium arsenide.

As an example, in the channel structure layer 850, the number of the channel layers 860 is three. In other embodiments, the channel layer may be other numbers.

The insulating layer 870 is used to isolate the adjacent raised portions 810 from each other, and also to isolate the substrate 800 from the gate structure 830.

The material of the insulating layer 870 includes one or more of silicon oxide, silicon oxynitride, silicon nitride, silicon carbide, silicon carbonitride oxide, boron nitride, and boron carbonitride. As an example, the material of the insulating layer 870 is silicon oxide.

The gate structure 830 is used to control the turning on and off of the conduction channel during device operation.

In this embodiment, the gate structure 830 is a metal gate structure, and the gate structure 830 includes a gate dielectric layer (not shown), a work function layer (not shown) on the gate dielectric layer, and a gate electrode layer (not shown) on the work function layer and filled in the through-trench and the gate opening.

The gate dielectric layer is used for realizing electrical isolation between the work function layer and the gate electrode layer and the channel. The gate dielectric layer comprises silicon oxide, nitrogen doped silicon oxide and HfO ₂ 、ZrO ₂ 、HfSiO、HfSiON、HfTaO、HfTiO、HfZrO、La ₂ O ₃ And Al ₂ O ₃ One or more of the following.

As an example, the gate dielectric layer includes a high-k gate dielectric layer, and the material of the high-k gate dielectric layer is a high-k dielectric material. The material of the high-k gate dielectric layer may also be selected from ZrO ₂ HfSiO, hfSiON, hfTaO, hfTiO, hfZrO or Al ₂ O ₃ . In other embodiments, the gate dielectric layer may include a gate oxide layer and a high-k gate dielectric layer on the gate oxide layer, or the gate dielectric layer may include only the gate oxide layer.

The work function layer is used for adjusting the work function of the grid structure and further adjusting the threshold voltage of the field effect transistor. When the NMOS transistor is formed, the work function layer is an N-type work function layer, and the material of the work function layer comprises one or more of titanium aluminide, tantalum carbide, aluminum or titanium carbide; when the PMOS transistor is formed, the work function layer is a P-type work function layer, and the material of the work function layer includes one or more of titanium nitride, tantalum nitride, titanium carbide, tantalum silicon nitride, titanium silicon nitride, and tantalum carbide.

The gate electrode layer is used as an external electrode for electrically connecting the gate structure 830 to an external circuit. The material of the gate electrode layer is a conductive material including one or more of TiN, taN, ti, ta, tiAL, tiALC, tiSiN, W, co, al, cu, ag, au, pt and Ni.

In this embodiment, the gate structure 830 is taken as an example of a metal gate structure. In other embodiments, the gate structure may also be other types of gate structures based on actual process requirements, such as: is a polysilicon gate structure or an amorphous silicon gate structure.

The gate structure 830 includes: a first portion 831 located between the filling layer 900 and the channel layer 860 adjacent to the filling layer 900; a second portion 832 spans the channel structure layer 850.

In this embodiment, the semiconductor structure further includes: an inner sidewall wall 880 on a sidewall of the first portion 831 and exposing an end of each channel layer 860 of the channel structure layer 850; a gate sidewall 890 is located on the sidewall of the second portion 832 and exposes an end of each channel layer 860 in the channel structure layer 850.

The inner wall 880 is configured to isolate the source-drain doped layer 840 from the gate structure 830, and to increase the distance between the gate structure 830 and the source-drain doped layer 840, so as to reduce the parasitic capacitance between the gate structure 830 and the source-drain doped layer 840.

In this embodiment, the materials of the inner wall 880 include: one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbide or silicon oxycarbonitride, boron nitride, and boron carbonitride; as an example, the material of the inner wall 880 is silicon nitride.

The gate sidewall 890 is used for defining a formation position of the source-drain doped layer 840, and the gate sidewall 890 is also used for protecting a sidewall of the gate structure 830.

In this embodiment, the material of the gate sidewall 890 includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbide or silicon oxycarbonitride, boron nitride and boron carbonitride, and the gate sidewall 890 has a single-layer or laminated structure. As an example, the gate sidewall 890 has a single-layer structure, and the material of the gate sidewall 890 is silicon nitride.

The source-drain doped layer 840 is used as a source or drain of a field effect transistor, and the source-drain doped layer 840 is used to provide a carrier source when the field effect transistor is operated.

In this embodiment, the source-drain doped layer 840 includes a stress layer doped with ions, and the stress layer is used to provide stress to the channel region, so as to improve the mobility of carriers. Specifically, when forming the NMOS transistor, the source-drain doped layer 840 includes a stress layer doped with N-type ions, and the material of the stress layer is Si or SiC; when forming a PMOS transistor, the source drain doped layer 840 includes a stress layer doped with P-type ions, and the material of the stress layer is Si or SiGe.

In this embodiment, the semiconductor structure further includes: the interlayer dielectric layer 910 is located on the isolation layer 820 and covers the sidewalls of the gate sidewall 890 and the source-drain doped layer 840.

The interlayer dielectric layer 910 is used to isolate adjacent devices. In this embodiment, the material of the interlayer dielectric layer 910 is silicon oxide. The material of the interlayer dielectric layer 910 may also be other insulating materials.

In this embodiment, the interlayer dielectric layer 910 further covers the isolation layer 820 (i.e., the second isolation layer 822) of the second region II.

Correspondingly, the invention further provides a method for forming the semiconductor structure. Fig. 9 to 30 are schematic structural views corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention.

The method for forming the semiconductor structure of the present embodiment will be described in detail below with reference to the accompanying drawings.

Referring to fig. 9, a base is provided, which includes a substrate 100 and a plurality of protrusions 10 protruding from the substrate 100, a sacrificial layer 20, an etching stop layer 40 and a stacked structure 30 are sequentially formed on the protrusions 10, the material of the etching stop layer 40 is a semiconductor material, the stacked structure 30 includes one or a plurality of channel stacks 31 stacked sequentially from bottom to top, and each channel stack 31 includes a placeholder layer 32 and a channel layer 33 located on the placeholder layer 32.

The substrate is used for providing a process platform for subsequent processes. In this embodiment, a fully-enclosed Gate (GAA) transistor is formed as an example. In other embodiments, the formation method may also be used to form a fork gate transistor (fork gate) or a Complementary Field Effect Transistor (CFET).

In this embodiment, the substrate 100 is a silicon substrate, that is, the material of the substrate 100 is monocrystalline silicon. In other embodiments, the substrate material may be one or more of germanium, silicon carbide, gallium nitride, gallium arsenide, and indium gallium arsenide, and the substrate may be a silicon-on-insulator substrate or a germanium-on-insulator substrate, among other types of substrates.

The boss 10 stands proud of the substrate 100 so that a subsequent insulating layer can be located on the substrate 100 and around the boss 10. The raised portions 10 also serve to provide support for the channel stack 31. In this embodiment, the bump 10 and the substrate 100 are in an integral structure, and the material of the bump 10 and the material of the substrate 100 are the same, and are both silicon.

In other embodiments, the material of the protrusions may be different from the material of the substrate, and the material of the protrusions may be other suitable materials, such as: germanium, silicon carbide, gallium nitride, gallium arsenide, and indium gallium.

The sacrificial layer 20 is used to occupy space for the subsequent formation of isolation layers.

A higher selectivity between the material of the sacrificial layer 20 and the material of the bump 10 is required in order to improve the integrity of the bump 10 during the subsequent step of removing the sacrificial layer 20 to form a channel.

In this embodiment, the material of the sacrificial layer 20 is a semiconductor material, so that the sacrificial layer 20 can be formed by an epitaxial process, and the semiconductor material can be epitaxially grown on the sacrificial layer 20 on the basis of the sacrificial layer 20, so that the etching stop layer 40 can be formed on the sacrificial layer 20.

In this embodiment, the materials of the sacrificial layer 20 include: single crystal silicon, germanium, silicon carbide, gallium nitride, gallium arsenide, and indium gallium. As an example, the material of the sacrificial layer 20 is: siGe.

In this embodiment, the step of forming the sacrificial layer 20 includes: the sacrificial material layer (not shown) is formed on the boss 10. As an example, the sacrificial material layer is formed on the bump 10 using an epitaxial process.

The etching stop layer 40 is used for providing a process basis for the subsequent formation of the source/drain doped layer, and the process for forming the source/drain doped layer generally includes an epitaxial process, and in the step of forming the source/drain doped layer, besides taking the channel layer 33 as a growth basis of the epitaxial process, the etching stop layer 40 can be used as a growth basis for forming the source/drain doped layer by performing the epitaxial process, so that a process platform for performing the epitaxial process is increased, and the epitaxial quality of the source/drain doped layer is further improved.

In addition, in the subsequent step of forming the recess in the laminated structure 30, the top surface of the etching stop layer 40 serves as an etching stop position, and over etching is avoided, so that the sacrificial layer 20 located under the etching stop layer 40 is protected; and, in the subsequent step of removing the sacrificial layer, the bottom surface of the etching stop layer 40 can be used as an etching stop position, which is beneficial to reducing the probability of causing false etching to the laminated structure 30.

In this embodiment, the material of the etching stop layer 40 is a semiconductor material, so as to provide a process basis for the subsequent formation of the source-drain doped layer, and specifically, the etching stop layer 40 can be used as an epitaxial growth basis for the subsequent formation of the source-drain doped layer; in addition, the material of the etching stop layer 40 and the material of the placeholder layer 32 have a high selection ratio, so that the etching stop layer 40 can effectively protect the sacrificial layer 20 in the subsequent step of forming the groove; and in the subsequent step of removing the sacrificial layer 20, a higher selectivity is provided between the material of the etching stop layer 40 and the material of the sacrificial layer 20, and the etching stop layer 40 can effectively protect the bottom of the laminated structure 30.

As an example, when the material of the sacrificial layer 20 is SiGe, the material of the etch stop layer 40 may be Si. The sacrificial layer 20 and the spacer layer 32 have higher etching selectivity, and the etching stop layer 40 is made of the same material as the channel layer 33, so that the sacrificial layer 20 and the etching stop layer 40 can be formed by using the process of forming the channel stack 31, which is advantageous in improving the process integration and avoiding the introduction of additional material types.

The channel stack 31 provides a process basis for the subsequent formation of a suspended spaced apart channel layer 33.

Specifically, the channel layer 33 is configured to provide a conductive channel of the field effect transistor, the placeholder layer 32 is configured to support the channel layer 33, so as to provide a process foundation for a subsequent implementation of a space suspension arrangement of the channel layer 33, and the placeholder layer 32 is further configured to occupy a space position for a subsequent formation of a gate structure.

In this embodiment, an NMOS transistor is formed, the material of the channel layer 33 is Si, and the material of the placeholder layer 32 is SiGe. In the subsequent process of removing the placeholder layer 32, the etching selection of SiGe and Si is relatively high, and by setting the material of the placeholder layer 32 to SiGe and the material of the channel layer 33 to Si, the influence of the removal process of the placeholder layer 32 on the channel layer 33 can be effectively reduced, thereby improving the quality of the channel layer 33 and further being beneficial to improving the device performance.

In other embodiments, to enhance the performance of the PMOS transistor when the PMOS transistor is formed, siGe channel technology may be used, where the channel layer is SiGe and the placeholder layer is Si. In other embodiments, the material of the channel layer may also be one or more of germanium, silicon carbide, gallium nitride, gallium arsenide, and indium gallium arsenide.

As one example, the step of providing a substrate may include: providing a semiconductor layer; sequentially forming a sacrificial material layer, an etching stop material layer and one or more channel laminated films on the semiconductor layer; and sequentially patterning the channel laminated film, the etching stop material layer, the sacrificial material layer and the semiconductor layer with partial thickness, wherein the residual channel laminated film is used as the channel laminated film, the residual etching stop material layer is used as the etching stop layer, the residual sacrificial material layer is used as the sacrificial layer, and the residual semiconductor layer comprises a substrate and a protruding part.

And forming a sacrificial material layer, an etching stop material layer and one or more layers of channel laminated films in sequence by adopting an epitaxial process.

Referring to fig. 10, an insulating layer 50 surrounding the bump 10, the sacrificial layer 20, and the etch stop layer 40 is formed on the substrate 100.

The insulating layer 50 is used for isolating the adjacent protruding portions 10 from each other, and also for isolating the substrate 100 from the gate structure.

In this embodiment, a dummy gate structure is subsequently formed on the insulating layer 50 across the stacked structure 30, and grooves are formed in the stacked structure 30 on both sides of the dummy gate structure, the grooves exposing the channel layer 33. The insulating layer 50 exposes the stacked structure 30, so that the source-drain doped layer can be formed on the basis of the etching stop layer 40 as an epitaxial process, and the source-drain doped layer can be formed by epitaxial growth on the basis of the channel layer 33.

In this embodiment, the insulating layer 50 also covers the sidewalls of the sacrificial layer 20 and the etching stop layer 40, so that the insulating layer 50 can protect the sacrificial layer 20 and the etching stop layer 40 from erroneous etching caused by the sacrificial layer 20 and the etching stop layer 40 in the subsequent step of forming grooves in the stacked structure 30 on both sides of the dummy gate structure.

The material of the insulating layer 50 includes one or more of silicon oxide, silicon oxynitride, silicon nitride, silicon carbide, silicon carbonitride oxide, boron nitride, and boron carbonitride. As an example, the material of the insulating layer 50 is silicon oxide.

Referring to fig. 11, a dummy gate structure 60 is formed on the insulating layer 50 across the stacked structure 30.

The dummy gate structure 60 is used to pre-occupy a spatial location for subsequent gate structure formation.

The dummy gate structure 60 may have a stacked structure or a single layer structure. In this embodiment, the dummy gate structure 60 is a stacked structure, and includes a dummy gate oxide layer (not shown) and a dummy gate layer (not shown) on the dummy gate oxide layer.

Specifically, the dummy gate structure 60 is a polysilicon gate structure or an amorphous silicon gate structure, the material of the dummy gate oxide layer may be silicon oxide or silicon oxynitride, and the material of the dummy gate layer may be polysilicon or amorphous silicon.

Referring to fig. 12, a gate sidewall 70 is formed on the sidewall of the dummy gate structure 60.

The gate sidewall 70 is used together with the dummy gate structure 60 as an etching mask for a subsequent etching process for forming a recess, so as to define a formation position of the source-drain doped layer, and the gate sidewall 70 is also used for protecting the sidewalls of the dummy gate structure 60 and the subsequent gate structure.

In this embodiment, the material of the gate sidewall 70 includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbide or silicon oxycarbonitride, boron nitride and boron carbonitride, and the gate sidewall 70 has a single-layer or stacked-layer structure. As an example, the gate sidewall 70 has a single-layer structure, and the material of the gate sidewall 70 is silicon nitride.

Referring to fig. 13, grooves 80 are formed in the stacked structure 30 at both sides of the dummy gate structure 60, and bottoms of the grooves 80 expose the etch stop layer 40.

The recess 80 is used to provide a space for forming a source-drain doped layer.

The sidewalls of the grooves 80 expose the stacked structure 30, so that a source-drain doped layer is formed on the sidewalls of the grooves 80 exposing the channel layer 33 through an epitaxial process; and, it is convenient to remove the part of the thickness of the occupying layer 12 exposed by the side wall of the groove 80 along the extending direction of the channel layer 33, so as to form an inner groove.

In addition, in this embodiment, the bottom of the groove 80 exposes the etching stop layer 40, so that in the subsequent process of forming a protection sidewall on the sidewall of the groove 80, the protection sidewall can cover a part of the top surface of the etching stop layer 40, and a part of the etching stop layer 40 covered by the protection sidewall can be reserved in the subsequent process, so that in the subsequent step of forming a source/drain doped layer, besides taking the channel layer 20 as a growth basis of an epitaxial process, an epitaxial process can be performed on the basis of the growth of the etching stop layer 40 to form a source/drain doped layer, so that a process platform for performing the epitaxial process is increased, and further the epitaxial quality of the source/drain doped layer is improved.

In this embodiment, the bottom of the recess 80 exposes the etching stop layer 40, so that the stacked structures 30 on both sides of the dummy gate structure 60 can be etched by using the top surface of the etching stop layer 40 as an etching stop position, and the position of the bottom of the recess 80 is defined by the etching stop layer 40 correspondingly, so that the sacrificial layer 20 under the recess 80 can be retained, so that the sacrificial layer 20 can be removed later and an isolation layer is formed at the position of the sacrificial layer 20.

Specifically, in this embodiment, an anisotropic etching process (e.g., an anisotropic dry etching process) is used to etch the stacked structure 30 on both sides of the dummy gate structure 60 and the gate sidewall 70, which is beneficial to improving the profile quality of the recess 80, so as to facilitate precise control of the sidewall morphology of the recess 80.

Referring to fig. 14, the method for forming the semiconductor structure further includes: after the grooves 80 are formed in the stacked structure 30 on both sides of the dummy gate structure 60, the space occupying layer 32 is removed along the extending direction of the channel layer 33, and an inner trench 81 is formed.

The inner channel 81 provides a spatial location for the subsequent formation of the inner side wall.

In this embodiment, the vapor etching process is used to etch the placeholder layer 32 with a thickness of a sidewall portion of the recess 80 along the extending direction of the channel layer 33. The vapor etching process is an isotropic etching process, and can etch the space occupying layer 32 along the direction of the protruding portion 10, and the vapor etching process is easy to realize a larger etching selection ratio, thereby being beneficial to reducing the difficulty of etching the space occupying layer 32 and reducing the probability of damaging other film structures (such as the channel layer 33).

In this embodiment, the material of the placeholder layer 32 is SiGe, the material of the channel layer 33 is Si, and the HCl vapor is used to vapor etch the placeholder layer 32 on the sidewall of the recess 80. The etching rate of the SiGe material by the HCl vapor is much greater than that of the Si material, so that the probability of damage to the channel layer 33 can be effectively reduced.

In other embodiments, when the channel layer is SiGe, the bit is occupiedWhen the material of the layer is Si, a dry etching process can be adopted to etch the occupying layer on the side wall of the groove along the extending direction of the channel layer. The etchant of the dry etching process may include CF ₄ 、O ₂ 、N ₂ Is a mixture of plasmas of (a) and (b). The larger difference between the etching rate of Si and the etching rate of SiGe by the plasma mixture can also effectively reduce the probability of damage to the channel layer 33.

Referring to fig. 15, a protection sidewall 90 is formed on a sidewall of the recess 80, and the protection sidewall 90 covers a portion of the top surface of the etching stop layer 40.

The protection side wall 90 occupies a space position for subsequently forming the source-drain doped layer, the protection side wall 90 covers a part of the top surface of the etching stop layer 40, the etching stop layer 40 right below the bottom of the protection side wall 90 is protected, so that the etching stop layer 40 below the protection side wall 90 can be reserved in the process of subsequently removing the protection side wall 90, a process foundation is provided for subsequently forming the source-drain doped layer, a process platform for performing an epitaxial process is increased, and the epitaxial quality of the source-drain doped layer is further improved.

Furthermore, the protection sidewall 90 is used for protecting the stacked structure 30 during the subsequent removal of the sacrificial layer 20 and the etching stop layer 40, so as to reduce the damage probability of the stacked structure 30.

In addition, in the subsequent process of removing the sacrificial layer 20, the etching stop layer 40 and the sacrificial layer 20 exposed by the protection sidewall 90 may be removed first, so that the sidewall of the sacrificial layer 20 under the stacked structure 30 is exposed, so that the sacrificial layer 20 under the stacked structure 30 is removed through the exposed sidewall of the sacrificial layer 20.

The material of the protection sidewall 90 needs to have a higher selectivity to the sacrificial layer 20, so as to effectively protect the stacked structure 30 in the subsequent step of removing the sacrificial layer 20 to form a channel.

In this embodiment, the materials for protecting the side wall 90 include: one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbide or silicon oxycarbonitride, boron nitride, and boron carbonitride; as an example, the material of the protection sidewall 90 is silicon nitride.

It should be noted that the thickness of the protection sidewall 90 should not be too small or too large. If the thickness of the protection sidewall 90 is too small, the area of the etching stop layer 40 exposed subsequently is too small, which may cause the growth foundation for forming the source-drain doped layer subsequently to be too small, so as to reduce the process platform during the epitaxy process, and further reduce the epitaxy quality of the source-drain doped layer; if the thickness of the protection sidewall 90 is too large, the area of the etching stop layer 40 exposed subsequently is too large, so that the growth foundation for forming the source-drain doped layer is too large, and the formation space of the interlayer dielectric layer subsequently is reduced, and accordingly, the isolation effect of the adjacent devices is reduced. For this reason, in this embodiment, the thickness of the protection sidewall 90 is 5nm to 10nm.

In this embodiment, in the step of forming the protection sidewall 90, the protection sidewall 90 is further filled in the inner trench 81, so that in the subsequent step of removing the protection sidewall 90 located on the sidewall of the channel layer 33, the remaining protection sidewall 90 filled in the inner trench 81 is reserved for being used as the inner sidewall 91, and further the process steps of forming the protection sidewall 90 and removing the sacrificial layer 20 can be integrated with the process of forming the inner sidewall 91, thereby improving the process integration degree and the process compatibility, and further being beneficial to simplifying the process flow.

In this embodiment, the protection sidewall 90 is formed on the sidewall of the gate sidewall 70.

Specifically, in this embodiment, the step of forming the protection sidewall 90 includes: forming a protective material layer (not shown) on the sidewalls of the gate sidewall 70, on the top of the dummy gate structure 60, on the top of the insulating layer 50, and on the top of the etch stop layer 40; a portion of the protective material layer on both sides of the dummy gate structure 60 is remained, the protective material layer on top of the dummy gate structure 60, the insulating layer 50 and the etch stop layer 40 is removed, and the protective material layer on the sidewall of the gate sidewall 70 remains as the protective sidewall 90.

As an example, the protective material layer is formed by an atomic layer deposition process (Atomic Layer Deposition, ALD). The atomic layer deposition process can accurately control the thickness of the protective material layer on the atomic layer level, form a high-quality protective material layer and improve the step coverage capability of the protective material layer.

As an example, the protective material layer on top of the dummy gate structure 60, the insulating layer 50 and the etch stop layer 40 is removed by an anisotropic etching process, and the protective material layer on the sidewalls of the gate sidewall 70 remains as the protective sidewall 90. And an anisotropic etching process (such as an anisotropic dry etching process) is adopted to etch the protective material layers on the side walls on both sides of the dummy gate structure 60, so as to facilitate precise control of the side wall morphology of the protective side wall 90.

Referring to fig. 16, the etching stop layer 40 exposed by the protection sidewall 90 is removed, and the top surface of the sacrificial layer 20 is exposed, so that the etching stop layer 40 is subsequently removed.

Specifically, with the protective sidewall 90 as a mask, the etching stop layer 40 at the bottom of the recess 80 is removed in a direction perpendicular to the surface of the substrate 100 by using an anisotropic etching process, so as to expose the top surface of the sacrificial layer 20.

As an example, the etching stop layer 40 at the bottom of the recess 80 is removed using an anisotropic dry etching process, exposing the top surface of the sacrificial layer 20. The dry etching process has high process controllability and can accurately control the removal thickness.

In other embodiments, other types of anisotropic etching processes (e.g., anisotropic wet etching processes) may be used to remove the etch stop layer 40 at the bottom of the recess.

With continued reference to fig. 16 and 17, the sacrificial layer 20 is removed, and a channel 110 is formed between the etch stop layer 40 and the bump 10 and below the recess 80, the channel 110 being surrounded by the insulating layer 50, the bump 10 and the etch stop layer 40.

The channel 110 is located between the etch stop layer 40 and the bump 10 and below the recess 80, so that an isolation layer subsequently formed in the channel 110 can be located between the etch stop layer 40 and the bump 10 and below the recess 80, so that after forming a source-drain doped layer on the etch stop layer 40 and replacing the placeholder layer 32 with a gate structure, the isolation layer can realize isolation between the source-drain doped layer and the bump 10 and between the gate structure and the bump 10.

The step of removing the sacrificial layer 40 and forming the channel 110 in this embodiment will be described in detail with reference to the accompanying drawings.

As shown in fig. 16, the sacrificial layer 20 at the bottom of the recess 80 is removed.

Specifically, in this embodiment, an anisotropic etching process is used to remove the sacrificial layer 20 at the bottom of the recess 80.

Specifically, with the protective sidewall 90 as a mask, an anisotropic etching process is adopted to remove the sacrificial layer 20 located at the bottom of the recess 80 along a direction perpendicular to the surface of the substrate 100, which is favorable for preventing etching of the etching stop layer 40 located below the stacked structure 30, so that the etching stop layer 40 located below the stacked structure 30 can be retained, so that in a subsequent step of removing the sacrificial layer 20 located below the stacked structure 30, the etching stop layer 40 located below the stacked structure 30 can play a role of defining an etching stop position, thereby protecting the stacked structure 30 and reducing the damage probability of the stacked structure 30.

As an example, the sacrificial layer 20 at the bottom of the recess 80 is removed using an anisotropic dry etching process. The dry etching process has high process controllability and can accurately control the removal thickness.

In other embodiments, other types of anisotropic etching processes may be used to remove the sacrificial layer at the bottom of the recess, for example: an anisotropic wet etching process.

As shown in fig. 17, the sacrificial layer 20 located under the laminated structure 30 is removed.

In this embodiment, an isotropic etching process is used to remove the sacrificial layer 20 under the stacked structure 30. Specifically, in this embodiment, an isotropic dry etching process is used to remove the sacrificial layer 20 under the stacked structure 30. The use of an isotropic dry etch process facilitates subsequent removal of reactive impurities and ensures cleaning of the channel 110.

In this embodiment, in the process of removing the sacrificial layer 20 below the stacked structure 30, the etching stop layer 40 above the sacrificial layer 20 can define the position of etching stop, so as to protect the bottom of the stacked structure 30.

Referring to fig. 18 to 20, a spacer 120 is formed within the channel 110.

The isolation layer 120 is used to isolate the source-drain doped layer from the raised portion 10 and isolate the gate structure from the raised portion 10, which is beneficial to preventing the parasitic device from being formed by the source-drain doped layer, the gate structure and the raised portion 10 below the source-drain doped layer and the gate structure, and further to eliminate the leakage channel generated in the raised portion 10, thereby reducing the leakage current of the device and improving the performance of the semiconductor structure. In addition, the spacer 120 provides a process basis for the subsequent formation of the channel.

For this purpose, the material of the isolation layer 120 is an electrically insulating material. Specifically, the material of the isolation layer 120 includes one or more of silicon oxide, silicon oxynitride, silicon nitride, silicon carbide, silicon carbonitride oxide, boron nitride, and boron carbonitride; as an example, the material of the isolation layer 120 is silicon oxide.

The step of forming the isolation layer 120 according to this embodiment will be described in detail with reference to the accompanying drawings.

As shown in fig. 18, a first isolation layer 121 is filled in the channel 110 between the etch stop layer 40 and the bump 10.

The first isolation layer 121 is used for isolating the gate structure from the protruding portion 10 and the source-drain doped layer from the protruding portion 10.

In this embodiment, the step of forming the first isolation layer 121 includes: forming a first isolation material layer (not shown) in the channel 110 between the etch stop layer 40 and the bump 10; the first isolation material layer at the bottom of the recess 80 is removed, and the remaining first isolation material layer filled under the stacked structure 30 is used as a first isolation layer 121.

Specifically, a first isolation material layer (not shown) is deposited by chemical vapor deposition (Chemical Vapor Deposition, CVD) within the channel 110 between the etch stop layer 40 and the boss 10; the first layer of isolation material at the bottom of the recess 80 is removed using an isotropic etching process.

In this embodiment, in the step of forming the first isolation layer 121, the protection sidewall 90 may protect the channel layer on the sidewall of the groove 80, so as to reduce the probability of damage to the channel layer.

As shown in fig. 20 to 21, a second isolation layer 122 is formed in the channel 110 at both sides of the gate structure, and the second isolation layer 122 and the first isolation layer 121 are in contact to constitute the isolation layer 120.

The second isolation layer 122 is used for further isolating the source-drain doped layer from the protruding portion 10.

Specifically, in the present embodiment, the step of forming the second isolation layer 122 includes: as shown in fig. 20, a second isolation material layer 123 is formed on the exposed protrusion 10 and the insulating layer 50, the second isolation material layer 123 covering the sidewalls of the gate sidewall 70 and the sidewalls of the etch stop layer 40 and filling the channel 110; as shown in fig. 21, the second isolation material layer 123 located at a partial thickness on the protrusion 10 and the second isolation material layer located on the insulating layer 50 are removed, and the second isolation material layer 123 remaining filled in the channel 110 is used as the second isolation layer 122.

Wherein forming the second isolation material layer 123 includes: depositing a barrier film (not shown) on the exposed convex portion 10 and the insulating layer 50; the isolation film is planarized with a hard mask layer (not shown) on top of the dummy gate structure 60 as a stop position, and the isolation film under the hard mask layer on top of the dummy gate structure 60 remains as the second isolation material layer 123 over the bump 10 and the insulating layer 50.

In this embodiment, a barrier film is deposited on the exposed protrusion 10 and the insulating layer 50 by a chemical vapor deposition process; the planarization process is performed using a chemical mechanical polishing (Chemical Mechanical Polishing, CMP) process.

In this embodiment, an anisotropic etching process is used to remove a portion of the thickness of the second isolation material layer 123 on the insulating layer 50 and on the protruding portion 10.

As an example, the second isolation material layer 123 is etched using an anisotropic dry etching process. The anisotropic dry etching process is advantageous in precisely controlling the removal thickness of the second insulating material layer 123.

In this embodiment, the top surface of the second isolation layer 122 is flush with the etching stop layer 40.

Note that, referring to fig. 19, the protection sidewall 90 on the sidewall of the channel layer 33 is removed, and the sidewall of the channel layer 33 and the etching stop layer 40 on both sides of the dummy gate structure 60 are exposed.

And removing the protection side wall 90 on the channel layer 33 on the side wall of the groove to expose the channel layer 33, so that in the subsequent step of forming a source-drain doped layer, besides taking the channel layer 33 as a growth basis of an epitaxial process, the etching stop layer 40 can be used as a growth basis to form a source-drain doped layer by an epitaxial process, a process platform in the process of carrying out the epitaxial process is increased, and further the epitaxial quality of the source-drain doped layer is improved.

Specifically, in this embodiment, after the first isolation layer 121 is formed, the protection sidewall 90 on the sidewall of the channel layer 33 is removed before the second isolation layer 122 is formed.

In this embodiment, the method for forming a semiconductor structure further includes: in the step of removing the protection sidewall 90 on the sidewall of the channel layer, the remaining protection sidewall 90 filled in the inner trench 81 is reserved for being used as an inner sidewall 91.

In the step of forming the protection sidewall 90, the protection sidewall 90 is further filled in the inner trench 81, so that in the step of removing the protection sidewall 90 located on the channel layer 33 of the sidewall of the recess 80 after the sacrificial layer 20 is removed, the protection sidewall 90 filled in the inner trench 81 can be used as an inner sidewall 91, and further, the process steps of forming the protection sidewall 90 and removing the sacrificial layer 20 can be integrated with the process of forming the inner sidewall 91, thereby improving the process integration degree and the process compatibility, and also facilitating the simplification of the process flow.

The inner sidewall 91 is used for realizing isolation between the source-drain doped layer and the gate structure, and can increase the distance between the gate structure and the source-drain doped layer, thereby being beneficial to reducing parasitic capacitance between the gate structure and the source-drain doped layer.

Accordingly, in this embodiment, the material of the inner side wall 91 is the same as the material of the protection side wall 90.

Specifically, an isotropic etching process is adopted to etch the protection sidewall 90 located at the outer side of the channel layer 33, so as to expose the channel layer 33. The isotropic etching process may be an isotropic dry etching process.

Referring to fig. 22, source-drain doped layers 130 are formed on the etch stop layer 40 at both sides of the dummy gate structure 60, and the source-drain doped layers 130 are in contact with the ends of the channel layer 33 in the extending direction.

The source-drain doped layer 130 is used as a source or a drain of the field effect transistor, and the source-drain doped layer 130 is used for providing a carrier source when the field effect transistor works.

The source/drain doped layer 130 uses the channel layer as a growth base of an epitaxial process, and uses the etching stop layer 40 as a growth base, so that a process platform for performing the epitaxial process is increased, and further, the epitaxial quality of the source/drain doped layer 130 is improved. In addition, the source-drain doped layer 130 is suspended on the protruding portion 10, so that isolation between the source-drain doped layer and the protruding portion 10 can be achieved.

In this embodiment, the source-drain doped layer 130 includes a stress layer doped with ions, and the stress layer is used to provide stress to the channel region, so as to improve the mobility of carriers. Specifically, when forming the NMOS transistor, the source-drain doped layer 130 includes a stress layer doped with N-type ions, and the material of the stress layer is Si or SiC; when forming a PMOS transistor, the source drain doped layer 130 includes a stress layer doped with P-type ions, and the material of the stress layer is Si or SiGe.

In this embodiment, an epitaxial process is used to form a stress layer, and ions are self-doped in situ during the process of forming the stress layer, and the stress layer doped with ions is used as the source/drain doped layer 130.

Referring to fig. 23 to 24, the etching stop layer 40 is removed to form a trench 180, where the trench 180 is surrounded by the isolation layer 120, the insulating layer 50, the stacked structure 30, and the source-drain doped layers 130 located at two sides of the stacked structure 30, and the stacked structure 30 and the source-drain doped layers 130 are suspended above the isolation layer 120.

The trenches 180 are used to provide spatial locations for the subsequent formation of a fill layer.

Specifically, the trench 180 is located under the stacked structure 30 and the source-drain doped layer 130, so that the filling layer subsequently formed in the trench 180 can be located under the stacked structure 30 and the source-drain doped layer 130, so that after the space occupying layer 32 is subsequently replaced with a gate structure, the filling layer and the isolation layer 120 can realize isolation between the source-drain doped layer 130 and the bump 10, and between the gate structure and the bump 10.

The step of removing the etching stop layer 40 and forming the trench 180 according to this embodiment will be described in detail with reference to the accompanying drawings.

As shown in fig. 23, the insulating layer 50 and the isolation layer 120 are removed to expose the sidewalls of the etch stop layer 40 by removing the exposed portions of the dummy gate structure 60 and the source/drain doped layer 130.

Specifically, in this embodiment, an anisotropic etching process is used to remove the thickness of the insulating layer 50 and the isolation layer 120 from the exposed portions of the dummy gate structure 60 and the source-drain doped layer 130, which is favorable to prevent the insulating layer 50 located below the dummy gate structure 60 from being etched by mistake, so that the insulating layer 50 located below the dummy gate structure 60 can play a sufficient supporting role on the dummy gate structure 60.

As an example, the insulating layer 50 and the isolation layer 120 are removed by using an anisotropic dry etching process to remove the exposed portions of the dummy gate structure 60 and the source/drain doped layer 130. The anisotropic dry etching process facilitates precise control of the removal thickness of the insulating layer 50 and the isolation layer 120.

In other embodiments, other types of anisotropic etching processes may be used, while removing the etch stop layer and the sacrificial layer at the bottom of the recess, for example: an anisotropic wet etching process.

As shown in fig. 24, the trench 180 is formed by removing the etch stop layer 40 through the exposed sidewall of the etch stop layer 40.

The material of the insulating layer 50 and the material of the etch stop layer 40 have a high selectivity, which is advantageous in preventing erroneous etching of the insulating layer 50 under the dummy gate structure 60 and protecting the insulating layer 50 under the dummy gate structure 60.

In this embodiment, an isotropic etching process is used to selectively etch the etching stop layer 40 under the source/drain doped layer 130. As an example, the subsequent removal of reactive impurities using an isotropic dry etch process is advantageous to ensure cleaning of the trench 180.

Referring to fig. 25, a filling layer 200 is formed within the trench 180.

The filling layer 200 is located between the stacked structure 30 and the isolation layer 120, and between the source/drain doped layer 130 and the isolation layer 120, so that after the space-occupying layer 32 is replaced by a gate structure, the filling layer 200 and the first isolation layer 121 jointly achieve isolation between the source/drain doped layer 130 and the protruding portion 10, and between the gate structure and the protruding portion 10.

Specifically, the material of the filling layer 200 includes one or more of silicon oxide, silicon oxynitride, silicon nitride, silicon carbide, silicon carbonitride oxide, boron nitride, and boron carbonitride. As an example, the material of the filling layer 200 is silicon oxide.

In this embodiment, the step of forming the filling layer 200 includes: a filling material layer (not shown) is formed in the trench 180, the filling material layers located at both sides of the source/drain doped layer 130 are removed, and the filling material layers filled under the stacked structure 30 and the source/drain doped layer 130 remain as the filling layer 200.

Specifically, in the present embodiment, the filler material layer is formed by a chemical vapor deposition (Chemical Vapor Deposition, CVD) process.

In this embodiment, the source/drain doped layer 130 is used as a mask, and an anisotropic etching process is used to remove the filling material layers on two sides of the source/drain doped layer 130 along the direction perpendicular to the surface of the substrate 100.

As an example, the filling material layer located at both sides of the source and drain doped layer 130 is removed using an anisotropic dry etching process. The dry etching process has high process controllability and can accurately control the removal thickness.

In this embodiment, in the step of forming the filling layer 200, the gate sidewall 70 can protect the channel layer 33 on the sidewall of the recess 80, so as to reduce the probability of damage to the channel layer 33.

Referring to fig. 26 and 27, fig. 26 is a perspective view, and fig. 27 is a cross-sectional view of fig. 26 along the X-X direction, the method for forming the semiconductor structure further includes: after the filling layer 200 is formed, an interlayer dielectric layer 170 is formed on the isolation layer 120 and the insulating layer 50 at the side of the dummy gate structure 60 to cover the source/drain doped layer 130.

Specifically, the interlayer dielectric layer 170 covers the sidewall of the gate sidewall 70 and the source-drain doped layer 130. The interlayer dielectric layer 170 is used for isolating adjacent devices, and is also used for supporting the channel layer 33 during the subsequent removal of the dummy gate structure 60 and the removal of the placeholder layer 32, so as to realize suspended spacing arrangement of the channel layer 33.

In this embodiment, the material of the interlayer dielectric layer 170 is silicon oxide. The material of the interlayer dielectric layer 170 may also be other insulating materials.

In this embodiment, the interlayer dielectric layer 170 also exposes the top of the dummy gate structure 60, so as to facilitate the subsequent removal of the dummy gate structure 60.

In this embodiment, the interlayer dielectric layer 170 further covers the isolation layer 120 (i.e., the second isolation layer 122) of the second region II.

Referring to fig. 28 and 29, fig. 28 is a perspective view, fig. 29 is a cross-sectional view of fig. 28 along the X-X direction, the dummy gate structure 60 is removed, and a gate opening 140 is formed to expose the stacked structure 30.

The gate openings 140 are used to provide spatial locations for forming gate structures. The gate opening 140 exposes the stack structure 30 to facilitate subsequent removal of the placeholder layer 32 in the channel stack 31 through the gate opening 140.

In this embodiment, the gate opening 140 spans the stacked structure 30, and the gate opening 140 is located in the interlayer dielectric layer 170.

With continued reference to fig. 28 and 29, the gate opening 140 is used to remove the placeholder layer 32, so as to form a through groove 160, where the through groove 160 is surrounded by the adjacent channel layer 33, or is surrounded by the channel layer 33 and the isolation layer 120.

The through slots 160 and the gate openings 140 together provide a spatial location for forming a gate structure. The through slot 160 communicates with the gate opening 140.

The spacer layer 32 is removed after the source-drain doped layer 130 is formed, so that after the spacer layer 32 is removed, two ends of the channel layer 33 are connected with the source-drain doped layer 130 along the direction of the protruding portion 10, and the channel layer 33 is suspended in the gate opening 140, so that the channel layer 33 can be surrounded by a subsequent gate structure.

In this embodiment, a vapor etching process is used to remove the placeholder layer 32. Specifically, the material of the channel layer 33 is Si, and the material of the placeholder layer 32 is SiGe, so that the placeholder layer 32 exposed by the HCl vapor removing gate opening 140 has a high etching selectivity ratio between SiGe and Si, which is beneficial to improving the removal efficiency of the placeholder layer 32 and reducing the probability of damage to the channel layer 33.

Referring to fig. 30 and 31, fig. 30 is a perspective view, and fig. 31 is a sectional view of fig. 30 taken along the X-X direction. A gate structure 150 is filled in the gate opening 140 and the via 160, the gate structure 150 surrounds the channel layer 33, and the gate structure 150 is further located on top of the filling layer 200 and spans the filling layer 200.

The gate structure 150 is used to control the turning on and off of the conduction channel during operation of the device.

The gate structure 150 is further located on top of the filling layer 200 and spans the filling layer 200, so that isolation between the gate structure 150 and the bump 10 is achieved through the filling layer 200, and further the gate structure 150 and the bump 10 are prevented from forming parasitic devices, accordingly leakage channels generated in the bump 10 are prevented, and performance of the semiconductor structure is optimized.

In this embodiment, the gate structure 150 is a metal gate structure, and the gate structure 150 includes a gate dielectric layer (not shown), a work function layer (not shown) on the gate dielectric layer, and a gate electrode layer (not shown) on the work function layer and filled in the through-trench 160 and the gate opening 140.

For gate dielectric layersElectrical isolation between the work function layer and the gate electrode layer and the conductive channel is achieved. The gate dielectric layer comprises silicon oxide, nitrogen doped silicon oxide and HfO ₂ 、ZrO ₂ 、HfSiO、HfSiON、HfTaO、HfTiO、HfZrO、La ₂ O ₃ And Al ₂ O ₃ One or more of the following.

In this embodiment, the gate dielectric layer includes a high-k gate dielectric layer, and the material of the high-k gate dielectric layer is a high-k dielectric material. The material of the high-k gate dielectric layer may be selected from ZrO ₂ HfSiO, hfSiON, hfTaO, hfTiO, hfZrO or Al ₂ O ₃ . In other embodiments, the gate dielectric layer may further include a gate oxide layer and a high-k gate dielectric layer located on the gate oxide layer, or the gate dielectric layer may include only the gate oxide layer.

The work function layer is used to adjust the work function of the gate structure 150 and thus the threshold voltage of the field effect transistor. When the NMOS transistor is formed, the work function layer is an N-type work function layer, and the material of the work function layer comprises one or more of titanium aluminide, tantalum carbide, aluminum or titanium carbide; when the PMOS transistor is formed, the work function layer is a P-type work function layer, and the material of the work function layer includes one or more of titanium nitride, tantalum nitride, titanium carbide, tantalum silicon nitride, titanium silicon nitride, and tantalum carbide.

The gate electrode layer serves as an external electrode for electrically connecting the gate structure 150 to an external circuit. The material of the gate electrode layer is a conductive material including one or more of TiN, taN, ti, ta, tiAL, tiALC, tiSiN, W, co, al, cu, ag, au, pt and Ni.

In this embodiment, the gate structure 150 is taken as an example of a metal gate structure. In other embodiments, the gate structure may also be other types of gate structures based on actual process requirements, such as: is a polysilicon gate structure or an amorphous silicon gate structure.

Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.

Claims

1. A semiconductor structure, comprising:

a substrate;

a plurality of protruding portions protruding from the substrate;

the isolation layer is positioned on the protruding part and comprises a first area and second areas positioned on two sides of the first area along the extending direction of the protruding part;

a fill layer located on the first region of the isolation layer;

The channel structure layer is positioned above the filling layer and is suspended in the air at intervals with the filling layer, and comprises one or more channel layers which are sequentially arranged at intervals, and the channel layers are stacked along the direction vertical to the surface of the substrate;

an insulating layer on the substrate and surrounding the protrusion, the isolation layer and the filling layer, the insulating layer covering sidewalls of the isolation layer and the filling layer and exposing the channel structure layer;

a gate structure on the insulating layer and crossing the channel structure layer and surrounding the channel layer, the gate structure also being on top of and crossing the fill layer;

the source-drain doping layers are positioned on the filling layers at two sides of the grid structure and are in contact with the end parts of each channel layer in the channel structure layer along the extending direction.

2. The semiconductor structure of claim 1, wherein the gate structure comprises: a first portion located between the filling layer and a channel layer adjacent to the filling layer or between adjacent ones of the channel structure layers; a second portion crossing the channel structure layer;

The semiconductor structure further includes: the inner side wall is positioned on the side wall of the first part and exposes the end part of each channel layer in the channel structure layer; and the grid side wall is positioned on the side wall of the second part and exposes the end part of each channel layer in the channel structure layer.

3. The semiconductor structure of claim 2, wherein the material of the interior sidewall wall comprises one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbide or silicon oxycarbonitride, boron nitride, and boron carbonitride;

the material of the grid side wall comprises one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbide or silicon oxycarbonitride, boron nitride and boron carbonitride.

4. The semiconductor structure of claim 1, wherein the material of the substrate comprises one or more of monocrystalline silicon, germanium, silicon carbide, gallium nitride, gallium arsenide, and indium gallium arsenide;

the material of the protruding part comprises one or more of monocrystalline silicon, germanium, silicon carbide, gallium nitride, gallium arsenide and indium gallium;

the material of the isolation layer comprises one or more of silicon oxide, silicon oxynitride, silicon nitride, silicon carbide, silicon carbonitride oxide, boron nitride and boron carbonitride;

The material of the filling layer comprises one or more of silicon oxide, silicon oxynitride, silicon nitride, silicon carbide, silicon carbonitride oxide, boron nitride and boron carbonitride;

the material of the channel structure layer comprises one or more of monocrystalline silicon, germanium, silicon carbide, gallium nitride, gallium arsenide and indium gallium;

the material of the insulating layer comprises one or more of silicon oxide, silicon oxynitride, silicon nitride, silicon carbide, silicon carbonitride oxide, boron nitride and boron carbonitride.

5. The semiconductor structure of claim 1, wherein the gate structure comprises a gate dielectric layer and a gate electrode layer on the gate dielectric layer.

6. The semiconductor structure of claim 5, wherein the gate dielectric layer material comprises one or more of silicon oxide, silicon oxynitride, hfO2, zrO2, hfSiO, hfSiON, hfTaO, hfTiO, hfZrO, la O3, and Al2O 3;

the material of the gate electrode layer includes one or more of TiN, taN, ti, ta, tiAL, tiALC, tiSiN, W, co, al, cu, ag, au, pt and Ni.

7. The semiconductor structure of claim 1, wherein an extension direction of the channel layer is lateral, and a lateral width of the filling layer between the source-drain doped layer and the isolation layer is 5nm to 10nm.

8. A method of forming a semiconductor structure, comprising:

providing a substrate, wherein the substrate comprises a substrate and a plurality of protruding parts protruding out of the substrate, a sacrificial layer, an etching stop layer and a laminated structure are sequentially formed on the protruding parts, the etching stop layer is made of a semiconductor material, the laminated structure comprises one or a plurality of channel laminated layers which are sequentially stacked from bottom to top, and each channel laminated layer comprises a space occupying layer and a channel layer positioned on the space occupying layer;

forming an insulating layer surrounding the bump, the sacrificial layer, and the etch stop layer on the substrate;

forming a dummy gate structure on the insulating layer across the stacked structure;

forming grooves in the laminated structures at two sides of the pseudo gate structure, wherein the bottoms of the grooves expose the etching stop layer;

forming a protection side wall on the side wall of the groove, wherein the protection side wall covers part of the top surface of the etching stop layer;

removing the etching stop layer exposed by the protection side wall, and exposing the top surface of the sacrificial layer;

removing the sacrificial layer, and forming a channel between the etching stop layer and the protruding part and below the groove, wherein the channel is surrounded by the insulating layer, the protruding part and the etching stop layer;

Forming an isolation layer within the channel;

removing the protection side wall on the side wall of the channel layer, exposing the side wall of the channel layer and the etching stop layers on two sides of the pseudo gate structure;

forming source-drain doped layers on the etching stop layers at two sides of the pseudo gate structure, wherein the source-drain doped layers are in contact with the end parts of the channel layer along the extending direction;

removing the etching stop layer to form a groove, wherein the groove is surrounded by the isolation layer, the insulating layer, the laminated structure and source-drain doping layers positioned on two sides of the laminated structure, and the laminated structure and the source-drain doping layers are suspended on the isolation layer;

forming a filling layer in the groove;

removing the dummy gate structure after the filling layer is formed, forming a gate opening, and exposing the laminated structure;

removing the occupying layer through the grid opening to form a through groove, wherein the through groove is surrounded by adjacent channel layers or is surrounded by the channel layers and the filling layer;

and filling a gate structure in the gate opening and the through groove, wherein the gate structure surrounds the channel layer, and the gate structure is also positioned on the top of the filling layer and spans the filling layer.

9. The method of forming a semiconductor structure of claim 8, wherein the process of forming the etch stop layer comprises: and (5) an epitaxial process.

10. The method of claim 8, wherein in the step of forming the protective sidewall, a thickness of the protective sidewall is 5nm to 10nm.

11. The method of forming a semiconductor structure of claim 8, further comprising: and after the source-drain doped layer is formed, removing the insulating layer and the isolating layer in the thickness of the exposed parts of the dummy gate structure and the source-drain doped layer before removing the sacrificial layer, and exposing the side wall of the etching stop layer.

12. The method of forming a semiconductor structure of claim 8, wherein the etch stop layer is removed using an isotropic etching process.

13. The method of forming a semiconductor structure of claim 8, wherein the material of the etch stop layer comprises: single crystal silicon, germanium, silicon carbide, gallium nitride, gallium arsenide, and indium gallium.

14. The method of forming a semiconductor structure of claim 8, wherein removing the sacrificial layer comprises: removing the sacrificial layer at the bottom of the groove; and removing the sacrificial layer positioned below the laminated structure after removing the sacrificial layer positioned at the bottom of the groove.

15. The method of claim 14, wherein the sacrificial layer at the bottom of the recess is removed using an anisotropic etching process;

and removing the sacrificial layer positioned below the laminated structure by adopting an isotropic etching process.

16. The method of forming a semiconductor structure of claim 8, further comprising: after forming grooves in the laminated structures at two sides of the pseudo gate structure and before forming the protection side wall, removing the occupying layer with the thickness of part exposed by the side wall of the groove along the extending direction of the channel layer to form an inner groove;

in the step of forming the protection side wall, the protection side wall is also filled in the inner groove;

the method for forming the semiconductor structure further comprises the following steps: and in the step of removing the protection side wall on the side wall of the channel layer, reserving the rest protection side wall filled in the inner groove for serving as an inner side wall.

17. The method of forming a semiconductor structure of claim 8, wherein the step of forming the isolation layer comprises: filling a first isolation layer in a channel between the etching stop layer and the convex part; and forming a second isolation layer in the channels at two sides of the grid structure, wherein the second isolation layer is in contact with the first isolation layer and is used for forming the isolation layer.

18. The method of forming a semiconductor structure of claim 8, wherein forming the fill layer comprises: and forming a filling material layer in the groove, removing the filling material layers positioned on two sides of the source-drain doped layer, and taking the filling material layer which is filled below the laminated structure and the source-drain doped layer as a filling layer.

19. The method of forming a semiconductor structure of claim 18, wherein removing said fill material layer on both sides of said source drain doped layer comprises: an isotropic etching process.