CN117012820A

CN117012820A - Semiconductor structure and forming method thereof

Info

Publication number: CN117012820A
Application number: CN202210461328.8A
Authority: CN
Inventors: 李政宁; 张海洋; 涂武涛; 柯星; 赵振阳
Original assignee: Semiconductor Manufacturing International Shanghai Corp
Current assignee: Semiconductor Manufacturing International Shanghai Corp
Priority date: 2022-04-28
Filing date: 2022-04-28
Publication date: 2023-11-07

Abstract

A semiconductor structure and a method of forming the same, the semiconductor structure comprising: the substrate comprises a substrate and a fin part protruding out of the substrate; the channel structure layer is suspended above the fin part and comprises one or more channel layers which are sequentially arranged at intervals along the direction vertical to the surface of the substrate; a gate structure located above the fin, the gate structure crossing the channel structure layer and surrounding the channel layer; the grid side walls cover the side walls of the grid structure, a preset distance is reserved between the outer side walls of the grid side walls on the same grid structure side wall along the direction perpendicular to the side walls of the grid structure, and the length of a channel layer covered by the grid structure is smaller than the preset distance; the source-drain doping layers are positioned on fin parts at two sides of the grid structure and are contacted with the end parts of each channel layer in the channel structure layer along the extending direction; and the inner side wall is positioned between the grid structure below the channel layer and the source-drain doped layer. The embodiment of the invention is beneficial to improving the performance of the semiconductor structure.

Description

Semiconductor structure and forming method thereof

Technical Field

Embodiments of the present disclosure relate to semiconductor manufacturing, and more particularly, to a semiconductor structure and a method for forming the same.

Background

With the rapid development of semiconductor manufacturing technology, semiconductor devices are being developed toward higher element density and higher integration, and the development trend of semiconductor process nodes following moore's law is continuously decreasing. Transistors are currently being widely used as the most basic semiconductor devices, and therefore, as the element density and integration level of the semiconductor devices are improved, the channel length of the transistors has to be continuously shortened in order to accommodate the reduction of process nodes.

To better accommodate the scaling requirements of device sizes, semiconductor processes are increasingly beginning to transition from planar transistors to three-dimensional transistors with higher power, such as Gate-all-around (GAA) transistors. In the fully-enclosed gate transistor, the gate encloses the region where the channel is located from the periphery, and compared with a planar transistor, the gate of the fully-enclosed gate transistor has stronger control capability on the channel and can better inhibit the short channel effect.

However, the performance of the fully-surrounding gate transistor is still to be improved.

Disclosure of Invention

The embodiment of the invention solves the problem of providing a semiconductor structure and a forming method thereof, and reduces leakage current of a device, thereby improving performance of the semiconductor structure.

To solve the above problems, an embodiment of the present invention provides a semiconductor structure, including: the substrate comprises a substrate and a fin part protruding out of the substrate; the channel structure layer is suspended above the fin part and comprises one or more channel layers which are sequentially arranged at intervals along the direction vertical to the surface of the substrate; a gate structure located above the fin, the gate structure crossing the channel structure layer and surrounding the channel layer; the grid side walls cover the side walls of the grid structure, a preset distance is reserved between the outer side walls of the grid side walls on the same grid structure side wall along the direction perpendicular to the side walls of the grid structure, and the length of a channel layer covered by the grid structure is smaller than the preset distance; the source-drain doping layers are positioned on fin parts at two sides of the grid structure and are contacted with the end parts of each channel layer in the channel structure layer along the extending direction; and the inner side wall is positioned between the grid structure below the channel layer and the source-drain doped layer.

Correspondingly, the embodiment of the invention also provides a method for forming the semiconductor structure, which comprises the following steps: providing a substrate, wherein the substrate comprises a substrate, a discrete fin part protruding from the substrate and a laminated structure positioned on the fin part, the laminated structure comprises one or more channel laminated layers which are sequentially stacked from bottom to top, each channel laminated layer comprises a space occupying layer and a channel layer positioned on the space occupying layer, a pseudo gate structure is formed on the fin part, the pseudo gate structure spans the laminated structure, the pseudo gate structure covers part of top wall and part of side wall of the laminated structure, and a grid side wall is formed on the side wall of the pseudo gate structure; forming grooves penetrating through the laminated structure on two sides of the pseudo gate structure; removing the occupying layer with partial width exposed from the side wall of the groove along the extending direction of the channel layer to form an inner groove; forming an inner side wall in the inner groove; after the inner side wall is formed, removing part of the channel layer along the extending direction of the channel layer; after removing part of the length of the channel layer, forming a source-drain doping layer in the groove, wherein the source-drain doping layer is contacted with the end part of the channel layer along the extending direction; removing the pseudo gate structure after forming the source-drain doped layer to form a gate opening; removing the occupying layer through the gate opening to form a through groove, wherein the through groove is surrounded by the adjacent channel layers or is surrounded by the adjacent channel layers and the fin parts; a gate structure is formed within the gate opening and the via, the gate structure surrounding the channel layer.

Compared with the prior art, the technical scheme of the embodiment of the invention has the following advantages:

according to the semiconductor structure provided by the embodiment of the invention, the preset distance is reserved between the outer side walls of the grid side walls on the same grid structure side wall, and the length of the channel layer covered by the grid structure is smaller than the preset distance, so that the ratio of the length of the grid structure between adjacent channel layers to the length of the channel layer is increased, the wrapping force of the grid structure on the channel layer is further improved, and correspondingly, the control capability of the grid structure on the channel is improved, so that the performance of the semiconductor device (for example, the opening and closing capability of the semiconductor device) is improved.

In the method for forming the semiconductor structure, provided by the embodiment of the invention, the channel layer with partial length is removed, so that the end part of the residual channel layer along the extending direction is retracted inwards relative to the outer side wall of the grid side wall at the same side, after the space occupying layer is replaced by the grid structure, the ratio of the length of the grid structure between the adjacent channel layers to the length of the channel layer is increased, the wrapping force of the grid structure on the channel layer is further improved, and correspondingly, the control capability of the grid structure on the channel is improved, so that the performance of the semiconductor device is improved; in addition, after the inner side wall is formed, the channel layer with partial length is removed, compared with the scheme that the inner side wall is formed after the channel layer with partial length is removed, the probability that sediment is formed at the corner where the pseudo gate structure is connected with the channel layer in the process of forming the inner side wall (for example, the residual material layer of the inner side wall) is reduced, namely, the probability that the sediment covers the end part of the channel layer is reduced, the forming quality of the source-drain doped layer is guaranteed, and accordingly, the performance of the semiconductor device is improved.

Drawings

Fig. 1 to 8 are schematic structural views corresponding to steps in a method for forming a semiconductor structure;

FIG. 9 is a schematic diagram of a semiconductor structure according to an embodiment of the present invention;

fig. 10 to 19 are schematic structural views corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention.

Detailed Description

As known from the background art, the performance of the current semiconductor structure needs to be improved. The reason why the performance of a semiconductor structure is to be improved is analyzed by combining a method for forming the semiconductor structure. Fig. 1 to 8 are schematic structural views corresponding to steps in a method for forming a semiconductor structure.

Referring to fig. 1, a base (not shown) is provided, the base including a substrate (not shown), a discrete fin 101 protruding above the substrate, and a stack structure 110 located on the fin, the stack structure 110 including one or more channel stacks 105 stacked sequentially from bottom to top, the channel stacks including a placeholder layer 103 and a channel layer 104 located on the placeholder layer 103, a dummy gate structure 108 being formed on the fin 101, the dummy gate structure 108 crossing the stack structure 110, the dummy gate structure 108 covering a portion of a top wall and a portion of a side wall of the stack structure 110.

Referring to fig. 2, gate sidewalls 109 are formed on sidewalls and top of the dummy gate structures 108 and on the stack structure 110 between the dummy gate structures 108.

Referring to fig. 3, the top of the dummy gate structure 108, and the gate sidewall 109 on the stack 110 are removed.

With continued reference to fig. 3, after removing the top of the dummy gate structure 108 and the gate sidewall 109 on the stack structure 110, a recess 111 penetrating the stack structure 110 is formed on both sides of the dummy gate structure 108 using the remaining gate sidewall 109 on the sidewall of the dummy gate structure 108 as a mask.

Referring to fig. 4, the space occupying layer 103 of a partial width exposed by the side wall of the recess 111 is removed along a direction perpendicular to the side wall of the dummy gate structure 108, and an inner trench 112 is formed.

Referring to fig. 5, an inner sidewall material layer 115 is formed on the top of the dummy gate structure 108, the sidewalls of the remaining gate sidewall 109, and the sidewalls and bottom of the recess 111, and the inner sidewall material layer 115 is further filled in the inner trench 112.

Referring to fig. 6, the inner sidewall material layer 115 located outside the groove 111, on the sidewall of the channel layer 104, and at the bottom of the inner trench 112 is removed, the end of the channel layer 104 in the extending direction is exposed, and the remaining inner sidewall material layer 115 filled in the inner trench 112 remains for use as the inner sidewall 117.

Referring to fig. 7, a source-drain doped layer 118 is formed in the recess 111, the source-drain doped layer 118 being in contact with an end of the channel layer 104 in the extending direction.

Referring to fig. 8, after the source-drain doped layer 118 is formed, an interlayer dielectric layer 188 is formed on the substrate at the side of the dummy gate structure 108, and the interlayer dielectric layer 188 covers the source-drain doped layer 118; removing the dummy gate structure 108 and forming a gate opening (not shown) in the interlayer dielectric layer 188; removing the space occupying layer 103 through the gate opening to form a through groove (not shown), wherein the through groove is surrounded by the adjacent channel layers 104 or is surrounded by the adjacent channel layers 104 and the fin 101; a gate structure 119 is formed in the gate opening and the via, the gate structure 119 surrounding the channel layer 104.

In forming the recess 111, the remaining gate sidewall 109 on the sidewall of the dummy gate structure 108 is used as a mask, so that the length of the gate structure 119 between adjacent channel layers 104 is determined by the distance W (refer to fig. 3) between the outer sidewalls of the remaining gate sidewall 109 on the same sidewall of the dummy gate structure 108.

While a portion of the space between longitudinally adjacent channel layers 104 is occupied by the sidewall walls 117, resulting in a smaller ratio of the length of the gate structure 119 to the length of the channel layer 104 between adjacent channel layers 104, which is detrimental to improving the packing ability of the gate structure 119 into the channel layer 104, and correspondingly, a lower control ability of the gate structure 119 into the channel layer 104, which in turn results in lower performance of the semiconductor device (e.g., turn-on and turn-off ability of the semiconductor device).

In order to solve the technical problem, the embodiment of the invention provides a semiconductor structure, wherein a preset distance is reserved between the outer side walls of grid side walls on the same grid structure side wall, and the length of a channel layer covered by the grid structure is smaller than the preset distance, so that the ratio of the length of the grid structure between adjacent channel layers to the length of the channel layer is increased, the wrapping force of the grid structure on the channel layer is further improved, correspondingly, the control capability of the grid structure on the channel layer is improved, and the performance of a semiconductor device (for example, the opening and closing capability of the semiconductor device) is improved.

In order to solve the technical problem, the embodiment of the invention also provides a method for forming a semiconductor structure, which is characterized in that a part of the channel layer is removed, so that the end part of the rest channel layer along the extending direction is retracted inwards relative to the outer side wall of the grid side wall on the same side, after the space occupying layer is replaced by the grid structure, the ratio of the length of the grid structure between the adjacent channel layers to the length of the channel layer is increased, the wrapping force of the grid structure on the channel layer is further improved, and correspondingly, the control capability of the grid structure on the channel layer is improved, so that the performance of a semiconductor device is improved; in addition, after the inner side wall is formed, the channel layer with partial length is removed, compared with the scheme that the inner side wall is formed after the channel layer with partial length is removed, the probability that sediment is formed at the corner where the pseudo gate structure is connected with the channel layer in the process of forming the inner side wall (for example, the residual material layer of the inner side wall) is reduced, namely, the probability that the sediment covers the end part of the channel layer is reduced, the forming quality of the source-drain doped layer is guaranteed, and accordingly, the performance of the semiconductor device is improved.

In order that the above objects, features and advantages of embodiments of the invention may be readily understood, a more particular description of the invention will be rendered by reference to specific embodiments thereof which are illustrated in the appended drawings. Referring to fig. 9, a schematic structure diagram of an embodiment of the semiconductor structure of the present invention is shown.

As shown in fig. 9, in the present embodiment, the semiconductor structure includes: a base (not shown) including a substrate (not shown) and a fin 601 protruding above the substrate; the channel structure layer 666 is suspended above the fin portion 601, and the channel structure layer 666 comprises one or more channel layers 604 which are sequentially arranged at intervals along the direction perpendicular to the surface of the substrate; a gate structure 619 over the fin 601, the gate structure 619 crossing the channel structure layer 666 and surrounding the channel layer 604; the gate sidewall 609 covers the sidewall of the gate structure 619, and a preset distance a is provided between the outer sidewalls 655 of the gate sidewall 609 on the same gate structure 619 along the direction perpendicular to the sidewall of the gate structure 619, and the length B of the channel layer covered by the gate structure 619 is smaller than the preset distance a; the source-drain doped layers 618 are located on the fin portions on two sides of the gate structure 619 and are in contact with the end portions of each channel layer 604 in the channel structure layer 666 along the extending direction; the sidewall spacers 617 are located between the gate structure 619 under the channel layer 604 and the source drain doped layer 618.

In this embodiment, a semiconductor structure is taken as an example of a fully-enclosed Gate (GAA) transistor. In other embodiments, the semiconductor structure may also be a fork gate transistor (fork gate) or other type of transistor.

The substrate is used to provide a process platform for the formation of semiconductor structures. In this embodiment, the substrate is a silicon substrate, that is, the material of the substrate is monocrystalline silicon. In other embodiments, the substrate material may be one or more of germanium, silicon carbide, gallium nitride, gallium arsenide, and indium gallium arsenide, and the substrate may be a silicon-on-insulator substrate or a germanium-on-insulator substrate, among other types of substrates.

The fin 601 serves to provide support for the laminate structure 610. In this embodiment, the fin 601 and the substrate are in an integrated structure, and the material of the fin 601 and the material of the substrate are the same, and are all silicon. In other embodiments, the material of the fin may be different from the material of the substrate, and the material of the fin may be other suitable materials, such as: germanium, silicon carbide, gallium nitride, gallium arsenide, and indium gallium.

The channel layer 604 is used to provide a conductive channel of the transistor. In this embodiment, the material of the channel layer 604 is Si, which is beneficial to improve the performance of the NMOS transistor. In other embodiments, when the semiconductor structure is a PMOS transistor, siGe channel technology may be used to enhance the performance of the PMOS transistor, and the material of the channel layer is SiGe. In other embodiments, the material of the channel layer may also be one or more of germanium, silicon carbide, gallium nitride, gallium arsenide, and indium gallium arsenide.

As an example, in the channel structure layer 666, the number of channel layers 604 is 3. In other embodiments, the channel layer may be other numbers.

Specifically, in a direction perpendicular to the sidewalls of the gate structure 619, the difference between the length a of the channel layer 604 and the width B of the gate structure 619 may be positive, and when the difference is positive, the length of the channel layer 604 is greater than the width B of the gate structure 619, i.e. the end of the channel layer 604 protrudes from the sidewalls of the gate structure 619. However, if the difference is too large, the length of the channel layer 604 is too large, and the ratio of the width B of the gate structure 619 between adjacent channel layers 604 to the length of the channel layer 604 is small, thereby reducing the wrapping of the channel layer 104 by the gate structure 619 and correspondingly reducing the control capability of the gate structure 619 on the channel layer 604.

The difference may also be negative, where the difference is negative, the length of the channel layer 604 is less than the width B of the gate structure 619, i.e., the sidewalls of the gate structure 619 protrude from the ends of the channel layer 604. However, the absolute value of the difference is not preferably too large, and if the absolute value of the difference is too large, the length of the channel layer 604 is too short, and the probability of poor contact between the source and drain doped layers 618 and the channel layer 604 is increased during formation of the source and drain doped layers 618.

Thus, the difference between the length of the channel layer 604 and the width of the gate structure 619B is 50 to 100 angstroms in a direction perpendicular to the sidewalls of the gate structure 619.

In this embodiment, the difference between the length of the channel layer 604 and the width B of the gate structure is 0, that is, the end of the channel layer 604 is flush with the sidewall of the gate structure 619, so that the wrapping force of the gate structure 619 on the channel layer 604 is improved on the premise that the length of the channel layer 604 meets the electrical parameters of the device, and accordingly, the turn-on and turn-off capability of the semiconductor device is improved.

It should be noted that, in other embodiments, the end portion of the gate structure may slightly protrude from the end portion of the channel layer, so as to further improve the coating force of the gate structure on the channel layer.

The gate structure 619 is used to control the turning on and off of the conductive channel during operation of the device. In this embodiment, the gate structure 619 is a metal gate structure, and the gate structure 619 includes a gate dielectric layer (not shown), a work function layer (not shown) on the gate dielectric layer, and a gate electrode layer (not shown) on the work function layer and filled in the through-trench and the gate opening.

The gate dielectric layer is used for realizing electrical isolation between the work function layer and the gate electrode layer and the conductive channel. The gate dielectric layer is made of one or more of silicon oxide, nitrogen doped silicon oxide, hfO2, zrO2, hfSiO, hfSiON, hfTaO, hfTiO, hfZrO, la2O3 and Al2O 3.

In this embodiment, the gate dielectric layer includes a high-k gate dielectric layer, and the material of the high-k gate dielectric layer is a high-k dielectric material. The material of the high-k gate dielectric layer may be selected from ZrO2, hfSiO, hfSiON, hfTaO, hfTiO, hfZrO or Al2O3. In other embodiments, the gate dielectric layer may further include a gate oxide layer and a high-k gate dielectric layer on the gate oxide layer, or the gate dielectric layer may include only the gate oxide layer.

Gate sidewall 609 is used to protect the gate structure 619. In this embodiment, the material of gate sidewall 609 includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbide or silicon oxycarbonitride, boron nitride, and boron carbonitride. As an example, the material of gate sidewall 609 is silicon nitride.

In this embodiment, gate sidewall 609 has an outer sidewall 655. In particular, outer sidewall 655 is the sidewall of gate sidewall 609 facing away from gate structure 609.

The source-drain doped layer 618 is used to serve as a source or drain of a field effect transistor, and the source-drain doped layer 618 is used to provide a carrier source when the field effect transistor is operating. In this embodiment, the source-drain doped layer 618 includes a stress layer doped with ions, and the stress layer is used to provide stress to the channel region, so as to improve the mobility of carriers. Specifically, when forming an NMOS transistor, the source-drain doped layer 618 includes a stress layer doped with N-type ions, and the material of the stress layer is Si or SiC; when forming a PMOS transistor, the source drain doped layer 618 includes a stress layer doped with P-type ions, and the material of the stress layer is Si or SiGe.

The sidewall spacer 617 is used to support the channel layer 604, and implements isolation between the source/drain doped layer 618 and the gate structure 619, so as to increase a distance between the gate structure 619 and the source/drain doped layer 618, and facilitate reducing parasitic capacitance between the gate structure 619 and the source/drain doped layer 618.

In this embodiment, the materials of the inner side wall 617 include: one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbide or silicon oxycarbonitride, boron nitride, and boron carbonitride; as an example, the material of the inner sidewall 617 is silicon nitride.

In this embodiment, along the direction perpendicular to the sidewall of the gate structure 619, the end of the inner sidewall 617 is flush with the end of the channel layer 604 on the same side, so that a flat interface is provided for forming the source-drain doped layer 618 in the process of forming the source-drain doped layer 618, so that the forming quality of the source-drain doped layer 618 is increased, the probability of the source-drain doped layer 618 contacting the channel layer 604 is increased, and the quality of the source-drain doped layer 618 is improved.

In other embodiments, the ends of the inner side walls 617 may be slightly recessed or slightly raised from the ends of the channel layer 604.

In this embodiment, the semiconductor structure further includes: an interlayer dielectric layer 688, the interlayer dielectric layer 688 being located on the substrate on the sides of the gate structure 619 and covering the sidewalls of the gate structure 619. The interlayer dielectric layer 688 is used to isolate adjacent devices. In this embodiment, the material of the interlayer dielectric layer 688 is silicon oxide. The material of the interlayer dielectric layer 688 may also be other insulating materials.

Correspondingly, the invention further provides a method for forming the semiconductor structure. Fig. 10 to 19 are schematic structural views corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention.

The method for forming the semiconductor structure of the present embodiment will be described in detail below with reference to the accompanying drawings.

Referring to fig. 10, a base (not shown) is provided, the base comprising a substrate (not shown), a discrete fin 801 protruding above the substrate, and a stack structure 810 overlying fin 801, stack structure 810 comprising one or more channel stacks 805 stacked sequentially from bottom to top, channel stacks 805 comprising a placeholder layer 803 and a channel layer 804 overlying placeholder layer 803, fin 801 having a dummy gate structure 808 formed thereon, dummy gate structure 808 spanning stack structure 810, dummy gate structure 808 covering a portion of the top wall and a portion of the side wall of stack structure 810, the side wall of dummy gate structure 808 having a gate side wall 809 formed thereon.

Fin 801 serves to provide support for stacked structure 810. In this embodiment, fin 801 and the substrate are in an integrated structure, and the material of fin 801 and the material of the substrate are the same, and are all silicon. In other embodiments, the material of the protrusions may be different from the material of the substrate, and the material of the protrusions may be other suitable materials, such as: germanium, silicon carbide, gallium nitride, gallium arsenide, and indium gallium.

The channel stack 805 is used to provide a process basis for the subsequent formation of the channel layer 804 and the gate mechanism surrounding the channel layer 804. In this embodiment, the number of channel stacks 805 is 3, and in other embodiments, the number of channel stacks 805 may be other numbers.

The channel layer 804 is used to provide the conductive channel of the transistor. The spacer 803 is used for supporting the channel 804, so as to provide a process foundation for the subsequent implementation of the space suspension arrangement of the channel 804, and the spacer 803 is also used for occupying a space position for the subsequent formation of the gate structure wrapping the channel 804.

In this embodiment, the NMOS transistor is formed, the channel layer 804 is made of Si, and the spacer layer 803 is made of SiGe. In the subsequent process of removing the space layer 803, the etching selection of SiGe and Si is relatively high, and by setting the material of the space layer 803 to SiGe and the material of the channel layer 804 to Si, the influence of the removal process of the space layer 803 on the channel layer 804 can be effectively reduced, so that the quality of the channel layer 804 is improved, and further the device performance is improved.

Dummy gate structure 808 is used to pre-occupy a spatial location for subsequent gate structure formation. Specifically, the dummy gate structure 808 is a polysilicon gate structure or an amorphous silicon gate structure, the material of the dummy gate oxide layer may be silicon oxide or silicon oxynitride, and the material of the dummy gate layer may be polysilicon or amorphous silicon.

Specifically, the step of forming the dummy gate structure 808 includes: forming a dummy gate structure material layer (not shown) over fin 801; forming a patterned gate mask layer 821 on the dummy gate structure material layer; the dummy gate structure material layer is etched, using the gate mask layer 821 as a mask, exposing a portion of the top wall of the stack structure 810, the remaining dummy gate structure material layer acting as a dummy gate structure 808,

the gate mask layer 821 is used as a mask during formation of the dummy gate structure 808.

The gate sidewall 809 is used as an etching mask for a subsequent etching process for forming the recess, and the gate sidewall 809 is also used to protect the dummy gate structure 808. In this embodiment, the material of the gate sidewall 809 includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbide or silicon oxycarbonitride, boron nitride and boron carbonitride. As an example, the material of the gate sidewall 809 is silicon nitride.

In this embodiment, the gate sidewall 809 also covers the top wall of the exposed stacked structure 810.

Referring to fig. 11, grooves 811 penetrating the stacked structure 810 are formed at both sides of the dummy gate structure 808.

The recess 811 is used to provide a space for the subsequent formation of the source-drain doped layer.

Specifically, in this embodiment, an anisotropic etching process (e.g., an anisotropic dry etching process) is used to etch the stacked structure 810 on both sides of the dummy gate structure 808, which is beneficial to improving the profile quality of the groove 811, so as to facilitate precise control of the sidewall morphology of the groove 811.

Note that before etching the stacked structure 810 on both sides of the dummy gate structure 808, the method further includes: the top of the dummy gate structure 808 and the gate sidewall 809 on the stacked structure are etched away.

Correspondingly, the stacked structures 810 on both sides of the dummy gate structure 808 are etched using the gate sidewall 809 on the sidewall of the dummy gate structure 808 as a mask to form a recess 811.

Referring to fig. 12, the spacer 803 is removed along the extending direction of the channel layer 804 to form an inner trench 812.

The inner trench 812 provides a spatial location for the subsequent formation of an inner sidewall.

In this embodiment, a vapor etching process is used to etch the space occupying layer 803 with a partial width exposed by the sidewall of the groove 811 along the extending direction of the channel layer 804. The vapor etching process is an isotropic etching process, and can etch the space occupying layer 803 along the extending direction of the channel layer 804, and the vapor etching process is easy to realize a larger etching selection ratio, thereby being beneficial to reducing the difficulty of etching the space occupying layer 803 and reducing the probability of damaging other film structures (such as the channel layer 804).

In this embodiment, in the step of forming the inner trench 812, along the extending direction of the channel layer 804, the depth of the inner trench 812 is greater than the width of the gate sidewall 809. Since the channel layer 804 with a part of the length is removed along the extending direction of the channel layer 804, the depth of the inner trench 812 is larger than the width of the gate sidewall 809, which is beneficial to ensuring that the width of the subsequently formed inner sidewall meets the process requirement and the inner sidewall can be flush with the end of the remaining channel layer 804.

In this embodiment, the material of the space layer 803 is SiGe, the material of the channel layer 804 is Si, and the space layer 803 on the sidewall of the groove 811 is vapor etched by HCl vapor. The etching rate of the HCl vapor to the SiGe material is much greater than the etching rate to the Si material, which effectively reduces the probability of damage to the channel layer 804.

Referring to fig. 13-16, a sidewall wall 817 is formed within the trench 812 (as shown in fig. 16).

The sidewall wall 817 is used to support the channel layer 804, so as to facilitate the replacement of the dummy gate structure 808 with a gate structure, and in addition, the sidewall wall 817 is used to realize isolation between the source-drain doped layer 818 and the gate structure 819, so as to increase the distance between the gate structure 819 and the source-drain doped layer 818, and facilitate the reduction of parasitic capacitance between the gate structure 819 and the source-drain doped layer 818.

In this embodiment, along the extending direction of the channel layer 804, the width of the inner sidewall 817 is smaller than the depth of the inner trench 812, so that the thickness of the inner sidewall 817 is reduced, and further, in the subsequent process, the inner sidewall 817 is taken as a stop position, so that the channel layer 804 with a part of the length is removed.

In this embodiment, the material of the inner sidewall 817 includes: one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbide or silicon oxycarbonitride, boron nitride, and boron carbonitride; as an example, the material of the inner sidewall 817 is silicon nitride.

The steps of forming the inner sidewall 817 according to the present embodiment will be described in detail with reference to the accompanying drawings.

As shown in fig. 13, an inner sidewall material layer 830 is formed on the sidewalls of the dummy gate structure 808 and the sidewalls of the recess 811, and the inner sidewall material layer 830 is further filled in the inner trench 812, and the sidewall material layer in the inner trench 812 serves as an initial inner sidewall 831.

The initial sidewall spacers 831 are used to form the sidewall spacers subsequently.

Specifically, the inner sidewall material layer 830 is formed on the sidewall of the dummy gate structure 808 and the sidewall of the recess 811 by an atomic layer deposition process (Atomic Layer Deposition, ALD), which has good step coverage, and accordingly, the inner sidewall material layer 830 having high quality and high thickness uniformity is formed.

Note that, since the gate sidewall 809 is formed on the sidewall of the dummy gate structure 808, the gate sidewall 809 is covered by the inner sidewall material layer 830 located on the sidewall of the dummy gate structure 808.

As shown in fig. 14 to 16, the inner sidewall material layer 830 located at both sides of the dummy gate structure 808 and a part of the initial inner sidewall 831 having a width are removed, and the remaining initial inner sidewall 831 serves as the inner sidewall 817.

The inner sidewall material layers 830 and the initial inner sidewall 831 with partial widths on both sides of the dummy gate structure 808 are removed, so that the thickness of the inner sidewall 817 is reduced, and the subsequent removal of the channel layer 804 with the inner sidewall 817 as a stop position is facilitated.

As shown in fig. 14 and 15, the step of removing the inner sidewall material layer 830 of a partial width on the sidewalls of the dummy gate structure 808 in a direction perpendicular to the sidewalls of the dummy gate structure 808 includes: the inner sidewall material layer 830 is thinned one or more times until the inner sidewall material layer 830 on the sidewalls of the dummy gate structure 808 is flush with the inner sidewall material layer 830 on the sidewalls of the recess 811.

The inner sidewall material layer 830 on the side wall of the dummy gate structure 808 is flush with the side wall of the inner sidewall material layer 830 on the side wall of the recess 811, so that the thickness of the remaining inner sidewall material layer 830 on the side wall of the dummy gate structure 808 is similar to the thickness of the side wall of the inner sidewall material layer 830 on the side wall of the recess 811, and further, the inner sidewall material layer 830 on the side wall of the dummy gate structure 808 and the initial inner sidewall 831 with partial width are removed in the same step.

In this embodiment, the thinning process is stopped until the inner sidewall material layer 830 on the sidewall of the dummy gate structure 808 is flush with the sidewall of the inner sidewall material layer 830 on the sidewall of the recess 811. In other embodiments, after the thinning process is completed, the inner sidewall material layer on the sidewalls of the dummy gate structure may slightly protrude from the inner sidewall material layer sidewalls on the sidewalls of the recess.

The thinning process is used to remove a portion of the width of the inner sidewall material layer 830 on the sidewalls of the dummy gate structure 808, thereby reducing the thickness difference between the inner sidewall material layer 830 on the sidewalls of the dummy gate structure 808 and the inner sidewall material layer 830 on the sidewalls of the recess 811.

As shown in fig. 14, the thinning process includes: a protective layer 840 is formed on top of the dummy gate structure 808.

The protective layer 840 serves to protect the dummy gate structure 808, thereby advantageously reducing the probability of damage to the dummy gate structure 808 when the portion of the width of the inner sidewall material layer 830 on the sidewalls of the dummy gate structure 808 is subsequently removed.

In this embodiment, the process of forming the protection layer 840 includes: and (5) a dry etching process. Specifically, a reaction gas is introduced into the reaction chamber, and the reaction gas is dissociated to form the protection layer 840.

In the present embodiment, the reaction gas is CH ₄ ，CH ₄ To clean the energy source and thus facilitate reducing environmental pollution, in other embodiments, the reactant gas may also be CH ₃ F。

In this embodiment, the flow rate of the reaction gas is not too small or too large. If the flow rate of the reaction gas is too small, the rate of forming the protective layer 840 is too low, thereby being disadvantageous in terms of saving the process cost; if the flow rate of the reaction gas is excessively large, the rate of forming the protective layer 840 is excessively high, thereby being disadvantageous in controlling the occurrence and stop of the reaction. For this reason, in this embodiment, the flow rate of the reaction gas is 20sccm to 200sccm.

In this embodiment, the process time should not be too short or too long. If the process time is too short, the reaction is not easy to control; if the process time is too long, it is disadvantageous to save the process cost. For this reason, in the present embodiment, the process time is 10 seconds to 100 seconds.

In this embodiment, the material of the protection layer 840 is a polymer, which has a strong impact resistance, so as to be beneficial to protecting the dummy gate structure 808. Moreover, by using a polymer as the material of the protection layer 840, the protection layer 840 can be gradually removed during the subsequent removal of the inner sidewall material layer 830 with a partial width on the sidewall of the dummy gate structure 808, thereby omitting the step of removing the protection layer 840.

As shown in fig. 15, the thinning process further includes: the inner sidewall material layer 830 of a partial width at both sides of the protective layer 840 is removed.

The inner sidewall material layer 830 is removed by partially removing the width of both sides of the protection layer 840, thereby facilitating the selection of the width of the inner sidewall material layer 830 to be removed according to the width and thickness of the protection layer 840.

Specifically, the step of removing the inner sidewall material layer 830 located on both sides of the dummy gate structure 808 and the initial inner sidewall 831 having a partial width includes: the partial width of the inner sidewall material layer 830 on the sidewalls of the dummy gate structure 808 is removed in a direction perpendicular to the sidewalls of the dummy gate structure 808 so that the sidewalls of the remaining inner sidewall material layer 830 on the sidewalls of the dummy gate structure 808 are flush with the sidewalls of the inner sidewall material layer 830 on the sidewalls of the recess 811.

The sidewalls of the remaining inner sidewall material layer 830 on the sidewalls of the dummy gate structure 808 are flush with the sidewalls of the inner sidewall material layer 830 on the sidewalls of the recess 811, thereby advantageously preventing the problem of having a large amount of inner sidewall material layer 830 on the sidewalls of the dummy gate structure 808 after subsequent removal of the inner sidewall material layer 830 on the sidewalls of the recess 811, and advantageously providing sufficient space for subsequent removal of a portion of the length of the channel layer 804.

In this embodiment, the process for removing the inner sidewall material layer 830 with partial width at both sides of the protection layer 840 includes: the anisotropic dry etching process is beneficial to improving the profile quality of the inner side wall material layer 830 on both sides of the removed protection layer 840 by the anisotropic dry etching process, thereby being beneficial to accurately controlling the profile of the inner side wall material layer 830.

In this embodiment, inner sidewall material layer 830 is removed at the same time as inner sidewall material layer 830 is removed at the partial width of both sides of protection layer 840, and the surface of fin 801 is also removed.

It should be noted that, in the process of removing the inner sidewall material layer 830 with a partial width at two sides of the protection layer 840, the protection layer 840 is removed, so that the step of removing the protection layer 840 is omitted, and further, the process cost is saved.

As an example, the number of thinning processes is described as one example. In other embodiments, the number of thinning processes may be multiple times depending on the thickness of the inner sidewall material layer on the sidewalls of the dummy gate structure.

As shown in fig. 16, the initial sidewall 831 having a partial width is removed, and the remaining initial sidewall serves as a sidewall 817.

The initial sidewall 831 is removed to a partial width to facilitate formation of a sidewall 817, where the sidewall 817 is used to define a stop location for the channel layer 804 of a subsequent removed partial length.

Specifically, in a direction perpendicular to the sidewalls of the gate structure 819, a difference between the length of the channel layer 804 and the width C of the gate structure 819 may be positive, and when the difference is positive, the length of the channel layer 804 is greater than the width C of the gate structure 819, i.e., an end portion of the channel layer 804 protrudes from the sidewalls of the gate structure 819. However, if the difference is too large, the length of the channel layer 804 is too large, and the ratio of the width C of the gate structure 819 between adjacent channel layers 804 to the length of the channel layer 804 is smaller, thereby reducing the wrapping of the channel layer 104 by the gate structure 819 and correspondingly reducing the control capability of the channel layer 804 by the gate structure 819.

The difference may also be negative, when the difference is negative, the length of the channel layer 804 is less than the width C of the gate structure 819, i.e., the sidewalls of the gate structure 819 protrude from the ends of the channel layer 804. However, the absolute value of the difference is not too large, and if the absolute value of the difference is too large, the length of the channel layer 804 is too short, so that the probability of poor contact between the source and drain doped layers 818 and the channel layer 804 is increased in the process of forming the source and drain doped layers 818.

Thus, the difference between the length of the channel layer 804 and the width C of the gate structure 819 along a direction perpendicular to the sidewalls of the gate structure 819 is 50 angstroms to 100 angstroms.

In the step of forming the inner sidewall 831 in the inner trench, along the extending direction of the channel layer 804, the difference between the length of the channel layer 804 and the width C of the gate structure 819 is 0, that is, the end of the inner sidewall 804 is flush with the sidewall of the gate structure 819, so that the wrapping force of the gate structure 819 on the channel layer 804 is improved on the premise that the length of the channel layer 804 meets the electrical parameters of the device, and accordingly, the turn-on and turn-off capability of the semiconductor device is improved.

It should be noted that, in other embodiments, the end portion of the gate structure may slightly protrude from the end portion of the channel layer, so as to further improve the coating force of the gate structure on the channel layer. In this embodiment, the remaining inner sidewall material layer 830 on the sidewall of the dummy gate structure 808 is removed, and the inner sidewall material layer 830 on the end portion of the channel layer 804 and the initial inner sidewall 831 with partial width are removed, so that the end portion of the channel layer 804 is exposed, thereby facilitating the contact between the subsequent channel layer 804 and the source/drain doped layer.

In the process of removing the initial sidewall wall with a partial width, the sidewall of the dummy gate structure 808 and the end portion of the channel layer 804 are exposed in the process environment for removing the initial sidewall wall for a short time, so that the probability of damaging the dummy gate structure 808 and the channel layer 804 is reduced.

Specifically, the process of removing the remaining inner sidewall material layer 830 on the sidewalls of the dummy gate structure 808, and simultaneously removing the inner sidewall material layer 830 on the end of the channel layer 804, and the initial inner sidewall of a portion of the width, includes: the wet etching process is advantageous for uniformly removing the inner sidewall material layer 830 on the end of the channel layer 804 and the initial inner sidewall with a partial width.

Referring to fig. 17, after forming the inner sidewall 817 in the inner trench 812, a portion of the channel layer 804 is removed along the extension direction of the channel layer 804, so that the end of the remaining channel layer 804 along the extension direction is retracted inward with respect to the outer sidewall 855 of the gate sidewall 809 on the same side.

The channel layers 804 with partial lengths are removed along the extending direction of the channel layers 804, so that the end parts of the remaining channel layers 804 along the extending direction are retracted inwards relative to the outer side walls 855 of the grid side walls 809 at the same side, and therefore the ratio of the length of the grid structure between the adjacent channel layers 804 to the length of the channel layer is increased after the space occupying layer 803 is replaced by the grid structure, the wrapping force of the grid structure on the channel layers 804 is improved, and correspondingly, the control capability of the grid structure on the channel layers 804 is improved, and the performance of the semiconductor device is improved.

In this embodiment, in the step of removing part of the length of the channel layer 804 along the extending direction of the channel layer 804, the end of the remaining channel layer 804 along the extending direction is flush with the end of the inner sidewall 817, which is favorable for providing a flat interface for forming the source-drain doped layer 818 in the process of forming the subsequent source-drain doped layer, thereby increasing the forming quality of the source-drain doped layer, and being favorable for improving the probability of the contact between the source-drain doped layer 818 and the channel layer 804, and further being favorable for improving the quality of the source-drain doped layer.

In addition, in the step of removing the channel layer 804 with a part of the length, the channel layer 804 is removed with the sidewall 817 as a stop position. It should be noted that, in other implementations, the end of the channel layer may be slightly convex or slightly concave from the end of the inner sidewall.

In this embodiment, the gate sidewall 809 has an outer sidewall 855. In particular, the outer sidewall 855 is the sidewall of the gate sidewall 809 that faces away from the gate structure 809.

In this embodiment, after the inner sidewall wall 817 is formed, the channel layer 804 with a part of length is removed, and compared with the scheme that the inner sidewall wall is formed after the channel layer with a part of length is removed, the probability that the inner sidewall wall material layer 830 remains at the corner where the pseudo gate structure is connected with the channel layer 804 in the process of forming the inner sidewall wall 817 is reduced, that is, the probability that the inner sidewall wall material layer 830 covers the end part of the channel layer 804 is reduced, the end part of the channel layer 804 can be exposed, and accordingly, the formation quality of the source and drain doped layers is guaranteed, and the performance of the semiconductor device is correspondingly improved; in addition, the probability of damaging the channel layer 804 after removing the inner sidewall material layer 830 on the sidewall of the channel layer 804 is reduced when removing more inner sidewall material layers 830 later.

In this embodiment, the end of the inner sidewall 817 is taken as a stop position, and the channel layer 804 with a partial length located at both sides of the end of the inner sidewall 817 is removed.

Specifically, the process of removing a portion of the length of the channel layer 804 includes: the isotropic dry etching process has good selectivity, thereby being beneficial to purposefully removing part of the length of the channel layer 804.

Referring to fig. 18, after removing a portion of the length of the channel layer 804, a source/drain doped layer 818 is formed in the recess 811, and the source/drain doped layer 818 is in contact with an end portion of the channel layer 804 in the extending direction.

The source drain doped layer 818 is used to serve as a source or drain for a field effect transistor, and the source drain doped layer 818 is used to provide a carrier source when the field effect transistor is operating.

In this embodiment, the source-drain doped layer 818 includes a stress layer doped with ions, and the stress layer is used to provide stress to the channel region, so as to improve the mobility of carriers. Specifically, when forming an NMOS transistor, the source-drain doped layer 818 includes a stress layer doped with N-type ions, where the material of the stress layer is Si or SiC; when forming a PMOS transistor, the source drain doped layer 818 includes a stress layer doped with P-type ions, the material of the stress layer being Si or SiGe.

In this embodiment, an epitaxial process is used to form a stress layer, and ions are self-doped in situ during the formation of the stress layer, and the stress layer doped with ions is used as the source/drain doped layer 818.

In other embodiments, the stress layer may be ion implanted after the stress layer is formed.

Referring to fig. 19, after forming the source/drain doped layer 818, an interlayer dielectric layer 888 is formed on the substrate at the side of the dummy gate structure 808, the interlayer dielectric layer 888 covering the source/drain doped layer 818; after forming the interlayer dielectric layer 888, removing the dummy gate structure 808 to form a gate opening; removing the space occupying layer 803 through the gate opening to form a through groove, wherein the through groove is surrounded by the adjacent channel layers 804 or is surrounded by the adjacent channel layers 804 and the fin 801; a gate structure 819 is formed within the gate opening and the via, the gate structure 819 surrounding the channel layer 804.

Specifically, an interlayer dielectric layer 888 covers the sidewalls of the gate sidewall 809 and the source drain doped layer 818. The interlayer dielectric layer 888 is used for isolating adjacent devices, and is also used for supporting the channel layer 804 in the process of removing the dummy gate structure 808 and the placeholder layer 803, so as to realize suspended interval arrangement of the channel layer 804. In this embodiment, the material of the interlayer dielectric layer 888 is silicon oxide. The material of the interlayer dielectric layer 888 can also be other insulating materials.

The gate openings are used to provide a spatial location for forming the gate structures 819. The gate opening exposes the stack 810 to facilitate subsequent removal of the placeholder layer 803 in the channel stack 805 through the gate opening.

In this embodiment, the gate opening spans the stack 810. The via and gate opening together provide a spatial location for forming the gate structure 819. The through slot is communicated with the grid opening.

In this embodiment, the placeholder 803 is removed by a vapor etching process. Specifically, the material of the channel layer 804 is Si, and the material of the space layer 803 is SiGe, so that the space layer 803 exposed by the gate opening is removed by HCl vapor, and the HCl vapor has a higher etching selectivity ratio between SiGe and Si, which is beneficial to improving the removal efficiency of the space layer 803 and reducing the probability of damage to the channel layer 804.

The gate structure 819 is used to control the turning on and off of the conductive channel during device operation. In this embodiment, the gate structure 819 is a metal gate structure, and the gate structure 819 includes a gate dielectric layer (not shown), a work function layer (not shown) on the gate dielectric layer, and a gate electrode layer (not shown) on the work function layer and filling the via and the gate opening.

The gate dielectric layer is used for realizing electrical isolation between the work function layer and the gate electrode layer and the conductive channel. The gate dielectric layer comprises silicon oxide, nitrogen doped silicon oxide and HfO ₂ 、ZrO ₂ 、HfSiO、HfSiON、HfTaO、HfTiO、HfZrO、La ₂ O ₃ And Al ₂ O ₃ One of (a)One or more.

In this embodiment, the gate dielectric layer includes a high-k gate dielectric layer, and the material of the high-k gate dielectric layer is a high-k dielectric material. The material of the high-k gate dielectric layer may be selected from ZrO ₂ HfSiO, hfSiON, hfTaO, hfTiO, hfZrO or Al ₂ O ₃ . In other embodiments, the gate dielectric layer may further include a gate oxide layer and a high-k gate dielectric layer on the gate oxide layer, or the gate dielectric layer may include only the gate oxide layer.

The work function layer is used to adjust the work function of the gate structure 819 and thus the threshold voltage of the field effect transistor. When the NMOS transistor is formed, the work function layer is an N-type work function layer, and the material of the work function layer comprises one or more of titanium aluminide, tantalum carbide, aluminum or titanium carbide; when the PMOS transistor is formed, the work function layer is a P-type work function layer, and the material of the work function layer includes one or more of titanium nitride, tantalum nitride, titanium carbide, tantalum silicon nitride, titanium silicon nitride, and tantalum carbide.

The gate electrode layer is used as an external electrode for electrically connecting the gate structure 819 to an external circuit. The material of the gate electrode layer is a conductive material including one or more of TiN, taN, ti, ta, tiAL, tiALC, tiSiN, W, co, al, cu, ag, au, pt and Ni.

In this embodiment, the gate structure 819 is taken as an example for explanation. In other embodiments, the gate structure may also be other types of gate structures based on actual process requirements, such as: is a polysilicon gate structure or an amorphous silicon gate structure.

Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.

Claims

1. A semiconductor structure, comprising:

the substrate comprises a substrate and a fin part protruding out of the substrate;

the channel structure layer is suspended above the fin part and comprises one or more channel layers which are sequentially arranged at intervals along the direction perpendicular to the surface of the substrate;

a gate structure located above the fin, the gate structure crossing the channel structure layer and surrounding the channel layer;

the grid side walls cover the side walls of the grid structure, a preset distance is reserved between the outer side walls of the grid side walls on the same side wall of the grid structure along the direction perpendicular to the side walls of the grid structure, and the length of the channel layer covered by the grid structure is smaller than the preset distance;

The source-drain doping layers are positioned on the fin parts at two sides of the grid structure and are in contact with the end parts of each channel layer in the channel structure layer along the extending direction;

and the inner side wall is positioned between the grid structure below the channel layer and the source-drain doped layer.

2. The semiconductor structure of claim 1, wherein a difference between a length of the channel layer and a width of the gate structure in a direction perpendicular to sidewalls of the gate structure is 50 angstroms to 100 angstroms.

3. The semiconductor structure of claim 1, wherein an end of the sidewall spacer is flush with an end of the channel layer on the same side in a direction perpendicular to the gate structure sidewall.

4. The semiconductor structure of claim 1, wherein the gate sidewall material comprises one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbide or silicon oxycarbonitride, boron nitride, and boron carbonitride.

5. The semiconductor structure of claim 1, wherein the material of the interior sidewall wall comprises one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbide or silicon oxycarbonitride, boron nitride, and boron carbonitride.

6. A method of forming a semiconductor structure, comprising:

providing a substrate, wherein the substrate comprises a substrate, a discrete fin part protruding out of the substrate and a laminated structure positioned on the fin part, the laminated structure comprises one or more channel laminated layers which are sequentially stacked from bottom to top, the channel laminated layer comprises a space occupying layer and a channel layer positioned on the space occupying layer, a pseudo gate structure is formed on the fin part and spans across the laminated structure, the pseudo gate structure covers part of top wall and part of side wall of the laminated structure, and a grid side wall is formed on the side wall of the pseudo gate structure;

forming grooves penetrating through the laminated structure on two sides of the pseudo gate structure;

removing the occupying layer with partial width exposed by the side wall of the groove along the extending direction of the channel layer to form an inner groove;

forming an inner side wall in the inner groove;

after forming the inner side wall, removing part of the channel layer along the extending direction of the channel layer;

after removing part of the length of the channel layer, forming a source-drain doped layer in the groove, wherein the source-drain doped layer is contacted with the end part of the channel layer along the extending direction;

Removing the pseudo gate structure after forming the source-drain doped layer to form a gate opening;

removing the occupying layer through the gate opening to form a through groove, wherein the through groove is surrounded by the adjacent channel layers or is surrounded by the adjacent channel layers and the fin parts;

and forming a gate structure in the gate opening and the through groove, wherein the gate structure surrounds the channel layer.

7. The method of forming a semiconductor structure according to claim 6, wherein in the step of forming an inner sidewall in the inner trench, a width of the inner sidewall is smaller than a depth of the inner trench along an extending direction of the channel layer.

8. The method of forming a semiconductor structure of claim 7, wherein in the step of forming a sidewall within the trench, an end of the sidewall is flush with a sidewall of the dummy gate structure along an extension direction of the channel layer.

9. The method of forming a semiconductor structure according to claim 7, wherein in the step of removing a part of the length of the channel layer in the extending direction of the channel layer, an end of the remaining channel layer in the extending direction is made flush with an end of the inner side wall.

10. The method of forming a semiconductor structure of claim 7, wherein in the step of forming the inner trench, a depth of the inner trench is greater than a width of the gate sidewall along an extension direction of the channel layer.

11. The method of forming a semiconductor structure of claim 7, wherein forming an interior sidewall within the interior trench comprises: forming an inner side wall material layer on the side wall of the grid structure and the side wall of the groove, wherein the inner side wall material layer is also filled in the inner groove, and the side wall material layer in the inner groove is used as an initial inner side wall;

and removing the inner side wall material layers positioned on two sides of the pseudo gate structure and the initial inner side wall with partial width, wherein the rest initial inner side walls are used as inner side walls.

12. The method of forming a semiconductor structure of claim 11, wherein removing the layer of sidewall material on both sides of the dummy gate structure and the portion of the initial sidewall of the width comprises: removing part of the width inner side wall material layer on the side wall of the pseudo gate structure along the direction perpendicular to the side wall of the pseudo gate structure, so that the side wall of the rest inner side wall material layer on the side wall of the pseudo gate structure is flush with the side wall of the inner side wall material layer on the side wall of the groove;

And removing the residual inner side wall material layer positioned on the side wall of the pseudo gate structure, and simultaneously removing the inner side wall material layer positioned on the end part of the channel layer and the initial inner side wall with partial width to expose the end part of the channel layer.

13. The method of forming a semiconductor structure of claim 12, wherein removing the remaining sidewall material layer on the sidewalls of the dummy gate structure while removing the sidewall material layer on the ends of the channel layer and the initial sidewall wall having a partial width comprises: wet etching process.

14. The method of forming a semiconductor structure of claim 12, wherein removing a portion of the width of the inner sidewall material layer on the dummy gate sidewalls in a direction perpendicular to the dummy gate sidewalls comprises: thinning the inner side wall material layer for one or more times until the inner side wall material layer on the side wall of the pseudo gate structure is flush with the side wall of the inner side wall material layer on the side wall of the groove;

the thinning process includes: forming a protective layer on the top of the pseudo gate structure; removing part of the width of the inner side wall material layers at two sides of the protective layer; and removing the protective layer.

15. The method of forming a semiconductor structure of claim 14, wherein the thinning process comprises: an anisotropic dry etching process.

16. The method of claim 14, wherein the protective layer is removed during the removing of the inner sidewall material layer having a partial width on both sides of the protective layer.

17. The method of forming a semiconductor structure of claim 14, wherein the material of the protective layer comprises a polymer.

18. The method of forming a semiconductor structure of claim 17, wherein the process of forming the protective layer comprises: and (5) a dry etching process.

19. The method of forming a semiconductor structure of claim 18, wherein the process parameters of the dry etching process comprise: the reaction gas includes CH ₃ F or CH ₄ The flow rate of the reaction gas is 20sccm to 200sccm, and the process time is 10 seconds to 100 seconds.

20. The method of forming a semiconductor structure of claim 6, wherein removing a portion of the length of the channel layer comprises: an isotropic dry etching process.