CN117276200A - Method for forming semiconductor structure - Google Patents

Method for forming semiconductor structure Download PDF

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Publication number
CN117276200A
CN117276200A CN202210675140.3A CN202210675140A CN117276200A CN 117276200 A CN117276200 A CN 117276200A CN 202210675140 A CN202210675140 A CN 202210675140A CN 117276200 A CN117276200 A CN 117276200A
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China
Prior art keywords
layer
side wall
material layer
forming
channel
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CN202210675140.3A
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Chinese (zh)
Inventor
迟帅杰
詹焰坤
俞涛
崇二敏
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Semiconductor Manufacturing International Shanghai Corp
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Semiconductor Manufacturing International Shanghai Corp
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Priority to CN202210675140.3A priority Critical patent/CN117276200A/en
Publication of CN117276200A publication Critical patent/CN117276200A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823412—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823431—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

A method for forming a semiconductor structure includes: providing a substrate, wherein a laminated structure is formed on the substrate, the laminated structure comprises one or more channel laminated layers which are sequentially stacked from bottom to top, the channel laminated layer comprises a space occupying layer and a channel layer positioned on the space occupying layer, and a pseudo gate structure is also formed on the substrate, spans the laminated structure and covers part of the top and part of the side wall of the laminated structure; forming grooves penetrating through the laminated structure on two sides of the pseudo gate structure; removing the occupying layer with part of the length exposed by the side wall of the groove along the extending direction of the channel layer to form an inner groove; forming an inner side wall material layer on the side wall of the pseudo gate structure and the side wall of the groove, wherein the inner side wall material layer is also filled in the inner groove; and modifying the inner side wall material layer outside the inner groove, wherein the modification treatment is used for converting the inner side wall material layer into a sacrificial layer, and the sacrificial layer, the inner side wall material layer and the channel layer are all provided with etching selection ratios. The embodiment of the invention is beneficial to the performance of the semiconductor device.

Description

Method for forming semiconductor structure
Technical Field
The embodiment of the invention relates to the field of semiconductor manufacturing, in particular to a method for forming a semiconductor structure.
Background
With the gradual development of semiconductor process technology, the development trend of the semiconductor process node following moore's law is continuously reduced. To accommodate the reduction in process nodes, the channel length of MOSFET field effect transistors is also correspondingly reduced. However, as the channel length of the device is reduced, the distance between the source and drain of the device is reduced, and the control capability of the gate to the channel is deteriorated.
Accordingly, to better accommodate the demands of device scaling, semiconductor processes are increasingly beginning to transition from planar MOSFET transistors to three-dimensional transistors with higher efficiency, such as fin field effect transistors (finfets). In a FinFET, the gate may control ultra-thin bodies (fins) from at least two sides, with much greater gate-to-channel control capability than planar MOSFET devices.
However, the performance of the semiconductor structure formed by the prior art needs to be improved.
Disclosure of Invention
The embodiment of the invention solves the problem of providing a method for forming a semiconductor structure, which is beneficial to improving the performance of a semiconductor device.
In order to solve the above-mentioned problems, an embodiment of the present invention further provides a method for forming a semiconductor structure, including: providing a substrate, wherein a laminated structure is formed on the substrate, the laminated structure comprises one or more channel laminated layers which are sequentially stacked from bottom to top, the channel laminated layers comprise a space occupying layer and a channel layer positioned on the space occupying layer, and a pseudo gate structure is also formed on the substrate, and spans the laminated structure and covers part of the top and part of the side wall of the laminated structure; forming grooves penetrating through the laminated structure on two sides of the pseudo gate structure; removing the occupying layer with part of the length exposed by the side wall of the groove along the extending direction of the channel layer to form an inner groove; forming an inner side wall material layer on the side wall of the pseudo gate structure and the side wall of the groove, wherein the inner side wall material layer is also filled in the inner groove; modifying the inner side wall material layer outside the inner groove, wherein the modification is used for converting the inner side wall material layer into a sacrificial layer, and the sacrificial layer, the inner side wall material layer and the channel layer are provided with etching selection ratios; and removing the sacrificial layer, and reserving the residual inner side wall material layer positioned in the inner groove as an inner side wall.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following advantages:
in the method for forming the semiconductor structure provided by the embodiment of the invention, the inner side wall material layer outside the inner groove is subjected to modification treatment and is used for converting the inner side wall material layer into the sacrificial layer, and the sacrificial layer, the inner side wall material layer and the channel layer are provided with etching selection ratios, so that the probability of damage to the residual inner side wall material layer positioned in the inner groove and the channel layer can be reduced when the sacrificial layer is removed subsequently, the integrity of the inner side wall and the channel layer is ensured, and in addition, the shape quality and the width uniformity of the formed inner side wall are improved, and accordingly, the performance of the semiconductor device is improved.
Drawings
Fig. 1 to 8 are schematic structural views corresponding to steps in a method for forming a semiconductor structure;
fig. 9 to 17 are schematic structural views corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention.
Detailed Description
As known from the background art, the performance of the current semiconductor structure needs to be improved. The reason why the performance of a semiconductor structure is to be improved is analyzed by combining a method for forming the semiconductor structure. Fig. 1 to 8 are schematic structural views corresponding to steps in a method for forming a semiconductor structure.
Referring to fig. 1, a substrate (not shown) is provided, on which a stack structure 610 is formed, the stack structure 610 comprising one or more channel stacks 605 stacked sequentially from bottom to top, the channel stacks 605 comprising a placeholder layer 603 and a channel layer 604 on the placeholder layer 603, and a dummy gate structure 608 is further formed on the substrate, the dummy gate structure 608 crossing the stack structure 610 and covering a portion of the top and a portion of the sidewalls of the stack structure 610.
Referring to fig. 2, grooves 666 are formed through the stack 610 on both sides of the dummy gate 608.
Referring to fig. 3, after the recess 666 is formed, the portion of the spacer layer 604 exposed by the sidewall of the recess 666 is removed along the extending direction of the channel layer 604, so as to form an inner trench 688.
Referring to fig. 4, an inner sidewall material layer 633 is formed on the sidewalls of the dummy gate structure 608 and the sidewalls of the recess 666, and the inner sidewall material layer 633 is further filled in the inner trench 688.
Referring to fig. 5, the inner sidewall material layer 633 outside the inner trench 688 is removed, an end of the channel layer 604 in the extending direction thereof is exposed, and the remaining inner sidewall material layer 633 filled in the inner trench 688 remains for use as the inner sidewall 635.
Referring to fig. 6, after the inner sidewall 635 is formed, a source-drain doped layer 699 is formed in the recess 666, and the source-drain doped layer 699 is in contact with an end portion of the channel layer 604 in the extending direction thereof.
Referring to fig. 7, after the source/drain doped layer 699 is formed, an interlayer dielectric layer 698 is formed on the substrate at the side of the dummy gate structure 608, and the interlayer dielectric layer 698 covers the source/drain doped layer 699.
Referring to fig. 8, the dummy gate structure 608 is removed to form a gate opening (not shown); removing the space occupying layer 603 through the gate opening, and forming a through groove (not shown), wherein the through groove is surrounded by the adjacent channel layers 604, or is surrounded by the adjacent channel layers 604 and the substrate; a gate structure 655 is formed within the gate opening and the via, the gate structure 655 surrounding the channel layer 604.
In the step of removing the inner sidewall material layer 633 outside the inner trench 688 and exposing the end portion of the channel layer 604 in the extending direction, since the etching selection of the material of the channel layer 604 and the material of the inner sidewall material layer 633 is smaller, in the process of removing a portion of the inner sidewall material layer 633, the channel layer 604 is easily mistakenly etched, so that the integrity of the channel layer 604 is reduced, and accordingly, the performance of the semiconductor device is reduced.
In order to solve the technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate, wherein a laminated structure is formed on the substrate, the laminated structure comprises one or more channel laminated layers which are sequentially stacked from bottom to top, the channel laminated layers comprise a space occupying layer and a channel layer positioned on the space occupying layer, and a pseudo gate structure is also formed on the substrate, and spans the laminated structure and covers part of the top and part of the side wall of the laminated structure; forming grooves penetrating through the laminated structure on two sides of the pseudo gate structure; removing the occupying layer with part of the length exposed by the side wall of the groove along the extending direction of the channel layer to form an inner groove; forming an inner side wall material layer on the side wall of the pseudo gate structure and the side wall of the groove, wherein the inner side wall material layer is also filled in the inner groove; modifying the inner side wall material layer outside the inner groove, wherein the modification is used for converting the inner side wall material layer into a sacrificial layer, and the sacrificial layer, the inner side wall material layer and the channel layer are provided with etching selection ratios; and removing the sacrificial layer, and reserving the residual inner side wall material layer positioned in the inner groove as an inner side wall.
In the method for forming the semiconductor structure provided by the embodiment of the invention, the inner side wall material layer outside the inner groove is subjected to modification treatment and is used for converting the inner side wall material layer into the sacrificial layer, and the sacrificial layer, the inner side wall material layer and the channel layer are provided with etching selection ratios, so that the probability of damage to the residual inner side wall material layer positioned in the inner groove and the channel layer can be reduced when the sacrificial layer is removed subsequently, the integrity of the inner side wall and the channel layer is ensured, and in addition, the shape quality and the width uniformity of the formed inner side wall are improved, and accordingly, the performance of the semiconductor device is improved.
In order that the above objects, features and advantages of embodiments of the invention may be readily understood, a more particular description of the invention will be rendered by reference to specific embodiments thereof which are illustrated in the appended drawings. Fig. 9 to 17 are schematic structural views corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention.
The method for forming the semiconductor structure of the present embodiment will be described in detail below with reference to the accompanying drawings.
Referring to fig. 9, a substrate (not shown) is provided, on which a stack structure 810 is formed, the stack structure 810 including one or more channel stacks 810 stacked sequentially from bottom to top, the channel stacks 810 including a placeholder layer 803 and a channel layer 804 on the placeholder layer 803, and a dummy gate structure 808 is further formed on the substrate, the dummy gate structure 808 crossing the stack structure 810 and covering a portion of the top and a portion of the sidewalls of the stack structure 810.
In this embodiment, a semiconductor structure is taken as an example of a fully-enclosed Gate (GAA) transistor. In other embodiments, the semiconductor structure may also be a fork gate transistor (fork gate) or other type of transistor.
In this embodiment, in the step of providing the base, the base includes a substrate (not shown), and a fin 801 located on the substrate, and the stacked structure 810 is located on top of the fin 801.
The substrate is used to provide a process platform for the formation of semiconductor structures. In this embodiment, the substrate is a silicon substrate, that is, the material of the substrate is monocrystalline silicon. In other embodiments, the substrate material may be one or more of germanium, silicon carbide, gallium nitride, gallium arsenide, and indium gallium arsenide, and the substrate may be a silicon-on-insulator substrate or a germanium-on-insulator substrate, among other types of substrates.
Fin 801 serves to provide support for stacked structure 810. In this embodiment, fin 801 and the substrate are in an integrated structure, and the material of fin 801 and the material of the substrate are the same, and are all silicon. In other embodiments, the material of the protrusions may be different from the material of the substrate, and the material of the protrusions may be other suitable materials, such as: germanium, silicon carbide, gallium nitride, gallium arsenide, and indium gallium.
The channel stack 805 is used to provide a process basis for the subsequent formation of the channel layer 804 and the gate structure surrounding the channel layer 804. In this embodiment, the number of channel stacks 805 is 3, and in other embodiments, the number of channel stacks 805 may be other numbers.
The channel layer 804 is used to provide the conductive channel of the transistor. The spacer 803 is used for supporting the channel 804, so as to provide a process foundation for the subsequent implementation of the space suspension arrangement of the channel 804, and the spacer 803 is also used for occupying a space position for the subsequent formation of the gate structure wrapping the channel 804.
In this embodiment, the NMOS transistor is formed, the channel layer 804 is made of Si, and the spacer layer 803 is made of SiGe. In the subsequent process of removing the space layer 803, the etching selection of SiGe and Si is relatively high, and by setting the material of the space layer 803 to SiGe and the material of the channel layer 804 to Si, the influence of the removal process of the space layer 803 on the channel layer 804 can be effectively reduced, so that the quality of the channel layer 804 is improved, and further the device performance is improved.
Dummy gate structure 808 is used to pre-occupy a spatial location for subsequent gate structure formation. Specifically, the dummy gate structure 808 is a polysilicon gate structure or an amorphous silicon gate structure.
The dummy gate structure 808 may be a stacked structure or a single layer structure. In this embodiment, the dummy gate structure 808 is a stacked structure, and includes a dummy gate oxide layer (not shown) and a dummy gate layer (not shown) on the dummy gate oxide layer. The material of the dummy gate oxide layer can be silicon oxide or silicon oxynitride, and the material of the dummy gate layer can be polysilicon or amorphous silicon.
Specifically, the step of forming the dummy gate structure 808 includes: forming a dummy gate structure material layer (not shown) over fin 801; forming a patterned gate mask layer 821 on the dummy gate structure material layer; the dummy gate structure material layer is etched using the gate mask layer 821 as a mask, exposing a portion of the top wall of the stack structure 810, and the remaining dummy gate structure material layer serves as a dummy gate structure 808.
The gate mask layer 821 is used as a mask during formation of the dummy gate structure 808.
In this embodiment, the gate mask layer 821 has a stacked structure, and the gate mask layer 821 includes a silicon nitride layer (not shown) and a silicon oxide layer (not shown) on the silicon nitride layer. In other embodiments, the gate mask layer may also have a single-layer structure.
In this embodiment, in the step of providing the substrate, a gate sidewall 809 is formed on a sidewall of the dummy gate structure 808.
The gate sidewall 809 is used as an etching mask for a subsequent etching process for forming the recess, and the gate sidewall 809 is also used to protect the dummy gate structure 808. In this embodiment, the material of the gate sidewall 809 includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbide or silicon oxycarbonitride, boron nitride and boron carbonitride. As an example, the material of the gate sidewall 809 is silicon nitride.
In this embodiment, the gate sidewall 809 also covers the top of the exposed stack 810 and the top of the dummy gate 808.
Referring to fig. 10, grooves 811 penetrating the stacked structure 810 are formed at both sides of the dummy gate structure 808.
The recess 811 is used to provide a space for the subsequent formation of the source-drain doped layer.
Specifically, in this embodiment, an anisotropic etching process (e.g., an anisotropic dry etching process) is used to etch the stacked structure 810 on both sides of the dummy gate structure 808, which is beneficial to improving the profile quality of the groove 811, so as to facilitate precise control of the sidewall morphology of the groove 811.
Note that before etching the stacked structure 810 on both sides of the dummy gate structure 808, the method further includes: the top of the dummy gate structure 808 and the gate sidewall 809 on the stacked structure are etched away.
Correspondingly, the stacked structures 810 on both sides of the dummy gate structure 808 are etched using the gate sidewall 809 on the sidewall of the dummy gate structure 808 as a mask to form a recess 811.
Referring to fig. 11, the spacer 803 is removed along a portion of the length of the exposed sidewall of the groove 811 along the extending direction of the channel layer 804, so as to form an inner trench 812.
The inner trench 812 provides a spatial location for the subsequent formation of an inner sidewall.
In this embodiment, a vapor etching process is used to etch the space occupying layer 803 with a partial width exposed by the sidewall of the groove 811 along the extending direction of the channel layer 804. The vapor etching process is an isotropic etching process, and can etch the space occupying layer 803 along the extending direction of the channel layer 804, and the vapor etching process is easy to realize a larger etching selection ratio, thereby being beneficial to reducing the difficulty of etching the space occupying layer 803 and reducing the probability of damaging other film structures (such as the channel layer 804).
In this embodiment, the material of the space layer 803 is SiGe, the material of the channel layer 804 is Si, and the space layer 803 on the sidewall of the groove 811 is vapor etched by HCl vapor. The etching rate of the HCl vapor to the SiGe material is much greater than the etching rate to the Si material, which effectively reduces the probability of damage to the channel layer 804.
Referring to fig. 12, an inner sidewall material layer 830 is formed on the sidewalls of the dummy gate structure 808 and the sidewalls of the recess 811, and the inner sidewall material layer 830 is also filled in the inner trench 812.
The interior sidewall material layer 830 is used to subsequently form interior sidewalls.
Specifically, the inner sidewall material layer 830 is formed on the sidewall of the dummy gate structure 808 and the sidewall of the recess 811 by an atomic layer deposition process (Atomic Layer Deposition, ALD), which has good step coverage, and accordingly, the inner sidewall material layer 830 having high quality and high thickness uniformity is formed.
Note that, since the gate sidewall 809 is formed on the sidewall of the dummy gate structure 808, the gate sidewall 809 is covered by the inner sidewall material layer 830 located on the sidewall of the dummy gate structure 808.
In this embodiment, in the step of forming the inner sidewall material layer 830, the material of the inner sidewall material layer 830 is one or more of silicon nitride and a low-k dielectric material, where the low-k dielectric material refers to a material with a dielectric constant k less than 3.9. The low-k dielectric material includes: silicon carbide, silicon carbonitride, silicon oxynitride, boron nitride, and boron carbonitride. As an example, the material of the inner side wall material layer is silicon nitride.
Referring to fig. 13, the inner sidewall material layer 830 outside the inner trench 812 is modified to convert the inner sidewall material layer 830 into a sacrificial layer 875, where the sacrificial layer 875 has an etching selectivity to the inner sidewall material layer 830 and the channel layer 804.
In this embodiment, the modification treatment is performed on the inner sidewall material layer 830 outside the inner trench 812, so as to convert the inner sidewall material layer 830 into the sacrificial layer 875, where the sacrificial layer 875, the inner sidewall material layer 830 and the channel layer 804 have etching selectivity, so that when the sacrificial layer 875 is removed later, the probability of damage to the remaining inner sidewall material layer 830 and the channel layer 804 in the inner trench 812 can be reduced, thereby being beneficial to ensuring the integrity of the inner sidewall and the channel layer 804, and in addition, the uniformity of the morphology quality and the width of the formed inner sidewall is improved, and accordingly, the performance of the semiconductor device is improved.
The sacrificial layer 875 is used to be subsequently removed, thereby leaving the remaining interior sidewall material layer 830 within the interior trench 812 as an interior sidewall.
In this embodiment, the sacrificial layer 875, the inner sidewall material layer 830 and the channel layer 804 have etching selectivity, so that when the sacrificial layer 875 is selectively removed, the probability of damage to the remaining inner sidewall material layer 830 and the channel layer 804 in the inner trench 812 is reduced, thereby ensuring the integrity of the inner sidewall and the channel layer 804.
In this embodiment, before the modification treatment is performed on the inner wall material layer 830 outside the inner trench 812, the method further includes: a preset thickness a of the inner sidewall material layer 830 on the sidewall of the dummy gate structure 808 is obtained.
In this embodiment, the preset thickness a is a thickness of the inner sidewall material layer 830 on the sidewall of the dummy gate structure 808.
The preset thickness a of the inner side wall material layer 830 on the side wall of the dummy gate structure 808 is obtained, so that it is beneficial to select parameters for performing subsequent modification treatment according to the preset thickness a of the inner side wall material layer 830, and then the modification treatment is performed on the inner side wall material layer 830 with the preset thickness in a targeted manner.
In this embodiment, the method for obtaining the preset thickness a of the inner sidewall material layer 830 on the sidewall of the dummy gate structure 808 is an optical feature size (OCD) measurement method, where the optical feature size measurement method is beneficial to obtaining the preset thickness of the inner sidewall material layer 830 with higher accuracy.
In this embodiment, the modification treatment of the inner wall material layer 830 outside the inner trench 812 includes the following steps: the inner sidewall material layer 830 having a predetermined thickness outside the inner channel 812 is modified.
The inner sidewall material layer 830 having a predetermined thickness outside the inner trench 812 is modified so that only the remaining inner sidewall material layer 830 located in the inner trench 812 remains later.
In this embodiment, the preset thickness a of the inner sidewall material layer 830 on the sidewall of the dummy gate structure 808 is equal to the preset thickness outside the inner trench 812, so that the modification treatment can be performed on the inner sidewall material layer 830 with the preset thickness outside the inner trench 812 according to the preset thickness of the inner sidewall material layer 830 on the sidewall of the dummy gate structure 808.
It should be noted that, since the thickness of the modified inner sidewall material layer 830 may be adjusted by adjusting the parameters of the modification process, and the etching selectivity between the sacrificial layer 875 (i.e., the modified inner sidewall material layer 830) and the unmodified inner sidewall material layer 830 is provided, the removal amount may be controlled more precisely when the sacrificial layer 875 is removed later.
In this embodiment, in the step of modifying the inner sidewall material layer 830 outside the inner trench, the sacrificial layer 875 satisfies: the etch selectivity of the sacrificial layer 875 and the interior sidewall material layer 830 is greater than 6:1. The etching selectivity of the sacrificial layer 875 and the inner sidewall material layer 830 is not too small, and if the etching selectivity of the sacrificial layer 875 and the inner sidewall material layer 830 is too small, the inner sidewall material layer 830 is easily mistakenly etched in the subsequent process of removing the sacrificial layer 875, so that the integrity of the subsequently formed inner sidewall is reduced.
In this embodiment, the sacrificial layer 875 further satisfies: the etch selectivity of the sacrificial layer 875 to the channel layer 804 is greater than 50:1. The etching selectivity of the sacrificial layer 875 and the channel layer 804 is not too small, and if the etching selectivity of the sacrificial layer 875 and the channel layer 804 is too small, the channel layer 804 is easily mistakenly etched in the subsequent process of removing the sacrificial layer 875, so that the integrity of the channel layer 804 is reduced.
In this embodiment, the modification process is a plasma process, and the directionality of the plasma process is strong, so that the modification process can be performed on the inner sidewall material layer 830 outside the trench in a targeted manner. In other embodiments, the modification process may also be an ion implantation process.
In this embodiment, the process parameters of the plasma processing process include bias power, where the bias power is not too small or too large, and if the bias power is too small, the effect of modifying the inner sidewall material layer 830 outside the inner trench 812 is not good, so that it is not beneficial to increase the etching selection ratio of the sacrificial layer 875 to the inner sidewall material layer 830, and further is not beneficial to the subsequent selective removal of the sacrificial layer 875; if the bias power is too high, the fin 801 under the inner sidewall material layer 830 may be damaged. For this reason, in the present embodiment, the bias power is 100wb to 200wb.
In this embodiment, the process parameters of the plasma treatment process include the plasma bombardment energy, where the plasma bombardment energy is not too small or too large, and if the plasma bombardment energy is too small, the effect of modifying the inner sidewall material layer 830 outside the inner trench 812 is not good, so that it is not beneficial to increase the etching selection ratio of the sacrificial layer 875 to the inner sidewall material layer 830, and further is not beneficial to the subsequent selective removal of the sacrificial layer 875; if the plasma bombardment energy is too great, then fin 801 located under inner sidewall material layer 830 may be damaged. For this reason, in this embodiment, the plasma bombardment energy is 450eV to 850eV.
In this embodiment, the process parameters of the plasma treatment process include a process time, and the thickness of the sacrificial layer 875 is increased correspondingly with the increase of the process time, but the process time is not too long, and in this embodiment, the process time is greater than 0 seconds and less than 600 seconds when the process time is increased to a certain extent under the condition that the bias power and the plasma bombardment energy are certain, so that the thickness of the inner wall material layer 830 affected by the modification treatment is saturated, and thus the unnecessary process time and the waste of the process cost are easily increased if the process time is too long.
In this embodiment, the process parameters of the plasma processing process include a reactive gas, which is helium, and the helium is beneficial to increase the effect of modifying the inner sidewall material layer 830 outside the inner trench 812, so as to selectively remove the sacrificial layer 875 later, and in other embodiments, the reactive gas further includes hydrogen or a mixed gas of hydrogen and helium.
It should be noted that, in the present embodiment, since the thickness of the inner sidewall material layer 830 affected by the modification treatment is saturated when the process time is increased to a certain extent under the condition that the bias power and the plasma bombardment energy are certain, the etching load effect between different patterns is advantageously improved.
Referring to fig. 14, the sacrificial layer 875 is removed, leaving the remaining inner sidewall material layer 830 within the inner trench 812 as the inner sidewall 817.
The sacrificial layer 875 is removed to expose the remaining interior sidewall material layer 830 as interior sidewall 817 and to expose the ends of the channel layer 804 in preparation for subsequent formation of source and drain doped layers.
In this embodiment, the sidewall spacer 817 is used to support the channel layer 804, so that the dummy gate structure 808 is replaced by a gate structure, and in addition, the sidewall spacer 817 is used to realize isolation between the source-drain doped layer and the gate structure, so as to increase the distance between the gate structure and the source-drain doped layer, and reduce the parasitic capacitance between the gate structure and the source-drain doped layer.
In this embodiment, the sacrificial layer 875 is removed, and in the step of reserving the remaining inner sidewall material layer 830 located in the inner trench 812 as an inner sidewall, the sidewall of the inner sidewall is flush with the end of the channel layer 804, so that it is beneficial to fully expose the end of the channel layer 804 and improve the flatness of the sidewall of the remaining space of the groove 811, so as to improve the probability of contacting the subsequently formed source-drain doped layer with the channel layer 804 and improve the quality of the source-drain doped layer.
In this embodiment, the process of removing the sacrificial layer 875 is a wet etching process, which is simple, has a high etching rate and a high etching selectivity, so that the sacrificial layer 875 is removed selectively, and damage to the channel layer 804 and the residual inner sidewall material layer 830 in the inner trench 812 is reduced. In other embodiments, the process of removing the sacrificial layer further comprises an isotropic dry etch.
In this embodiment, when the process of removing the sacrificial layer 875 is a wet etching process, the etching solution is a hydrofluoric acid solution, and the hydrofluoric acid solution can remove the sacrificial layer 875 formed by the modification treatment, and the etching selectivity of the hydrofluoric acid solution on the sacrificial layer 875 and the inner side wall material layer 830 is relatively large, so that selective removal of the sacrificial layer 875 is facilitated.
The hydrofluoric acid solution has a lower etching selectivity to the channel layer 804, so that the damage probability to the channel layer 804 is reduced, the interface foundation of the source-drain doped layer formed by the epitaxy process is improved, and the quality of the source-drain doped layer is improved correspondingly.
In this embodiment, the process of removing the sacrificial layer 875 is a wet etching process, and the process time of the wet etching process is not too short or too long, if the process time is too short, the effect of completely removing the sacrificial layer 875 is not good, the probability of remaining the sacrificial layer 875 on the sidewall of the sidewall wall is increased, and the probability of covering the end of the channel layer 804 is correspondingly increased, so that adverse effects are caused on the subsequent formation of the source-drain doped layer; if the process time is too long, the inner side wall 817 is easily etched by mistake, so that the flatness of the side wall of the inner side wall 817 is reduced. For this reason, in this embodiment, the process time of the wet etching process is 1 to 6 minutes.
Referring to fig. 15, after the sacrificial layer 875 is removed and the remaining inner sidewall material layer 830 located in the inner trench 812 is remained as the inner sidewall 817, the method further includes: a source-drain doped layer 818 is formed in the recess 811, and the source-drain doped layer 818 is in contact with an end portion of the channel layer 804 in the extending direction.
The source drain doped layer 818 is used to serve as a source or drain for a field effect transistor, and the source drain doped layer 818 is used to provide a carrier source when the field effect transistor is operating.
It should be noted that, in this embodiment, the sacrificial layer 875 is removed by using a hydrofluoric acid solution, and the selectivity of the hydrofluoric acid solution to the etching of the channel layer 804 is low, so that the probability of damage to the channel layer 804 is reduced, and further, the interface foundation of forming the source-drain doped layer 818 by an epitaxial process is improved, and accordingly, the quality of the source-drain doped layer 818 is improved.
In this embodiment, the source-drain doped layer 818 includes a stress layer doped with ions, and the stress layer is used to provide stress to the channel region, so as to improve the mobility of carriers. Specifically, when forming an NMOS transistor, the source-drain doped layer 818 includes a stress layer doped with N-type ions, where the material of the stress layer is Si or SiC; when forming a PMOS transistor, the source drain doped layer 818 includes a stress layer doped with P-type ions, the material of the stress layer being Si or SiGe.
In this embodiment, an epitaxial process is used to form a stress layer, and ions are self-doped in situ during the formation of the stress layer, and the stress layer doped with ions is used as the source/drain doped layer 818.
In other embodiments, the stress layer may be ion implanted after the stress layer is formed.
Referring to fig. 16, in this embodiment, after forming the source-drain doped layer 818, before forming the gate opening, the method further includes: an interlayer dielectric layer 888 is formed on the substrate on the sides of the dummy gate structure 808, the interlayer dielectric layer 888 covering the source drain doped layer 818.
The interlayer dielectric layer 888 is used for isolating adjacent devices, and is also used for supporting the channel layer 804 in the process of removing the dummy gate structure 808 and the placeholder layer 803, so as to realize suspended interval arrangement of the channel layer 804.
Specifically, an interlayer dielectric layer 888 covers the sidewalls of the gate sidewall 809 and the source drain doped layer 818.
In this embodiment, the material of the interlayer dielectric layer 888 is silicon oxide. The material of the interlayer dielectric layer 888 can also be other insulating materials.
Referring to fig. 17, the dummy gate structure 808 is removed to form a gate opening (not shown); removing the space occupying layer 803 through the gate opening to form a through groove (not shown), wherein the through groove is surrounded by the adjacent channel layers 804 or is surrounded by the adjacent channel layers 804 and the substrate; a gate structure 819 is formed within the gate opening and the via, the gate structure 819 surrounding the channel layer 804.
Specifically, after forming the interlayer dielectric layer 888, a gate opening is formed.
The gate openings are used to provide a spatial location for forming the gate structures 819. The gate opening exposes the stack 810 to facilitate subsequent removal of the placeholder layer 803 in the channel stack 805 through the gate opening.
In this embodiment, the gate opening spans the stack 810.
The via and gate opening together provide a spatial location for forming the gate structure 819. The through slot is communicated with the grid opening.
In this embodiment, the placeholder 803 is removed by a vapor etching process. Specifically, the material of the channel layer 804 is Si, and the material of the space layer 803 is SiGe, so that the space layer 803 exposed by the gate opening is removed by HCl vapor, and the HCl vapor has a higher etching selectivity ratio between SiGe and Si, which is beneficial to improving the removal efficiency of the space layer 803 and reducing the probability of damage to the channel layer 804.
The gate structure 818 is used to control the turning on and off of the conduction channel during operation of the device. In this embodiment, the gate structure is a metal gate structure, and the gate structure includes a gate dielectric layer (not shown), and a gate electrode layer (not shown) located on the gate dielectric layer.
The gate electrode layer is used as an external electrode for electrically connecting the gate structure with an external circuit.
The material of the gate electrode layer includes one or more of titanium nitride (TiN), tantalum nitride (TaN), tantalum (Ta), titanium (Ti), titanium aluminide (TiAl), tungsten (W), aluminum (Al), titanium silicon nitride (TiSiN), and titanium aluminum carbide (TiAlC).
In this embodiment, the gate electrode layer includes one or both of a work function layer and an electrode layer.
In this embodiment, the work function layer is used to adjust the threshold voltage of the transistor. For example, when forming an NMOS transistor, the work function layer is an N-type work function layer, the material of the N-type work function layer including one or more of titanium aluminide and titanium aluminum carbide; when forming a PMOS transistor, the work function layer is a P-type work function layer, and the material of the P-type work function layer includes one or more of titanium nitride, tantalum nitride, and titanium silicon nitride.
The electrode layer is used for being electrically connected with an external circuit. The electrode layer is made of conductive materials including one or more of tungsten and aluminum. In this embodiment, the electrode layer is made of tungsten.
The gate dielectric layer is used for realizing electric isolation between the gate electrode layer and the conductive channel.
In this embodiment, the gate dielectric layer material includes hafnium oxide (HfO 2 ) Zirconium oxide (ZrO) 2 ) Hafnium silicon oxide (HfSiO), hafnium silicon oxynitride (HfSiON), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), hafnium zirconium oxide (HfZrO), aluminum oxide (Al) 2 O 3 ) Silicon oxide (SiO) 2 ) And lanthanum oxide (La) 2 O 3 ) One or more of the following.
In this embodiment, the gate dielectric layer includes a high-k gate dielectric layer, and the material of the high-k gate dielectric layer is a high-k dielectric material. The material of the high-k gate dielectric layer may be selected from zirconium oxide (ZrO 2 ) Hafnium silicon oxide (HfSiO), hafnium silicon oxynitride (HfSiON), hafnium tantalum oxide (HfTaO)) Hafnium titanium oxide (HfTiO), hafnium zirconium oxide (HfZrO) or aluminum oxide (Al) 2 O 3 ). In other embodiments, the gate dielectric layer may further include a gate oxide layer and a high-k gate dielectric layer on the gate oxide layer, or the gate dielectric layer may include only the gate oxide layer.
In this embodiment, the gate structure 819 is taken as an example for explanation. In other embodiments, the gate structure may also be other types of gate structures based on actual process requirements, such as: is a polysilicon gate structure or an amorphous silicon gate structure.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.

Claims (13)

1. A method of forming a semiconductor structure, comprising:
providing a substrate, wherein a laminated structure is formed on the substrate, the laminated structure comprises one or more channel laminated layers which are sequentially stacked from bottom to top, the channel laminated layers comprise a space occupying layer and a channel layer positioned on the space occupying layer, and a pseudo gate structure is also formed on the substrate, and spans the laminated structure and covers part of the top and part of the side wall of the laminated structure;
forming grooves penetrating through the laminated structure on two sides of the pseudo gate structure;
removing the occupying layer with part of the length exposed by the side wall of the groove along the extending direction of the channel layer to form an inner groove;
forming an inner side wall material layer on the side wall of the pseudo gate structure and the side wall of the groove, wherein the inner side wall material layer is also filled in the inner groove;
modifying the inner side wall material layer outside the inner groove, wherein the modification is used for converting the inner side wall material layer into a sacrificial layer, and the sacrificial layer, the inner side wall material layer and the channel layer are provided with etching selection ratios;
and removing the sacrificial layer, and reserving the residual inner side wall material layer positioned in the inner groove as an inner side wall.
2. The method for forming a semiconductor structure according to claim 1, wherein removing the sacrificial layer, leaving a remaining inner sidewall material layer located in the inner trench as an inner sidewall, further comprises:
forming a source-drain doped layer in the groove, wherein the source-drain doped layer is contacted with the end part of the channel layer along the extending direction;
removing the pseudo gate structure to form a gate opening;
removing the space occupying layer through the grid opening to form a through groove, wherein the through groove is surrounded by adjacent channel layers or is surrounded by adjacent channel layers and a substrate;
and forming a gate structure in the gate opening and the through groove, wherein the gate structure surrounds the channel layer.
3. The method of forming a semiconductor structure according to claim 1, wherein in the step of modifying the inner sidewall material layer outside the inner trench, the sacrificial layer satisfies: the etching selection ratio of the sacrificial layer to the inner side wall material layer is greater than 6:1;
the etching selectivity ratio of the sacrificial layer to the channel layer is greater than 50:1.
4. The method of forming a semiconductor structure of claim 1, wherein before modifying the inner sidewall material layer outside the inner trench, further comprising: obtaining a preset thickness of the inner side wall material layer positioned on the side wall of the pseudo gate structure;
the modification treatment of the inner side wall material layer outside the inner groove comprises the following steps: and modifying the inner side wall material layer with the preset thickness outside the inner groove.
5. The method of forming a semiconductor structure of claim 1, wherein the process of modifying comprises: a plasma treatment process or an ion implantation process.
6. The method of forming a semiconductor structure of claim 5, wherein the process parameters of the plasma processing process comprise: bias power is 100wb to 200wb;
the plasma bombardment energy is 450eV to 850eV, and the process time is more than 0 seconds and less than 600 seconds.
7. The method of forming a semiconductor structure of claim 5, wherein the process parameters of the plasma processing process comprise: the reactant gas includes one or more of helium and hydrogen.
8. The method of forming a semiconductor structure of claim 1, wherein removing the sacrificial layer comprises: wet etching processes or isotropic dry etching.
9. The method of claim 1, wherein the process of removing the sacrificial layer is a wet etching process, and the etching solution of the wet etching process comprises a hydrofluoric acid solution.
10. The method of claim 1, wherein the process of removing the sacrificial layer is a wet etching process, the wet etching process having a process time of 1 minute to 6 minutes.
11. The method of claim 1, wherein the sacrificial layer is removed and a remaining sidewall material layer within the inner trench is left as an inner sidewall, wherein a sidewall of the inner sidewall is flush with an end of the channel layer.
12. The method of forming a semiconductor structure of claim 1, wherein the process of forming the inner sidewall material layer comprises: atomic layer deposition process.
13. The method of forming a semiconductor structure of claim 1, wherein in the step of forming the inner sidewall material layer, a material of the inner sidewall material layer includes: silicon nitride and a low-k dielectric material.
CN202210675140.3A 2022-06-15 2022-06-15 Method for forming semiconductor structure Pending CN117276200A (en)

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