CN117238951A

CN117238951A - Method for forming semiconductor structure

Info

Publication number: CN117238951A
Application number: CN202210641976.1A
Authority: CN
Inventors: 纪世良; 张海洋
Original assignee: Semiconductor Manufacturing International Shanghai Corp
Current assignee: Semiconductor Manufacturing International Shanghai Corp
Priority date: 2022-06-08
Filing date: 2022-06-08
Publication date: 2023-12-15

Abstract

A method for forming a semiconductor structure includes: providing a substrate, wherein a laminated structure and a pseudo gate structure are formed on the substrate, the laminated structure comprises one or more channel laminated layers which are sequentially stacked from bottom to top, the channel laminated layers comprise a space occupying layer and a channel layer positioned on the space occupying layer, and the pseudo gate structure spans the laminated structure and covers part of the top and part of the side wall of the laminated structure; forming grooves penetrating through the laminated structure on two sides of the pseudo gate structure; removing the occupying layer with part of the length exposed by the side wall of the groove along the extending direction of the channel layer to form an inner groove; forming an inner side wall in the inner groove, wherein the width of the inner side wall is smaller than the depth of the inner groove; after forming the inner side wall, removing part of the channel layer along the extending direction of the channel layer; and after removing part of the length of the channel layer, forming a source-drain doping layer in the groove, wherein the source-drain doping layer is contacted with the end part of the channel layer along the extending direction. The embodiment of the invention is beneficial to the performance of the semiconductor device.

Description

Method for forming semiconductor structure

Technical Field

The embodiment of the invention relates to the field of semiconductor manufacturing, in particular to a method for forming a semiconductor structure.

Background

With the gradual development of semiconductor process technology, the development trend of the semiconductor process node following moore's law is continuously reduced. To accommodate the reduction in process nodes, the channel length of MOSFET field effect transistors is also correspondingly reduced. However, as the channel length of the device is reduced, the distance between the source and drain of the device is reduced, and the control capability of the gate to the channel is deteriorated.

Accordingly, to better accommodate the demands of device scaling, semiconductor processes are increasingly beginning to transition from planar MOSFET transistors to three-dimensional transistors with higher efficiency, such as fin field effect transistors (finfets). In a FinFET, the gate may control ultra-thin bodies (fins) from at least two sides, with much greater gate-to-channel control capability than planar MOSFET devices.

However, the performance of the semiconductor structure formed by the prior art needs to be improved.

Disclosure of Invention

The embodiment of the invention solves the problem of providing a method for forming a semiconductor structure, which is beneficial to improving the performance of a semiconductor device.

In order to solve the above problems, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate, wherein a laminated structure and a pseudo gate structure are formed on the substrate, the laminated structure comprises one or more channel laminated layers which are sequentially stacked from bottom to top, the channel laminated layers comprise a space occupying layer and a channel layer positioned on the space occupying layer, and the pseudo gate structure spans the laminated structure and covers part of the top and part of the side wall of the laminated structure; forming grooves penetrating through the laminated structure on two sides of the pseudo gate structure; removing the occupying layer with part of the length exposed by the side wall of the groove along the extending direction of the channel layer to form an inner groove; forming an inner side wall in the inner groove, wherein the width of the inner side wall is smaller than the depth of the inner groove; after forming the inner side wall, removing part of the channel layer along the extending direction of the channel layer; and after removing part of the length of the channel layer, forming a source-drain doping layer in the groove, wherein the source-drain doping layer is contacted with the end part of the channel layer along the extending direction.

Compared with the prior art, the technical scheme of the embodiment of the invention has the following advantages:

in the method for forming the semiconductor structure provided by the embodiment of the invention, the inner groove is formed firstly, and after the inner side wall is formed in the inner groove, the channel layer with partial length is removed along the extending direction of the channel layer, so that when the inner groove is formed, the length of the channel layer is larger, the depth of the inner groove is correspondingly increased, when the inner side wall forming process needs to remove the inner side wall material with partial width in the inner groove, so that the effect that the thickness of the inner side wall is smaller than the depth of the inner groove is achieved, the depth of the inner groove is increased, the process window for removing the inner side wall material with partial width in the inner groove is increased, the thickness of the inner side wall can reach the target thickness, and the probability of damage of the end face of the inner side wall is reduced; in addition, in different steps, the occupying layer with partial length exposed by the side wall of the groove is removed, and the channel layer with partial length is removed along the extending direction of the channel layer, so that the thickness of the inner side wall and the length of the rest channel layer are respectively and accurately controlled, the uniformity of the thickness of each inner side wall and the uniformity of the length of each channel layer are improved, and accordingly, the performance of the semiconductor device is improved.

Drawings

Fig. 1 to 7 are schematic structural views corresponding to steps in a method for forming a semiconductor structure;

fig. 8 to 15 are schematic structural views corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention.

Detailed Description

As known from the background art, the performance of the current semiconductor structure needs to be improved. The reason why the performance of a semiconductor structure is to be improved is analyzed by combining a method for forming the semiconductor structure. Fig. 1 to 7 are schematic structural views corresponding to steps in a method for forming a semiconductor structure.

Referring to fig. 1, a substrate (not shown) is provided, on which a stack structure 610 and a dummy gate structure 608 are formed, the stack structure 610 comprising one or more channel stacks 605 stacked sequentially from bottom to top, the channel stacks 605 comprising a placeholder layer 603 and a channel layer 604 on the placeholder layer 603, the dummy gate structure 608 crossing the stack structure 610 and covering a portion of the top and a portion of the sidewalls of the stack structure 610.

Referring to fig. 2, grooves 666 are formed through the stack structure 610 on both sides of the dummy gate structure 608.

With continued reference to fig. 2, along the extension of the channel layer 604, a portion of the exposed length of the sidewall of the recess 666 is removed from the stack 610.

Referring to fig. 3, after removing the stacked structure 610 with a partial width, the portion of the spacer layer 603 exposed by the sidewall of the recess 666 is removed along the extending direction of the channel layer 604, so as to form an inner trench 688.

Referring to fig. 4, an inner sidewall material layer 633 is formed on the sidewalls of the dummy gate structure 608 and the sidewalls of the groove 666, and the inner sidewall material layer 633 is also filled in the inner trench 688.

Referring to fig. 5, the inner sidewall material layers 633 located at both sides of the dummy gate structure 608 are removed, and the remaining inner sidewall material layers 633 serve as inner sidewalls 635.

Referring to fig. 6, after forming the inner sidewall 635, a source-drain doped layer 699 is formed in the recess 666, and the source-drain doped layer 699 is in contact with an end portion of the channel layer 604 in the extending direction.

Referring to fig. 7, after forming the source/drain doped layer 699, an interlayer dielectric layer 698 is formed on the substrate at the side of the dummy gate structure 608, and the interlayer dielectric layer 698 covers the source/drain doped layer 699.

With continued reference to fig. 7, the dummy gate structure 608 is removed, forming a gate opening (not shown); removing the placeholder layer 603 through the gate opening to form a through trench (not shown), which is surrounded by the adjacent channel layer 604 or by the adjacent channel layer 604 and the substrate; a gate structure 655 is formed within the gate opening and the via, the gate structure 655 surrounding the channel layer 604.

The exposed part of the length of the laminated structure 610 is removed, and then the inner trench 688 is formed, where the depth of the inner trench 688 is equal to the target thickness of the inner wall 635 formed later, and then the thickness of the inner wall material layer 633 formed in the inner trench 688 is equal to the target thickness of the inner wall 635, and in the process of removing the inner wall material layers 633 on both sides of the dummy gate structure 608, in order to remove the inner wall material layers 633 on both sides of the dummy gate structure 608 completely, a certain degree of over-etching is usually performed, and the inner wall 635 with a partial width is easily lost, so that the width of the inner wall 635 is smaller than the target thickness.

In order to solve the technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate, wherein a laminated structure and a pseudo gate structure are formed on the substrate, the laminated structure comprises one or more channel laminated layers which are sequentially stacked from bottom to top, the channel laminated layers comprise a space occupying layer and a channel layer positioned on the space occupying layer, and the pseudo gate structure spans the laminated structure and covers part of the top and part of the side wall of the laminated structure; forming grooves penetrating through the laminated structure on two sides of the pseudo gate structure; removing the occupying layer with part of the length exposed by the side wall of the groove along the extending direction of the channel layer to form an inner groove; forming an inner side wall in the inner groove, wherein the width of the inner side wall is smaller than the depth of the inner groove; after forming the inner side wall, removing part of the channel layer along the extending direction of the channel layer; and after removing part of the length of the channel layer, forming a source-drain doping layer in the groove, wherein the source-drain doping layer is contacted with the end part of the channel layer along the extending direction.

In order that the above objects, features and advantages of embodiments of the invention may be readily understood, a more particular description of the invention will be rendered by reference to specific embodiments thereof which are illustrated in the appended drawings. Fig. 8 to 15 are schematic structural views corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention.

The method for forming the semiconductor structure of the present embodiment will be described in detail below with reference to the accompanying drawings.

Referring to fig. 8, a substrate (not shown) is provided, on which a stack structure 810 and a dummy gate structure 808 are formed, the stack structure 810 including one or more channel stacks 805 stacked sequentially from bottom to top, the channel stacks 805 including a placeholder layer 803 and a channel layer 804 on the placeholder layer 803, the dummy gate structure 808 crossing the stack structure 810 and covering a portion of the top and a portion of the sidewalls of the stack structure 810.

In this embodiment, a semiconductor structure is taken as an example of a fully-enclosed Gate (GAA) transistor. In other embodiments, the semiconductor structure may also be a fork gate transistor (fork gate) or other type of transistor.

In this embodiment, in the step of providing a base, the base includes a substrate (not shown), and a fin 801 on the substrate, and a stacked structure 810 is located on top of fin 801.

The substrate is used to provide a process platform for the formation of semiconductor structures. In this embodiment, the substrate is a silicon substrate, that is, the material of the substrate is monocrystalline silicon. In other embodiments, the substrate material may be one or more of germanium, silicon carbide, gallium nitride, gallium arsenide, and indium gallium arsenide, and the substrate may be a silicon-on-insulator substrate or a germanium-on-insulator substrate, among other types of substrates.

Fin 801 serves to provide support for stacked structure 810. In this embodiment, fin 801 and the substrate are in an integrated structure, and the material of fin 801 and the material of the substrate are the same, and are all silicon. In other embodiments, the material of the fin may be different from the material of the substrate, and the material of the fin may be other suitable materials, such as: germanium, silicon carbide, gallium nitride, gallium arsenide, and indium gallium.

The channel stack 805 is used to provide a process basis for the subsequent formation of the channel layer 804 and the gate mechanism surrounding the channel layer 804. In this embodiment, the number of channel stacks 805 is 3. In other embodiments, the number of channel stacks may also be other numbers.

The channel layer 804 is used to provide the conductive channel of the transistor. The spacer 803 is used for supporting the channel 804, so as to provide a process foundation for the subsequent implementation of the space suspension arrangement of the channel 804, and the spacer 803 is also used for occupying a space position for the subsequent formation of the gate structure wrapping the channel 804.

In this embodiment, the NMOS transistor is formed, the channel layer 804 is made of Si, and the spacer layer 803 is made of SiGe. In the subsequent process of removing the space layer 803, the etching selection of SiGe and Si is relatively high, and by setting the material of the space layer 803 to SiGe and the material of the channel layer 804 to Si, the influence of the removal process of the space layer 803 on the channel layer 804 can be effectively reduced, so that the quality of the channel layer 804 is improved, and further the device performance is improved.

Dummy gate structure 808 is used to pre-occupy a spatial location for subsequent gate structure formation. Specifically, the dummy gate structure 808 is a polysilicon gate structure or an amorphous silicon gate structure. Specifically, the dummy gate structure 808 includes a dummy gate oxide layer (not labeled) and a dummy gate layer (not labeled). The material of the dummy gate oxide layer can be silicon oxide or silicon oxynitride, and the material of the dummy gate layer can be polysilicon or amorphous silicon.

Specifically, the step of forming the dummy gate structure 808 includes: forming a dummy gate structure material layer (not shown) on a substrate; forming a patterned gate mask layer 821 on the dummy gate structure material layer; the dummy gate structure material layer is etched, using the gate mask layer 821 as a mask, exposing a portion of the top wall of the stack structure 810, the remaining dummy gate structure material layer acting as a dummy gate structure 808,

the gate mask layer 821 is used as a mask during formation of the dummy gate structure 808.

In this embodiment, the gate mask layer 821 has a stacked structure, and in other embodiments, the gate mask layer may have a single-layer structure.

In this embodiment, in the step of providing the substrate, the sidewall of the dummy gate structure 808 is formed with a gate sidewall 809.

The gate sidewall 809 is used as an etching mask for a subsequent etching process for forming the recess, and the gate sidewall 809 is also used to protect the dummy gate structure 808. In this embodiment, the material of the gate sidewall 809 includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbide or silicon oxycarbonitride, boron nitride and boron carbonitride. As an example, the material of the gate sidewall 809 is silicon nitride.

In this embodiment, the gate sidewall 809 also covers the top wall of the exposed stacked structure 810.

Referring to fig. 9, grooves 811 penetrating the stacked structure 810 are formed at both sides of the dummy gate structure 808.

The recess 811 is used to provide a space for the subsequent formation of the source-drain doped layer.

In this embodiment, in the step of forming the grooves 811 penetrating the stacked structure 810 at two sides of the dummy gate structure 808, along the extending direction of the channel layer 804, the end portion of the stacked structure 810 exposed by the grooves 811 is flush with the outer sidewall of the gate sidewall 809, so that it is beneficial to remove the space occupying layer 803 of a part of the length exposed by the sidewall of the groove 811 and remove the channel layer 804 of a part of the length along the extending direction of the channel layer 804 in different steps, so that it is beneficial to precisely control the thickness of the inner sidewall and the length of the remaining channel layer 804, which are formed later, respectively, so as to improve the uniformity of the thickness of each inner sidewall and the uniformity of the length of each channel layer, and accordingly, improve the performance of the semiconductor device. Wherein the outer sidewall of the gate sidewall 809 refers to the sidewall of the gate sidewall 809 facing away from the dummy gate structure 808.

Specifically, in this embodiment, the process of forming the grooves 811 penetrating the stacked structure 810 on both sides of the dummy gate structure 808 includes: the anisotropic dry etching process is beneficial to improving the profile quality of the groove 811 and further beneficial to accurately controlling the sidewall profile of the groove 811.

In this embodiment, the reaction gas of the anisotropic dry etching process includes CF ₄ 、SF ₆ 、N ₂ 、H ₂ 、O ₂ And NF (NF) ₃ One or more of the following. As an example, the reaction gas is SF ₆ 、N ₂ And O ₂ Is a mixed gas of (a) and (b).

In this embodiment, in order to improve the perpendicularity of the sidewall of the groove 811, the bias voltage of the anisotropic dry etching process is greater than or equal to 500V.

Specifically, the bias voltage is not too small nor too large. When the bias voltage is too small, the etching uniformity is easily degraded, so that the length of the channel stack 805 close to the substrate is easily longer than that of the channel stack 805 far from the substrate after etching, which is not beneficial to improving the verticality of the side wall of the groove 811; when the bias voltage is excessively large, the probability of damage to the gate mask layer 821 is easily increased during the anisotropic dry etching. For this reason, in the present embodiment, the bias voltage is 500V to 2000V.

In this embodiment, in order to improve the verticality of the sidewall of the groove 811, the process pressure of the anisotropic dry etching process is less than or equal to 30mT.

In particular, the process pressure should not be too low nor too high. When the process pressure is too small, the starting process is not facilitated; when the process pressure is too high, the stability of the etching rate is easily reduced, so that the uniformity of the shape of the groove 811 is reduced, and the perpendicularity of the side wall of the groove 811 is not improved. For this purpose, in the present embodiment, the process pressure is 5mT to 30mT.

In this embodiment, the process temperature of the anisotropic dry etching process is not too low or too high. When the process temperature is too small, the working efficiency of the process is easy to be reduced, and the process time is further increased; when the process temperature is too high, the uniformity of the shape of the groove 811 is easily reduced. For this purpose, in the present example, the process temperature is 60℃to 120 ℃.

Note that before etching the stacked structure 810 on both sides of the dummy gate structure 808, the method further includes: the top of dummy gate structure 808 and gate sidewall 809 on stack 810 are etched away.

Correspondingly, the stacked structures 810 on both sides of the dummy gate structure 808 are etched using the gate sidewall 809 on the sidewall of the dummy gate structure 808 as a mask to form a recess 811.

Referring to fig. 10, the spacer 803 is removed along a portion of the length of the exposed sidewall of the trench 811 along the extending direction of the channel layer 804, thereby forming an inner trench 812.

Specifically, an inner trench 812 is formed between adjacent channel layers 804, and between adjacent channel layers 804 and fin 801. The inner trench 812 provides a spatial location for the subsequent formation of an inner sidewall.

In this embodiment, when the inner trench 812 is formed, the length of the channel layer 804 is larger, which correspondingly increases the depth of the inner trench 812, and the subsequent process of forming the inner sidewall needs to remove the inner sidewall material with a partial width of the inner trench 812, so as to achieve the effect that the thickness of the inner sidewall is smaller than the depth of the inner trench 812, the depth of the inner trench 812 is increased, the process window for removing the inner sidewall material with a partial width of the inner trench 812 is increased, which is beneficial to enabling the thickness of the inner sidewall to reach the target thickness, and reducing the probability of damage to the end surface of the inner sidewall.

In this embodiment, a vapor etching process is used to etch the space occupying layer 803 with a partial width exposed by the sidewall of the groove 811 along the extending direction of the channel layer 804. The vapor etching process is an isotropic etching process, and can etch the space occupying layer 803 along the extending direction of the channel layer 804, and the vapor etching process is easy to realize a larger etching selection ratio, thereby being beneficial to reducing the difficulty of etching the space occupying layer 803 and reducing the probability of damaging other film structures (such as the channel layer 804).

In the step of forming the inner trench 812, the depth of the inner trench 812 is not too small or too large along the extending direction of the channel layer 804, and the thickness of the inner sidewall formed in the inner trench 812 is too small when the depth of the inner trench 812 is too small, which is not beneficial to supporting the channel layer 804; when the depth of the inner trench 812 is too large, the width of the gate structure formed later is reduced, so that the wrapping force of the gate structure on the channel layer 804 is reduced, and the control capability of the gate structure on the channel 804 is further reduced; for this reason, in the present embodiment, the depth of the inner trench 812 is 3nm to 20nm.

In this embodiment, the material of the space layer 803 is SiGe, the material of the channel layer 804 is Si, and the space layer 803 on the sidewall of the groove 811 is vapor etched by HCl vapor. The etching rate of the HCl vapor to the SiGe material is much greater than the etching rate to the Si material, which effectively reduces the probability of damage to the channel layer 804.

Referring to fig. 11 and 12, an inner sidewall 817 is formed in the inner trench 812, and the width of the inner sidewall 817 is smaller than the depth of the inner trench 812.

The inner sidewall wall 817 is used for supporting the channel layer 804, so that the replacement of the dummy gate structure 808 with the gate structure is facilitated, in addition, the inner sidewall wall 817 is used for realizing the isolation between the source-drain doped layer and the gate structure which are formed later, so that the distance between the gate structure and the source-drain doped layer is increased, and the parasitic capacitance between the gate structure and the source-drain doped layer is reduced.

Moreover, the width of the inner sidewall 817 is smaller than the depth of the inner trench 812, so that the distance between the source-drain doped layer and the gate structure can meet the design requirement, and meanwhile, the width of the inner sidewall 817 is smaller than the depth of the inner trench 812 because the channel layer 804 with part of the length is required to be removed along the extending direction of the channel layer 804, which is beneficial to improving the flatness of the side wall of the inner sidewall 817 and the end of the subsequent channel layer 804, thereby providing a good interface foundation for the subsequent formation of the source-drain doped layer 818 and further improving the formation quality of the source-drain doped layer 818.

In this embodiment, along the extending direction of the channel layer 804, the width of the inner sidewall 817 is smaller than the depth of the inner trench 812, specifically, since the inner sidewall material layers 830 on two sides of the dummy gate structure 808 are removed and the initial inner sidewall 831 with a partial width is removed during the forming of the inner sidewall 817, the initial inner sidewall 831 is easier to be removed, and thus the width of the inner sidewall 817 is smaller than the depth of the inner trench 812.

In the step of forming the inner sidewall 817 in the inner trench 812, the thickness of the inner sidewall 817 is not too small or too large along the extending direction of the channel layer, and when the thickness of the inner sidewall 817 is too small, the supporting of the channel layer 804 is not facilitated, and the isolation between the subsequently formed source-drain doped layer and the gate structure is not facilitated; when the thickness of the inner sidewall 817 is too large, it is not beneficial to provide a flat interface for the subsequently formed source-drain doped layer, so that the subsequently formed source-drain doped layer has poor quality, and the length of the subsequently formed gate structure is reduced, so that the control force of the gate structure on the channel layer 804 is reduced, and in this embodiment, the thickness of the inner sidewall 817 is 3nm to 8nm.

In this embodiment, in the step of forming the inner sidewall 817 in the inner trench 812, the material of the inner sidewall 817 includes: one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbide or silicon oxycarbonitride, boron nitride, and boron carbonitride; as an example, the material of the inner sidewall 817 is silicon nitride.

The steps of forming the inner sidewall 817 according to the present embodiment will be described in detail with reference to the accompanying drawings.

As shown in fig. 11, the step of forming the sidewall wall 817 in the inner trench 812 includes: an inner sidewall material layer 830 is formed on the sidewalls of the dummy gate structure 808 and on the sidewalls of the recess 811, the inner sidewall material layer 830 also filling the inner trench 812, the sidewall material layer 830 in the inner trench 812 serving as an initial inner sidewall 831.

The initial sidewall spacers 831 are used to form the sidewall spacers subsequently.

Specifically, the inner sidewall material layer 830 is formed on the sidewall of the dummy gate structure 808 and the sidewall of the recess 811 by an atomic layer deposition process (Atomic Layer Deposition, ALD), which has good step coverage, and accordingly, the inner sidewall material layer 830 having high quality and high thickness uniformity is formed.

Note that since the gate sidewall 809 is formed on the sidewall of the dummy gate structure 808, the gate sidewall 809 is covered by the inner sidewall material layer 830 located on the sidewall of the dummy gate structure 808.

As shown in fig. 12, the inner sidewall material layer 830 on both sides of the dummy gate structure 808 and a part of the initial inner sidewall 831 having a width are removed, and the remaining initial inner sidewall 831 serves as an inner sidewall 817.

The inner sidewall material layer 830 and the initial inner sidewall 831 having a partial width are removed from both sides of the dummy gate structure 808, thereby facilitating a reduction in the thickness of the inner sidewall 817.

In this embodiment, the process for removing the inner sidewall material layer 830 and the initial inner sidewall 831 with partial width on both sides of the dummy gate structure 808 includes: an isotropic dry etching process or a wet etching process. The isotropic dry etching process and the wet etching process both have the characteristic of isotropic etching, so that the initial inner side wall 831 positioned in the inner trench 812 can be laterally etched while the inner side wall material layers 830 on both sides of the dummy gate structure 808 are removed cleanly, so that the width of the initial inner side wall 831 is reduced, and the width of the inner side wall 817 is smaller than the depth of the inner trench 812.

As an example, the inner sidewall material layers 830 on both sides of the dummy gate structure 808 and the initial inner sidewall 831 with a partial width are removed by using an isotropic dry etching process, and the selectivity of the isotropic dry etching process is good, so that the initial inner sidewall 831 is removed in a targeted manner.

Referring to fig. 13, after forming the sidewall 817, a portion of the channel layer 804 is removed along an extension direction of the channel layer 804.

The channel layer 804 with part of the length is removed along the extending direction of the channel layer 804, so that the source-drain doped layer formed later is beneficial to applying stress to the channel layer 804, and the performance of the semiconductor device is improved.

In this embodiment, in the step of removing a part of the length of the channel layer 804 along the extending direction of the channel layer 804, the length of the channel layer 804 is not too long, and if the length of the channel layer 804 is too long, the probability of poor contact between the source/drain doped layer and the channel layer 804 is increased in the subsequent process of forming the source/drain doped layer. For this reason, in the present embodiment, the length of the removed channel layer 804 is greater than 0nm and less than or equal to 10nm.

Specifically, the process of removing a portion of the length of the channel layer 804 includes: the isotropic dry etching process has good selectivity, and based on the characteristic of isotropic etching, the channel layer 804 can be laterally etched, thereby being beneficial to the targeted removal of part of the length of the channel layer 804. In other embodiments, the process of removing a portion of the length of the channel layer further includes a wet etch process.

Referring to fig. 14, after removing a portion of the length of the channel layer 804, a source-drain doped layer 818 is formed in the recess 811, and the source-drain doped layer 818 is in contact with an end portion of the channel layer 804 in the extending direction.

The source drain doped layer 818 is used to serve as the source or drain of the transistor and the source drain doped layer 818 is used to provide a source of carriers when the transistor is operating.

In this embodiment, the source-drain doped layer 818 includes a stress layer doped with ions, and the stress layer is used to provide stress to the channel region, so as to improve the mobility of carriers. Specifically, when forming an NMOS transistor, the source-drain doped layer 818 includes a stress layer doped with N-type ions, where the material of the stress layer is Si or SiC; when forming a PMOS transistor, the source drain doped layer 818 includes a stress layer doped with P-type ions, the material of the stress layer being Si or SiGe.

In this embodiment, an epitaxial process is used to form a stress layer, and ions are self-doped in situ during the formation of the stress layer, and the stress layer doped with ions is used as the source/drain doped layer 818.

In other embodiments, the stress layer may be ion implanted after the stress layer is formed.

Referring to fig. 15, in this embodiment, after forming the source-drain doped layer 818, before forming the gate opening, the method further includes: an interlayer dielectric layer 888 is formed on the substrate on the sides of the dummy gate structure 808, the interlayer dielectric layer 888 covering the source drain doped layer 818.

The interlayer dielectric layer 888 is used for isolating adjacent devices, and is also used for supporting the channel layer 804 in the process of removing the dummy gate structure 808 and the placeholder layer 803, so as to realize suspended interval arrangement of the channel layer 804.

Specifically, an interlayer dielectric layer 888 covers the sidewalls of the gate sidewall 809 and the source drain doped layer 818.

In this embodiment, the material of the interlayer dielectric layer 888 is silicon oxide. The material of the interlayer dielectric layer 888 can also be other insulating materials.

With continued reference to fig. 15, after forming the source drain doped layer 818, further includes: removing the dummy gate structure 808 to form a gate opening (not shown); the space occupying layer 803 is removed through the gate opening, and a through groove (not shown) is formed, wherein the through groove is surrounded by the adjacent channel layers 804 or is surrounded by the adjacent channel layers 804 and the substrate; a gate structure 819 is formed within the gate opening and the via, the gate structure 819 surrounding the channel layer 804.

Specifically, after forming the interlayer dielectric layer 888, a gate opening is formed.

The gate openings are used to provide a spatial location for forming the gate structures 819. The gate opening exposes the stack 810 to facilitate subsequent removal of the placeholder layer 803 in the channel stack 805 through the gate opening.

In this embodiment, the gate opening spans the stack 810.

The via and gate opening together provide a spatial location for forming the gate structure 819. The through slot is communicated with the grid opening.

In this embodiment, the placeholder 803 is removed by a vapor etching process. Specifically, the material of the channel layer 804 is Si, and the material of the space layer 803 is SiGe, so that the space layer 803 exposed by the gate opening is removed by HCl vapor, and the HCl vapor has a higher etching selectivity ratio between SiGe and Si, which is beneficial to improving the removal efficiency of the space layer 803 and reducing the probability of damage to the channel layer 804.

The gate structure 819 is used to control the turning on and off of the conductive channel during device operation. In this embodiment, the gate structure 819 is a metal gate structure 819, and the gate structure 819 includes a gate dielectric layer (not shown), a work function layer (not shown) on the gate dielectric layer, and a gate electrode layer (not shown) on the work function layer and filling the via and the gate opening.

The gate dielectric layer is used for realizing electrical isolation between the work function layer and the gate electrode layer and the conductive channel. The material of the gate dielectric layer comprises one or more of silicon oxide, silicon oxynitride, hafnium oxide, zirconium oxide, hafnium silicon oxynitride, hafnium tantalum oxide, hafnium titanium oxide, hafnium zirconium oxide, aluminum oxide, silicon oxide and lanthanum oxide.

In this embodiment, the gate dielectric layer includes a high-k gate dielectric layer, and the material of the high-k gate dielectric layer is a high-k dielectric material. The material of the high-k gate dielectric layer may be selected from zirconium oxide, hafnium silicon oxynitride, hafnium tantalum oxide, hafnium titanium oxide, hafnium zirconium oxide, or aluminum oxide. In other embodiments, the gate dielectric layer may further include a gate oxide layer and a high-k gate dielectric layer on the gate oxide layer, or the gate dielectric layer may include only the gate oxide layer.

The work function layer is used to adjust the work function of the gate structure 819 and thus the threshold voltage of the field effect transistor. When the NMOS transistor is formed, the work function layer is an N-type work function layer, and the material of the work function layer comprises one or more of titanium aluminide, tantalum carbide, aluminum or titanium carbide; when the PMOS transistor is formed, the work function layer is a P-type work function layer, and the material of the work function layer includes one or more of titanium nitride, tantalum nitride, titanium carbide, tantalum silicon nitride, titanium silicon nitride, and tantalum carbide.

The gate electrode layer is used as an external electrode for electrically connecting the gate structure 819 to an external circuit. The material of the gate electrode layer is a conductive material including one or more of titanium nitride, tantalum, titanium aluminide, titanium aluminum carbide, titanium silicon nitride, tungsten, cobalt, aluminum, copper, silver, gold, platinum, and nickel.

In this embodiment, the gate structure 819 is taken as an example for explanation. In other embodiments, the gate structure may also be other types of gate structures based on actual process requirements, such as: is a polysilicon gate structure or an amorphous silicon gate structure.

Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.

Claims

1. A method of forming a semiconductor structure, comprising:

providing a substrate, wherein a laminated structure and a pseudo gate structure are formed on the substrate, the laminated structure comprises one or more channel laminated layers which are sequentially stacked from bottom to top, the channel laminated layers comprise a space occupying layer and a channel layer positioned on the space occupying layer, and the pseudo gate structure spans the laminated structure and covers part of the top and part of the side wall of the laminated structure;

forming grooves penetrating through the laminated structure on two sides of the pseudo gate structure;

removing the occupying layer with part of the length exposed by the side wall of the groove along the extending direction of the channel layer to form an inner groove;

forming an inner side wall in the inner groove, wherein the width of the inner side wall is smaller than the depth of the inner groove;

after forming the inner side wall, removing part of the channel layer along the extending direction of the channel layer;

and after removing part of the length of the channel layer, forming a source-drain doped layer in the groove, wherein the source-drain doped layer is contacted with the end part of the channel layer along the extending direction.

2. The method for forming a semiconductor structure according to claim 1, further comprising, after forming the source-drain doped layer: removing the pseudo gate structure to form a gate opening;

removing the space occupying layer through the grid opening to form a through groove, wherein the through groove is surrounded by adjacent channel layers or is surrounded by adjacent channel layers and a substrate;

and forming a gate structure in the gate opening and the through groove, wherein the gate structure surrounds the channel layer.

3. The method of forming a semiconductor structure of claim 1, wherein forming an interior sidewall within the interior trench comprises: forming an inner side wall material layer on the side wall of the pseudo gate structure and the side wall of the groove, wherein the inner side wall material layer is also filled in the inner groove, and the side wall material layer in the inner groove is used as an initial inner side wall;

and removing the inner side wall material layers positioned on two sides of the pseudo gate structure and the initial inner side wall with partial width, wherein the rest initial inner side walls are used as inner side walls.

4. The method of forming a semiconductor structure of claim 3, wherein the process of forming the inner sidewall material layer comprises: atomic layer deposition process.

5. The method of forming a semiconductor structure of claim 3, wherein removing the layer of sidewall material on both sides of the dummy gate structure and the portion of the initial sidewall of the width comprises: an isotropic dry etching process or a wet etching process.

6. The method of forming a semiconductor structure according to claim 1, wherein in the step of forming the inner trench, a depth of the inner trench is 3nm to 20nm along an extending direction of the channel layer.

7. The method of forming a semiconductor structure according to claim 1, wherein in the step of forming an inner sidewall in the inner trench, a thickness of the inner sidewall is 3nm to 8nm along an extending direction of the channel layer.

8. The method of forming a semiconductor structure according to claim 1, wherein in the step of removing a part of the length of the channel layer in the extending direction of the channel layer, the length of the channel layer is removed to be greater than 0nm and less than or equal to 10nm.

9. The method of forming a semiconductor structure of claim 1, wherein removing a portion of the length of the channel layer comprises: an isotropic dry etching process or a wet etching process.

10. The method of forming a semiconductor structure of claim 1, wherein in the step of providing a substrate, a sidewall of the dummy gate structure is formed with a gate sidewall;

and in the step of forming grooves penetrating through the laminated structure on two sides of the pseudo gate structure, along the extending direction of the channel layer, the end parts of the laminated structure exposed by the grooves are flush with the outer side walls of the grid side walls.

11. The method of forming a semiconductor structure of claim 1, wherein forming grooves through the stacked structure on both sides of the dummy gate structure comprises: an anisotropic dry etching process.

12. The method of forming a semiconductor structure of claim 11, wherein the process parameters of the anisotropic dry etching process comprise: the reaction gas includes CF ₄ 、SF ₆ 、N ₂ 、H ₂ 、O ₂ And NF (NF) ₃ One or more of the following; the bias voltage is 500V to 2000V; the process pressure is 5mT to 30mT; the process temperature is 60 ℃ to 120 ℃.

13. The method of claim 1, wherein in forming the liner within the liner trench, the liner wall comprises one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbide or silicon oxycarbonitride, boron nitride, and boron carbonitride.

14. The method of forming a semiconductor structure of claim 1, wherein in the step of providing a base, the base comprises a substrate and a fin on the substrate, the stacked structure being on top of the fin.