CN117410234A - Semiconductor structure and forming method thereof - Google Patents

Semiconductor structure and forming method thereof Download PDF

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Publication number
CN117410234A
CN117410234A CN202210788210.6A CN202210788210A CN117410234A CN 117410234 A CN117410234 A CN 117410234A CN 202210788210 A CN202210788210 A CN 202210788210A CN 117410234 A CN117410234 A CN 117410234A
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Prior art keywords
layer
channel
forming
device region
channel layer
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司进
殷立强
崇二敏
张海洋
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Semiconductor Manufacturing International Shanghai Corp
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Semiconductor Manufacturing International Shanghai Corp
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Priority to CN202210788210.6A priority Critical patent/CN117410234A/en
Publication of CN117410234A publication Critical patent/CN117410234A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823821—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0924—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

A semiconductor structure and a forming method thereof are provided, wherein the method is characterized in that a thinning treatment is carried out on the channel layer, a first channel material is grown on the thinned channel layer to form a first channel layer, so that the materials of the first channel layer and a second channel layer are different, the organic combination of a full-surrounding grid structure and a double-fin structure can be realized, and the performance of the formed semiconductor structure can be improved.

Description

Semiconductor structure and forming method thereof
Technical Field
The present disclosure relates to semiconductor manufacturing, and more particularly, to a semiconductor structure and a method for forming the same.
Background
With the rapid development of semiconductor manufacturing technology, semiconductor transistors are being developed toward higher element density and higher integration, and the development trend of semiconductor process nodes following moore's law is continuously decreasing. Transistors are currently being widely used as the most basic semiconductor transistors, and therefore, as the element density and integration level of the semiconductor transistors are increased, the channel length of the transistors has to be continuously shortened in order to accommodate the reduction of process nodes.
To better accommodate the demands of transistor scaling, semiconductor processes are gradually beginning to transition from planar transistors to three-dimensional transistors with higher power, such as fin field effect transistors (finfets), gate-all-around (GAA) transistors, and the like. Wherein the fully-enclosed gate transistors include vertical fully-enclosed gate transistors and horizontal fully-enclosed gate transistors. In the fully-enclosed gate transistor, the gate encloses the region where the channel is located from the periphery, and compared with a planar transistor, the gate of the fully-enclosed gate transistor has stronger control capability on the channel and can better inhibit the short channel effect.
With further shrinking device dimensions, how to achieve an organic bond between a fully-surrounding gate structure and a dual fin structure in order to improve the performance of the formed semiconductor structure has become a problem to be solved.
Disclosure of Invention
The invention solves the problem of providing a semiconductor structure and a forming method thereof, so as to realize the organic combination between a full-surrounding grid structure and a double-fin structure and improve the performance of the formed semiconductor structure.
In order to solve the above problems, the present invention provides a method for forming a semiconductor structure, including:
providing a base, wherein the base is provided with a first device region and a second device region, the base comprises a substrate, a first protruding part protruding on the substrate of the first device region and a second protruding part protruding on the substrate of the second device region, and the first protruding part and the second protruding part are made of different materials;
forming suspended channel layers on the first protruding part and the second protruding part;
performing thinning treatment on the channel layer on the first protruding part, and growing a first channel material on the thinned channel layer to form a first channel layer, wherein the first channel material is different from the channel layer; the channel layer on the second protruding portion serves as a second channel layer;
Forming a first gate structure on the first device region, crossing the first protrusion and surrounding the first channel layer;
a second gate structure is formed on the second device region, spanning the second protrusion and surrounding the second channel layer.
Optionally, the step of forming a suspended channel layer on the first and second protruding portions includes:
forming a channel stack on the first and second protrusions, the channel stack including a sacrificial layer and a channel layer on the sacrificial layer;
removing the sacrificial layers on the first protruding part and the second protruding part to form a suspended channel layer;
the step of forming the first gate structure and the second gate structure includes:
forming a dummy gate structure across the first protrusion, the second protrusion, and the channel stack after forming the channel stack;
removing the pseudo gate structure before removing the sacrificial layers on the first protruding portion and the second protruding portion to form a gate trench;
after forming a gate trench, removing the sacrificial layer exposed by the gate trench, and forming a first through groove positioned on the first device region and a second through groove positioned on the second device region;
And after the first channel layer is formed, filling the gate groove, the first through groove and the second through groove to form the first gate structure and the second gate structure.
Optionally, the material of the dummy gate structure includes polysilicon.
Optionally, after forming the dummy gate structure, the method further includes:
etching channel stacks on two sides of the pseudo gate structure of the first device region, and forming a first groove exposing the first protruding part in the channel stacks on two sides of the pseudo gate structure of the first device region;
etching channel stacks at two sides of the pseudo gate structure of the second device region, and forming a second groove exposing the second protruding part in the channel stacks at two sides of the pseudo gate structure of the second device region;
forming a first source-drain doping layer in the first groove;
and forming a second source-drain doping layer in the second groove.
Optionally, after forming the first groove and before forming the first source-drain doped layer, the method further includes: etching the sacrificial layer with partial thickness exposed out of the side wall of the first groove along a preset direction to form a first groove, wherein the first groove is surrounded by the adjacent channel layer and the rest sacrificial layer on the first protruding part, or the first groove is surrounded by the first protruding part, the channel layer adjacent to the first protruding part and the rest sacrificial layer, and the preset direction is a direction parallel to the substrate and perpendicular to the extending direction of the grid structure; forming a first inner wall layer in the first groove;
After forming the second groove and before forming the second source-drain doped layer, the method further comprises: etching the sacrificial layer with partial thickness exposed out of the side wall of the second groove along the preset direction to form a second groove, wherein the second groove is surrounded by the adjacent channel layer and the rest of the sacrificial layer on the second protruding part, or the second groove is surrounded by the second protruding part, the channel layer adjacent to the second protruding part and the rest of the sacrificial layer; and forming a second inner wall layer in the second groove.
Optionally, the step of forming the first groove includes:
forming a first side wall layer on the channel lamination layers at two sides of the pseudo gate structure of the first device region, and forming a second side wall layer on the channel lamination layers at two sides of the pseudo gate structure of the second device region;
and etching the channel stack layer by taking the pseudo gate structure, the first side wall layer and the second side wall layer as masks to form the first groove and the second groove.
Optionally, the process of forming the first recess and the second recess includes an anisotropic dry etching process.
Optionally, the materials of the first side wall layer and the second side wall layer include one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride oxide, silicon oxynitride, boron nitride and boron carbonitride.
Optionally, the material of the channel layer is silicon, and the material of the sacrificial layer is silicon germanium.
Optionally, the first device region is used for forming a PMOS transistor, and the second device region is used for forming an NMOS transistor;
the channel layer is made of silicon, and the first channel material is silicon germanium.
Optionally, the process of performing the thinning treatment on the channel layer on the first protruding portion is an atomic layer etching process.
Optionally, the process of forming the first channel material is an epitaxial process.
Correspondingly, the embodiment of the invention also provides a semiconductor structure, which comprises:
a base having a first device region and a second device region, the base including a substrate, a first protruding portion protruding on the substrate of the first device region, and a second protruding portion protruding on the substrate of the first device region;
the first channel layer is positioned on the first protruding part in a suspending mode, and comprises a thinned channel layer and a first channel material positioned on the thinned channel layer, wherein the thinned channel layer is obtained by thinning the suspended channel layer on the first protruding part; the first channel material is different from the material of the channel layer;
The second channel layer is positioned on the second protruding part in a suspending way and comprises a channel layer which is positioned on the second protruding part in a suspending way;
a first gate structure crossing the first protrusion and the first channel layer and surrounding the first channel layer;
and a second gate structure crossing the second protrusion and the second channel layer and surrounding the second channel layer.
Optionally, the first device region is used for forming a PMOS transistor, and the second device region is used for forming an NMOS transistor; the channel layer is made of silicon, and the first channel material is silicon germanium.
Optionally, the semiconductor structure further includes:
the first source-drain doping layer is positioned in the channel stack layers at two sides of the first grid structure;
and the second source-drain doped layer is positioned in the channel laminated layers at two sides of the second grid structure.
Optionally, the semiconductor structure further includes:
the first inner wall layer is positioned between the first source-drain doping layer and the first grid structure;
and the second inner wall layer is positioned between the second source-drain doping layer and the second grid structure. Compared with the prior art, the technical scheme of the invention has the following advantages:
the method for forming the semiconductor structure provided by the embodiment of the invention comprises the following steps: providing a base, wherein the base is provided with a first device region and a second device region, the base comprises a substrate, a first protruding part protruding on the substrate of the first device region and a second protruding part protruding on the substrate of the second device region, and the first protruding part and the second protruding part are made of different materials; forming suspended channel layers on the first protruding part and the second protruding part; performing thinning treatment on the channel layer on the first protruding part, and growing a first channel material on the thinned channel layer to form a first channel layer, wherein the first channel material is different from the channel layer; the channel layer on the second protruding portion serves as a second channel layer; forming a first gate structure on the first device region, crossing the first protrusion and surrounding the first channel layer; a second gate structure is formed on the second device region, spanning the second protrusion and surrounding the second channel layer.
It can be seen that the thinning process is performed on the channel layer on the first protruding portion, and a first channel material is grown on the thinned channel layer to form a first channel layer, where the first channel material is different from the material of the channel layer, so that the materials of the first channel layer and the second channel layer are different, and an organic combination of the fully-surrounding gate structure and the double-fin structure can be achieved, so that performance of the formed semiconductor structure can be improved.
Drawings
Fig. 1 to 10 are schematic views of intermediate structures formed by steps of a method for forming a semiconductor structure according to an embodiment of the present invention.
Detailed Description
As known from the background art, how to realize the organic combination of the fully-surrounding gate structure and the double-fin structure has higher difficulty and challenge.
In order to solve the above problems, a method for forming a semiconductor structure according to an embodiment of the present invention includes: providing a base, wherein the base is provided with a first device region and a second device region, the base comprises a substrate, a first protruding part protruding on the substrate of the first device region and a second protruding part protruding on the substrate of the second device region, and the first protruding part and the second protruding part are made of different materials; forming suspended channel layers on the first protruding part and the second protruding part; performing thinning treatment on the channel layer on the first protruding part, and growing a first channel material on the thinned channel layer to form a first channel layer, wherein the first channel material is different from the channel layer; the channel layer on the second protruding portion serves as a second channel layer; forming a first gate structure on the first device region, crossing the first protrusion and surrounding the first channel layer; a second gate structure is formed on the second device region, spanning the second protrusion and surrounding the second channel layer.
It can be seen that the thinning process is performed on the channel layer on the first protruding portion, and a first channel material is grown on the thinned channel layer to form a first channel layer, where the first channel material is different from the material of the channel layer, so that the materials of the first channel layer and the second channel layer are different, and an organic combination of the fully-surrounding gate structure and the double-fin structure can be achieved, so that performance of the formed semiconductor structure can be improved.
In order that the above objects, features and advantages of embodiments of the invention may be readily understood, a more particular description of the invention will be rendered by reference to specific embodiments thereof which are illustrated in the appended drawings.
Fig. 1 to 10 are schematic structural views corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention.
Referring to fig. 1, a base (not shown) having a first device region I and a second device region II is provided, the base including a substrate 10 and a first protrusion 11 protruding on the substrate 10 of the first device region I and a second protrusion 12 protruding on the substrate 10 of the second device region II, the first protrusion 11 being of a different material than the second protrusion 12.
The substrate provides a process platform for forming transistors with a combination of Gate-all-around (GAA) and Dual Fin structures.
In this embodiment, the substrate is a three-dimensional structure. Specifically, the base includes a substrate 10 and first and second protrusions 11 and 12 protruding from the substrate 10.
In this embodiment, the substrate 10 is a silicon substrate. In other embodiments, the substrate may also be made of other materials such as germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, and the substrate may also be made of other types of substrates such as silicon on insulator substrates or germanium on insulator substrates. In addition, the material of the substrate can be a material suitable for process requirements or easy integration.
The first device region I is used for forming a first type transistor, the second device region II is used for forming a second type transistor, and the doping types of the first type transistor and the second type transistor are different. Wherein the first type and the second type refer to the doping type of the transistor, namely the doping type of the source-drain doping layer in the transistor.
In this embodiment, the first device region I is used to form a PMOS transistor, and the second device region II is used to form an NMOS transistor. In other embodiments, the first device region can also be used to form NMOS transistors and the second device region can also be used to form PMOS transistors.
In this embodiment, the first protruding portion 11 is different from the material of the substrate 10, and the second protruding portion 12 is the same as the material of the substrate 10. Specifically, the material of the first bump 11 is silicon germanium, and the material of the second bump 12 is silicon.
Referring to fig. 2, a channel stack 20 is formed on the substrate 10 to cover the first and second protrusions 11 and 12, the channel stack 20 including a sacrificial layer 21 and a channel layer 22 on the sacrificial layer 21.
Channel stack 20 provides a basis for subsequent formation of a suspended channel layer over first device region I and second device region II.
Specifically, the sacrificial layer 21 is configured to support the channel layer 22, thereby providing a process basis for the channel layer 22 suspended and spaced above the first device region I and the second device region II to be subsequently realized, and occupying part of the spatial positions for the formation of the first gate structure and the second gate structure to be subsequently realized.
In order to effectively reduce the influence of the removal process of the sacrificial layer 21 on the channel layer 22 during the subsequent removal of the sacrificial layer 21, the sacrificial layer 21 should be made of a material having a higher etching selectivity rate with respect to the channel layer 22. In this embodiment, the material of the sacrificial layer 21 is silicon germanium, and the material of the channel layer 22 is silicon.
In this embodiment, the channel stack 20 is formed on the substrate 10 and covers the first protruding portion 11 and the second protruding portion 12, so as to provide a foundation for the subsequent formation of a suspended channel layer on the first protruding portion 11 and the second protruding portion 12.
The step of forming the channel stack 20 includes: providing a substrate 10; forming one or more stacked channel material stacks (not shown) on the substrate 10, the channel material stacks further covering the first and second protrusions 11 and 12, the channel material stacks including a sacrificial material layer (not shown) and a channel material layer (not shown) on the sacrificial material layer; the channel material stack is patterned to form one or more stacked channel stacks 20 on the first and second protrusions 11, 12.
In this embodiment, the number of channel stacks 20 is 3, and the number of channel material stacks is correspondingly 3.
In this embodiment, the channel material stack is formed on the substrate 10 and the first and second protruding portions 11 and 12 by an epitaxial growth process, and the epitaxial growth process may form a sacrificial material layer and a channel material layer with better quality, so that the sacrificial layer 21 and the channel layer 22 are formed with correspondingly better quality, and the channel of the formed transistor with the full-surrounding gate structure is located in a high-quality material, thereby being beneficial to improving the device performance.
Referring to fig. 3 and 4, in this embodiment, after the channel stack 20 is formed, the method for forming the semiconductor structure further includes: a dummy gate structure 30 is formed on the substrate 10 across the first raised portion 11, the second raised portion 12 and the channel stack 20.
The dummy gate structure 30 occupies a spatial position for subsequent formation of the first gate structure and the second gate structure.
In this embodiment, the dummy gate structure 30 covers a portion of the sidewall of the first protrusion 11 of the first device region I, a portion of the sidewall of the first protrusion 11 of the second device region II, and a portion of the top and a portion of the sidewall of the channel stack 20. Substrate and method for manufacturing the same
In this embodiment, the dummy gate structure 30 has a single layer structure. Specifically, the dummy gate structure 30 includes a dummy gate layer covering a portion of the sidewall of the first protrusion 11 of the first device region I, a portion of the sidewall of the first protrusion 11 of the second device region II, and a portion of the top and a portion of the sidewall of the channel stack 20.
Specifically, the step of forming the dummy gate structure 30 includes: forming a dummy gate material layer (not shown) across the channel stack 20; forming a gate mask layer (not shown) on the surface of the dummy gate material layer; and etching the dummy gate material layer by taking the gate mask layer as a mask until the channel stack 20 is exposed, thereby forming the dummy gate structure 30.
In this embodiment, the material of the dummy gate layer is polysilicon. In other embodiments, the material of the dummy gate layer may be silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, or amorphous carbon.
In this embodiment, the process of forming the dummy gate material layer is a chemical vapor deposition process. In other embodiments, the process of forming the dummy gate material layer can also be a physical vapor deposition process, an atomic layer deposition process, a high temperature furnace tube process, or the like.
In this embodiment, the material of the gate mask layer is silicon nitride.
In this embodiment, the process of forming the gate mask layer is a chemical vapor deposition process. In other embodiments, the process of forming the gate mask layer can also be at least one of a physical vapor deposition process and an atomic layer deposition process.
In other embodiments, the dummy gate structure may also be a stacked structure. Specifically, the gate structure includes a dummy gate oxide layer and a dummy gate layer on the dummy gate oxide layer. In this embodiment, the dummy gate oxide layer also conformally covers the exposed channel stack surface of the dummy gate layer. The material of the pseudo gate oxide layer is silicon oxide or silicon oxynitride.
Referring to fig. 5, after forming the dummy gate structure 30, the method further includes: forming a first side wall layer 41 on the channel stack 20 at two sides of the pseudo gate structure 30 of the first device region I, and forming a second side wall layer 42 on the channel stack 20 at two sides of the pseudo gate structure 30 of the second device region II; and etching the channel layers at two sides of the dummy gate structure 30 by using the dummy gate structure 30, the first side wall layer 41 and the second side wall layer 42 as masks to form a first groove 51 in the channel stack 20 at two sides of the dummy gate structure 30 of the first device region I and a second groove 52 in the channel stack 20 at two sides of the dummy gate structure 30 of the second device region II.
The first sidewall layer 41 and the second sidewall layer 42 are used as etching masks for subsequent etching processes to define formation regions of the subsequent first source/drain doped layer and second source/drain doped layer, and the first sidewall layer 41 and the second sidewall layer 42 are also used to protect sidewalls of the dummy gate structure 30 in the subsequent processes.
The material of the first sidewall layer 41 and the second sidewall layer 42 may be one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride oxide, silicon oxynitride, boron nitride and boron carbonitride. In this embodiment, the material of the first sidewall layer 41 and the second sidewall layer 42 is silicon nitride.
In other embodiments, the first sidewall layer 41 and the second sidewall layer 42 can also be a stacked structure.
The first recess 51 is used to provide a space for the subsequent formation of a first source-drain doped layer, and the second recess 52 is used to provide a space for the subsequent formation of a second source-drain doped layer.
In this embodiment, the process of etching the channel stack 20 on both sides of the dummy gate structure 30 is a dry etching process. The dry etching process is easy to realize anisotropic etching, and has good profile control, so that the shape quality of the formed first groove 51 and second groove 52 is improved, and the etching efficiency is improved.
After the first recess 51 and the second recess 52 are formed, the sidewall of the channel layer 22 and the sidewall of the sidewall 50 are flush in a direction perpendicular to the sidewall of the dummy gate structure 30.
Referring to fig. 6, in this embodiment, after forming the first groove 51 and the second groove 52, the method further includes: etching the sacrificial layer 21 with partial thicknesses exposed from the side walls of the first groove 51 and the second groove 52 along a preset direction to form a first groove and a second groove respectively, wherein the first groove is surrounded by the adjacent channel layer 22 and the residual sacrificial layer 21 on the first protruding part 11, or the first groove is surrounded by the first protruding part 11, the channel layer 22 adjacent to the first protruding part 11 and the residual sacrificial layer 21, and the second groove is surrounded by the adjacent channel layer 22 and the residual sacrificial layer 21 on the second protruding part 21, or the second groove is surrounded by the second protruding part 21, the channel layer 22 adjacent to the second protruding part 21 and the residual sacrificial layer 21; forming a first inner wall layer 61 in the first trench and a second inner wall layer 62 in the second trench; the predetermined direction is a direction parallel to the substrate 10 and perpendicular to the extending direction of the gate structure.
In this embodiment, the sacrificial layer 21 with partial thickness exposed from the sidewalls of the first recess 51 and the second recess 52 is etched by a wet etching process. The wet etching process is an isotropic etching process, so that the sacrificial layer 21 can be etched along the direction perpendicular to the side wall of the pseudo gate structure 30, and the wet etching process is easy to realize a large etching selection ratio, thereby being beneficial to reducing the difficulty of etching the sacrificial layer 21 and reducing the loss of other film structures.
In this embodiment, the material of the sacrificial layer 21 is silicon germanium, the material of the channel layer 11 is silicon, and the exposed sacrificial layer 21 is wet etched by hydrogen chloride (HCl) vapor. The etching rate of the hydrogen chloride vapor to the silicon germanium material is far greater than that of the silicon material, so that the hydrogen chloride vapor is adopted to etch the sacrificial layer 21 exposed by the first groove 51 and the second groove 52, and the probability of the channel layer 22 being worn can be effectively reduced.
The first inner wall layer 61 is used as an inner spacer for covering the sidewall of the first gate structure formed at the position of the remaining sacrificial layer 21 in the first device region I, and can isolate the first source-drain doped layer from the first gate structure, increase the distance between the first gate structure and the first source-drain doped layer, and further reduce the parasitic capacitance between the first gate structure and the first source-drain doped layer, thereby improving the performance of the formed semiconductor structure.
The second inner wall layer 62 is used as an inner wall for covering the side wall of the second gate structure formed at the position of the remaining sacrificial layer 21, can isolate the second source-drain doped layer from the second gate structure, and can increase the distance between the second gate structure formed at the subsequent position and the second source-drain doped layer, thereby reducing the parasitic capacitance between the second gate structure and the second source-drain doped layer and improving the performance of the formed semiconductor structure.
The material of the first inner wall layer 61 and the second inner wall layer 62 is a dielectric material. Specifically, the materials of the first inner wall layer 61 and the second inner wall layer 62 include silicon nitride, silicon oxide, silicon oxynitride, low-k dielectric material, or ultra-low-k dielectric material. In this embodiment, the material of the first inner wall layer 61 and the second inner wall layer 62 is silicon oxide. Silicon oxide is a dielectric material commonly used in semiconductor processes, which is beneficial to improving process compatibility and reducing process cost.
In the present embodiment, the first inner wall layer 61 and the second inner wall layer 62 are formed in the same process step.
Specifically, the step of forming the first inner wall layer 61 and the second inner wall layer 62 includes: forming an inner wall film (not shown) conformally covering the top and side walls of the dummy gate structure 30, the bottom and side walls of the first recess 51, and the bottom and side walls of the second recess 52; the top and side walls of the dummy gate structure 30, the channel layer 22 exposed at the bottom and side walls of the first recess 51, the bottom and side walls of the second recess 52, and the inner wall film on the channel layer 22 exposed at the side walls of the first recess 51 are removed, the inner wall film on the sacrificial layer 21 exposed at the side walls of the first recess 51 is remained as the first inner wall layer 61, and the inner wall film on the sacrificial layer 21 exposed at the side walls of the second recess 52 is remained as the second inner wall layer 62.
In this embodiment, an atomic layer deposition (Atomic Layer Deposition, ALD) process is used to form the inner wall film. The atomic layer deposition process has good step coverage capability, is beneficial to improving the conformal coverage capability of the inner wall film on the top and the side wall of the pseudo gate structure 30, the bottom and the side wall of the first groove 51 and the bottom and the side wall of the groove of the second groove 52, and is beneficial to precisely controlling the thickness of the inner wall film by adopting the atomic layer deposition process.
In other embodiments, other deposition processes with better filling properties may be used to form the inner wall film, such as low pressure chemical vapor deposition (Low Pressure Chemical Vapor Deposition, LPCVD) and the like.
In this embodiment, the inner wall film is etched by sequentially using an anisotropic etching process and an isotropic etching process, so that the inner wall film on the channel layer 22 exposed at the top and the side walls of the dummy gate structure 30, the bottom and the side walls of the first recess 51, and the bottom and the side walls of the second recess 52 can be removed. Wherein the inner wall film located in the first trench is difficult to be removed under the shielding of the adjacent channel layer 22, or the first protrusion 11 and the adjacent channel layer 22, and the inner wall film located in the second trench is difficult to be removed under the shielding of the adjacent channel layer 22, or the second protrusion 11 and the adjacent channel layer 22, so that the inner wall film located in the side wall of the first groove 51 and the side wall of the sacrificial layer 21 exposed from the side wall of the second groove 52 can be retained, forming the first inner wall layer 61 and the second inner wall layer 62, respectively.
With continued reference to fig. 6, in this embodiment, after forming the first inner wall layer 61 and the second inner wall layer 62, the method further includes: a first source-drain doped layer 71 is formed in the first recess 51 and a second source-drain doped layer 72 is formed in the second recess 52.
The first source-drain doped layer 71 and the second source-drain doped layer 72 are used to provide a source of carriers, respectively, when the device is in operation.
In this embodiment, the step of forming the first source-drain doped layer 71 and the second source-drain doped layer 72 includes: a first stress layer and a second stress layer are formed in the first groove 51 and the second groove 52 respectively by adopting an epitaxial process, and a first in-situ self-doping and a second in-situ self-doping are performed in the process of forming the first stress layer and the second stress layer respectively, so that the first source drain doping layer 71 and the second source drain doping layer 72 are formed.
The first source-drain doped layer 71 comprises a first stress layer, thereby providing compressive stress to the channel during operation of the device, which is beneficial for improving the mobility of carriers of the second type transistor.
The material of the second source-drain doped layer 72 includes a second stress layer to provide tensile stress to the channel during device operation, which is beneficial to improving the mobility of carriers of the second type transistor.
In this embodiment, the material of the first stress layer is silicon or silicon germanium, and the doped ions in the first stress layer are P-type ions; the material of the second stress layer is silicon or silicon carbide, and the doping ions in the second stress layer are N-type ions.
In this embodiment, the top surfaces of the first source-drain doped layer 71 and the second source-drain doped layer 72 are flush with the top surface of the channel stack 20. In other embodiments, the top surfaces of the first source-drain doped layer and the second source-drain doped layer can also be higher than the top surface of the channel stack, and accordingly, the first source-drain doped layer and the second source-drain doped layer also cover part of the side wall layer.
Referring to fig. 7, the sacrificial layer 21 of the first device region I is removed, so as to form a suspended channel layer 22 on the first protruding portion 11; and removing the sacrificial layer 21 of the second device region II to form a suspended channel layer 22 on the second protruding part 12.
After the sacrificial layer 21 of the first device region I is removed, the remaining channel layer 22 of the first region I provides a basis for forming a suspended first channel layer on the first protruding portion 11, where the first channel layer is used to provide a conductive channel when the first type transistor is operated.
In this embodiment, a wet etching process is used to remove the sacrificial layer 21 in the first device region I.
After the sacrificial layer 21 of the second device region II is removed, the remaining channel layer 22 of the second device region II is used as a second channel layer for providing a conductive channel when the second type transistor is in operation.
In this embodiment, the sacrificial layer 21 of the first device region I and the second device region II is removed in the same process.
In this embodiment, before removing the sacrificial layer 21 of the first device region I and the second device region II, the method further includes: the dummy gate structure 30 is removed to form a gate trench 31.
The gate trench 31 is used to provide a spatial location for the subsequent formation of the first gate structure and the second gate structure and to provide a basis for the removal of the sacrificial layer 21 of the first device region I and the second device region II.
In the present embodiment, the step of forming the gate trench 31 includes: forming a dielectric layer 80 covering the first and second source-drain doped layers 71 and 72 on the substrate 10 at the side of the dummy gate structure 30, the top surface of the dielectric layer 80 being flush with the top surface of the gate structure 120; the dummy gate structure 30 is removed and a gate trench 31 is formed in the dielectric layer 80 exposing the channel stack 20.
Dielectric layer 80 is used to achieve electrical isolation between adjacent semiconductor structures. In this embodiment, the material of the dielectric layer 80 is silicon oxide. In other embodiments, the material of the dielectric layer may be silicon nitride or silicon oxynitride.
Specifically, the step of forming the dielectric layer 80 includes: forming a dielectric material layer (not shown) covering the channel stack 20, the dummy gate structure 30, the first source-drain doped layer 71 and the second source-drain doped layer 72 on the substrate 10; the dielectric material layer is planarized until the top surface of the dummy gate structure 30 is exposed, forming the dielectric layer 80.
In this embodiment, a dry etching process is used to remove the dummy gate structure 30.
In this embodiment, after the gate trench 31 is formed, the sacrificial layer 21 of the first device region I and the second device region II is removed through the gate trench 31, that is, the sacrificial layer 21 exposed by the gate trench 31 is removed, so that the channel layer 22 of the first device region I forms the suspended channel layer 22 located on the first protruding portion 11, and the channel layer 22 of the second device region II forms the suspended channel layer 22 located on the second protruding portion 12, where the suspended channel layer 22 on the second protruding portion 12 is used as the second channel layer 322.
Specifically, the material of the sacrificial layer 21 is silicon germanium, and the material of the channel layer 22 is silicon, so that the sacrificial layer 21 exposed by the gate trench 31 is removed by HCl vapor.
The first source-drain doped layer 71 and the second source-drain doped layer 72 are formed before the sacrificial layer 21 in the first device region I and the second device region II is removed, so that after the sacrificial layer 21 exposed by the gate trench 31 is removed, two ends of the channel layer 22 in the first device region I are connected with the first source-drain doped layer 71 along the extending direction of the channel layer 11, two ends of the channel layer 22 in the second device region II are connected with the second source-drain doped layer 72, so that the channel layer 22 in the first device region I and the second device region II is in a suspended state in the gate trench 31, thereby providing a foundation for the first gate structure and the second gate structure which form the full-enclosure structure subsequently.
Accordingly, after the sacrificial layer 21 exposed by the gate trench 31 is removed, a first through groove 32 located in the first device region I and a second through groove 33 located in the second device region II are formed.
Specifically, the first through groove 32 is surrounded by the first protruding portion 11, the channel layer 22 located on the first protruding portion 11, and the first source-drain doped layer 71, or the first through groove 32 is surrounded by the adjacent channel layer 22 and the first source-drain doped layer 71, and the first through groove 32 is communicated with the gate trench 31.
The second through-slot 33 is surrounded by the second protruding portion 21, the channel layer 22 located on the second protruding portion 21, and the second source-drain doped layer 72, or the second through-slot 33 is surrounded by the adjacent channel layer 22 and the second source-drain doped layer 72, and the second through-slot 33 is communicated with the gate trench 31.
Referring to fig. 8, a thinning process is performed on the suspended channel layer 22 on the first protruding portion 11, so as to form a thinned channel layer 22.
The thinned channel layer 22 is used to provide a basis for the subsequent formation of the first channel layer.
In this embodiment, an Atomic Layer Etching (ALE) process is used to thin the suspended channel layer 22 on the first protruding portion 11, so as to improve the etching uniformity. Specifically, the suspended channel layer 22 on the first protruding portion 11 is etched from two directions of the upper surface and the lower surface, so as to achieve thinning treatment of the suspended channel layer 22 on the first protruding portion 11.
The step of performing the thinning process on the suspended channel layer 22 on the first protruding portion 11 includes: modifying the upper surface and the lower surface of the suspended channel layer 22 on the first protruding portion 11 by adopting a first process; and etching the modified upper surface and lower surface of the channel layer 22 by adopting a second process. The first process is used to modify the upper surface and the lower surface of the suspended channel layer 22 on the first protruding portion 11, and the second process is used to etch the modified upper surface and lower surface of the channel layer 22, so as to effectively thin the upper surface and the lower surface of the suspended channel layer 22 on the first protruding portion 11.
The first process and the second process are cyclically performed, so that the thinning process is repeatedly performed until the channel layer 22 after the thinning process reaches a preset thickness. The preset thickness may be selected according to actual process requirements, and is not limited herein.
Therefore, the number of times of the thinning process may be set according to the requirement of the preset thickness. For example, the thinning process may be circularly performed 10 to 30 times, so that the thickness of the channel layer 22 after the thinning process reaches the preset thickness.
In this embodiment, the first process and the second process may be plasma processes, and the modification and etching processes are circularly performed in the plasma chamber, so as to achieve the thinning of the suspended channel layer 22 on the first protruding portion 11. It can be appreciated that the first process and the second process are both plasma processes, so that the process flow can be simplified, and pollution of devices caused by different process environment changes can be avoided.
Referring to fig. 9, a first channel material 23 is formed on the thinned channel layer 22, forming a first channel layer 321; the first channel material is different from the material of the channel layer 22.
The first channel layer 321 is used for a channel layer of a first type device formed as the first device region I.
In this embodiment, an epitaxial growth process is used to form the first channel material 23 on the thinned channel layer 22. The first channel layer 321 is epitaxially grown on the basis of the thinned channel layer 22, so that the formed first channel layer 321 has better morphology and quality.
Specifically, during the process of forming the first channel layer 321, epitaxial growth is performed based on the thinned channel layer 22, so that it is beneficial to control the epitaxial growth direction of the first channel material 23, and control the growth direction of the first channel material 23 along the upper surface and the lower surface of the thinned channel layer 22, so that the morphology quality of the first channel layer 321 is ensured.
In this embodiment, the epitaxial growth process for forming the first channel material 23 may be regarded as a reverse process to the process for thinning the channel layer 22, and the etched thickness of the thinned channel layer 22 is the same as the grown thickness of the first channel material. Accordingly, the thickness of the first channel layer 321 is the same as the thickness of the second channel layer 322 or the initial thickness of the channel layer 22.
In other embodiments, the thickness of the first channel layer 321 may be different from the thickness of the second channel layer 322 according to actual needs, which is not limited herein.
In this embodiment, the first device region I is used to form a PMOS device, and the material of the second channel material layer is silicon germanium correspondingly.
Referring to fig. 10, a first gate structure 91 is formed on the first device region I, crossing the first protrusion 11 and the first channel layer 321, and surrounding the first channel layer 321; a second gate structure 92 is formed on the second device region II across the second raised portion 12 and the second channel layer 322, the second gate structure 92 also surrounding the second channel layer 322.
The first gate structure 91 is used to control the turning on or off of the conduction channel of the first type transistor when the device is in operation, and the second gate structure 92 is used to control the turning on or off of the conduction channel of the second type transistor when the device is in operation.
In this embodiment, the first gate structure 91 includes a high-k gate dielectric layer (not shown) in the gate trench of the first device region I, and a metal gate electrode layer (not shown) on the high-k gate dielectric layer. Specifically, the high-k gate dielectric layer is located on the upper surface, the lower surface, and the sides of the first channel layer 321, and also covers part of the top and part of the sidewalls of the first bump 11.
In this embodiment, the second gate structure 92 includes a high-k gate dielectric layer (not shown) located in the gate trench 31 above the second device region I, and a metal gate electrode layer (not shown) located on the high-k gate dielectric layer. Specifically, a high-k gate dielectric layer is located on the upper, lower, and sides of the second channel layer 322 and also covers portions of the top and portions of the sidewalls of the second raised portion 12.
In this embodiment, the material of the high-k gate dielectric layer is hafnium oxide (HfO 2 ) The material of the metal gate electrode layer is tungsten (W).
Accordingly, the step of forming the first gate structure and the second gate structure includes: forming an initial high-k gate dielectric layer surrounding the first channel layer 321 and the second channel layer 322 at the bottom and the sidewalls of the gate trench 31, the initial high-k gate dielectric layer further formed on the dielectric layer 80; forming an initial gate electrode layer filling the gate trench 31, the first through trench 32 and the second through trench 33, the initial gate electrode layer also covering the top surface of the dielectric layer 80; the initial gate electrode layer and the initial high-k gate dielectric layer are planarized to form the first gate structure 91 and the second gate structure 92.
Correspondingly, the embodiment of the invention also provides a semiconductor structure.
Referring to fig. 10, the semiconductor structure includes: a base (not shown) having a first device region I and a second device region II, and including a substrate 10, a first protrusion 11 protruding on the substrate 10 of the first device region I, and a second protrusion 12 protruding on the substrate 10 of the first device region I; the first channel layer 321 is located on the first protruding portion 11 in a suspended manner, the first channel layer 321 includes a thinned channel layer 22 and a first channel material 23 located on the thinned channel layer 22, and the thinned channel layer 22 is obtained by thinning the channel layer 22 on the first protruding portion 11 in a suspended manner; the first channel material 23 is different from the material of the channel layer 22; a suspended second channel layer 322 on the second bump 12; a first gate structure 91 that spans the first protrusion 11 and the first channel layer 321 and surrounds the first channel layer 321; a second gate structure 92 straddles the second protrusion 12 and the second channel layer 322 and surrounds the second channel layer 322.
In this embodiment, the first device region I is used to form a PMOS transistor, and the second device region II is used to form an NMOS transistor; the channel layer 22 is made of silicon, and the first channel material 23 is made of silicon germanium.
In this embodiment, the semiconductor structure further includes: the first source-drain doped layer 71 is located in the channel stack 20 at two sides of the first gate structure 91; a second source drain doped layer 72 is located in the channel stack 20 on both sides of the second gate structure 92.
In this embodiment, the semiconductor structure further includes: a first inner wall layer 91 located between the first source-drain doped layer 71 and the first gate structure 91; a second inner wall layer 92 is located between the second source-drain doped layer 72 and the second gate structure 92.
The semiconductor structure may be formed by the forming method described in the foregoing embodiments, or may be formed by other forming methods. For a specific description of the semiconductor structure in this embodiment, reference may be made to the corresponding description in the foregoing embodiment, which is not repeated here.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.

Claims (16)

1. A method of forming a semiconductor structure, comprising:
providing a base, wherein the base is provided with a first device region and a second device region, the base comprises a substrate, a first protruding part protruding on the substrate of the first device region and a second protruding part protruding on the substrate of the second device region, and the first protruding part and the second protruding part are made of different materials;
forming suspended channel layers on the first protruding part and the second protruding part;
performing thinning treatment on the channel layer on the first protruding part, and growing a first channel material on the thinned channel layer to form a first channel layer, wherein the first channel material is different from the channel layer; the channel layer on the second protruding portion serves as a second channel layer;
forming a first gate structure on the first device region, crossing the first protrusion and surrounding the first channel layer;
a second gate structure is formed on the second device region, spanning the second protrusion and surrounding the second channel layer.
2. The method of forming a semiconductor structure of claim 1, wherein forming a suspended channel layer over the first and second protrusions comprises:
Forming a channel stack on the first and second protrusions, the channel stack including a sacrificial layer and a channel layer on the sacrificial layer;
removing the sacrificial layers on the first protruding part and the second protruding part to form a suspended channel layer; the step of forming the first gate structure and the second gate structure includes:
forming a dummy gate structure across the first protrusion, the second protrusion, and the channel stack after forming the channel stack;
removing the pseudo gate structure before removing the sacrificial layers on the first protruding portion and the second protruding portion to form a gate trench;
after forming a gate trench, removing the sacrificial layer exposed by the gate trench, and forming a first through groove positioned on the first device region and a second through groove positioned on the second device region;
and after the first channel layer is formed, filling the gate groove, the first through groove and the second through groove to form the first gate structure and the second gate structure.
3. The method of claim 2, wherein the material of the dummy gate structure comprises polysilicon.
4. The method of forming a semiconductor structure of claim 2, further comprising, after forming the dummy gate structure:
etching channel stacks on two sides of the pseudo gate structure of the first device region, and forming a first groove exposing the first protruding part in the channel stacks on two sides of the pseudo gate structure of the first device region;
etching channel stacks at two sides of the pseudo gate structure of the second device region, and forming a second groove exposing the second protruding part in the channel stacks at two sides of the pseudo gate structure of the second device region;
forming a first source-drain doping layer in the first groove;
and forming a second source-drain doping layer in the second groove.
5. The method of forming a semiconductor structure of claim 4, further comprising, after forming the first recess and before forming the first source-drain doped layer: etching the sacrificial layer with partial thickness exposed out of the side wall of the first groove along a preset direction to form a first groove, wherein the first groove is surrounded by the adjacent channel layer and the rest sacrificial layer on the first protruding part, or the first groove is surrounded by the first protruding part, the channel layer adjacent to the first protruding part and the rest sacrificial layer, and the preset direction is a direction parallel to the substrate and perpendicular to the extending direction of the grid structure; forming a first inner wall layer in the first groove;
After forming the second groove and before forming the second source-drain doped layer, the method further comprises: etching the sacrificial layer with partial thickness exposed out of the side wall of the second groove along the preset direction to form a second groove, wherein the second groove is surrounded by the adjacent channel layer and the rest of the sacrificial layer on the second protruding part, or the second groove is surrounded by the second protruding part, the channel layer adjacent to the second protruding part and the rest of the sacrificial layer; and forming a second inner wall layer in the second groove.
6. The method of forming a semiconductor structure of claim 4, wherein the step of forming the first recess comprises:
forming a first side wall layer on the channel lamination layers at two sides of the pseudo gate structure of the first device region, and forming a second side wall layer on the channel lamination layers at two sides of the pseudo gate structure of the second device region;
and etching the channel stack layer by taking the pseudo gate structure, the first side wall layer and the second side wall layer as masks to form the first groove and the second groove.
7. The method of claim 6, wherein the process of forming the first recess and the second recess comprises an anisotropic dry etching process.
8. The method of claim 6, wherein the material of the first sidewall layer and the second sidewall layer comprises one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride, and boron carbonitride.
9. The method of claim 2, wherein the channel layer is silicon and the sacrificial layer is silicon germanium.
10. The method of forming a semiconductor structure of claim 1, wherein the first device region is used to form a PMOS transistor and the second device region is used to form an NMOS transistor; the channel layer is made of silicon, and the first channel material is silicon germanium.
11. The method of claim 1, wherein the process of performing a thinning process on the channel layer on the first bump is an atomic layer etching process.
12. The method of claim 1, wherein the process of forming the first channel material is an epitaxial process.
13. A semiconductor structure, comprising:
A base having a first device region and a second device region, the base including a substrate, a first protruding portion protruding on the substrate of the first device region, and a second protruding portion protruding on the substrate of the first device region;
the first channel layer is positioned on the first protruding part in a suspending mode and comprises a thinned channel layer and a first channel material surrounding the thinned channel layer, and the thinned channel layer is obtained by thinning the suspended channel layer on the first protruding part; the first channel material is different from the material of the channel layer;
the second channel layer is positioned on the second protruding part in a suspending way and comprises a channel layer which is positioned on the second protruding part in a suspending way;
a first gate structure crossing the first protrusion and the first channel layer and surrounding the first channel layer;
and a second gate structure crossing the second protrusion and the second channel layer and surrounding the second channel layer.
14. The semiconductor structure of claim 13, wherein the first device region is for forming a PMOS transistor and the second device region is for forming an NMOS transistor; the channel layer is made of silicon, and the first channel material is silicon germanium.
15. The semiconductor structure of claim 13, further comprising:
the first source-drain doping layer is positioned in the channel stack layers at two sides of the first grid structure;
and the second source-drain doped layer is positioned in the channel laminated layers at two sides of the second grid structure.
16. The semiconductor structure of claim 15, further comprising:
the first inner wall layer is positioned between the first source-drain doping layer and the first grid structure;
and the second inner wall layer is positioned between the second source-drain doping layer and the second grid structure.
CN202210788210.6A 2022-07-06 2022-07-06 Semiconductor structure and forming method thereof Pending CN117410234A (en)

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