CN111613581A

CN111613581A - Semiconductor structure and forming method thereof

Info

Publication number: CN111613581A
Application number: CN201910133512.8A
Authority: CN
Inventors: 王楠
Original assignee: Semiconductor Manufacturing International Shanghai Corp; Semiconductor Manufacturing International Beijing Corp
Current assignee: Semiconductor Manufacturing International Shanghai Corp; Semiconductor Manufacturing International Beijing Corp
Priority date: 2019-02-22
Filing date: 2019-02-22
Publication date: 2020-09-01
Anticipated expiration: 2039-02-22
Also published as: CN111613581B

Abstract

A semiconductor structure and a forming method thereof are provided, wherein the forming method comprises the following steps: providing a fin part and a channel lamination layer positioned on the fin part, wherein the channel lamination layer comprises a sacrificial layer and a channel layer positioned on the sacrificial layer, a part of the channel layer close to one side of the fin part is used as a first channel layer, and the rest of the channel layer positioned on the first channel layer is used as a second channel layer; forming a plurality of dummy gate structures across the channel stack; forming a first source drain doping layer in contact with the first channel layer in the channel laminated layers on the two sides of the pseudo gate structure; forming a second source-drain doping layer on the side wall of the second channel layer; and after the pseudo gate structure and the sacrificial layer are removed, forming a gate structure at the positions of the pseudo gate structure and the sacrificial layer. The first source-drain doping layer, the first channel layer and the grid structure surrounding the first channel layer in the grid structure are used for forming a transistor, the second source-drain doping layer, the second channel layer and the grid structure surrounding the second channel layer in the grid structure form another transistor, and therefore electrical performance of the semiconductor structure is optimized.

Description

Semiconductor structure and forming method thereof

Technical Field

Embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular, to a semiconductor structure and a method for forming the same.

Background

In Semiconductor manufacturing, with the trend of ultra-large scale integrated circuits, the feature size of the integrated circuit is continuously reduced, and in order to adapt to smaller feature sizes, the channel length of a Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) is also continuously shortened correspondingly. However, as the channel length of the device is shortened, the distance between the source and the drain of the device is also shortened, so the controllability of the gate structure to the channel is deteriorated, and the difficulty of the gate voltage to pinch off the channel is increased, so that the sub-threshold leakage (SCE) phenomenon, i.e. the so-called short-channel effect (SCE), is more likely to occur.

Therefore, in order to better accommodate the scaling requirements of device dimensions, semiconductor processes are gradually starting to transition from planar transistors to more power efficient three-dimensional transistors, such as Gate-all-around (GAA) transistors. In the fully-surrounded metal gate transistor, the gate surrounds the region where the channel is located from the periphery, and compared with a planar transistor, the fully-surrounded metal gate transistor has stronger control capability on the channel by the gate, and can better inhibit a short-channel effect.

The full-gate nanowire can be obtained by adding only two process modules in the existing replacement gate fin field effect transistor (FinTET) process flow, wherein the two process modules are as follows: one is to grow a layer of Silicon on bulk Silicon (bulk Silicon) or SOI wafer, which avoids leakage of bulk Silicon material. Second, selectively remove the silicon germanium on the replaceable metal gate loop, and then use HKMG (high-k insulating layer + metal gate) to stack the surrounding silicon channel to form the all-around metal gate transistor.

Disclosure of Invention

Embodiments of the present invention provide a semiconductor structure and a method for forming the same, which optimize electrical properties of the semiconductor structure.

To solve the above problems, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate, wherein the substrate comprises a substrate, a fin portion protruding from the substrate and a plurality of channel lamination layers located on the fin portion, each channel lamination layer comprises a sacrificial layer and a channel layer located on the sacrificial layer, a part of the channel layer close to one side of the fin portion is used as a first channel layer, and the rest of the channel layer located on the first channel layer is used as a second channel layer; forming a dummy gate structure crossing the channel lamination layer, wherein the dummy gate structure covers part of the top wall and part of the side wall of the channel lamination layer; forming a first source drain doping layer in the channel lamination layer on two sides of the pseudo gate structure, wherein the first source drain doping layer is in contact with the first channel layer; forming a second source-drain doping layer on the side wall of the second channel layer; forming an interlayer dielectric layer on the substrate exposed out of the pseudo gate structure, wherein the interlayer dielectric layer covers the first source-drain doping layer and the second source-drain doping layer and exposes out of the top of the pseudo gate structure; removing the pseudo gate structure, and forming a gate opening at the position of the pseudo gate structure; removing the sacrificial layer, and forming a channel communicated with the gate opening at the position of the sacrificial layer; and forming a gate structure in the gate opening and the channel.

Correspondingly, an embodiment of the present invention further provides a semiconductor structure, including: a substrate; a fin portion on the substrate; the first source drain doping layer is separated on the fin part; one or more spaced first channel layers located between the first source-drain doped layers and contacting the first source-drain doped layers, wherein the first channel layers are suspended above the fin portion; the second source-drain doping layer is suspended on the first source-drain doping layer in a discrete mode; one or more spaced second channel layers located between the second source-drain doped layers and contacting the first source-drain doped layers, wherein the second channel layers are suspended above the first channel layers; and the grid structure stretches across the first channel layer and the second channel layer on the fin part and surrounds the first channel layer and the second channel layer.

Compared with the prior art, the technical scheme of the embodiment of the invention has the following advantages:

in the embodiment of the invention, a plurality of channel laminated layers are formed on a fin part, each channel laminated layer comprises a sacrificial layer and a channel layer positioned on the sacrificial layer, wherein part of the channel layer close to one side of the fin part is used as a first channel layer, the rest of the channel layer positioned on the first channel layer is used as a second channel layer, then a pseudo gate structure which stretches across the channel laminated layers and covers part of the top wall and part of the side wall of the channel laminated layers is formed, first source-drain doped layers are formed in the channel laminated layers on two sides of the pseudo gate structure, second source-drain doped layers are formed on the side wall of the second channel layer, and after the pseudo gate structure and the sacrificial layer are removed, a gate structure is formed at the positions of the pseudo gate structure and the sacrificial layer. In the embodiment of the invention, the first source-drain doping layer, the first channel layer and part of the grid structure surrounding the first channel layer in the grid structure are used for forming the first transistor, and the second source-drain doping layer, the second channel layer and part of the grid structure surrounding the second channel layer in the grid structure are used for forming the second transistor, so that different transistors are formed on the grid structure in an up-and-down stacking mode, the integration level of the semiconductor structure is increased, and the electrical performance of the semiconductor structure is optimized.

Drawings

FIG. 1 is a schematic diagram of a semiconductor structure;

fig. 2 to 18 are schematic structural diagrams corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention.

Detailed Description

As can be seen from the background art, the performance of the devices formed at present is still not good. The reason for the poor performance of the device is analyzed in combination with a method for forming a semiconductor structure.

Referring to fig. 1, a corresponding structural schematic of a semiconductor structure is shown.

As shown in fig. 1, the base includes a substrate 1 and a fin portion 2 protruding from the substrate 1; the source drain doping layer 3 is separated on the fin part 2; the channel layer or the channel layers 4 are suspended between the source-drain doping layers 3 and are in contact with the source-drain doping layers 3, and the channel layer 4 is suspended on the fin portion 2; a metal gate structure 5 spanning the channel layer 4 on the fin 2 and surrounding the channel layer 4; and the dielectric layer 6 covers the source-drain doping layer 3 and the side wall of the metal gate structure 5.

Semiconductor devices are developed towards higher integration and smaller devices, and semiconductor structures are developed from original planar MOSFETs to GAA transistors with higher efficiency, but in general semiconductor structures, PMOS transistors or NMOS transistors are separately formed, and one GAA structure corresponds to only one transistor, which causes difficulty in further reduction of the size of the semiconductor structure, and thus, the performance of the semiconductor structure is difficult to further optimize.

In order to solve the technical problem, in the embodiment of the invention, a plurality of channel laminated layers are formed on a fin part, each channel laminated layer comprises a sacrificial layer and a channel layer positioned on the sacrificial layer, wherein a part of the channel layer close to one side of the fin part is used as a first channel layer, the rest of the channel layer positioned on the first channel layer is used as a second channel layer, then a pseudo gate structure which crosses the channel laminated layers and covers part of the top wall and part of the side wall of the channel laminated layer is formed, first source and drain doped layers are formed in the channel laminated layers on two sides of the pseudo gate structure, second source and drain doped layers are formed on the side wall of the second channel layer, and after the pseudo gate structure and the sacrificial layer are removed, a gate structure is formed at the positions of the pseudo gate structure and the sacrificial layer. In the embodiment of the invention, the first source-drain doping layer, the first channel layer and part of the grid structure surrounding the first channel layer in the grid structure are used for forming the first transistor, and the second source-drain doping layer, the second channel layer and part of the grid structure surrounding the second channel layer in the grid structure are used for forming the second transistor, so that different transistors are formed on the grid structure in an up-and-down stacking mode, the integration level of the semiconductor structure is increased, and the electrical performance of the semiconductor structure is optimized.

In order to make the aforementioned objects, features and advantages of the embodiments of the present invention comprehensible, specific embodiments accompanied with figures are described in detail below.

Referring to fig. 2, a substrate is provided, the substrate including a substrate 100 (as shown in fig. 2), a discrete fin 101 (as shown in fig. 2) protruding from the substrate 100, and a plurality of channel stacks 102 (as shown in fig. 2) on the fin 101, the channel stacks 102 including a sacrificial layer 1021 and a channel layer 1022 on the sacrificial layer 1021.

The substrate 100 is used to provide a process platform for the subsequent formation of a gate structure.

In this embodiment, the substrate 100 is a silicon substrate. In other embodiments, the material of the substrate may also be other materials such as germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, and the substrate may also be another type of substrate such as a silicon-on-insulator substrate or a germanium-on-insulator substrate.

In this embodiment, the material of the fin 101 is the same as that of the substrate 100. In other embodiments, the material of the fin may be different from the material of the substrate.

Channel stack 102 is used to provide a process foundation for the subsequent formation of a suspended channel layer 1022. The sacrificial layer 1021 is used to support the channel layer 1022, provide process conditions for the spacer-floating arrangement of the subsequent channel layer 1022, and also be used to occupy space for the subsequently formed gate structure.

In this embodiment, the difficulty of etching the channel layer 1022 is greater than that of etching the sacrificial layer 1021, and the channel layer 1022 is not easily damaged when the sacrificial layer 1021 is removed subsequently. In this embodiment, the material of the channel layer 1022 is silicon; the material of the sacrificial layer 1021 is silicon germanium. In other embodiments, the channel layer may also be made of other materials such as germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, and the sacrificial layer may also be made of silicon accordingly.

With continued reference to fig. 2, in the present embodiment, a portion of the channel layer 1022 close to the fin 101 serves as a first channel layer 1022a, and the remaining channel layer 1022 on the first channel layer 1022a serves as a second channel layer 1022 b.

In the present embodiment, the number of the channel layers 1022 is two, one is the first channel layer 1022a, and the other is the second channel layer 1022 b. In other embodiments, the number of the first channel layers may also be more than one, and the number of the second channel layers may also be more than one.

Note that the sacrificial layer 1021 between the adjacent first channel layer 1022a and the second channel layer 1022b is not too thick nor too thin. If the thickness of the sacrificial layer 1021 between the adjacent first channel layer 1022a and the second channel layer 1022b is too thick, the ratio of the total height to the width of the channel stack 102 is too large, so that the formed channel stack 102 is prone to tilt, and the process difficulty of forming the channel stack 102 is too large. The subsequent process includes forming a first source-drain doping layer on the sidewall of the first channel layer 1022a, and forming a second source-drain doping layer on the sidewall of the second channel layer 1022b, where the first source-drain doping layer and the second source-drain doping layer correspond to different transistors, and if the sacrificial layer 1021 between the adjacent first channel layer 1022a and the second channel layer 1022b is too thin, the first source-drain doping layer and the second source-drain doping layer formed subsequently may be easily contacted, resulting in poor performance of the semiconductor structure. In the present embodiment, the thickness of the sacrificial layer 1021 between adjacent first and

second channel layers

1022a and 1022b is 8 to 20 nanometers.

In other embodiments, the thickness of the sacrificial layer between the adjacent first and

second channel layers

1022a and 1022b may also follow a proportional relationship with the thickness of the channel layer, specifically, the thickness of the sacrificial layer between the adjacent first and

second channel layers

1022a and 1022b is 3 to 5 times the thickness of the channel layer.

After the channel stack 102 is formed, the method further includes: isolation structures 113 are formed on the substrate 100 where the fins 101 are exposed. The isolation structures 113 are used to electrically isolate the fins 101 from each other.

In the present embodiment, the material of the isolation structure 113 includes silicon oxide. In other embodiments, the material of the isolation structure may further include one or more of silicon nitride, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride, and boron carbonitride.

It should be noted that the top surface of the isolation structure 113 is not higher than the top wall of the fin 101, which is beneficial for the subsequent removal of the sacrificial layer 1021.

Referring to fig. 3, a dummy gate structure 106 is formed across the channel stack 102, and the dummy gate structure 106 covers a portion of the top wall and a portion of the sidewalls of the channel stack 102.

The dummy gate structure 106 occupies a space for forming a gate structure in a subsequent process. Dummy gate structure 106 includes a dummy gate oxide layer 1061 conformally covering a portion of the top surface and a portion of the sidewalls of channel stack 102 and a dummy gate layer 1062 situated over dummy gate oxide layer 1061.

In this embodiment, the material of the dummy gate oxide layer 1061 is silicon oxide. In other embodiments, the material of the dummy gate oxide layer may also be silicon oxynitride. In this embodiment, the material of the dummy gate layer 1062 is polysilicon. In other embodiments, the material of the dummy gate layer may also be silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, or amorphous carbon.

The step of forming the dummy gate structure 106 includes: forming a dummy gate oxide layer 1061 crossing said channel stack 102 and a dummy gate material layer (not shown) on said dummy gate oxide layer 1061; forming a gate mask layer 107 on the dummy gate material layer; and etching the dummy gate material layer by using the gate mask layer 107 as a mask to form a dummy gate layer 1062 on the dummy gate oxide layer 1061.

Referring to fig. 4 to 7, first source-drain doping layers 108 (as shown in fig. 7) are formed in the channel stack 102 at both sides of the dummy gate structure 106, and the first source-drain doping layers 108 are in contact with the first channel layer 1022 a.

The first source-drain doping layer 108 is in contact with the first channel layer 1022a, so that the first source-drain doping layer 108, the first channel layer 1022a, and a portion of a subsequently formed gate structure surrounding the first channel layer 1022a constitute a first transistor.

The step of forming the first source drain doping layer 108 includes: forming grooves 110 (shown in fig. 4) in the channel stack 102 on both sides of the dummy gate structure 106; forming a first epitaxial layer (not shown) doped with ions in the recess 110; and etching back the first epitaxial layer with partial thickness to form a first source drain doping layer 108.

As shown in fig. 4, the step of forming the groove 110 includes: the channel stack 102 is etched until the top surface of the fin 101 is exposed, forming a recess 110. In other embodiments, the step of forming the groove may further include: and etching the channel lamination and the top surface of the fin part with partial thickness to form a groove.

In this embodiment, the channel stack 102 on both sides of the dummy gate structure 106 is etched by a dry etching process to form a groove 110. In other embodiments, a wet etching process or a combination of a dry etching process and a wet etching process may be used to etch the channel stack layers on both sides of the dummy gate structure to form the groove.

As shown in fig. 7, in this embodiment, a first epitaxial layer (not shown) is epitaxially grown in the recess 110 by a Selective Epitaxial Growth (SEG), the first epitaxial layer covers a sidewall of the first channel layer 1022a, and ions are doped in situ during the formation of the first epitaxial layer; after the ions are doped, the first epitaxial layer with a part of thickness is etched back to form a first source drain doping layer 108. In other embodiments, after the first epitaxial layer is formed, ion doping may be performed on the first epitaxial layer in an ion implantation manner to form a first source-drain doping layer. The doping ions can achieve the effect of improving the carrier mobility of the transistor.

In this embodiment, a dry etching process is used to etch back a portion of the first epitaxial layer with a certain thickness to form the first source-drain doping layer 108. In other embodiments, a wet etching process or a combination of a wet etching process and a dry etching process may be used to etch back a portion of the thickness of the first epitaxial layer.

In this embodiment, the substrate 100, the first channel layer 1022a, and the second channel layer 1022b are all made of silicon, and in the process of forming the first epitaxial layer by using the selective epitaxial growth method, the first epitaxial layer is further formed on the sidewall of the second channel layer 1022b, and the first epitaxial layer located on the sidewall of the second channel layer 1022b is used as the excess first source-drain doping layer 112. Because the second channel layer 1022b is made of silicon, the adhesion between the excess first source-drain epitaxial layer 112 on the sidewall of the second channel layer 1022b and the second channel layer 1022b is strong, and when the first epitaxial layer with a partial thickness is etched back to form the first source-drain doping layer 108, the excess second source-drain epitaxial layer 112 is not easily removed. The excess first source drain doped layer 112 may be removed in a subsequent step.

In this embodiment, the first transistor formed subsequently is a PMOS (positive Channel Metal oxide semiconductor), that is, the first source-drain doping layer 108 is used as a source region and a drain region of the PMOS, and therefore, the material of the first source-drain doping layer 108 is silicon germanium doped with P-type ions. In this embodiment, P-type ions are doped in silicon germanium, so that the P-type ions replace positions of silicon atoms in the crystal lattice, and the more P-type ions are doped, the higher the concentration of majority ions is, and the stronger the conductivity is. Specifically, the P-type ions include B, Ga or In.

In other embodiments, when the subsequently formed first transistor is an NMOS (negative channel metal oxide semiconductor), that is, when the first source-drain doped layer is used as a source region and a drain region of an NMOS, the material of the first source-drain doped layer is correspondingly silicon carbide or silicon phosphide doped with N-type ions. By doping N-type ions in silicon carbide or silicon phosphide, the N-type ions are used for replacing the positions of silicon atoms in crystal lattices, and the more N-type ions are doped, the higher the concentration of majority ions is, and the stronger the conductivity is. Specifically, the N-type ions include P, As or Sb.

As shown in fig. 5 and 6, the method for forming the semiconductor structure further includes: after the groove 110 is formed, before the first source-drain doping layer 108 is formed (as shown in fig. 7), the sacrificial layer 1021 with a partial thickness on the sidewall of the groove 110 is etched along a direction perpendicular to the sidewall of the dummy gate structure 106, so as to form a sidewall groove 109 (as shown in fig. 5) surrounded by the sacrificial layer 1021 and the channel layer 1022, or form a sidewall groove 109 (as shown in fig. 5) surrounded by the sacrificial layer 1021, the channel layer 1022 and the fin 101; inner sidewalls 111 are formed in the sidewall recesses 109 (as shown in fig. 6).

In this embodiment, a wet etching process is used to remove a portion of the thickness of the sacrificial layer 1021 on the sidewall of the groove 110, so as to form the sidewall groove 109.

In this embodiment, the channel layer 1022 is made of Si, the sacrificial layer 1021 is made of SiGe, and the step of forming the sidewall recess 109 includes: the sacrificial layer 1021 on the sidewall of the groove 110 is etched in a direction perpendicular to the sidewall of the dummy gate structure 106 using an HCl solution.

The inner sidewall 111 is used for reducing a capacitive coupling effect among the first source-drain doping layer 108, the subsequently formed second source-drain doping layer and the subsequently formed gate structure, so that a parasitic capacitance is reduced, and the electrical performance of the transistor structure is improved.

Specifically, the step of forming the inner sidewall 111 includes: forming a conformal covering groove 110 and an inner sidewall material layer (not shown) of the dummy gate structure 106; the inner sidewall material layer exposing the sidewall recess 109 is removed to form an inner sidewall 111.

In this embodiment, a Chemical Vapor Deposition (CVD) process is used to form the inner wall material layer. In other embodiments, an Atomic Layer Deposition (ALD) process may be used to form the inner sidewall material Layer.

In this embodiment, the inner sidewall 111 is made of a low-K dielectric constant material, and the inner sidewall 111 is made of SiN doped with carbon or oxygen. In other embodiments, the inner sidewall spacer may also be made of a low-K dielectric constant material such as SiON, SiBCN, or SiCN.

Referring to fig. 8, after the first source-drain doping layer 108 is formed, the method further includes: an isolation layer 114 is formed to cover the first source-drain doping layer 108, and the isolation layer 114 exposes the second channel layer 1022 b.

The first source-drain doping layer 108, the first channel layer 1022a, and a part of the subsequently formed gate structure surrounding the first channel layer 1022a form a first transistor, the second source-drain doping layer formed on the sidewall of the second channel layer 1022b, and a part of the gate structure surrounding the second channel layer 1022b form a second transistor, and the isolation layer 114 is used for preventing the second source-drain doping layer from contacting the first source-drain doping layer 108 when the second source-drain doping layer is formed subsequently, so that the first source-drain doping layer 108 and the second source-drain doping layer are electrically isolated, and the first transistor and the second transistor can operate independently.

In addition, in the subsequent step of removing the redundant first source-drain doping layer 112, the isolation layer 114 can also protect the first source-drain doping layer 108, so as to reduce the probability of damage to the first source-drain doping layer 108, thereby ensuring the performance of the first source-drain doping layer 108, and further improving the electrical performance of the semiconductor structure.

The isolation layer 114 exposes the sidewall of the second channel layer 1022b, so as to facilitate the subsequent formation of a second source-drain doping layer on the sidewall of the second channel layer 1022 b.

The step of forming the isolation layer 114 includes: forming an isolation material layer covering the first source-drain doping layer 108, and carrying out planarization treatment on the isolation material layer; after the planarization process, the isolation material layer is etched back to a partial thickness to form the isolation layer 114.

In this embodiment, the isolation material layer is formed by a Flowable Chemical Vapor Deposition (FCVD) process.

In this embodiment, the isolation material layer is planarized by Chemical-Mechanical Planarization (CMP).

In this embodiment, the isolation layer 114 is formed by etching back the isolation material layer with a certain thickness by a dry etching process.

In this embodiment, the isolation layer 114 is made of a dielectric material. The dielectric material has good insulating properties and the isolation layer 114 need not be removed after formation, simplifying the process steps.

Specifically, the material of the isolation layer 114 includes one or more of silicon oxide, silicon nitride, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride, and boron carbonitride.

It should be noted that the isolation layer 114 on the first source/drain doping layer 108 is not too thick nor too thin. If the isolation layer 114 on the first source-drain doping layer 108 is too thick, and the distance between the isolation layer 114 and the adjacent second channel layer 1022b is too small, it is difficult to provide a sufficient space for forming a second source-drain doping layer on the sidewall of the second channel layer 1022b in the following process, and the formation quality of the second source-drain doping layer is easily reduced. If the isolation layer 114 on the first source-drain doping layer 108 is too thin, the isolation layer 114 may not well protect the first source-drain doping layer 112 when the excess first source-drain doping layer 112 on the sidewall of the second channel layer 1022b is removed, so that the first source-drain doping layer 112 is easily damaged. In this embodiment, the thickness of the isolation layer 114 on the first source-drain doping layer 108 is 3 nm to 10 nm.

In this embodiment, the method for forming a semiconductor structure further includes: after the isolation layer 114 is formed, the excess first source drain doping layer 112 is removed.

A second source-drain doping layer is formed on the sidewall of the second channel layer 1022b in the subsequent process, and the second channel layer 1022b is exposed by removing the redundant first source-drain doping layer 112, so that a good interface foundation is provided for the formation of the subsequent second source-drain doping layer, the quality of the subsequently formed second source-drain doping layer is better, and the performance of the subsequently formed second transistor is better.

Secondly, when the type of the doped ions in the first source-drain doping layer 108 is opposite to that of the doped ions in the second source-drain doping layer, the influence on the normal performance of the second source-drain doping layer can be avoided by removing the redundant first source-drain doping layer 112.

In this embodiment, a dry etching process is used to remove the excess first source-drain doping layer 112. In other embodiments, a wet etching process or a process combining a wet process and a dry process may be used to remove the excess first source-drain doping layer.

Referring to fig. 9, the second source-drain doping layer 115 is formed on sidewalls of the second channel layer 1022 b.

After a gate structure is formed at the positions of the dummy gate structure 106 and the sacrificial layer 1021, the second source-drain doping layer 115, the second channel layer 1022b, and a portion of the gate structure surrounding the second channel layer 1022b are used to form a second transistor. As can be seen from the foregoing description, the first source-drain doping layer 108, the first channel layer 1022a, and a portion of the gate structure surrounding the first channel layer 1022a in the gate structure are used to form the first transistor, so that different transistors are formed on the gate structure in a vertically stacked manner in the present embodiment, the integration level of the semiconductor structure is increased, and the electrical performance of the semiconductor structure is optimized.

The step of forming the second source-drain doping layer 115 includes: and growing a second epitaxial layer on the side wall of the second channel 1022b by using a selective epitaxial growth method, and doping ions in situ in the process of forming the second epitaxial layer to form a second source-drain doping layer 115.

In other embodiments, ions may be doped into the second epitaxial layer after the second epitaxial layer is formed on the sidewall of the second channel layer, so as to form a second source/drain doping layer. Specifically, the second epitaxial layer is ion-doped by means of ion implantation. The doping ions can achieve the effect of improving the carrier mobility of the transistor.

In this embodiment, the first transistor and the second transistor are formed to have different conductivity types, so that the semiconductor structure is formed to function as an inverter or a transmission gate. Accordingly, the dopant ion types in the first source drain doped layer 108 and the second source drain doped layer 115 are opposite. In other embodiments, the types of the doped ions in the first source-drain doped layer and the second source-drain doped layer may also be the same, so as to prepare for the subsequent formation of two identical transistor structures.

Therefore, in this embodiment, the second transistor is an NMOS, and the material of the second source-drain doping layer 115 is silicon carbide or silicon phosphide doped with N-type ions. Specifically, the N-type ions include P, As or Sb.

In other embodiments, when the second transistor is a PMOS, the second source-drain doping layer is made of silicon germanium doped with P-type ions. Specifically, the P-type ions include B, Ga or In.

Referring to fig. 10, an interlayer dielectric layer 116 is formed on the substrate 100 exposed by the dummy gate structure 106, and the interlayer dielectric layer 116 covers the first source-drain doping layer 108 and the second source-drain doping layer 115 and exposes the top surface of the dummy gate structure 106.

The interlayer dielectric layer 116 is used for realizing electrical isolation between adjacent transistors, and the material of the interlayer dielectric layer 116 is an insulating material. In this embodiment, the interlayer dielectric layer 116 is made of silicon oxide. In other embodiments, the material of the interlayer dielectric layer may also be one or more of silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride and silicon oxycarbonitride.

Specifically, the step of forming the interlayer dielectric layer 116 includes: forming an interlayer dielectric material layer (not shown) on the dummy gate structure 106 and on the substrate 100 exposed from the dummy gate structure 106, wherein the interlayer dielectric material layer covers the top of the dummy gate structure 106; and carrying out planarization treatment on the interlayer dielectric material layer, removing the interlayer dielectric material layer higher than the dummy gate structure 106, and taking the residual interlayer dielectric material layer after the planarization treatment as the interlayer dielectric layer 116.

In this embodiment, during the process of forming the interlayer dielectric layer 116, the gate mask layer 107 is also removed (as shown in fig. 9).

Referring to fig. 11, the dummy gate structure 106 (shown in fig. 10) is removed, and a gate opening 117 is formed at the position of the dummy gate structure 106; the sacrificial layer 1021 is removed (as shown in fig. 10), and a channel 118 is formed at the location of the sacrificial layer 1021, which is in communication with the gate opening 117.

In the present embodiment, the gate opening 117 exposes a portion of the top surface of the second channel layer 1022b and a portion of the sidewall of the channel layer 1022.

The step of forming the gate opening 117 includes: the dummy gate layer 1062 and the dummy gate oxide layer 1061 under the dummy gate layer 1062 are removed.

In this embodiment, after the gate opening 117 is formed, the sacrificial layer 1021 exposed by the gate opening 117 is removed, and a channel 118 surrounded by the inner sidewall 111, the fin 101, and the channel layer 1022, or the inner sidewall 111 and the channel layer 1022 is formed, where the channel 118 is communicated with the gate opening 117.

In this embodiment, the sacrificial layer 1021 is removed by a wet etching process to form the channel 118. During the wet etching, the etching rate of the sacrificial layer 1021 is greater than that of the channel layer 1022, so that the channel layer 1022 is not easily damaged during the process of removing the sacrificial layer 1021. Specifically, the sacrificial layer 1021 is removed by HCl solution to form the channel 118.

Referring to fig. 12-17, a gate structure 119 is formed in gate opening 117 and channel 118.

The step of forming the gate structure 119 includes: conformally covering the first work-function layer 120 over the first channel layer 1022a (as shown in figure 15); conformally covering the second work function layer 121 on the second channel layer 1022b (as shown in fig. 15); after forming the first work function layer 120 and the second work function layer 121, a gate layer 122 is formed in the gate opening 117 and the channel 118 (as shown in fig. 17).

The first work function layer 120 is used to adjust the threshold voltage of the first transistor, and the second work function layer 121 is used to adjust the threshold voltage of the second transistor, so that the first transistor and the second transistor can easily meet their performance requirements by forming the first work function layer corresponding to the first transistor and the second work function layer corresponding to the second transistor.

In this embodiment, the first transistor is formed as a PMOS, the second transistor is formed as an NMOS, and accordingly, the first work function layer 120 is a P-type work function layer, and the second work function layer 121 is an N-type work function layer.

Specifically, the material of the first work function layer 120 includes one or more of titanium aluminide, tantalum carbide, aluminum, or titanium carbide, and the material of the second work function layer 121 includes one or more of titanium nitride, tantalum nitride, titanium carbide, tantalum silicon nitride, titanium silicon nitride, and tantalum carbide.

In other embodiments, when the first transistor is an NMOS, the first work function layer is correspondingly an N-type work function layer. Similarly, when the second transistor is a PMOS, the second work function layer is correspondingly a P-type work function layer.

The step of conformally covering the first work function layer 120 on the first channel layer 1022a includes:

as shown in fig. 12, a first workfunction material layer 123 is formed that conformally covers at least the first channel layer 1022a and the second channel layer 1022 b.

In particular, the first work function material layer 123 conformally covers the via 118 and the respective faces of the gate opening 117.

In this embodiment, the first work function material layer 123 is formed by an Atomic Layer Deposition (ALD) process. In other embodiments, the first work function material layer may be formed by a Physical Vapor Deposition (PVD) process.

In particular, the first work function material layer 123 conformally covers the via 118 and the gate opening 117.

As shown in fig. 13 and 14, forming a protection layer 124 in the gate opening 117 and the channel 118 (as shown in fig. 14), wherein the protection layer 124 covers the first work-function material layer 123 on the surface of the first channel layer 1022a and exposes the first work-function material layer 123 on the second channel layer 1022 b; and removing the first work function material layer 123 exposed by the protective layer 124 by adopting a wet etching process, and taking the remaining first work function material layer 123 as the first work function layer 120.

The protection layer 124 is used to protect the first work function material layer 123 formed on the first channel layer 1022a during the process of removing the first work function material layer 123 exposed out of the protection layer 124, so as to reduce the probability that the first work function material layer 123 at the position is erroneously etched.

Specifically, the step of forming the protective layer 124 includes: forming a layer of protective material 125 filling the overlying channel 118 and gate opening 117; a portion of the thickness of the protective material layer 125 is etched back to form the protective layer 124.

In this embodiment, the material of the protection layer 124 is an organic material. The organic material is a material that is easily removed so that damage to the first work function layer 120 and the second work function layer 121 is reduced when the protective layer 124 is subsequently removed.

Specifically, the material of the protection layer 124 may be a BARC (bottom-antireflective coating) material, an ODL (organic dielectric layer) material, a photoresist, a DARC (dielectric-antireflective coating) material, a DUO (Deep UV light absorbing Oxide) material, or an APF (Advanced Patterning Film) material.

In this embodiment, the protective material layer 125 is formed by a spin coating process.

In this embodiment, the first work function material layer 123 exposed by the protection layer 124 is removed by a wet etching process to form the first work function layer 120. In other embodiments, a combined wet and dry process may be used to remove the first work function material layer exposed by the protective layer.

Referring to fig. 15, the step of conformally covering the second work function layer 121 on the second channel layer 1022b includes: after the first work function layer 120 is formed, a second work function layer 121 is formed to conformally cover at least the second channel layer 1022 b.

In this embodiment, the second work function layer 121 is formed by an atomic layer deposition process. In other embodiments, the second work function layer may be formed by a physical vapor deposition process.

The protection layer 124 covers the first work function layer 120, so as to prevent the second work function layer 121 from covering the first work function layer 120, so as to avoid affecting the performance of the formed first transistor.

As shown in fig. 16, after the second work function layer 121 is formed, the protective layer 124 is removed (as shown in fig. 15). By removing the protection layer 124, space is provided for the subsequent formation of the gate layer.

In this embodiment, the protective layer 124 is removed by an ashing process or a dry etching process.

The method for forming a semiconductor structure further includes: a gate dielectric layer (not shown) is formed in the gate opening 117 and the channel 118 before the first work function layer 120 and the second work function layer 121 are formed.

In this embodiment, the gate structure is a metal gate structure, and thus the material of the gate dielectric layer includes HfO₂、ZrO₂HfSiO, HfSiON, HfTaO, HfTiO, HfZrO and Al₂O₃One or more of them. In other embodiments, when the gate structure is a polysilicon gate structure, the gate dielectric layer is made of one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, and amorphous carbon.

As shown in fig. 17, after forming the first work function layer 120 and the second work function layer 121, a gate layer 126 is formed in the gate opening 117 (shown in fig. 12) and the channel 118 (shown in fig. 12).

The gate layer 126 serves as an electrode for achieving electrical connection with an external circuit.

In this embodiment, the gate layer 126 is a metal gate layer. In the present embodiment, the material of the gate layer 126 is magnesium-tungsten alloy. In other embodiments, the material of the gate layer may also be W, Al, Cu, Ag, Au, Pt, Ni, Ti, or the like.

In other embodiments, the gate layer may also be a polysilicon gate layer.

Referring to fig. 18, after forming the gate structure 119, the method further includes: forming a first contact hole plug 127 in the interlayer dielectric layer 116 on two sides of the gate structure 119, wherein the first contact hole plug 127 is positioned on the first source-drain doping layer 108 and is connected with the first source-drain doping layer 108; and forming a second contact hole plug 128 in the interlayer dielectric layer 116 on two sides of the gate structure 119, wherein the second contact hole plug 128 is positioned on the second source-drain doping layer 115 and connected with the second source-drain doping layer 115.

In this embodiment, the first contact hole plug 127 and the second contact hole plug 128 on one side of the gate structure 119 are isolated from each other, and the first contact hole plug 127 and the second contact hole plug 128 on the other side of the gate structure 119 are connected to each other, so that the first transistor and the second transistor constitute an inverter, that is, the formed semiconductor structure is an inverter. The gate structure 119 serves as an input terminal of the inverter, and the connected first contact plug 127 and second contact plug 128 serve as output terminals of the inverter.

The inverter is a basic digital circuit unit, is a basic constituent part of a memory circuit such as an SRAM and the like, and forms a first transistor and a second transistor on the gate structure 119 in a vertically stacked manner, so that the integration level of the inverter structure is increased, and the electrical performance of the semiconductor structure is optimized.

In other embodiments, the first contact hole plug and the second contact hole plug on either side of the gate structure are connected to each other, i.e., the source of one end of the gate structure is connected together and the drain of the other end of the gate structure is connected together, when the first transistor and the second transistor are connected together in parallel. Therefore, different transistors are formed on the gate structure in an up-and-down stacking mode, the integration level of the transmission gate structure is increased, the complexity of wiring is reduced, and the electrical performance of the semiconductor structure is optimized.

When the gate structure is loaded with a high voltage, the NMOS is turned on, and when the gate structure is loaded with a low voltage, the PMOS is turned on. The transmission gate is used for signal buffering on the circuit and drives a larger load.

In other embodiments, the first contact hole plug and the second contact hole plug on two sides of the gate structure are isolated from each other, at this time, the first transistor and the second transistor are two transistors working independently, and different transistors are formed on the gate structure in an up-down stacking manner, so that the area of the semiconductor structure is reduced, the integration level of the semiconductor structure is improved, the energy consumption is reduced, and the electrical performance of the semiconductor structure is improved.

Correspondingly, the embodiment of the invention also provides a semiconductor structure. Referring to fig. 18, a schematic structural diagram of an embodiment of a semiconductor structure of the present invention is shown.

A substrate 100; a fin 101 on the substrate 100; a first source-drain doping layer 108 which is separated on the fin portion 101; one or more spaced apart first channel layers 1022a located between the first source-drain doping layers 108 and contacting the first source-drain doping layers 108, the first channel layers 1022a being suspended above the fin 101; the second source-drain doping layer is separately suspended on the first source-drain doping layer 108; one or more spaced apart second channel layers 1022b between the second source-drain doping layers 115 and in contact with the first source-drain doping layers 108; the gate structure 119 crosses the first channel layer 1022a and the second channel layer 1022b on the fin 101 and surrounds the first channel layer 1022a and the second channel layer 1022 b.

The first source-drain doping layer 108 is in contact with the first channel layer 1022a, so that the first source-drain doping layer 108, the first channel layer 1022a, and a portion of the gate structure 119, which surrounds the first channel layer 1022a, of the gate structure 119 constitute a first transistor; the second source-drain doping layer 115, the second channel layer 1022b and the gate structure 119 surrounding the second channel layer 1022b in the gate structure 119 form a second transistor, and in the embodiment of the invention, different transistors are formed on the gate structure 119 in an up-and-down stacking manner, so that the integration level of the semiconductor structure is increased, and the electrical performance of the semiconductor structure is optimized.

In this embodiment, the material of the fin 101 is the same as that of the substrate 100. In this embodiment, the substrate 100 is a silicon substrate. In other embodiments, the material of the substrate may also be other materials such as germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, and the substrate may also be another type of substrate such as a silicon-on-insulator substrate or a germanium-on-insulator substrate. In other embodiments, the material of the fin may be different from the material of the substrate.

In the present embodiment, the material of the first channel layer 1022a and the second channel layer 1022b is silicon. In other embodiments, the material of the first channel layer or the second channel layer may also be germanium, silicon carbide, gallium arsenide, indium gallium arsenide, or other materials.

In the present embodiment, the number of the first channel layers 1022a is one, and the number of the second channel layers 1022b is one. In other embodiments, the number of the first channel layers may also be more than one, and the number of the second channel layers may also be more than one.

In this embodiment, the first channel layer 1022a and the second channel layer 1022b have the same thickness.

Note that, the distance between the adjacent first channel layer 1022a and the second channel layer 1022b is not too large or too small. If the distance is too large, the volume of the formed semiconductor structure is easily too large. The first source-drain doping layer 108 and the second source-drain doping layer 115 correspond to different transistors, and if the distance between the first channel layer 1022a and the second channel layer 1022b is too small, the first source-drain doping layer 108 and the second source-drain doping layer 115 are easily contacted, so that the performance of the semiconductor structure is poor. In the present embodiment, the distance between the adjacent first and

second channel layers

1022a and 1022b is 8 to 20 nanometers.

In other embodiments, the distance between adjacent first and second channel layers and the thickness of the first channel layer may also follow a proportional relationship according to scaling of device feature size, and specifically, the distance between adjacent first and second channel layers is 3 to 5 times the thickness of the first or second channel layer.

The first source drain doped layer 108 is used as a source and drain region of the first transistor, and the second source drain doped layer 115 is used as a source and drain region of the second transistor.

In this embodiment, the conductivity types of the first transistor and the second transistor are different, so that the semiconductor structure is used as an inverter or a transmission gate. Accordingly, the dopant ion types in the first source drain doped layer 108 and the second source drain doped layer 115 are opposite. In other embodiments, the types of the doped ions in the first source-drain doped layer and the second source-drain doped layer may also be the same.

In this embodiment, the first transistor is a PMOS, and the material of the first source-drain doping layer 108 is silicon germanium doped with P-type ions. Specifically, the P-type ions include B, Ga or In. Correspondingly, the second transistor is an NMOS, and the material of the second source-drain doping layer 115 is silicon carbide or silicon phosphide doped with N-type ions. Specifically, the N-type ions include P, As or Sb.

In other embodiments, when the first transistor is an NMOS, the material of the first source-drain doped layer is silicon carbide or silicon phosphide doped with N-type ions. Similarly, when the second transistor is a PMOS, the second source-drain doped layer is made of silicon germanium doped with P-type ions.

The gate structure 119 includes: a first work function layer 120 conformally covering the first channel layer 1022 a; a second work function layer 121 conformally covering the second channel layer 1022 b; and a gate layer 126 surrounding the first work function layer 120 and the second work function layer 121.

The first work function layer 120 is used to adjust the threshold voltage of the first transistor, and the second work function layer 121 is used to adjust the threshold voltage of the second transistor, so that the first transistor and the second transistor can easily meet their performance requirements through the first work function layer corresponding to the first transistor and the second work function layer corresponding to the second transistor.

In other embodiments, when the first transistor is an NMOS, the first work function layer may also be an N-type work function layer. Similarly, when the second transistor is a PMOS, the second work function layer may also be a P-type work function layer.

In this embodiment, the gate structure 119 is a metal gate structure, and thus the gate layer 126 is a metal gate layer. In the present embodiment, the material of the gate layer 126 is magnesium-tungsten alloy. In other embodiments, the material of the gate layer may also be W, Al, Cu, Ag, Au, Pt, Ni, Ti, or the like.

In other embodiments, the gate structure may also be a polysilicon gate structure, and the gate layer is correspondingly a polysilicon gate layer.

In this embodiment, the gate structure 119 further includes: gate dielectric layers (not shown) at least between the first work function layer 120 and the first channel layer 1022a, and between the second work function layer 121 and the second channel layer 1022 b; the first work function layer 120 and the second work function layer 121 are located on the gate dielectric layer.

In the present embodiment, the gate layer 126 is a metal gate layer, and thus the material of the gate dielectric layer includes HfO₂、ZrO₂HfSiO, HfSiON, HfTaO, HfTiO, HfZrO and Al₂O₃One or more of them. In other embodiments, when the gate layer is a polysilicon gate, the material of the gate dielectric layer includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, and amorphous carbon.

The semiconductor structure further includes: and the interlayer dielectric layer 116 covers the first source-drain doping layer 108 and the second source-drain doping layer 115, and the interlayer dielectric layer 116 exposes the top surface of the gate structure 119.

The semiconductor structure further includes: the first contact hole plug 127 is positioned on the first source-drain doping layer 108, the first contact hole plug 127 is connected with the first source-drain doping layer 108, and the first contact hole plug 127 is positioned in the interlayer dielectric layer 116 on two sides of the gate structure 119; and the second contact hole plug 128 is positioned on the second source-drain doping layer 115, the second contact hole plug 128 is connected with the second source-drain doping layer 115, and the second contact hole plug 128 is positioned in the interlayer dielectric layer 116 on two sides of the gate structure 119.

In this embodiment, the first contact hole plug 127 and the second contact hole plug 128 of one side of the gate structure 119 are isolated from each other, and the first contact hole plug 127 and the second contact hole plug 128 of the other side of the gate structure 119 are connected to each other, so that the first transistor and the second transistor constitute an inverter, that is, the semiconductor structure is an inverter. The gate structure 119 serves as an input terminal of the inverter, and the connected first contact plug 127 and second contact plug 128 serve as output terminals of the inverter.

In other embodiments, the first contact hole plug and the second contact hole plug on either side of the gate structure are connected to each other. I.e. the sources at one end of the gate structure are connected together and the drains at the other end of the gate structure are connected together, while the first and second transistors are connected together in parallel. Therefore, different transistors are formed on the gate structure in an up-and-down stacking mode, the integration level of the transmission gate structure is increased, the complexity of wiring is reduced, and the electrical performance of the semiconductor structure is optimized.

In other embodiments, the first contact hole plug and the second contact hole plug on two sides of the gate structure are isolated from each other, the first transistor and the second transistor are two transistor structures which work independently, and the area of the semiconductor structure is reduced, the integration level of the semiconductor structure is improved, the energy consumption is reduced, and the electrical performance of the semiconductor structure is improved in an up-and-down stacking mode.

The semiconductor structure further includes: the inner sidewall spacers 111 are located between the gate structure 119 under the topmost second channel layer 1022b and the interlayer dielectric layer 116, and between the gate structure 119 under the topmost second channel layer 1022b and the first source-drain doping layer 108.

The inner sidewall 111 is used for reducing a capacitive coupling effect between the first source-drain doping layer 108 and the gate structure 119 and between the second source-drain doping layer 115 and the gate structure 119, so that a parasitic capacitance is reduced, and the electrical performance of the transistor structure is improved.

The semiconductor structure further includes: the isolation layer 114 covers the first source-drain doping layer 108, and the isolation layer 114 exposes the second channel layer 1022 b. Specifically, the isolation layer 114 is located between the first source drain doping layer 108 and the second source drain doping layer 115.

The isolation layer 114 on the first source-drain doped layer 108 should not be too thick nor too thin. If the isolation layer 114 on the first source-drain doping layer 108 is too thick, and the distance between the isolation layer 114 and the adjacent second channel layer 1022b is too small, it is difficult to provide enough space for forming the second source-drain doping layer 115 on the sidewall of the second channel layer 1022b, so that the formation quality of the second source-drain doping layer 115 is too low. If the isolation layer 114 on the first source-drain doping layer 108 is too thin, the isolation layer 114 does not easily electrically isolate the first source-drain doping layer 108 from the second source-drain doping layer, so that the first transistor and the second transistor are not easily operated independently. In this embodiment, the thickness of the isolation layer 114 on the first source-drain doping layer 108 is 3 nm to 10 nm.

In this embodiment, the isolation layer 114 is made of a dielectric material. Specifically, the material of the isolation layer 114 includes one or more of silicon oxide, silicon nitride, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride, and boron carbonitride.

In addition, the semiconductor structure further includes: an isolation structure 113 is formed on the substrate 100 where the fin 101 is exposed. The isolation structures 113 are used to electrically isolate the fins 101 from each other.

The semiconductor structure may be formed by the formation method of the foregoing embodiment, or may be formed by other formation methods. For a detailed description of the semiconductor structure of this embodiment, reference may be made to the corresponding description in the foregoing embodiments, and details of this embodiment are not repeated herein.

Although the embodiments of the present invention are disclosed above, the embodiments of the present invention are not limited thereto. Various changes and modifications may be effected therein by one of ordinary skill in the pertinent art without departing from the scope or spirit of the present embodiments, and it is intended that the scope of the present embodiments be defined by the appended claims.

Claims

1. A method of forming a semiconductor structure, comprising:

providing a substrate, wherein the substrate comprises a substrate, a fin portion protruding from the substrate and a plurality of channel lamination layers located on the fin portion, each channel lamination layer comprises a sacrificial layer and a channel layer located on the sacrificial layer, a part of the channel layer close to one side of the fin portion is used as a first channel layer, and the rest of the channel layer located on the first channel layer is used as a second channel layer;

forming a dummy gate structure crossing the channel lamination layer, wherein the dummy gate structure covers part of the top wall and part of the side wall of the channel lamination layer;

forming a first source drain doping layer in the channel lamination layer on two sides of the pseudo gate structure, wherein the first source drain doping layer is in contact with the first channel layer;

forming a second source-drain doping layer on the side wall of the second channel layer;

forming an interlayer dielectric layer on the substrate exposed out of the pseudo gate structure, wherein the interlayer dielectric layer covers the first source-drain doping layer and the second source-drain doping layer and exposes out of the top of the pseudo gate structure;

removing the pseudo gate structure, and forming a gate opening at the position of the pseudo gate structure;

removing the sacrificial layer, and forming a channel communicated with the gate opening at the position of the sacrificial layer;

and forming a gate structure in the gate opening and the channel.

2. The method of forming a semiconductor structure of claim 1, wherein a thickness of the sacrificial layer between adjacent first and second channel layers is 8 nm to 20 nm.

3. The method for forming a semiconductor structure according to claim 1, wherein the step of forming the first source-drain doping layer comprises: forming grooves in the channel laminated layers on two sides of the pseudo gate structure; forming a first epitaxial layer doped with ions in the groove; and etching back the first epitaxial layer with partial thickness to form the first source drain doped layer.

4. The method for forming a semiconductor structure according to claim 1, wherein a second epitaxial layer is grown on the side wall of the second channel layer by a selective epitaxial growth method, and ions are doped in situ during the formation of the second epitaxial layer to form the second source-drain doping layer;

or forming a second epitaxial layer on the side wall of the second channel layer; and doping ions in the second epitaxial layer to form the second source-drain doping layer.

5. The method for forming the semiconductor structure according to claim 1, wherein the type of the doped ions in the first source-drain doped layer is opposite to the type of the doped ions in the second source-drain doped layer; or the type of the doped ions in the first source-drain doped layer is the same as that of the doped ions in the second source-drain doped layer.

6. The method for forming a semiconductor structure according to claim 1, wherein in the step of forming the first source-drain doping layer, an excess first source-drain doping layer is further formed on a sidewall of the second channel layer;

before forming the second source-drain doping layer, the method further comprises the following steps: and removing the redundant first source drain doping layer.

7. The method for forming a semiconductor structure according to claim 1 or 6, wherein after forming the first source-drain doping layer and before forming the second source-drain doping layer, the method further comprises: and forming an isolation layer covering the first source-drain doping layer, wherein the isolation layer exposes the second channel layer.

8. The method of forming a semiconductor structure of claim 7, wherein a material of the isolation layer is a dielectric material.

9. The method for forming a semiconductor structure according to claim 7, wherein the thickness of the isolation layer on the first source-drain doping layer is 3 nm to 10 nm.

10. The method of forming a semiconductor structure of claim 1, wherein forming the gate structure comprises: conformally covering a first work function layer on the first channel layer; conformally covering a second work function layer on the second channel layer; and forming a gate layer in the gate opening and the channel after forming the first work function layer and the second work function layer.

11. The method of forming a semiconductor structure of claim 10, wherein forming the first and second work function layers comprises: forming a first work-function material layer conformally covering at least the first channel layer and the second channel layer; forming a protective layer in the gate opening and the channel, the protective layer covering the first work function material layer on the first channel layer and exposing the first work function material layer on the second channel layer; removing the first work function material layer exposed out of the protective layer by adopting a wet etching process, and taking the remaining first work function material layer as the first work function layer; after the first work function layer is formed, a second work function layer at least conformally covering the second channel layer is formed; and after the second work function layer is formed, removing the protective layer.

12. The method of claim 11, wherein the protective layer is a BARC material, an ODL material, a photoresist, a DARC material, a DUO material, or an APF material.

13. The method of forming a semiconductor structure of claim 1, further comprising, after forming the gate structure: forming a first contact hole plug in the interlayer dielectric layers on two sides of the grid structure, wherein the first contact hole plug is positioned on the first source drain doping layer and is connected with the first source drain doping layer; forming a second contact hole plug in the interlayer dielectric layers on two sides of the grid structure, wherein the second contact hole plug is positioned on the second source drain doping layer and is connected with the second source drain doping layer;

the first contact hole plug and the second contact hole plug on one side of the grid structure are isolated from each other, and the first contact hole plug and the second contact hole plug on the other side of the grid structure are connected with each other;

or the first contact hole plug and the second contact hole plug on the two sides of the grid structure are isolated from each other; or, the first contact hole plug and the second contact hole plug on any side of the gate structure are connected with each other.

14. A semiconductor structure, comprising:

a substrate;

a fin portion on the substrate;

the first source drain doping layer is separated on the fin part;

one or more spaced first channel layers located between the first source-drain doped layers and contacting the first source-drain doped layers, wherein the first channel layers are suspended above the fin portion;

the second source-drain doping layer is suspended on the first source-drain doping layer in a discrete mode;

one or more spaced second channel layers located between the second source-drain doped layers and contacting the first source-drain doped layers, wherein the second channel layers are suspended above the first channel layers;

and the grid structure stretches across the first channel layer and the second channel layer on the fin part and surrounds the first channel layer and the second channel layer.

15. The semiconductor structure of claim 14, wherein the semiconductor structure further comprises: and the isolation layer covers the first source-drain doping layer, and the second channel layer is exposed out of the isolation layer.

16. The semiconductor structure of claim 15, wherein a material of the isolation layer is a dielectric material.

17. The semiconductor structure of claim 15, wherein a thickness of the isolation layer on the first source drain doped layer is 3 nm to 10 nm.

18. The semiconductor structure of claim 14, wherein a pitch of adjacent first and second channel layers is 8 to 20 nanometers.

19. The semiconductor structure of claim 14, wherein the dopant ions in the first source drain doped layer are of opposite type to the dopant ions in the second source drain doped layer; or the type of the doped ions in the first source-drain doped layer is the same as that of the doped ions in the second source-drain doped layer.

20. The semiconductor structure of claim 14, wherein the gate structure further comprises: the first work function layer covers the first channel layer in a shape-preserving mode; the second work function layer covers the second channel layer in a shape-preserving mode; a gate layer surrounding the first work function layer and the second work function layer.

21. The semiconductor structure of claim 14, wherein the semiconductor structure further comprises: the first contact hole plug is positioned on the first source drain doping layer on two sides of the grid structure and is connected with the first source drain doping layer; the second contact hole plug is positioned on the second source-drain doping layer on two sides of the grid structure and is connected with the second source-drain doping layer;