CN109216454A - Nano-wire transistor and forming method thereof - Google Patents

Nano-wire transistor and forming method thereof Download PDF

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Publication number
CN109216454A
CN109216454A CN201710550773.0A CN201710550773A CN109216454A CN 109216454 A CN109216454 A CN 109216454A CN 201710550773 A CN201710550773 A CN 201710550773A CN 109216454 A CN109216454 A CN 109216454A
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Prior art keywords
layer
nano
gate structure
side wall
source
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Chinese (zh)
Inventor
唐粕人
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Priority to CN201710550773.0A priority Critical patent/CN109216454A/en
Publication of CN109216454A publication Critical patent/CN109216454A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
    • H01L29/0653—Dielectric regions, e.g. SiO2 regions, air gaps adjoining the input or output region of a field-effect device, e.g. the source or drain region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66553—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using inside spacers, permanent or not
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Thin Film Transistor (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

The present invention provides a kind of nano-wire transistor and forming method thereof, wherein the forming method includes: offer substrate；Composite structure is formed over the substrate, the composite structure includes one or more combination layers being stacked, the combination layer includes the sacrificial layer on the substrate and the channel layer on the sacrificial layer, and the material of the channel layer and sacrificial layer is not identical；The sacrificial layer of the composite structure side wall is performed etching, is formed and is recessed in the composite structure sidewall surfaces；Separation layer is formed in the sacrificial layer surface exposed that is recessed；It is formed after the separation layer, forms source and drain doping layer on the substrate of the composite structure two sides, there is the separation layer between the source and drain doping layer and the sacrificial layer；It is formed after source and drain doping layer, removes remaining sacrificial layer；Form the gate structure for surrounding the channel layer.Being formed by transistor can reduce parasitic capacitance, improve transistor performance.

Description

Nano-wire transistor and forming method thereof
Technical field
The present invention relates to technical field of manufacturing semiconductors more particularly to a kind of nano-wire transistor and forming method thereof.
Background technique
With the development of semiconductor technology, the characteristic size of semiconductor devices seldom reduces.Enter deep Asia in device size After micron-scale, short-channel effect becomes the obstacle of conventional planar transistor continuous miniaturization.This is derived from grid control ability Decline, while the influence to drain to bulk potential is increasing.
Nano-wire transistor (NWFET) is expected to solve the problems, such as this.On the one hand, small channel thickness and width make nano wire The grid of transistor facilitates the enhancing of transistor gate ability, and nano-wire transistor closer to the various pieces of channel Enclosing structure is mostly used greatly, grid is modulated channel from all directions, can further enhance modulation capability, improvement threshold Characteristic.Therefore, nano-wire transistor is able to suppress short-channel effect, reduces transistor size.On the other hand, nano-wire transistor Improve grid regulating power using the rill road and enclosing structure of itself and inhibit short-channel effect, alleviates thinned gate dielectric layer The requirement of thickness can reduce grid leakage current.
However, the grid and the distance between source and drain doping layer of the nano-wire transistor that the prior art is formed are smaller, cause Parasitic capacitance between grid and source and drain doping layer is larger, keeps the performance of nano-wire transistor poor.
Summary of the invention
Problems solved by the invention is to provide a kind of nano-wire transistor and forming method thereof, can reduce grid and source and drain Parasitic capacitance between doped layer improves the performance of nano-wire transistor.
To solve the above problems, technical solution of the present invention provides a kind of forming method of nano-wire transistor, comprising: provide Substrate；Composite structure is formed over the substrate, and the composite structure includes one or more combination layers being stacked, described Combination layer includes the sacrificial layer and the channel layer on the sacrificial layer, the channel layer and sacrificial layer on the substrate Material it is not identical；The sacrificial layer of the composite structure side wall is performed etching, is formed in the composite structure sidewall surfaces recessed It falls into；Separation layer is formed in the sacrificial layer surface exposed that is recessed；It is formed after the separation layer, in the composite structure two Source and drain doping layer is formed on the substrate of side, and there is the separation layer between the source and drain doping layer and the sacrificial layer；Formation source After leaking doped layer, remaining sacrificial layer is removed；After removing remaining sacrificial layer, the grid knot for surrounding the channel layer is formed Structure.
Optionally, it is formed before gate structure, forms dummy gate structure, institute in the composite structure side wall and top surface Dummy gate structure sidewall surfaces are stated with side wall；The step of forming the composite structure, dummy gate structure and side wall includes: in institute Formation initial pool structure on substrate is stated, the initial pool structure includes the single or multiple initial pool layers being stacked, The initial pool layer includes the initial sacrificial layer on the substrate and the initial ditch on the initial sacrificial layer Channel layer；It is developed across the dummy gate structure of the initial pool structure, the dummy gate structure covers the initial pool structure Partial sidewall and top surface；Shape covers the side wall of the dummy gate structure side wall；It is to cover with the dummy gate structure and side wall Film performs etching to the substrate surface is exposed the initial pool structure, forms composite structure；Formed gate structure it Before, the forming method further include: dielectric layer is formed on the source and drain doping layer and substrate, the dielectric layer covers the puppet Gate structure sidewall；The dummy gate structure is removed, forms gate openings in the dielectric layer；The gate structure is located at institute It states in gate openings.
Optionally, the thickness of the side wall is greater than or equal to the depth of the recess, and the depth of the recess is described recessed It is trapped in perpendicular to the size in the composite structure sidewall direction.
Optionally, the width of the side wall is 2nm~20nm；The depth of the recess is 2nm~20nm.
Optionally, the technique sacrificial layer of the composite structure side wall performed etching include wet-etching technology or respectively to Same sex dry etch process.
Optionally, the step of forming the separation layer includes: in the sacrificial layer surface that exposes and described of being recessed Channel layer sidewall surfaces form initial seal coat；It is formed after the initial seal coat, forms mask layer in the recess；Shape After mask layer, the initial seal coat is performed etching, removes the initial seal coat of the channel layer sidewall surfaces, is formed Separation layer.
Optionally, it is formed before the source and drain doping layer, further includes: remove the mask layer.
Optionally, the mask layer is identical as the material of the initial seal coat；The exposure mask is removed by same technique The initial seal coat of layer and the channel layer sidewall surfaces.
Optionally, the mask layer is not identical as the material of the initial seal coat；Remove the channel layer sidewall surfaces Initial seal coat after, remove the mask layer.
Optionally, the technique for removing the initial seal coat of the channel layer sidewall surfaces includes: isotropic dry etch The combination of one or both of technique or wet-etching technology.
Optionally, the material of the mask layer and separation layer is siliceous compound, and the siliceous compound includes nitrogen One of element, oxygen element or carbon or multiple combinations.
Optionally, the step of forming the mask layer includes: to form the original mask for covering the initial seal coat surface Layer, the gap that the initial seal coat that the original mask layer is filled up completely in the recess surrounds；Removal covers the channel layer The original mask layer of side wall forms mask layer.
Optionally, removing the technique of the original mask layer on the initial seal coat surface of the channel layer side wall includes each to same Property one or both of dry etch process and wet-etching technology combination.
Optionally, the mask layer with a thickness of 3nm~10nm；The separation layer with a thickness of 1nm~4nm.
Optionally, the step of forming the separation layer include: to be formed cover it is described be recessed the sacrificial layer surface that exposes and The initial seal coat of the channel layer sidewall surfaces, the initial seal coat are filled up completely the recess；Removal covers the ditch The initial seal coat of channel layer side wall forms separation layer.
Correspondingly, technical solution of the present invention also provides a kind of nano-wire transistor, comprising: substrate；On the substrate Channel layer and gate structure, the gate structure surrounds the channel layer；It is served as a contrast positioned at the gate structure and channel layer two sides Source and drain doping layer on bottom, the source and drain doping layer are contacted with the channel layer；Positioned at the source and drain doping layer and the grid Separation layer between structure.
Optionally, there is recess, the separation layer is located at described recessed between the source and drain doping layer and the gate structure Fall into the gate structure and channel layer surface exposed.
Optionally, there is gap between the separation layer and the source and drain doping layer.
Optionally, the material of the separation layer is siliceous compound, and the siliceous compound includes nitrogen, oxygen member One of element or carbon or multiple combinations.
Optionally, the depth of the recess is the recess perpendicular to the size on the gate structure sidewall direction； The depth of the recess is 2nm~20nm.
Compared with prior art, technical solution of the present invention has the advantage that
In the forming method for the nano-wire transistor that technical solution of the present invention provides, the source and drain doping layer and the sacrifice There is the separation layer between layer, then there is separation layer between the source and drain doping layer and the gate structure.The separation layer The spacing between the gate structure and source and drain doping layer can be increased, so as to reduce the gate structure and source and drain doping Parasitic capacitance between layer, and then the performance of formed nano-wire transistor can be improved.
Further, it is formed after the separation layer, removes the mask layer, the source and drain doping layer and grid knot can be made Gap is formed between structure.Since the dielectric constant of air is smaller, the gap can reduce gate structure and source and drain doping layer it Between parasitic capacitance, so as to improve the performance of formed semiconductor structure.
Further, the recess is being less than or equal to the side wall perpendicular to the size in the channel layer sidewall direction Thickness, then the recess can be completely covered at the both ends along the gate structure extending direction, thus the side in the side wall Wall, separation layer and source and drain doping layer are capable of forming closed gap.Therefore, in the process for being subsequently formed dielectric layer and gate structure In, dielectric layer material and gate structure material are not easily accessed the gap, and then can reduce formed nano-wire transistor Parasitic capacitance.
In the nano-wire transistor that technical solution of the present invention provides, have between the source and drain doping layer and the gate structure There is separation layer.The separation layer can increase the spacing between the gate structure and source and drain doping layer, so as to reduce The parasitic capacitance between gate structure and source and drain doping layer is stated, and then the performance of formed nano-wire transistor can be improved.
Further, there is gap between the source and drain doping layer and gate structure.Since the dielectric constant of air is smaller, institute Stating gap can reduce parasitic capacitance between the gate structure and source and drain doping layer, so as to improve formed semiconductor structure Performance.
Detailed description of the invention
Fig. 1 to Fig. 3 is a kind of structural schematic diagram of each step of forming method of nano-wire transistor；
Fig. 4 to Figure 16 is the structural schematic diagram of each step of one embodiment of forming method of nano-wire transistor of the present invention.
Specific embodiment
There are problems for the nano-wire transistor of the prior art, such as: the parasitism electricity between grid and source and drain doping layer Hold larger, the performance of nano-wire transistor is poor.
Now in conjunction with a kind of forming method of nano-wire transistor, the grid for the nano-wire transistor that the prior art is formed is analyzed Parasitic capacitance between source and drain doping layer is larger, the poor reason of the performance of nano-wire transistor:
Fig. 1 to Fig. 3 is a kind of structural schematic diagram of each step of forming method of nano-wire transistor.
Referring to FIG. 1, providing substrate 100；Composite structure is formed on the substrate 100, the composite structure includes more A combination layer being stacked, the combination layer include the sacrificial layer 112 on the substrate 100 and are located at the sacrifice Channel layer 111 on layer 112；It is developed across the dummy gate structure 120 of the composite structure, the dummy gate structure 120 covers The composite structure partial sidewall and top surface have mask layer in dummy gate structure 120；In the dummy gate structure 120 sidewall surfaces form side wall 121.
Referring to FIG. 2, Fig. 2 is subsequent step schematic diagram on the basis of sectional view of the Fig. 1 along direction 11-12, described Source and drain doping layer 130 is formed in the composite structure of 121 two sides of side wall；Dielectric layer 140 is formed on the source and drain doping layer 130, The dielectric layer 140 covers 121 side wall of side wall；The dummy gate structure 120 (as shown in Figure 1) is removed, in the medium The first opening 123 is formed in layer 140；After removing the dummy gate structure 120, the sacrificial layer 112 is removed (such as Fig. 1 institute Show), form the second opening 113.
Referring to FIG. 3, forming gate dielectric layer in first opening 123 and the second 113 side walls of opening and bottom surface 141；It is formed after the gate dielectric layer 141, forms grid 140 in first opening 123 and the second opening 113.
Wherein, only there is gate dielectric layer between the grid 140 and the source and drain doping layer 130 in second opening 113 141.Grid 140, gate dielectric layer 141 and source and drain doping layer 130 in second opening 113 form capacitor.The grid are situated between Matter layer 141 is high-k dielectric layer, and the dielectric constant of the gate dielectric layer 141 is larger, and the thickness of the gate dielectric layer 141 is smaller, Capacitance so as to cause the capacitor is larger, and the performance for being formed by nano-wire transistor is poor.
To solve the technical problem, the present invention provides a kind of forming methods of nano-wire transistor, comprising: to described The sacrificial layer of composite structure side wall performs etching, and is formed and is recessed in the composite structure sidewall surfaces；In the concave bottom table Face forms separation layer；It is formed after the separation layer, forms source and drain doping layer on the substrate of the composite structure two sides, it is described There is separation layer between source and drain doping layer and the sacrificial layer.Wherein, have between the source and drain doping layer and the sacrificial layer The separation layer then has separation layer between the source and drain doping layer and the gate structure.The separation layer can increase institute The spacing between gate structure and source and drain doping layer is stated, so as to reduce posting between the gate structure and source and drain doping layer Raw capacitor.
To make the above purposes, features and advantages of the invention more obvious and understandable, with reference to the accompanying drawing to the present invention Specific embodiment be described in detail.
Fig. 4 to Figure 16 is the structural schematic diagram of each step of one embodiment of forming method of nano-wire transistor of the present invention.
Referring to FIG. 4, providing substrate 200, the substrate 200 is used to form nano-wire transistor.
In the present embodiment, the substrate 200 is silicon substrate.In other embodiments, the substrate can also for germanium substrate, The semiconductor substrates such as silicon-Germanium substrate, silicon-on-insulator substrate or germanium substrate on insulator.
Subsequent that composite structure is formed on the substrate 200, the composite structure includes single combination layer or multiple stackings The combination layer of setting, the combination layer include the sacrificial layer on the substrate 200 and the channel on the sacrificial layer The material of layer, the channel layer and sacrificial layer is not identical.
The present invention will be described for grid technique after the present embodiment.In other embodiments, front gate work can be passed through Skill forms the semiconductor structure.
In the present embodiment, being formed before gate structure, the composite structure side wall and top surface have dummy gate structure, The dummy gate structure sidewall surfaces have side wall.The step of forming the dummy gate structure, side wall and composite structure such as Fig. 4 are extremely Shown in Fig. 6.
With continued reference to FIG. 4, forming initial pool structure on the substrate 200, the initial pool structure includes single A or multiple initial pool layers being stacked, the initial pool layer include the initial sacrificial layer on the substrate 200 202 and the original trench layer 201 on the initial sacrificial layer 202.
The initial pool layer is for being subsequently formed combination layer, and the initial pool structure is for being subsequently formed combination knot Structure.
In the present embodiment, the number of the combination layer is multiple, and multiple combination layers are stacked.In other embodiments In, the number of the combination layer can be 1.
The initial pool layer is long strip type.
The step of forming the initial pool layer includes: the formation initial sacrificial film on the substrate 200；Described initial Original trench film is formed on expendable film, the original trench film is not identical as the material of the initial sacrificial film；To described initial Expendable film and original trench film are patterned, and form the initial pool layer.
In the present embodiment, the material of the initial sacrificial film is silicon.In other embodiments, the material of the initial sacrificial film Material is germanium, SiGe or silicon carbide.
In the present embodiment, the material of the original trench film is SiGe.In other embodiments, the original trench film Material is silicon, germanium or silicon carbide.
The technique for forming the initial sacrificial film and original trench film includes epitaxial growth technology.
Referring to FIG. 5, being developed across the dummy gate structure 220 of the initial pool structure, the dummy gate structure 220 is covered Cover the initial pool structure division side wall and atop part surface；Form the side wall for covering 220 side wall of dummy gate structure 221。
The dummy gate structure 220 is used to take up space to be subsequently formed gate structure.
In the present embodiment, the dummy gate structure 220 includes: the gate oxide across the initial pool structure, described Gate oxide covers the initial pool structure division side wall and top surface；Dummy grid on the gate oxide；Position Mask layer on the dummy grid.
The material of the grid oxide layer is silica, and the material of the mask layer is silicon nitride or silicon oxynitride.
In the present embodiment, the material of the dummy grid is polysilicon.In other embodiments, the material of the dummy grid is Polycrystalline germanium or polycrystalline silicon germanium.
The side wall 221 is used to define the position for the source and drain doping layer being subsequently formed.
The side wall 221 and dummy gate structure 220 cover the initial sacrificial layer 202 perpendicular to the dummy gate structure The partial sidewall of 220 extending directions.
In the present embodiment, the material of the side wall 221 is silicon nitride.In other embodiments, the material of the side wall is also It can be silicon oxynitride.
If the thickness of the side wall 221 is too small, it is easy the formed transistor of source and drain doping layer distance for making to be subsequently formed Channel it is excessively close, thus be easy increase short-channel effect；If the thickness of the side wall 221 is excessive, it is easily reduced to form crystalline substance The integrated level of body pipe.Specifically, the side wall 221 with a thickness of 2nm~20nm.
Referring to FIG. 6, Fig. 6 is subsequent step schematic diagram of the Fig. 5 on the basis of the sectional view in the direction cutting line 21-22, with The dummy gate structure 220 and the side wall 221 are exposure mask, perform etching the initial pool structure to exposing the lining 200 surface of bottom forms composite structure.
In other embodiments, the step of forming the composite structure includes: the formation figure in the initial pool structure The graph layer of shape；The initial pool structure is performed etching using the graph layer as exposure mask, exposes the substrate, is formed The composite structure；It is formed after the composite structure, removes the graph layer.
After performing etching to the initial pool structure, groove 230 is formed in the initial pool structure, it is adjacent recessed Initial pool structure between slot 230 forms composite structure.
In the present embodiment, the groove 230 extends upward through the initial pool in the side perpendicular to 200 surface of substrate Structure, and the groove 230 runs through the initial pool structure on being parallel to 220 extending direction of dummy gate structure.
In the present embodiment, the technique performed etching to the initial pool structure includes dry etch process and wet etching The combination of one or both of technique.
After performing etching to the initial pool structure, the initial sacrificial layer 202 forms sacrificial layer 212, described first Beginning channel layer 201 forms channel layer 211, and the channel layer 211 is not identical as the material of the sacrificial layer 212.
The sacrificial layer 212 is used for be subsequently formed gate structure and providing space, and the channel layer 211 is for being subsequently formed Transistor channel.
In the present embodiment, the material of the sacrificial layer 212 is silicon.In other embodiments, the material of the sacrificial layer is Germanium, SiGe or silicon carbide.
In the present embodiment, the material of the channel layer 211 is SiGe.In other embodiments, the material of the channel layer For silicon, germanium or silicon carbide.
Referring to FIG. 7, being performed etching to the sacrificial layer 212 of the composite structure side wall, in the composite structure side wall table Face forms recess 231.
The recess 231 is for making to form gap between the grid being subsequently formed and source and drain doping layer 260, to reduce grid Parasitic capacitance between pole and source and drain doping layer 260, and then improve the performance of formed nano-wire transistor.
In the present embodiment, the technique performed etching to 212 side wall of sacrificial layer includes wet-etching technology.In other realities It applies in example, the technique performed etching to the sacrificial layer side wall includes isotropic dry etch technique.
In the present embodiment, it includes H that the technological parameter performed etching to 212 side wall of sacrificial layer, which includes: etching liquid,2O2、 NH4One of OH, KOH or multiple combinations, such as SC1 solution, SC1 solution are H2O2And NH4The mixed solution of OH.
The depth of the recess 231 is recessed 231 perpendicular to the size in the composite structure sidewall direction to be described.
If the depth of the recess 231 is excessive, it is easy to cause the grid size being subsequently formed in grid hole too small, from And be unfavorable for control of the grid to carrier in channel, in addition if it is described recess 231 depth it is excessive, the side wall 221, after The continuous source and drain doping layer formed and separation layer are not easy to surround closed gap, thus when being subsequently formed dielectric layer and grid, It is easy filled media layer material or grid material in gap, is unfavorable for reducing the capacitor between source and drain doping layer and grid.Cause This, the depth of the recess 231 is less than or equal to the thickness of the side wall 221.If the depth of the recess 231 is too small, no It is subsequently formed the distance between grid and source and drain doping layer in grid hole conducive to increasing, is formed in grid to be unfavorable for reducing Parasitic capacitance between grid in the hole of pole and source and drain doping layer.Specifically, in the present embodiment, the depth of the recess 231 with The thickness of the side wall 221 is equal, 212 surface of sacrificial layer and the side wall 221 and gate structure that the recess 231 exposes 220 contact surface is coplanar.Specifically, the depth of the recess 231 is 2nm~20nm.
It should be noted that the thickness of the side wall 221 is greater than or equal to the depth of the recess 231, the then side wall 221 can be completely covered the recess 231 at the both ends along 231 extending directions of the recess, thus the side wall 221, subsequent The separation layer and source and drain doping layer of formation are capable of forming closed gap.Therefore, dielectric layer and gate structure are being subsequently formed In the process, dielectric layer material and gate structure material are not easily accessed the gap, and then it is brilliant to reduce formed nano wire The parasitic capacitance of body pipe.In addition, 212 surface of sacrificial layer and the side wall 221 and gate structure that 231 expose that be recessed 220 contact surface is coplanar, can make the of same size of the gate structure in the gate structure and grid hole in subsequent gate opening, So as to increase the homogeneity for being formed by nano-wire transistor performance.
It is subsequent to form separation layer on 212 surface of sacrificial layer that the recess 231 exposes.
In the present embodiment, the step of forming the separation layer, is as shown in Figs. 8 to 11.
Referring to FIG. 8, forming 212 side wall of sacrificial layer and the channel layer 211 that the covering recess 231 exposes The initial seal coat 240 of sidewall surfaces.
The initial seal coat 240 is for being subsequently formed separation layer.
The initial seal coat 240 is also located at 221 side wall of side wall, the gate structure top surface and the lining 200 surface of bottom.
In the present embodiment, the material of the initial seal coat 240 is siliceous compound, and the siliceous compound includes One of nitrogen, oxygen element or carbon or multiple combinations, such as: silica, silicon nitride, silicon oxynitride or SiOCN.? In other embodiments, the material of the initial seal coat can also be low k (k is less than 3.9) dielectric material.
The technique for forming the initial seal coat 240 includes chemical vapor deposition process, physical gas-phase deposition or original Sublayer depositing operation.
If the thickness of the initial seal coat 240 is excessive, easy reduction is subsequently formed grid and source in grid hole The size for leaking gap between doped layer, to be unfavorable for reducing the parasitic capacitance；If the thickness of the initial seal coat 240 It is too small, it is easy to increase technology difficulty.Specifically, the initial seal coat 240 with a thickness of 1nm~4nm.
It is subsequently formed after the initial seal coat 240, forms mask layer in the recess 231.
In the present embodiment, the step of forming the mask layer, is as shown in Figure 9 and Figure 10.
Referring to FIG. 9, forming original mask layer 250, the original mask layer 250 on 240 surface of initial seal coat The gap that the initial seal coat 240 being filled up completely in 231 (as shown in Figure 8) of the recess surrounds.
The original mask layer 250 is for being subsequently formed mask layer.
In the present embodiment, the material of the original mask layer 250 is siliceous compound, and the siliceous compound includes One of nitrogen, oxygen element or carbon or multiple combinations, such as: silicon nitride, silica or silicon oxynitride.In other realities It applies in example, the mask layer can also be low k (k is less than 3.9) dielectric material.
The technique for forming the original mask layer 250 includes chemical vapor deposition process, physical gas-phase deposition or original Sublayer depositing operation.
If the thickness of the original mask layer 250 is too small, it is unfavorable for making the original mask layer 250 to be filled up completely described The gap that initial seal coat 240 in recess 231 surrounds, thus in the original mask of subsequent removal covering 211 side wall of channel layer During layer 250, the original mask layer 250 in the recess 231 is easily removed, to be not easily formed mask layer；Such as The thickness of original mask layer 250 described in fruit is excessive, is easy to increase the original mask layer of subsequent removal covering 211 side wall of channel layer 250 technology difficulty.Specifically, the original mask layer 250 with a thickness of 3nm~10nm.
Referring to FIG. 10, removal covers the original mask layer 250 of 211 side wall of channel layer, mask layer 251 is formed.
The mask layer 251 is used as the exposure mask of initial seal coat 240 described in subsequent etching.
The step of original mask layer 250 of removal covering 211 side wall of channel layer includes: to the original mask layer 250 carry out mask etching.
The technique of the mask etching includes: one of isotropic dry etch technique and wet-etching technology or two Kind combination.
It should be noted that since the original mask layer 250 is filled up completely the initial seal coat in the recess 231 240 gaps surrounded, thus etch the reactant of the original mask only with the original mask that is parallel to 221 side wall of side wall The contact of 250 surface of layer.250 thickness of original mask layer on 240 surface of initial seal coat in the recess 231 is larger.Therefore institute After stating mask etching, still there is original mask layer 250 in the recess 231, form mask layer 251.
Figure 11 is please referred to, is that exposure mask performs etching the initial seal coat 240 with the mask layer 251, removal covering The initial seal coat 240 of 211 side wall of channel layer forms separation layer 241.
The separation layer 241 is used to be isolated the gap and the sacrificial layer 212 that the separation layer 241 surrounds, and prevents subsequent 272 material of grid is formed in the gap.
The technique that removal covers the initial seal coat 240 of 211 side wall of channel layer includes: isotropic dry etch work The combination of one or both of skill and wet-etching technology.
The initial seal coat 240 of 211 sidewall surfaces of channel layer is removed for exposing 211 side wall of channel layer Come, so that the gate structure being subsequently formed be made to contact with the channel layer 211.
In the present embodiment, the thickness of the separation layer 241 is identical as the thickness of initial seal coat 240.Specifically, it is described every Absciss layer 241 with a thickness of 1nm~4nm.
Figure 12 is please referred to, is formed after separation layer 241, removes the mask layer 251.
It should be noted that removing the mask layer 251 can be such that the grid being subsequently formed mixes with source and drain in the present embodiment Gap is formed between diamicton, so as to reduce the dielectric constant of medium between the grid being subsequently formed and source and drain doping layer, into And the parasitic capacitance between grid and source and drain doping layer can be reduced.In other embodiments, the exposure mask can not also be removed Layer.
In the present embodiment, the technique for removing the mask layer 251 includes wet-etching technology or isotropic dry etch The combination of one or both of technique.
In the present embodiment, the thickness of the separation layer 241 is smaller, can make the grid being subsequently formed and source and drain doping layer it Between form gap, to reduce parasitic capacitance.
In other embodiments, the step of forming the separation layer includes: in the sacrificial layer and channel layer sidewall surfaces Initial seal coat is formed, the initial seal coat is filled up completely the recess；The initial seal coat is performed etching, institute is removed The initial seal coat of channel layer sidewall surfaces is stated, separation layer is formed.
Figure 13 is please referred to, is formed after the separation layer 241, forms source on the substrate 200 of the composite structure two sides Doped layer 260 is leaked, there is the separation layer 241 between the source and drain doping layer 260 and the sacrificial layer 212.
Specifically, forming the source and drain doping layer 260 in the groove 230 (as shown in figure 12).
The step of forming source and drain doping layer 260 include: by source and drain epitaxial growth technology in the groove 230 shape At epitaxial layer；The epitaxial layer is doped, source and drain doping source is mixed in the epitaxial layer and forms source and drain doping layer 260.
It should be noted that the separation layer 241 is non-since 212 sidewall surfaces of sacrificial layer have separation layer 241 Therefore brilliant material in the source and drain epitaxial growth process, is not easily formed epitaxial film materials in the recess 231, from And make to form gap between the source and drain doping layer 260 and the sacrificial layer 212.It is described since the dielectric constant of air is smaller Gap can reduce the dielectric constant of medium between the grid being subsequently formed and source and drain doping layer 260, so as to reduce parasitism Capacitor.
In the present embodiment, since the side wall 221 covers the gap along the both ends of 220 extending direction of dummy gate structure, So that the separation layer 241, source and drain doping layer 260 and side wall 221 close the gap.It is described in other embodiments Side wall can only cover the gap along the portions end of 220 extending direction of dummy gate structure.
In the present embodiment, the step of being doped to the epitaxial layer includes: in the source and drain epitaxial growth process In, doping in situ is carried out to the epitaxial layer, forms source and drain doping layer 260.In other embodiments, it can also be infused by ion Enter and the epitaxial layer is doped.
If being formed by nano-wire transistor is PMOS transistor, the material of the epitaxial layer is SiGe or silicon.Institute The conduction type for stating source and drain doping source is p-type, such as boron atom.In other embodiments, by ion implanting in the extension The source and drain doping source is mixed in layer, the source and drain doping source is P-type ion, such as boron ion or BF2 +Ion.
If being formed by nano-wire transistor is NMOS transistor, the material of the epitaxial layer is silicon carbide or silicon. The conduction type in the source and drain doping source is N-type, such as arsenic atom or phosphorus atoms.In other embodiments, pass through ion implanting The source and drain doping source is mixed in the epitaxial layer, the source and drain doping source is N-type ion, such as phosphonium ion or arsenic ion.
Figure 14 is please referred to, forms dielectric layer 261, the dielectric layer 261 on the source and drain doping layer 260 and substrate 200 221 side wall of side wall is covered, and the dielectric layer 261 exposes 220 top of dummy gate structure.
The dielectric layer 261 is electrically insulated for realizing the gate structure being subsequently formed and external circuit.
The material of the dielectric layer 261 is silica, silicon nitride or silicon oxynitride.
The technique for forming the dielectric layer 261 includes chemical vapor deposition process, physical gas-phase deposition or atomic layer Depositing operation.
Figure 15 is please referred to, is formed after source and drain doping layer 260, removes remaining sacrificial layer 212 (as shown in figure 14), is formed Grid hole 270.
The grid hole 270 is used for subsequent receiving gate structure, so that gate structure is made to surround the channel layer 211, into And increase gate structure to the control action of carrier in channel layer 211.
Before removing remaining sacrificial layer 212, the forming method further include: the dummy gate structure 220 is removed, in institute State formation gate openings 222 in dielectric layer 261.
It should be noted that remaining sacrificial layer 212 hangs down after removing the dummy gate structure 220 (as shown in figure 14) Directly it is exposed in the side wall of 222 extending direction of gate openings, it is remaining sacrificial so as to be removed by etching technics Domestic animal layer 212.
In the present embodiment, the technique for removing the dummy gate structure 220 includes: wet-etching technology and dry etch process One or both of combination.
In the present embodiment, the technique for removing remaining sacrificial layer 212 includes: that wet-etching technology and isotropism dry method are carved One or both of erosion combination.
Figure 16 is please referred to, the gate structure for surrounding the channel layer 211 is formed.
There is the separation layer 241,241 energy of separation layer between the gate structure and the source and drain doping layer 260 Enough increase the distance between gate structure and the source and drain doping layer 260, to reduce the source and drain doping layer 260 and grid knot Parasitic capacitance between structure, and then semiconductor structure performance can be improved.
The gate structure is located at the grid hole 270 and neutralizes in the gate openings 222.
In the present embodiment, the gate structure is located in the gate openings 222 and the grid hole 270, the grid Structure surrounds the channel layer 211.
The step of forming the gate structure includes: in 222 bottom and side wall of gate openings and the grid hole 270 each sidewall surfaces form gate dielectric layer 271；It is formed after the gate dielectric layer 271, in the grid hole 270 and grid Grid 272 is formed in opening 222.
It is formed before the gate dielectric layer 271, further includes: in 222 bottom and side wall of gate openings and the grid The each sidewall surfaces in pole hole 270 form boundary layer (not shown).
The boundary layer is for reducing the interface state density between channel layer 211 and the gate dielectric layer 271.
The material of the boundary layer is silica.
It should be noted that since the gap is enclosure space, during forming the gate structure, the grid Pole structural material is not easily accessed in the gap.In other embodiments, the side wall covers the gap section end, then Since the size in the gap is smaller, the gate structure is not easily accessed the gap.
In the present embodiment, the grid 272 has the gap with source and drain doping layer 260, since the gap is hollow The dielectric constant of gas is smaller, so as to reduce the parasitic capacitance between grid 272 and the source and drain doping layer 260, improves institute The performance of the nano-wire transistor of formation.
The material of the gate dielectric layer 271 is high K medium material, such as: HfO2、La2O3、HfSiON、HfAlO2、ZrO2、 Al2O3Or HfSiO4。
The material of the grid 272 is TiN, TaN, TiAlC, Co, Al, Cu, Ag, Au, Ni, Ti, W, WN or WSi.
6 are continued to refer to figure 1, the embodiment of the present invention also provides a kind of nano-wire transistor, comprising: substrate 200；Positioned at institute Channel layer 211 and the gate structure on substrate 200 are stated, the gate structure surrounds the channel layer 211；Positioned at the grid knot Source and drain doping layer 260 on 211 two sides substrate 200 of structure and channel layer, the source and drain doping layer 260 connect with the channel layer 211 Touching；Separation layer 241 between the source and drain doping layer 260 and the gate structure.
In the present embodiment, there is recess, the separation layer 241 between the source and drain doping layer 260 and the gate structure Positioned at 211 surface of gate structure and channel layer for being recessed and exposing, the separation layer 241 and the source and drain doping layer 260 Between have gap.In other embodiments, can not have the gap between the separation layer and the source and drain doping layer.
In other embodiments, there can also be mask layer in the gap.The material of the mask layer is silicon nitride, oxygen SiClx, silicon oxynitride or low k (k is less than 3.9) dielectric material, low k (k is less than 3.9) dielectric material includes: fluorine silica glass, polyamides Imines porous material, polyethylene porous material or fluoropolymer porous material.
In the present embodiment, the material of the separation layer 241 is siliceous compound, and the siliceous compound includes nitrogen member One of element, oxygen element or carbon or multiple combinations.In other embodiments, the material of the separation layer can also be low K (k is less than 3.9) dielectric material.
In the present embodiment, the depth of the recess is 2nm~20nm.
Although present disclosure is as above, present invention is not limited to this.Anyone skilled in the art are not departing from this It in the spirit and scope of invention, can make various changes or modifications, therefore protection scope of the present invention should be with claim institute Subject to the range of restriction.

Claims (20)

1. a kind of forming method of nano-wire transistor characterized by comprising
Substrate is provided；
Composite structure is formed over the substrate, and the composite structure includes one or more combination layers being stacked, described Combination layer includes the sacrificial layer and the channel layer on the sacrificial layer, the channel layer and sacrificial layer on the substrate Material it is not identical；
The sacrificial layer of the composite structure side wall is performed etching, is formed and is recessed in the composite structure sidewall surfaces；
Separation layer is formed in the sacrificial layer surface exposed that is recessed；
It is formed after the separation layer, forms source and drain doping layer, the source and drain doping on the substrate of the composite structure two sides There is the separation layer between layer and the sacrificial layer；
It is formed after source and drain doping layer, removes remaining sacrificial layer；
After removing remaining sacrificial layer, the gate structure for surrounding the channel layer is formed.
2. the forming method of nano-wire transistor as described in claim 1, which is characterized in that it is formed before gate structure, The composite structure side wall and top surface form dummy gate structure, and the dummy gate structure sidewall surfaces have side wall；
The step of forming the composite structure, dummy gate structure and side wall includes: to form initial pool structure over the substrate, The initial pool structure includes the single or multiple initial pool layers being stacked, and the initial pool layer includes positioned at described Initial sacrificial layer on substrate and the original trench layer on the initial sacrificial layer；It is developed across the initial pool knot The dummy gate structure of structure, the dummy gate structure cover the initial pool structure division side wall and top surface；Shape covers institute State the side wall of dummy gate structure side wall；The initial pool structure is performed etching using the dummy gate structure and side wall as exposure mask To the substrate surface is exposed, composite structure is formed；
It is formed before gate structure, the forming method further include: form dielectric layer on the source and drain doping layer and substrate, institute It states dielectric layer and covers the dummy gate structure side wall；The dummy gate structure is removed, forms gate openings in the dielectric layer； The gate structure is located in the gate openings.
3. the forming method of nano-wire transistor as claimed in claim 2, which is characterized in that the thickness of the side wall be greater than or Equal to the depth of the recess, the depth of the recess is the recess perpendicular to the ruler in the composite structure sidewall direction It is very little.
4. the forming method of nano-wire transistor as claimed in claim 3, which is characterized in that the width of the side wall is 2nm ~20nm；The depth of the recess is 2nm~20nm.
5. the forming method of nano-wire transistor as described in claim 1, which is characterized in that the composite structure side wall The technique that sacrificial layer performs etching includes wet-etching technology or isotropic dry etch technique.
6. the forming method of nano-wire transistor as described in claim 1, which is characterized in that the step of forming the separation layer It include: in the sacrificial layer surface exposed and the channel layer sidewall surfaces formation initial seal coat of being recessed；Form institute After stating initial seal coat, mask layer is formed in the recess；It is formed after mask layer, the initial seal coat is carved Erosion removes the initial seal coat of the channel layer sidewall surfaces, forms separation layer.
7. the forming method of nano-wire transistor as claimed in claim 6, which is characterized in that formed the source and drain doping layer it Before, further includes: remove the mask layer.
8. the forming method of nano-wire transistor as claimed in claim 7, which is characterized in that the mask layer and described initial The material of separation layer is identical；The initial seal coat of the mask layer and the channel layer sidewall surfaces is removed by same technique.
9. the forming method of nano-wire transistor as claimed in claim 7, which is characterized in that the mask layer and described initial The material of separation layer is not identical；After the initial seal coat for removing the channel layer sidewall surfaces, the mask layer is removed.
10. the forming method of nano-wire transistor as claimed in claim 6, which is characterized in that remove the channel layer side wall The technique of the initial seal coat on surface includes: one or both of isotropic dry etch technique or wet-etching technology group It closes.
11. the forming method of nano-wire transistor as claimed in claim 6, which is characterized in that the mask layer and separation layer Material be siliceous compound, the siliceous compound includes one of nitrogen, oxygen element or carbon or a variety of Combination.
12. the forming method of nano-wire transistor as claimed in claim 6, which is characterized in that form the step of the mask layer It suddenly include: to form the original mask layer for covering the initial seal coat surface, the original mask layer is filled up completely the recess In the gap that surrounds of initial seal coat；Removal covers the original mask layer of the channel layer side wall, forms mask layer.
13. the forming method of nano-wire transistor as claimed in claim 6, which is characterized in that remove the channel layer side wall The technique of original mask layer on initial seal coat surface include in isotropic dry etch technique and wet-etching technology One or two combination.
14. the forming method of nano-wire transistor as claimed in claim 6, which is characterized in that the mask layer with a thickness of 3nm~10nm；The separation layer with a thickness of 1nm~4nm.
15. the forming method of nano-wire transistor as described in claim 1, which is characterized in that form the step of the separation layer It suddenly include: to form the initial seal coat for covering the sacrificial layer surface and the channel layer sidewall surfaces for being recessed and exposing, institute It states initial seal coat and is filled up completely the recess；Removal covers the initial seal coat of the channel layer side wall, forms separation layer.
16. a kind of nano-wire transistor, is characterized in that, comprising:
Substrate；
Channel layer and gate structure on the substrate, the gate structure surround the channel layer；
Source and drain doping layer on the gate structure and channel layer two sides substrate, the source and drain doping layer and the channel layer Contact；
Separation layer between the source and drain doping layer and the gate structure.
17. nano-wire transistor as claimed in claim 16, which is characterized in that the source and drain doping layer and the gate structure Between there is recess, the separation layer is located at the gate structure and channel layer surface that expose of being recessed.
18. nano-wire transistor as claimed in claim 17, which is characterized in that the separation layer and the source and drain doping layer it Between have gap.
19. nano-wire transistor as claimed in claim 18, which is characterized in that the material of the separation layer is siliceous chemical combination Object, the siliceous compound include one of nitrogen, oxygen element or carbon or multiple combinations.
20. nano-wire transistor as claimed in claim 17, which is characterized in that the depth of the recess is that the recess is being hung down Directly in the size on the gate structure sidewall direction；The depth of the recess is 2nm~20nm.
CN201710550773.0A 2017-07-07 2017-07-07 Nano-wire transistor and forming method thereof Pending CN109216454A (en)

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Application publication date: 20190115