CN111341661B - Transistors and methods of forming them - Google Patents

Abstract

A transistor and a method for forming the same. The forming method includes: providing a substrate. The substrate includes a substrate, a discrete fin protruding from the substrate, and one or more channel stacks located on the fins. The channel stack includes The sacrificial layer and the channel layer located on the sacrificial layer; forming a gate structure on the fin, the gate structure spanning the channel stack, and the gate structure covering part of the top wall and part of the sidewall of the channel stack; etching The channel stack on both sides of the gate structure forms grooves on both sides of the gate structure; the fins located under the gate structure are ion doped through the bottom of the groove to increase the threshold voltage of the parasitic device; in the groove Source and drain doping layers are formed in the trench. When the fin is doped with ions, the Fermi level of the semiconductor tends to the top of the valence band or the bottom of the conduction band, and the Fermi potential of the semiconductor increases, that is, the difference between the center of the semiconductor bandgap and the Fermi level becomes larger. Large, the threshold voltage increases, making it difficult to turn on the parasitic devices in the fins, optimizing the electrical performance of the transistor.

Description

Transistors and methods of forming them

Technical field

The present invention relates to the field of semiconductor manufacturing, and in particular to a transistor and a method for forming the same.

Background technique

In semiconductor manufacturing, with the development trend of very large-scale integrated circuits, the feature size of integrated circuits continues to decrease. In order to adapt to the smaller feature size, Metal-Oxide-Semiconductor Field-Effect Transistor (Metal-Oxide-Semiconductor Field-Effect Transistor, MOSFET) channel length has also been shortened accordingly. However, as the channel length of the device shortens, the distance between the source and drain of the device also shortens, so the gate structure's ability to control the channel becomes worse, and the gate voltage pinches off the channel. The difficulty of the channel is also increasing, making the subthreshold leakage phenomenon, the so-called short-channel effect (SCE: short-channel effects) more likely to occur.

Therefore, in order to reduce the impact of short channel effects, semiconductor processes have gradually begun to transition from planar MOSFETs to three-dimensional transistors with higher efficiency, such as fin field effect transistors (FinFETs). In FinFET, the gate structure can at least control the ultra-thin body (fin) from both sides. Compared with planar MOSFET, the gate structure has stronger control over the channel and can well suppress the short channel effect; Compared with other devices, FinFET has better compatibility with existing integrated circuit manufacturing.

Contents of the invention

The problem solved by embodiments of the present invention is to provide a transistor and a method for forming the transistor to optimize the electrical performance of the transistor.

In order to solve the above problems, embodiments of the present invention provide a method for forming a transistor, including: providing a substrate, the substrate includes a substrate, a discrete fin protruding from the substrate, and a fin located on the fin. or a plurality of channel stacks, the channel stack including a sacrificial layer and a channel layer located on the sacrificial layer; a gate structure is formed on the fin, the gate structure spans the trench channel stack, the gate structure covers part of the top wall and part of the side wall of the channel stack; etching the channel stack on both sides of the gate structure, on both sides of the gate structure Grooves are formed respectively; the fins located below the gate structure are ion-doped through the bottom of the grooves to increase the threshold voltage of the parasitic device; and source and drain doping layers are formed in the grooves.

Optionally, ion doping is performed in the fin portion through ion implantation.

Optionally, the process parameters of the ion doping are: the angle between the implantation direction and the sidewall of the gate structure is 10 degrees to 45 degrees, the implantation energy is 1.0KeV to 50KeV, and the implantation dose is 1.0E13atm/cm ² to 1.0 E15atm/cm ² .

Optionally, the type of doping ions is different from the type of transistor.

Optionally, the transistor is a PMOS, and the doped ions are phosphorus or arsenic; or the transistor is an NMOS, and the doped ions are boron, aluminum, or gallium.

Optionally, the method of forming the transistor further includes: after forming the groove, and before performing ion doping on the fin located below the gate structure, forming a layer covering the sidewalls of the groove and the gate. The side wall layer of the side walls of a structure.

Optionally, the sidewall layer is SiN, SiON, SiBCN or SiCN.

Optionally, the step of forming a spacer layer includes: forming a spacer material layer conformally covering the groove and the gate structure; removing the spacer material layer on the top of the gate structure and the bottom of the groove to form The side wall layer.

Optionally, an atomic layer deposition process or a low-pressure chemical vapor deposition process is used to form the sidewall material layer.

Optionally, with the direction perpendicular to the sidewalls of the gate structure being lateral, the method of forming the transistor further includes: after forming the groove and before forming the sidewall material layer, etching the transistor laterally. The partial width of the sacrificial layer on the sidewall of the groove forms a sidewall groove surrounded by the channel layer and the sacrificial layer or the channel layer, the sacrificial layer and the fin; forming sidewalls In the material layer step, the sidewall material layer is also filled in the sidewall groove to form an inner wall layer.

Optionally, in the step of forming a sidewall groove, the sacrificial layer on the sidewall of the groove is laterally etched to a width of 2 nanometers to 8 nanometers.

Optionally, a wet etching process is used to remove part of the thickness of the sacrificial layer on the sidewalls of the grooves to form sidewall grooves.

Optionally, the material of the channel layer is Si, and the material of the sacrificial layer is SiGe. The step of forming the sidewall groove includes: using HCl solution to laterally etch the sacrificial layer on the sidewall of the groove.

Correspondingly, embodiments of the present invention also provide a transistor, including: a substrate; a plurality of discrete fins located on the substrate; a source-drain doping layer discretely located on the fins; one or more Spaced channel layers are located between the source and drain doped layers and in contact with the source and drain doped layers. The channel layers are suspended above the fins; a metal gate structure is located on the source and drain doped layers. On the fin part and surrounding the channel layer; doping ions are located in the fin part below the metal gate structure, and the doping ions increase the threshold voltage of the parasitic device.

Optionally, the type of doping ions is different from the type of transistor.

Optionally, the transistor is a PMOS, and the doped ions are phosphorus or arsenic; or the transistor is an NMOS, and the doped ions are boron, aluminum, or gallium.

Optionally, the channel layer is made of silicon.

Optionally, the transistor further includes: an inner wall layer located between the metal gate structure and the source-drain doping layer.

Optionally, the inner wall layer is made of SiN, SiON, SiBCN or SiCN.

Optionally, in a direction perpendicular to the sidewalls of the metal gate structure, the width of the inner wall layer is 2 nanometers to 8 nanometers.

Compared with the existing technology, the technical solutions of the embodiments of the present invention have the following advantages:

In the embodiment of the present invention, after the source-drain doping layer is formed, the gate structure is removed, and a metal gate structure is formed in the position of the original gate structure. The metal gate structure includes an interface layer and a metal gate layer located on the interface layer. Work function layer, the material of the fin part is usually a semiconductor material, the material of the interface layer is usually a dielectric material, the material of the work function layer is usually a metal material; therefore, the fin part, the interface layer and the work function layer constitutes a parasitic device. The ions are first doped at the bottom of the groove. In the process of forming the source-drain doped layer, the source-drain doped layer will undergo an annealing process, and the ions doped at the bottom of the groove will diffuse through the annealing process. to the channel position when the parasitic device is working. When the channel position in the parasitic device is doped with ions, the Fermi level of the semiconductor tends to change towards the top of the valence band, or towards the bottom of the conduction band, and the Fermi potential of the semiconductor increases, that is, the center of the forbidden band of the semiconductor The greater the difference from the Fermi level, the more difficult it is for the inversion layer to be generated, which can increase the threshold voltage of the parasitic device, making it difficult to turn on the parasitic device, and optimizing the electrical performance of the transistor.

Description of the drawings

Figures 1 to 3 are schematic structural diagrams corresponding to each step in a method of forming a transistor;

4 to 15 are schematic structural diagrams corresponding to each step in a method for forming a transistor according to an embodiment of the present invention.

Detailed ways

It can be known from the background art that currently formed devices still have problems with poor performance. Now we will analyze the reasons for poor device performance based on a transistor formation method.

Referring to FIGS. 1 to 3 , a schematic structural diagram corresponding to each step in a method for forming a transistor is shown.

Referring to FIG. 1 , a substrate is provided, which includes a substrate 1 , a discrete fin 2 protruding from the substrate 1 , and one or more channel stacks 3 located on the fin 2 , The channel stack 3 includes a sacrificial layer 31 and a channel layer 32 located on the sacrificial layer 31; a dummy gate structure 4 is formed on the fin 2, and the dummy gate structure 4 spans the channel stack. 3, and the dummy gate structure 4 covers part of the top wall and part of the sidewall of the channel stack 3.

Referring to FIG. 2 , the channel stack 3 on both sides of the dummy gate structure 4 is etched to form a groove 5 . The groove 5 provides process space for subsequent formation of source and drain doping layers.

Referring to Figure 3, a source-drain doping layer 6 is formed in the groove 5 (shown in Figure 2); the dummy gate structure 4 (shown in Figure 2) and the sacrificial layer 31 (shown in Figure 2) are removed ), an opening (not shown in the figure) is formed, and a metal gate structure 7 is formed in the opening. The metal gate structure 7 is located on the fin portion 2 and surrounds the channel layer 32 .

This is a gate-all-around field effect transistor (GAA). The metal gate structure 7 completely surrounds the channel layer 32. Therefore, the channel layer 32 is strongly controlled by the metal gate structure 7. Conducive to the depletion of the channel layer. In the fully surrounded field effect transistor, because the metal gate structure 7 is formed on the fin 2, the side walls and bottom surface of the fin 2 are not surrounded by the metal gate structure. When the device is working, the fin 2 The channel in the fin cannot be completely depleted, so that there are parasitic devices in the fin 2, thereby affecting the threshold voltage of the transistor.

In order to solve the technical problem, an embodiment of the present invention provides a method for forming a transistor, including: providing a substrate, the substrate includes a substrate, separate fins protruding from the substrate, and a method located on the fins. One or more channel stacks, the channel stack includes a sacrificial layer and a channel layer located on the sacrificial layer; a gate structure is formed on the fin, and the gate structure spans the The channel stack, the gate structure covers part of the top wall and part of the sidewall of the channel stack; etching the channel stack on both sides of the gate structure, in the gate structure Grooves are formed on both sides respectively; the fins located below the gate structure are ion-doped through the bottom of the grooves to increase the threshold voltage of the parasitic device; a source-drain doping layer is formed in the grooves.

In the embodiment of the present invention, after the source-drain doping layer is formed, the gate structure is removed, and a metal gate structure is formed in the position of the original gate structure. The metal gate structure includes an interface layer and a metal gate layer located on the interface layer. Work function layer, the material of the fin part is usually a semiconductor material, the material of the interface layer is usually a dielectric material, the material of the work function layer is usually a metal material; therefore, the fin part, the interface layer and the work function layer constitutes a parasitic device. The ions are first doped at the bottom of the groove. In the process of forming the source-drain doped layer, the source-drain doped layer will undergo an annealing process, and the ions doped at the bottom of the groove will diffuse through the annealing process. to the channel position when the parasitic device is working. When the channel position in the parasitic device is doped with ions, the Fermi level of the semiconductor tends to change towards the top of the valence band, or towards the bottom of the conduction band, and the Fermi potential of the semiconductor increases, that is, the center of the forbidden band of the semiconductor The greater the difference from the Fermi level, the more difficult it is for the inversion layer to be generated, which can increase the threshold voltage of the parasitic device, making it difficult to turn on the parasitic device, and optimizing the electrical performance of the transistor.

In order to make the above objects, features and advantages of the embodiments of the present invention more obvious and understandable, specific embodiments of the embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

4 to 15 are schematic structural diagrams corresponding to each step in a method for forming a transistor according to an embodiment of the present invention.

Referring to FIGS. 4 and 5 , a schematic diagram along the fin extension direction and a schematic diagram perpendicular to the fin extension direction are respectively shown. The method of forming a transistor in this embodiment includes: providing a substrate, which includes a substrate 100, a discrete fin 101 protruding from the substrate 100, and one or more channel stacks located on the fin 101. Layer 102 , the channel stack 102 includes a sacrificial layer 1021 and a channel layer 1022 located on the sacrificial layer 1021 .

The substrate 100 is used to provide a process platform for subsequent formation of a fully surrounded metal gate structure.

In this embodiment, the material of the substrate 100 is a silicon substrate. In other embodiments, the substrate is made of silicon, germanium, silicon carbide, gallium arsenide or indium gallium, and the substrate can also be a silicon-on-insulator substrate or a germanium-on-insulator substrate. Components such as PMOS transistors, CMOS transistors, NMOS transistors, resistors, capacitors or inductors can also be formed in the substrate 100 . An interface layer can also be formed on the surface of the substrate 100. The material of the interface layer is silicon oxide, silicon nitride, silicon oxynitride, or the like.

The substrate further includes: an isolation layer 103 located on the substrate 100 where the fin portion 101 is exposed. The isolation layer 103 is used to isolate adjacent devices.

In this embodiment, the isolation layer 103 is made of silicon oxide. In other embodiments, the isolation layer is made of silicon nitride or silicon oxynitride.

In this embodiment, the sacrificial layer 1021 is used to support the channel layer 1022, thereby preparing for the subsequent implementation of the floating arrangement of the channel layer 1022, and is also used to occupy space for the subsequently formed metal gate structure. Location.

The etching rate of the sacrificial layer 1021 is greater than the etching rate of the channel layer 1022, so that when the sacrificial layer 1021 is removed, the removal process causes less damage to the channel layer 1022.

In this embodiment, the material of the channel layer 1022 is Si, and the material of the sacrificial layer 1021 is SiGe.

In this embodiment, the number of the channel stacks 102 is multiple. In other embodiments, the number of the channel stacks may be one.

Referring to FIG. 6 , a gate structure 104 is formed on the fin 101 , the gate structure 104 spans the channel stack 102 , and the gate structure 104 covers part of the top of the channel stack 102 . wall and part of the side wall.

In this embodiment, the gate structure 104 is a dummy gate structure, and the gate structure 104 includes a dummy gate oxide layer 1041 and a dummy gate layer 1042 located on the dummy gate oxide layer 1041 . The gate structure 104 is used to occupy a spatial position for a subsequently formed metal gate structure. In other embodiments, the gate structure is a polysilicon gate structure, and the polysilicon gate structure serves as the final gate structure.

In this embodiment, the material of the dummy gate oxide layer 1041 is silicon oxide. In other embodiments, the material of the dummy gate oxide material layer may also be silicon oxynitride.

In this embodiment, the material of the dummy gate layer 1042 is polysilicon. In other embodiments, the material of the dummy gate layer may also be silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, silicon oxynitride, or amorphous carbon.

The step of forming the gate structure 104 includes: forming a gate structure material layer covering the substrate 100 and the channel stack 102, and forming a gate mask layer 107 on the gate structure material layer, so that The gate mask layer 107 is a mask for etching the gate structure material layer to form a gate structure 104. The gate structure 104 spans the channel stack 102, and the gate structure 104 covers the Part of the top wall and part of the side wall of the channel stack 102 .

The method of forming the transistor further includes forming spacers 105 on the sidewalls of the dummy gate layer 1042 . The sidewalls 105 can be used as an etching mask for subsequent etching processes, and are used to define the formation regions of subsequent source and drain doping layers.

In this embodiment, the sidewall 105 is made of silicon nitride. In other embodiments, the material of the sidewalls may be one or more of silicon oxide, silicon carbide, silicon carbonitride, silicon oxynitride, silicon oxynitride, boron nitride and boron carbonitride. In this embodiment, the side wall 105 has a single-layer structure. In other embodiments, the side walls may be of a laminated structure.

In this embodiment, according to actual process requirements, the thickness of the sidewall 105 is 2 nm to 8 nm. The thickness of the side wall 105 refers to the size of the side wall 105 in a direction perpendicular to the side wall of the side wall 105 .

Referring to FIG. 7 , the channel stack 102 on both sides of the gate structure 104 is etched, and grooves 106 are formed on both sides of the gate structure 104 . The groove 106 is used to provide space for forming source and drain doped layers in subsequent processes.

In this embodiment, the step of forming the groove 106 includes etching the channel stack 102 until the top surface of the fin 101 is exposed to form the groove 106 . In other embodiments, the step of forming the groove includes etching the channel stack and a partial thickness of the top surface of the fin to form the groove.

In this embodiment, a dry etching process is used to etch the channel stack 102 on both sides of the gate structure 104 to form grooves 106 . In other embodiments, a wet etching process may also be used to etch the channel stack on both sides of the gate structure to form grooves.

Referring to FIGS. 8 to 12 , the fin portion 101 located below the gate structure 104 is ion-doped through the bottom of the groove 106 to increase the threshold voltage of the parasitic device.

In the embodiment of the present invention, the source-drain doped layer is subsequently formed; after forming the source-drain doped layer, the gate structure 104 is removed, and a metal gate structure is formed at the position of the original gate structure 104. The metal gate structure includes The interface layer and the work function layer located on the interface layer, the material of the fin portion 101 is usually a semiconductor material, the material of the interface layer is usually a dielectric material, and the material of the work function layer is usually a metal material; therefore The fin 101, the interface layer and the work function layer constitute a parasitic device. The ions are first doped at the bottom of the groove 106 (as shown in FIG. 8 ). In the process of forming the source-drain doped layer, the source-drain doped layer will undergo an annealing process, and the ions will be doped in the recess. The ions at the bottom of the groove 106 undergo annealing treatment and diffuse to the channel position where the parasitic device operates. When the channel position in the parasitic device is doped with ions, the Fermi level of the semiconductor tends to change towards the top of the valence band, or towards the bottom of the conduction band, and the Fermi potential of the semiconductor increases, that is, the center of the forbidden band of the semiconductor The greater the difference from the Fermi level, the more difficult it is for the inversion layer to be generated, which can increase the threshold voltage of the parasitic device, making it difficult to turn on the parasitic device, and optimizing the electrical performance of the transistor.

As shown in FIGS. 8 to 10 , the method of forming the transistor in this embodiment further includes: after forming the groove 106 and before performing ion doping, forming a gate structure 104 covering the sidewalls of the groove 106 and the gate structure 104 . The side wall layer 108 of the side wall (shown in Figure 10). The spacer layer 108 is used to subsequently dope the bottom of the groove 106 with ions, so that the ions cannot easily enter the channel layer 1022 . In other embodiments, the spacer layer 108 may not be formed, and the fins at the bottom of the grooves may be directly ion doped.

As shown in Figures 8 and 9, the step of forming the spacer layer 108 includes: forming a spacer material layer 109 conformally covering the groove 106 and the gate structure 104; as shown in Figure 10, removing the gate electrode The spacer material layer 109 on the top of the structure 104 and the bottom of the groove 106 forms the spacer layer 108 .

In this embodiment, the spacer layer 108 is made of a material with a low K dielectric constant, and the material of the spacer layer 108 is SiN. In other embodiments, the material of the spacer layer may also be a low-K dielectric constant material such as SiON, SiBCN or SiCN.

In this embodiment, the spacer material layer 109 is formed using an atomic layer deposition (ALD) process or a low-pressure chemical vapor deposition (CVD) process.

Continuing to refer to FIG. 8 , in this embodiment, taking the direction perpendicular to the sidewalls of the gate structure 104 as the lateral direction, the method of forming the transistor further includes: after forming the groove 106 , forming the sidewalls. Before the material layer 109, a part of the width of the sacrificial layer 1021 on the sidewall of the groove 106 is laterally etched to form a structure surrounded by the channel layer 1022 and the sacrificial layer 1021 or composed of the channel layer 1022 and the sacrificial layer 1021. and the side wall groove 110 surrounded by the fin portion 101.

In the step of forming the sidewall material layer 109 , the sidewall material layer 109 is also filled in the sidewall groove 110 to form an inner sidewall layer 111 . The inner wall layer 111 is used to reduce the capacitive coupling effect between the subsequently formed metal gate structure and the source-drain doped layer, thereby reducing parasitic capacitance and improving the electrical performance of the transistor structure.

In other embodiments, the sidewall groove 110 and the inner wall layer 111 located in the sidewall groove 110 may not be formed.

Specifically, in this embodiment, a wet etching process is used to remove part of the thickness of the sacrificial layer 1021 on the sidewall of the groove 106 to form the sidewall groove 110 .

In this embodiment, the material of the channel layer 1022 is Si, and the material of the sacrificial layer 1021 is SiGe. The step of forming the sidewall groove 110 includes: using HCl solution to laterally etch the sidewalls of the groove 106 sacrificial layer.

It should be noted that in the step of forming the sidewall groove 110, the width D (as shown in FIG. 8) of the sacrificial layer 1021 on the groove sidewall 110 should not be too large or too small. If the width D of the sacrificial layer 1021 is laterally etched too large, the subsequently formed metal gate structure will be too small, which is not conducive to the control of the channel layer 1022 by the metal gate structure; if the width D of the sacrificial layer 1021 is laterally etched, The width D of the layer 1021 is too small, so that the width of the inner wall layer 111 formed is too small, which is not conducive to reducing the capacitive coupling effect between the metal gate structure and the source-drain doped layer, thereby reducing the parasitic capacitance. In this embodiment, the width D of the sacrificial layer 1021 on the sidewall 110 of the groove is laterally etched from 2 nanometers to 8 nanometers.

As shown in FIG. 11 , the fin portion 101 located below the gate structure 104 is ion-doped through the bottom of the groove 106 to increase the threshold voltage of the parasitic device.

In this embodiment, the transistor is an NMOS, and the doped ions are boron, aluminum or gallium. In other embodiments, the transistor is PMOS, and the doped ions are phosphorus or arsenic.

The ions doped at the bottom of the groove 106 are diffused to the channel position of the parasitic device when the parasitic device is working through the annealing process. When the channel position in the parasitic device is doped with ions, the Fermi level of the semiconductor tends to change towards the top of the valence band, or towards the bottom of the conduction band, and the Fermi potential of the semiconductor increases, that is, the center of the forbidden band of the semiconductor The greater the difference from the Fermi level, the more difficult it is for the inversion layer to be generated, which can increase the threshold voltage of the parasitic device, making it difficult to turn on the parasitic device, and optimizing the electrical performance of the transistor.

In this embodiment, ion doping is performed in the fin portion 101 through ion implantation.

Specifically, the process parameters of the ion doping are: the angle between the implantation direction and the sidewall of the gate structure 104 is 10 degrees to 45 degrees, the implantation energy is 1.0KeV to 50KeV, and the implantation dose is 1.0E13atm/cm ² to 1.0 E15atm/cm ² .

It should be noted that the injection angle should not be too large or too small. If the injection angle is too large, it is difficult for ions to be injected into the fins 101 on both sides of the gate structure 104. The ions are easily injected into the sidewall layer 108 and cannot increase the threshold voltage of the parasitic device; if the ions are injected The angle is too small, and the injected ions are far away from the channel when the parasitic device is working. When the source and drain doped layers are subsequently annealed, it is difficult for the injected ions to diffuse to the channel position when the parasitic device is working, and cannot function. to increase the threshold voltage of parasitic devices. In this embodiment, the angle between the injection direction and the sidewall of the gate structure 104 is 10 degrees to 45 degrees.

It should be noted that the energy of ion implantation should not be too large or too small. If the injected energy is too large and the injected ions are too deep, the injected ions will be far away from the channel when the parasitic device is working, so that the doped ions cannot play the role of increasing the threshold voltage of the parasitic device; if the injected energy If it is too small, the doped ions will be close to the surface of the fin 101 and will be easily lost during the formation of the semiconductor structure, and will not be able to increase the threshold voltage of the parasitic device. In this embodiment, the injection energy is 1.0KeV to 50KeV.

It should be noted that the implantation dose of ions should not be too large or too small. If the injected dose is too large, it will cause excessive damage to the fin portion 101. During the subsequent annealing process of the source and drain doped layers, the damage to the fin portion 101 may not be completely repairable; if the injected dose is too small, it cannot be completely repaired. It plays the role of increasing the threshold voltage of parasitic devices. In this embodiment, the injection dose is 1.0E13atm/cm ² to 1.0E15atm/cm ² .

As shown in FIG. 12 , the method of forming the transistor further includes: after ion doping the groove 106 and before forming the source and drain doping layer, removing the spacer layer 108 (as shown in FIG. 11 ).

In this embodiment, the gate mask layer 107 is used as a mask to remove the spacer layer 108 .

Referring to FIG. 13 , a source-drain doped layer 112 is formed in the groove 106 .

In this embodiment, an epitaxial layer is epitaxially grown in the groove 106 by a selective epitaxial growth method, and ions are doped in situ during the formation of the epitaxial layer; the ion-doped epitaxial layer is annealed to form a source and drain. Doped layer 112.

In this embodiment, the semiconductor device is a Negative channel Metal Oxide Semiconductor (NMOS), and the material of the source-drain doping layer 112 is phosphorus-doped silicon carbide or silicon phosphide. In this embodiment, phosphorus ions are doped into the silicon carbide or silicon phosphide, so that the phosphorus ions replace the positions of silicon atoms in the crystal lattice. The more phosphorus ions doped, the higher the concentration of polyions, and the conductivity improves. The stronger. In other embodiments, the doped ions may also be arsenic.

In other embodiments, the semiconductor device is a PMOS (Positive Channel Metal Oxide Semiconductor). The source and drain doped layer is made of boron-doped silicon germanium. In this embodiment, boron ions are doped into the silicon germanium, so that boron ions replace the positions of silicon atoms in the crystal lattice. The more boron ions doped, the higher the concentration of polyons and the stronger the conductivity. . In other embodiments, the doped ions may also be aluminum or gallium.

It should be noted that during the annealing process to form the source-drain doped layer 112, the doped ions located at the bottom of the groove 106 (as shown in FIG. 8) diffuse to the channel position when the parasitic device operates. , increasing the threshold voltage of parasitic devices.

In this embodiment, the transistor is an NMOS, and the boron, aluminum or gallium doped at the bottom of the groove 106 diffuses to the channel position when the parasitic device is working, so that the Fermi energy level of the semiconductor tends to change to the bottom of the conduction band, and the semiconductor As the Fermi potential increases, that is, the greater the difference between the center of the semiconductor bandgap and the Fermi level, the more difficult it is to generate an inversion layer. When the semiconductor structure is working, the threshold voltage of the NMOS increases, making it difficult for the parasitic devices in the fin 101 to is turned on, improving the electrical performance of the transistor.

In other embodiments, the transistor is a PMOS, and the phosphorus or arsenic doped at the bottom of the groove diffuses to the channel position when the parasitic device is working, causing the semiconductor Fermi level to change toward the top of the valence band, then the semiconductor Fermi potential increases, that is, the greater the difference between the center of the semiconductor bandgap and the Fermi level, the more difficult it is to generate an inversion layer. When the semiconductor structure is working, the threshold voltage of PMOS increases, making it difficult to turn on the parasitic devices in the fins, which increases Electrical properties of transistors.

Referring to Figure 14, after the source-drain doped layer 112 is formed, an interlayer dielectric layer 113 covering the source-drain doped layer 112 is formed, and the interlayer dielectric layer 113 exposes the top of the gate structure 104; The gate structure 104 is removed to form the first opening 114; the sacrificial layer 1021 is removed to form the inner wall layer 111, the fin 101 and the channel layer 1022, or the inner wall layer 111 and the channel layer 1022. A channel 115 is enclosed, and the channel 115 is connected with the first opening 114 .

The material of the interlayer dielectric layer 113 is an insulating material. The interlayer dielectric layer 113 is used to achieve electrical isolation between adjacent transistors. The interlayer dielectric layer 113 is also used to define the subsequently formed metal gate structure. size and location.

Specifically, the step of forming the interlayer dielectric layer 113 covering the source-drain doped layer 112 includes: forming an interlayer dielectric material layer on the substrate 100 exposed by the gate structure 104 and the gate structure 104, The interlayer dielectric material layer covers the top of the gate structure 104; the interlayer dielectric material layer is planarized, the interlayer dielectric material layer higher than the gate structure 104 is removed, and the remaining layer after planarization is The interlayer dielectric material layer serves as the interlayer dielectric layer 113 .

In this embodiment, the material of the interlayer dielectric layer 113 is silicon oxide. In other embodiments, the material of the interlayer dielectric layer is one or more of silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon oxycarboxynitride.

In this embodiment, during the process of forming the interlayer dielectric layer 113, the gate mask layer 107 is also removed (as shown in FIG. 13).

In this embodiment, the first opening 114 exposes part of the top surface of the topmost channel layer 1022 and part of the sidewalls of the channel layer 1022 .

In this embodiment, the step of removing the gate structure 104 and forming the first opening 114 includes removing the dummy gate layer 1042 and the dummy gate oxide layer 1041 located under the dummy gate layer 1042 .

It should be noted that the step of removing the dummy gate oxide layer 1041 below the dummy gate layer 1042 includes: removing the dummy gate oxide layer 1041 exposed by the sidewall 105 , and the channel layer 1022 at the top and the The dummy gate oxide layer 1041 between the spacers 105 is retained.

In this embodiment, a wet etching process is used to remove the sacrificial layer 1021 to form the channel 115 . During the wet etching process, the etching rate of the sacrificial layer 1021 is greater than the etching rate of the channel layer 1022 .

Specifically, HCl solution is used to remove the sacrificial layer 1021 to form the channel 115 .

Referring to FIG. 15 , a metal gate structure 116 is formed in the first opening 114 (shown in FIG. 14 ) and the channel 115 (shown in FIG. 14 ). The metal gate structure 116 completely surrounds and covers the channel layer 1022 .

The step of forming the metal gate structure 116 that completely surrounds the channel layer 1022 includes: forming a gate dielectric layer 1161 conformally covering the first opening 114 and the channel 115; after forming the gate dielectric layer 1161, A metal gate layer 1162 that completely surrounds the channel layer 1022 is formed in the first opening 114 and the channel 115 .

Correspondingly, the present invention also provides a transistor. Referring to FIG. 15 , a schematic structural diagram of an embodiment of a transistor of the present invention is shown.

The transistor includes: a substrate 100; a plurality of discrete fins 101 located on the substrate 100; a source and drain doped layer 112 discretely located on the fins 101; one or more spaced apart channels. Layer 1022 is located between the source-drain doped layer 112 and is in contact with the source-drain doped layer 112. The channel layer 1022 is suspended above the fin 101; the metal gate structure 116 is located On the fin portion 101 and surrounding the channel layer 1022; doping ions are located in the fin portion 101 below the metal gate structure 116, and the doping ions increase the threshold voltage of the parasitic device.

In this embodiment, the transistor is an NMOS, and the doped ions in the fin portion 101 are boron, aluminum or gallium. The doped ions are located at the channel position of the parasitic device when it is working, so that the Fermi level of the semiconductor tends to be conductive. When the band bottom changes, the Fermi potential of the semiconductor increases, that is, the greater the difference between the center of the semiconductor band gap and the Fermi level, the more difficult it is to generate an inversion layer. When the semiconductor structure is working, the threshold voltage of the parasitic device in NMOS increases. , making it difficult for the parasitic device in the fin 101 to turn on, thereby improving the electrical performance of the transistor.

In other embodiments, the transistor is a PMOS, and the doped ions in the fin are phosphorus or arsenic. The doped ions are located at the channel position when the parasitic device is working, and the semiconductor Fermi level tends to change at the top of the valence band, then The Fermi potential of the semiconductor increases, that is, the greater the difference between the center of the semiconductor bandgap and the Fermi level, the more difficult it is to generate an inversion layer. When the semiconductor structure is working, the threshold voltage of PMOS increases, making it difficult for parasitic devices in the fins to is turned on, improving the electrical performance of the transistor.

In this embodiment, the material of the substrate 100 is a silicon substrate. In other embodiments, the substrate is made of silicon, germanium, silicon carbide, gallium arsenide or indium gallium, and the substrate can also be a silicon-on-insulator substrate or a germanium-on-insulator substrate. Components such as PMOS transistors, CMOS transistors, NMOS transistors, resistors, capacitors or inductors can also be formed in the substrate 100 . An interface layer can also be formed on the surface of the substrate 100. The material of the interface layer is silicon oxide, silicon nitride, silicon oxynitride, or the like.

The substrate further includes: an isolation layer 103 located on the substrate 100 where the fin portion 101 is exposed. The isolation layer 103 is used to isolate adjacent devices.

In this embodiment, the isolation layer 103 is made of silicon oxide. In other embodiments, the isolation layer 103 is made of silicon nitride or silicon oxynitride.

In this embodiment, the number of channel layers 1022 is multiple. In other embodiments, the number of the channel layer may also be one.

In this embodiment, the material of the channel layer 1022 is Si.

The transistor also includes: sidewalls 105 located on the sidewalls of the metal gate structure 116 .

In this embodiment, the sidewall 105 is made of silicon nitride. In other embodiments, the material of the sidewalls may be one or more of silicon oxide, silicon carbide, silicon carbonitride, silicon oxynitride, silicon oxynitride, boron nitride and boron carbonitride.

In this embodiment, the side wall 105 has a single-layer structure. In other embodiments, the side walls may be of a laminated structure.

In this embodiment, according to actual process requirements, the thickness of the sidewall 105 is 2 nm to 8 nm. The thickness of the side wall 105 refers to the size of the side wall 105 in a direction perpendicular to the side wall of the side wall 105 .

The transistor further includes: an inner wall layer 111 located between the metal gate structure 116 and the source-drain doping layer 112 . The inner wall layer 111 is used to reduce the capacitive coupling effect between the metal gate structure 116 and the source-drain doped layer 112, thereby reducing parasitic capacitance and improving the electrical performance of the transistor structure.

In this embodiment, the inner wall layer 111 is made of a material with a low K dielectric constant, and the material of the inner wall layer 111 is SiN. In other embodiments, the material of the inner wall layer may also be a low-K dielectric constant material such as SiON, SiBCN or SiCN.

It should be noted that the width of the inner wall layer 111 should not be too large or too small. If the width of the inner wall layer 111 is too large, the space of the metal gate structure 116 will be too small, causing the metal gate structure to be too small. 116 cannot control the channel layer 1022 well; if the width of the inner wall layer 111 is too small, it is not conducive to reducing the capacitive coupling effect between the metal gate structure 116 and the source-drain doped layer 112, thereby reducing parasitic capacitance. In this embodiment, the width of the inner wall layer 111 is 2 to 8 nanometers in a direction perpendicular to the sidewall of the metal gate structure 116 .

In this embodiment, the semiconductor device is a Negative channel Metal Oxide Semiconductor (NMOS), and the material of the source-drain doping layer 112 is phosphorus-doped silicon carbide or silicon phosphide. In this embodiment, phosphorus ions are doped into the silicon carbide or silicon phosphide, so that the phosphorus ions replace the positions of silicon atoms in the crystal lattice. The more phosphorus ions doped, the higher the concentration of polyions, and the conductivity improves. The stronger. In other embodiments, the doped ions may also be arsenic.

In other embodiments, the semiconductor device is a PMOS (Positive Channel Metal Oxide Semiconductor). The source and drain doped layer is made of boron-doped silicon germanium. In this embodiment, boron ions are doped into the silicon germanium, so that boron ions replace the positions of silicon atoms in the crystal lattice. The more boron ions doped, the higher the concentration of polyons and the stronger the conductivity. . In other embodiments, the doped ions may also be aluminum or gallium.

In this embodiment, the metal gate structure 116 includes a gate dielectric layer 1161 and a metal gate layer 1162 located on the gate dielectric layer 1161 . The metal gate layer 1162 completely surrounds the channel layer 1022 .

In this embodiment, the material of the gate dielectric layer 1161 is a high-K dielectric layer, and the material of the high-k dielectric layer refers to a dielectric material whose relative dielectric constant is greater than the relative dielectric constant of silicon oxide. The material of the high-K dielectric layer is one or more of HfO ₂ , ZrO ₂ , HfSiO, HfSiON, HfTaO, HfTiO, HfZrO or Al ₂ O ₃ .

The metal gate layer 1162 is made of magnesium-tungsten alloy, and the metal gate layer 1162 is made of magnesium-tungsten alloy, Al, Cu, Ag, Au, Pt, Ni or Ti.

The transistor may be formed using the forming method described in the previous embodiment, or may be formed using other forming methods. For the specific description of the transistor described in this embodiment, reference may be made to the corresponding description in the foregoing embodiments, which will not be described again in this embodiment.

Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be subject to the scope defined by the claims.

Claims (20)

1. A method of forming a transistor, comprising:

providing a substrate, wherein the substrate comprises a substrate, a discrete fin part protruding out of the substrate and one or more channel laminated layers positioned on the fin part, and the channel laminated layers comprise a sacrificial layer and a channel layer positioned on the sacrificial layer;

forming a gate structure on the fin, the gate structure crossing the channel stack, the gate structure covering a portion of a top wall and a portion of a side wall of the channel stack;

etching the channel lamination layers at two sides of the gate structure, and forming grooves at two sides of the gate structure respectively;

ion doping is carried out on the fin parts positioned below the grid electrode structure through the bottoms of the grooves so as to increase the threshold voltage of the parasitic device;

and forming a source-drain doped layer in the groove, wherein the step of forming the source-drain doped layer comprises annealing treatment, and ions doped at the bottom of the groove are diffused to the position of the channel through the annealing treatment.

2. The method of claim 1, wherein ion doping is performed in the fin by ion implantation.

3. The method of forming a transistor according to claim 1 or 2, wherein the ion doping process parameters are: the included angle between the implantation direction and the side wall of the grid structure is 10-45 degrees, the implantation energy is 1.0 KeV-50 KeV, and the implantation dosage is 1.0E13atm/cm 2-1.0E15 atm/cm2.

4. The method of forming a transistor of claim 1, wherein the type of dopant ions is different from the type of transistor.

5. The method of forming a transistor of claim 1, wherein the transistor is PMOS and the doped ion is phosphorus or arsenic;

or,

the transistor is NMOS, and the doped ions are boron, aluminum or gallium.

6. The method of forming a transistor of claim 1, further comprising: and after the groove is formed, forming a side wall layer covering the side wall of the groove and the side wall of the gate structure before ion doping is carried out on the fin part below the gate structure.

7. The method of claim 6, wherein the sidewall layer is SiN, siON, siBCN or SiCN.

8. The method of forming a transistor of claim 6, wherein the step of forming a sidewall layer comprises: forming a side wall material layer which conformally covers the groove and the grid structure;

and removing the side wall material layers at the top of the grid structure and the bottom of the groove to form the side wall layer.

9. The method of claim 8, wherein the sidewall material layer is formed by an atomic layer deposition process or a low pressure chemical vapor deposition process.

10. The method of forming a transistor of claim 8,

taking the direction perpendicular to the side wall of the grid structure as the transverse direction, the forming method of the transistor further comprises the following steps: after the groove is formed, before the side wall material layer is formed, the sacrificial layer with partial width on the side wall of the groove is transversely etched, and a side wall groove which is formed by the channel layer and the sacrificial layer in a surrounding mode or by the channel layer, the sacrificial layer and the fin part in a surrounding mode is formed;

in the step of forming the side wall material layer, the side wall material layer is further filled in the side wall groove to form an inner side wall layer.

11. The method of forming a transistor of claim 10, wherein in the step of forming a sidewall recess, a width of the sacrificial layer on a sidewall of the recess is 2nm to 8nm.

12. The method of claim 10, wherein a wet etching process is used to remove a portion of the sacrificial layer on the sidewall of the recess to form a sidewall recess.

13. The method of forming a transistor of claim 10, wherein the channel layer is Si, the sacrificial layer is SiGe, and the step of forming sidewall recesses comprises: and transversely etching the sacrificial layer on the side wall of the groove by adopting HCl solution.

14. A transistor, comprising:

a substrate;

a plurality of discrete fins located on the substrate;

the source-drain doping layer is separated on the fin part;

one or more channel layers which are arranged between the source-drain doping layers and are in contact with the source-drain doping layers, wherein the channel layers are suspended above the fin parts;

a metal gate structure located on the fin and surrounding the channel layer;

and doped ions are positioned at channel positions in the fin part below the metal gate structure, and the doped ions are used for improving the threshold voltage of the parasitic device.

15. The transistor of claim 14, wherein the type of dopant ions is different from the type of transistor.

16. The transistor of claim 14 wherein the transistor is PMOS and the doped ion is phosphorus or arsenic;

or,

the transistor is NMOS, and the doped ions are boron, aluminum or gallium.

17. The transistor of claim 14, wherein the material of the channel layer is silicon.

18. The transistor of claim 14, wherein the transistor further comprises: and the inner side wall layer is positioned between the metal gate structure and the source-drain doped layer.

19. The transistor of claim 18 wherein the material of the inner sidewall layer is SiN, siON, siBCN or SiCN.

20. The transistor of claim 18, wherein the width of said inner sidewall layer is between 2nm and 8nm in a direction perpendicular to the sidewalls of said metal gate structure.