CN111341661B - Transistor and forming method thereof - Google Patents

Transistor and forming method thereof Download PDF

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Publication number
CN111341661B
CN111341661B CN201811557662.3A CN201811557662A CN111341661B CN 111341661 B CN111341661 B CN 111341661B CN 201811557662 A CN201811557662 A CN 201811557662A CN 111341661 B CN111341661 B CN 111341661B
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layer
transistor
forming
channel
gate structure
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CN111341661A (en
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周飞
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

A transistor and a method of forming the same, the method of forming includes: providing a substrate, wherein the substrate comprises a substrate, a discrete fin part protruding out of the substrate and one or more channel laminated layers positioned on the fin part, and the channel laminated layers comprise a sacrificial layer and a channel layer positioned on the sacrificial layer; forming a gate structure on the fin, the gate structure crossing the channel stack, the gate structure covering a portion of a top wall and a portion of a side wall of the channel stack; etching channel lamination layers at two sides of the grid structure, and forming grooves at two sides of the grid structure respectively; ion doping is carried out on the fin parts below the grid electrode structure through the bottoms of the grooves so as to increase the threshold voltage of the parasitic device; and forming a source-drain doped layer in the groove. When the fin is doped with ions, the semiconductor fermi level tends to the top of the valence band or the bottom of the conduction band, and then the semiconductor fermi potential increases, i.e. the larger the difference between the semiconductor forbidden band center and the fermi level, the higher the threshold voltage, so that parasitic devices in the fin are difficult to turn on, and the electrical performance of the transistor is optimized.

Description

Transistor and forming method thereof
Technical Field
The present disclosure relates to semiconductor manufacturing, and more particularly, to a transistor and a method for forming the same.
Background
In semiconductor manufacturing, with the trend of very large scale integrated circuits, the feature size of integrated circuits is continuously reduced, and in order to adapt to smaller feature sizes, the channel length of Metal-Oxide-semiconductor field effect transistors (MOSFETs) is also continuously shortened. However, as the channel length of the device is shortened, the distance between the source and the drain of the device is also shortened, so that the control capability of the gate structure on the channel is further and further reduced, and the difficulty of pinching off (pin off) the channel by the gate voltage is further and further increased, so that the phenomenon of subthreshold leakage (subthreshold leakage), namely the so-called short-channel effect (SCE), is more likely to occur.
Accordingly, to reduce the impact of short channel effects, semiconductor processes are gradually beginning to transition from planar MOSFETs to three-dimensional transistors with higher efficiency, such as fin field effect transistors (finfets). In the FinFET, the gate structure can control the ultrathin body (fin part) from at least two sides, and compared with a planar MOSFET, the gate structure has stronger control capability on a channel and can well inhibit short channel effect; and finfets have better compatibility with existing integrated circuit fabrication than other devices.
Disclosure of Invention
The embodiment of the invention solves the problem of providing a transistor and a forming method thereof, and optimizes the electrical performance of the transistor.
In order to solve the above problems, an embodiment of the present invention provides a method for forming a transistor, including: providing a substrate, wherein the substrate comprises a substrate, a discrete fin part protruding out of the substrate and one or more channel laminated layers positioned on the fin part, and the channel laminated layers comprise a sacrificial layer and a channel layer positioned on the sacrificial layer; forming a gate structure on the fin, the gate structure crossing the channel stack, the gate structure covering a portion of a top wall and a portion of a side wall of the channel stack; etching the channel lamination layers at two sides of the gate structure, and forming grooves at two sides of the gate structure respectively; ion doping is carried out on the fin parts positioned below the grid electrode structure through the bottoms of the grooves so as to increase the threshold voltage of the parasitic device; and forming a source-drain doping layer in the groove.
Optionally, ion doping is performed in the fin portion by means of ion implantation.
Optionally, the process parameters of ion doping are as follows: the included angle between the implantation direction and the side wall of the grid structure is 10-45 degrees, the implantation energy is 1.0 KeV-50 KeV, and the implantation dosage is 1.0E13atm/cm 2 To 1.0E15atm/cm 2 。
Optionally, the type of dopant ions is different from the type of transistor.
Optionally, the transistor is PMOS, and the doped ion is phosphorus or arsenic; alternatively, the transistor is an NMOS, and the doped ion is boron, aluminum, or gallium.
Optionally, the method for forming a transistor further includes: and after the groove is formed, forming a side wall layer covering the side wall of the groove and the side wall of the gate structure before ion doping is carried out on the fin part below the gate structure.
Optionally, the side wall layer is SiN, siON, siBCN or SiCN.
Optionally, the step of forming the sidewall layer includes: forming a side wall material layer which conformally covers the groove and the grid structure; and removing the side wall material layers at the top of the grid structure and the bottom of the groove to form the side wall layer.
Optionally, an atomic layer deposition process or a low-pressure chemical vapor deposition process is adopted to form the side wall material layer.
Optionally, the forming method of the transistor further includes, taking a direction perpendicular to the sidewall of the gate structure as a lateral direction: after the groove is formed, before the side wall material layer is formed, the sacrificial layer with partial width on the side wall of the groove is transversely etched, and a side wall groove which is formed by the channel layer and the sacrificial layer in a surrounding mode or by the channel layer, the sacrificial layer and the fin part in a surrounding mode is formed; in the step of forming the side wall material layer, the side wall material layer is further filled in the side wall groove to form an inner side wall layer.
Optionally, in the step of forming the sidewall groove, the width of the sacrificial layer on the sidewall of the groove is 2nm to 8nm.
Optionally, a wet etching process is used to remove a part of the thickness of the sacrificial layer on the side wall of the groove, so as to form a side wall groove.
Optionally, the material of the channel layer is Si, the material of the sacrificial layer is SiGe, and the step of forming the sidewall groove includes: and transversely etching the sacrificial layer on the side wall of the groove by adopting HCl solution.
Correspondingly, the embodiment of the invention also provides a transistor, which comprises: a substrate; a plurality of discrete fins located on the substrate; the source-drain doping layer is separated on the fin part; one or more channel layers which are arranged between the source-drain doping layers and are in contact with the source-drain doping layers, wherein the channel layers are suspended above the fin parts; a metal gate structure located on the fin and surrounding the channel layer; and doping ions in the fin under the metal gate structure, wherein the doping ions are used for increasing the threshold voltage of the parasitic device.
Optionally, the type of dopant ions is different from the type of transistor.
Optionally, the transistor is PMOS, and the doped ion is phosphorus or arsenic; alternatively, the transistor is an NMOS, and the doped ion is boron, aluminum, or gallium.
Optionally, the material of the channel layer is silicon.
Optionally, the transistor further includes: and the inner side wall layer is positioned between the metal gate structure and the source-drain doped layer.
Optionally, the material of the inner side wall layer is SiN, siON, siBCN or SiCN.
Optionally, the width of the inner side wall layer is 2nm to 8nm in a direction perpendicular to the side wall of the metal gate structure.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following advantages:
after the source-drain doped layer is formed, removing the gate structure, and forming a metal gate structure at the original position of the gate structure, wherein the metal gate structure comprises an interface layer and a work function layer positioned on the interface layer, the material of the fin part is usually a semiconductor material, the material of the interface layer is usually a dielectric material, and the material of the work function layer is usually a metal material; the fin, the interface layer and the work function layer thus constitute a parasitic device. The ions are doped at the bottom of the groove, the source-drain doped layer is annealed in the process of forming the source-drain doped layer, and the ions doped at the bottom of the groove are diffused to the channel position of the parasitic device during working through the annealing. When ions are doped at the channel position in the parasitic device, the semiconductor fermi level tends to change at the top of the valence band or tends to change at the bottom of the conduction band, and then the semiconductor fermi potential increases, namely, the larger the difference between the center of the semiconductor forbidden band and the fermi level is, the more difficult an inversion layer is generated, so that the threshold voltage of the parasitic device can be increased, the parasitic device is difficult to turn on, and the electrical performance of the transistor is optimized.
Drawings
Fig. 1 to 3 are schematic structural views corresponding to steps in a method for forming a transistor;
fig. 4 to 15 are schematic structural views corresponding to steps in an embodiment of a method for forming a transistor according to the present invention.
Detailed Description
As can be seen from the background art, the devices formed at present still have the problem of poor performance. The reason for poor device performance is now analyzed in conjunction with a method of forming a transistor.
Referring to fig. 1 to 3, schematic structural diagrams corresponding to steps in a method for forming a transistor are shown.
Referring to fig. 1, a base is provided, the base comprising a substrate 1, a discrete fin 2 protruding above the substrate 1, and one or more channel stacks 3 located on the fin 2, the channel stacks 3 comprising a sacrificial layer 31 and a channel layer 32 located on the sacrificial layer 31; a dummy gate structure 4 is formed on the fin 2, the dummy gate structure 4 straddles the channel stack 3, and the dummy gate structure 4 covers a portion of a top wall and a portion of a side wall of the channel stack 3.
Referring to fig. 2, the channel stack 3 on both sides of the dummy gate structure 4 is etched to form a recess 5. The grooves 5 provide process space for forming source-drain doped layers later.
Referring to fig. 3, a source-drain doped layer 6 is formed in the recess 5 (shown in fig. 2); the dummy gate structure 4 (shown in fig. 2) and the sacrificial layer 31 (shown in fig. 2) are removed, an opening (not shown) is formed, and a metal gate structure 7 is formed in the opening, wherein the metal gate structure 7 is located on the fin 2 and surrounds the channel layer 32.
This is a fully-enclosed field effect transistor (GAA), and the metal Gate structure 7 fully encloses the channel layer 32, so that the channel layer 32 is strongly controlled by the metal Gate structure 7, which is beneficial to depletion of the channel layer. In the fully-enclosed field effect transistor, because the metal gate structure 7 is formed on the fin portion 2, the side wall and the bottom surface of the fin portion 2 are not enclosed by the metal gate structure, and when the device is in operation, the channel in the fin portion 2 cannot be fully depleted, so that parasitic devices exist in the fin portion 2, and the threshold voltage of the transistor is affected.
In order to solve the technical problem, an embodiment of the present invention provides a method for forming a transistor, including: providing a substrate, wherein the substrate comprises a substrate, a discrete fin part protruding out of the substrate and one or more channel laminated layers positioned on the fin part, and the channel laminated layers comprise a sacrificial layer and a channel layer positioned on the sacrificial layer; forming a gate structure on the fin, the gate structure crossing the channel stack, the gate structure covering a portion of a top wall and a portion of a side wall of the channel stack; etching the channel lamination layers at two sides of the gate structure, and forming grooves at two sides of the gate structure respectively; ion doping is carried out on the fin parts positioned below the grid electrode structure through the bottoms of the grooves so as to increase the threshold voltage of the parasitic device; and forming a source-drain doping layer in the groove.
After the source-drain doped layer is formed, removing the gate structure, and forming a metal gate structure at the original position of the gate structure, wherein the metal gate structure comprises an interface layer and a work function layer positioned on the interface layer, the material of the fin part is usually a semiconductor material, the material of the interface layer is usually a dielectric material, and the material of the work function layer is usually a metal material; the fin, the interface layer and the work function layer thus constitute a parasitic device. The ions are doped at the bottom of the groove, the source-drain doped layer is annealed in the process of forming the source-drain doped layer, and the ions doped at the bottom of the groove are diffused to the channel position of the parasitic device during working through the annealing. When ions are doped at the channel position in the parasitic device, the semiconductor fermi level tends to change at the top of the valence band or tends to change at the bottom of the conduction band, and then the semiconductor fermi potential increases, namely, the larger the difference between the center of the semiconductor forbidden band and the fermi level is, the more difficult an inversion layer is generated, so that the threshold voltage of the parasitic device can be increased, the parasitic device is difficult to turn on, and the electrical performance of the transistor is optimized.
In order to make the above objects, features and advantages of the embodiments of the present invention more comprehensible, a detailed description of specific embodiments of the present invention is provided below with reference to the accompanying drawings.
Fig. 4 to 15 are schematic structural diagrams corresponding to steps in an embodiment of a method for forming a transistor according to the present invention.
With reference to fig. 4 and 5, a schematic view along the fin extension direction and a schematic view perpendicular to the fin extension direction are shown, respectively. The method for forming the transistor in the embodiment comprises the following steps: a base is provided, the base comprising a substrate 100, a discrete fin 101 protruding above the substrate 100, and one or more channel stacks 102 located on the fin 101, the channel stacks 102 comprising a sacrificial layer 1021 and a channel layer 1022 located on the sacrificial layer 1021.
The substrate 100 is used to provide a process platform for the subsequent formation of a fully surrounding metal gate structure.
In this embodiment, the material of the substrate 100 is a silicon substrate. In other embodiments, the substrate material is silicon, germanium, silicon carbide, gallium arsenide, or indium gallium oxide, and the substrate can also be a silicon-on-insulator substrate or a germanium-on-insulator substrate. Components such as PMOS transistors, CMOS transistors, NMOS transistors, resistors, capacitors, inductors, or the like can also be formed within the substrate 100. The surface of the substrate 100 may further be formed with an interface layer, and the material of the interface layer may be silicon oxide, silicon nitride, silicon oxynitride, or the like.
The substrate further comprises: and the isolation layer 103 is positioned on the substrate 100 exposed by the fin portion 101. The isolation layer 103 is used to isolate adjacent devices.
In this embodiment, the material of the isolation layer 103 is silicon oxide. In other embodiments, the material of the isolation layer is silicon nitride or silicon oxynitride.
In this embodiment, the sacrificial layer 1021 is configured to support the channel layer 1022, so as to provide for the subsequent implementation of the spaced-apart suspended arrangement of the channel layer 1022, and also to occupy a space for the subsequently formed metal gate structure.
The sacrificial layer 1021 is etched at a rate greater than the channel layer 1022, so that the removal process has less damage to the channel layer 1022 when the sacrificial layer 1021 is removed.
In this embodiment, the material of the channel layer 1022 is Si, and the material of the sacrificial layer 1021 is SiGe.
In this embodiment, the number of the channel stacks 102 is plural. In other embodiments, the number of channel stacks may also be one.
Referring to fig. 6, a gate structure 104 is formed on the fin 101, the gate structure 104 straddles the channel stack 102, and the gate structure 104 covers a portion of a top wall and a portion of a side wall of the channel stack 102.
In this embodiment, the gate structure 104 is a dummy gate structure, and the gate structure 104 includes a dummy gate oxide 1041 and a dummy gate 1042 located on the dummy gate oxide 1041. The gate structure 104 is used to occupy a spatial position for a subsequently formed metal gate structure. In other embodiments, the gate structure is a polysilicon gate structure, which serves as the final gate structure.
In this embodiment, the material of the dummy gate oxide layer 1041 is silicon oxide. In other embodiments, the material of the dummy gate oxide material layer may also be silicon oxynitride.
In this embodiment, the material of the dummy gate layer 1042 is polysilicon. In other embodiments, the material of the dummy gate layer may be silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride oxide, or amorphous carbon.
The step of forming the gate structure 104 includes: a gate structure material layer is formed to cover the substrate 100 and the channel stack 102, a gate mask layer 107 is formed on the gate structure material layer, the gate structure 104 is formed by etching the gate structure material layer with the gate mask layer 107 as a mask, the gate structure 104 spans the channel stack 102, and the gate structure 104 covers a portion of the top wall and a portion of the side wall of the channel stack 102.
The method for forming the transistor further comprises the following steps: a sidewall 105 is formed on the sidewall of the dummy gate 1042. The sidewall 105 may be used as an etching mask for a subsequent etching process to define a formation region of a subsequent source/drain doped layer.
In this embodiment, the material of the sidewall 105 is silicon nitride. In other embodiments, the material of the sidewall may be one or more of silicon oxide, silicon carbide, silicon carbonitride, silicon oxynitride, boron nitride, and boron carbonitride. In this embodiment, the sidewall 105 has a single-layer structure. In other embodiments, the sidewall may be a stacked structure.
In this embodiment, the thickness of the sidewall 105 is 2nm to 8nm according to the actual process requirement. The thickness of the sidewall 105 refers to: and the dimension of the side wall 105 in the direction perpendicular to the side wall 105.
Referring to fig. 7, the channel stack 102 is etched on both sides of the gate structure 104, and recesses 106 are formed on both sides of the gate structure 104, respectively. The recess 106 is used to provide space for forming a source/drain doped layer in a subsequent process.
In this embodiment, the step of forming the recess 106 includes: and etching the channel stack 102 until the top surface of the fin portion 101 is exposed, and forming a groove 106. In other embodiments, the step of forming the recess includes: and etching the channel lamination and the top surface of the fin part with partial thickness to form a groove.
In this embodiment, a dry etching process is used to etch the channel stack 102 on both sides of the gate structure 104 to form the recess 106. In other embodiments, a wet etching process may be further used to etch the channel stack on both sides of the gate structure to form the recess.
Referring to fig. 8-12, the fin 101 under the gate structure 104 is ion doped through the bottom of the recess 106 to increase the threshold voltage of the parasitic device.
The source-drain doped layer is formed subsequently; removing the gate structure 104 after forming the source-drain doped layer, and forming a metal gate structure at the position of the original gate structure 104, wherein the metal gate structure comprises an interface layer and a work function layer positioned on the interface layer, the material of the fin portion 101 is usually a semiconductor material, the material of the interface layer is usually a dielectric material, and the material of the work function layer is usually a metal material; the fin 101, the interface layer and the work function layer thus constitute a parasitic device. The ions are doped at the bottom of the groove 106 (as shown in fig. 8), and during the process of forming the source-drain doped layer, the source-drain doped layer is annealed, and the ions doped at the bottom of the groove 106 are diffused to the channel position of the parasitic device during operation. When ions are doped at the channel position in the parasitic device, the semiconductor fermi level tends to change at the top of the valence band or tends to change at the bottom of the conduction band, and then the semiconductor fermi potential increases, namely, the larger the difference between the center of the semiconductor forbidden band and the fermi level is, the more difficult an inversion layer is generated, so that the threshold voltage of the parasitic device can be increased, the parasitic device is difficult to turn on, and the electrical performance of the transistor is optimized.
As shown in fig. 8 to 10, the method for forming a transistor according to the present embodiment further includes: after forming the recess 106, a sidewall layer 108 is formed to cover the sidewalls of the recess 106 and the sidewalls of the gate structure 104 (as shown in fig. 10) before performing ion doping. The sidewall layer 108 is used to make ions not easy to enter the channel layer 1022 when the bottom of the recess 106 is doped with ions later. In other embodiments, the fin portion at the bottom of the recess may be directly doped without forming the sidewall layer 108.
As shown in fig. 8 and 9, the step of forming the sidewall layer 108 includes: forming a sidewall material layer 109 conformally covering the recess 106 and the gate structure 104; as shown in fig. 10, the sidewall material layer 109 on the top of the gate structure 104 and the bottom of the recess 106 is removed, so as to form the sidewall layer 108.
In this embodiment, the sidewall layer 108 is made of a material with a low K dielectric constant, and the material of the sidewall layer 108 is SiN. In other embodiments, the material of the sidewall layer may be a low K dielectric constant material such as SiON, siBCN, or SiCN.
In this embodiment, the sidewall material layer 109 is formed by an atomic layer deposition process (Atomic layer deposition, ALD) or a low pressure chemical vapor deposition process (Chemical Vapor Deposition, CVD).
With continued reference to fig. 8, in this embodiment, the transistor forming method further includes, with a direction perpendicular to the sidewall of the gate structure 104 as a lateral direction: after the recess 106 is formed, before the sidewall material layer 109 is formed, the sacrificial layer 1021 with a partial width on the sidewall of the recess 106 is laterally etched, so as to form a sidewall recess 110 surrounded by the channel layer 1022 and the sacrificial layer 1021 or surrounded by the channel layer 1022, the sacrificial layer 1021 and the fin 101.
In the step of forming the sidewall material layer 109, the sidewall material layer 109 is further filled in the sidewall groove 110 to form an inner sidewall layer 111. The inner sidewall layer 111 is used for reducing the capacitive coupling effect between the metal gate structure and the source-drain doped layer formed later, thereby reducing parasitic capacitance and improving the electrical performance of the transistor structure.
In other embodiments, the sidewall recess 110 and the inner sidewall layer 111 located in the sidewall recess 110 may not be formed.
Specifically, in this embodiment, a wet etching process is used to remove a part of the sacrificial layer 1021 on the sidewall of the recess 106, so as to form a sidewall recess 110.
In this embodiment, the material of the channel layer 1022 is Si, the material of the sacrificial layer 1021 is SiGe, and the step of forming the sidewall recess 110 includes: the sacrificial layer on the sidewalls of the recess 106 is etched laterally using HCl solution.
It should be noted that, in the step of forming the sidewall groove 110, the width D (as shown in fig. 8) of the sacrificial layer 1021 on the groove sidewall 110 should not be too large or too small, and if the width D of the sacrificial layer 1021 is too large, the metal gate structure formed subsequently is too small, which is not beneficial to control of the channel layer 1022 by the metal gate structure; if the width D of the sacrificial layer 1021 is too small, the width of the formed inner sidewall layer 111 is too small, which is not beneficial to reducing the capacitive coupling effect between the metal gate structure and the source/drain doped layer, thereby reducing the parasitic capacitance. In this embodiment, the width D of the sacrificial layer 1021 on the sidewall 110 of the recess is 2nm to 8nm.
As shown in fig. 11, the fin 101 under the gate structure 104 is ion doped through the bottom of the recess 106 to increase the threshold voltage of the parasitic device.
In this embodiment, the transistor is an NMOS, and the doped ion is boron, aluminum, or gallium. In other embodiments, the transistor is a PMOS and the doped ion is phosphorus or arsenic.
Ions doped at the bottom of the recess 106 are annealed to diffuse to the channel location where the parasitic device is operating. When ions are doped at the channel position in the parasitic device, the semiconductor fermi level tends to change at the top of the valence band or tends to change at the bottom of the conduction band, and then the semiconductor fermi potential increases, namely, the larger the difference between the center of the semiconductor forbidden band and the fermi level is, the more difficult an inversion layer is generated, so that the threshold voltage of the parasitic device can be increased, the parasitic device is difficult to turn on, and the electrical performance of the transistor is optimized.
In this embodiment, ion doping is performed in the fin 101 by means of ion implantation.
Specifically, the ion doping process parameters are as follows: the angle between the implantation direction and the sidewall of the gate structure 104 is 10-45 degrees, the implantation energy is 1.0 KeV-50 KeV, and the implantation dose is 1.0E13atm/cm 2 To 1.0E15atm/cm 2 。
It should be noted that the implantation angle should not be too large or too small. If the implantation angle is too large, ions are not easy to be implanted into the fin portions 101 at two sides of the gate structure 104, and the ions are easy to be implanted into the side wall layer 108, so that the effect of increasing the threshold voltage of the parasitic device cannot be achieved; if the angle of ion implantation is too small, the implanted ions are far away from the channel when the parasitic device works, and subsequently when the source-drain doped layer is annealed, the implanted ions are difficult to diffuse to the position of the channel when the parasitic device works, and the effect of increasing the threshold voltage of the parasitic device cannot be achieved. In this embodiment, the included angle between the implantation direction and the sidewall of the gate structure 104 is 10 to 45 degrees.
The energy of ion implantation should not be too large or too small. If the energy of the implantation is too large, the position of the implanted ions is too deep, and the distance between the implanted ions and a channel of the parasitic device is far when the parasitic device works, so that the doped ions cannot play a role in increasing the threshold voltage of the parasitic device; if the energy of implantation is too small, the doped ions are easily lost during the formation of the semiconductor structure near the surface of the fin 101, and cannot function to increase the threshold voltage of the parasitic device. In this embodiment, the implant energy is 1.0KeV to 50KeV.
The ion implantation dose should not be too large or too small. If the injected dose is too large, damage to the fin portion 101 is too large, and the damage of the fin portion 101 is not necessarily completely repaired in the subsequent annealing process of the source-drain doped layer; if the implanted dose is too small, it cannot function to increase the threshold voltage of the parasitic device. In this example, the implantation dose was 1.0E13atm/cm 2 To 1.0E15atm/cm 2 。
As shown in fig. 12, the method for forming the transistor further includes: after ion doping is performed on the recess 106, the sidewall layer 108 is removed (as shown in fig. 11) before forming a source-drain doped layer.
In this embodiment, the gate mask layer 107 is used as a mask, and the sidewall layer 108 is removed.
Referring to fig. 13, a source drain doped layer 112 is formed in the recess 106.
In this embodiment, an epitaxial layer is epitaxially grown in the recess 106 by a selective epitaxial growth method, and ions are doped in situ during the process of forming the epitaxial layer; and annealing the ion doped epitaxial layer to form a source drain doped layer 112.
In this embodiment, the semiconductor device is NMOS (Negative channel Metal Oxide Semiconductor), and the material of the source-drain doped layer 112 is phosphorus doped silicon carbide or phosphorus doped silicon. In this embodiment, by doping phosphorus ions into the silicon carbide or the silicon phosphide, the phosphorus ions replace the positions of silicon atoms in the crystal lattice, and the more the phosphorus ions are doped, the higher the concentration of the polyions and the stronger the conductivity. In other embodiments, the doped ion may also be arsenic.
In other embodiments, the semiconductor device is PMOS (Positive Channel Metal Oxide Semiconductor). The source-drain doped layer is made of boron-doped silicon germanium. In this embodiment, by doping boron ions in the silicon germanium, the more boron ions are doped, the higher the concentration of the polyton is, and the stronger the conductivity is. In other embodiments, the doped ions may also be aluminum or gallium.
During the process of forming the source-drain doped layer 112 by annealing, the dopant ions at the bottom of the recess 106 (as shown in fig. 8) diffuse to the channel position of the parasitic device during operation, so as to increase the threshold voltage of the parasitic device.
In this embodiment, the transistor is an NMOS, boron, aluminum or gallium doped at the bottom of the recess 106 diffuses into a channel position when the parasitic device works, so that the fermi level of the semiconductor tends to change toward the bottom of the conduction band, and the fermi level of the semiconductor increases, i.e. the larger the difference between the center of the semiconductor forbidden band and the fermi level, the harder the inversion layer is generated.
In other embodiments, the transistor is a PMOS, phosphorus or arsenic doped at the bottom of the groove diffuses to a channel position when the parasitic device works, so that the fermi level of the semiconductor tends to change at the top of the valence band, and the fermi level of the semiconductor increases, i.e. the larger the difference between the center of the forbidden band of the semiconductor and the fermi level is, the harder the inversion layer is generated, and when the semiconductor structure works, the threshold voltage of the PMOS is increased, so that the parasitic device in the fin is difficult to turn on, and the electrical performance of the transistor is improved.
Referring to fig. 14, after the source-drain doped layer 112 is formed, an interlayer dielectric layer 113 is formed to cover the source-drain doped layer 112, and the interlayer dielectric layer 113 exposes the top of the gate structure 104; removing the gate structure 104 to form a first opening 114; the sacrificial layer 1021 is removed, and a channel 115 surrounded by the inner sidewall layer 111, the fin 101 and the channel layer 1022, or the inner sidewall layer 111 and the channel layer 1022 is formed, wherein the channel 115 is communicated with the first opening 114.
The interlayer dielectric layer 113 is made of an insulating material, the interlayer dielectric layer 113 is used for realizing electrical isolation between adjacent transistors, and the interlayer dielectric layer 113 is also used for defining the size and the position of a subsequently formed metal gate structure.
Specifically, the step of forming the interlayer dielectric layer 113 covering the source-drain doped layer 112 includes: forming an interlayer dielectric material layer on the substrate 100 exposed by the gate structure 104 and the gate structure 104, wherein the interlayer dielectric material layer covers the top of the gate structure 104; and carrying out planarization treatment on the interlayer dielectric material layer, and removing the interlayer dielectric material layer higher than the gate structure 104, wherein the remaining interlayer dielectric material layer after the planarization treatment is used as the interlayer dielectric layer 113.
In this embodiment, the material of the interlayer dielectric layer 113 is silicon oxide. In other embodiments, the material of the interlayer dielectric layer is one or more of silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride and silicon oxycarbonitride.
In this embodiment, during the process of forming the interlayer dielectric layer 113, the gate mask layer 107 is also removed (as shown in fig. 13).
In this embodiment, the first opening 114 exposes a portion of the top surface of the topmost channel layer 1022 and a portion of the sidewall of the channel layer 1022.
In this embodiment, the step of removing the gate structure 104 to form the first opening 114 includes: the dummy gate layer 1042 and the dummy gate oxide 1041 under the dummy gate layer 1042 are removed.
It should be noted that the step of removing the dummy gate oxide 1041 below the dummy gate 1042 includes: the dummy gate oxide 1041 exposed from the sidewall 105 is removed, and the dummy gate oxide 1041 between the channel layer 1022 at the top and the sidewall 105 is retained.
In this embodiment, a wet etching process is used to remove the sacrificial layer 1021 to form the channel 115. During the wet etching, the etched rate of the sacrificial layer 1021 is greater than the etched rate of the channel layer 1022.
Specifically, HCl solution is used to remove the sacrificial layer 1021, thereby forming the channel 115.
Referring to fig. 15, a metal gate structure 116 is formed in the first opening 114 (shown in fig. 14) and the channel 115 (shown in fig. 14). The metal gate structure 116 entirely surrounds and covers the channel layer 1022.
The step of forming the metal gate structure 116 that completely surrounds the channel layer 1022 includes: forming a gate dielectric layer 1161 conformally covering the first openings 114 and the channels 115; after forming the gate dielectric layer 1161, a metal gate layer 1162 is formed in the first opening 114 and the channel 115, which completely surrounds the channel layer 1022.
Correspondingly, the invention further provides a transistor. Referring to fig. 15, a schematic diagram of the structure of an embodiment of a transistor of the present invention is shown.
The transistor includes: a substrate 100; a plurality of discrete fins 101 located on the substrate 100; a source-drain doped layer 112, which is separated on the fin portion 101; one or more spaced-apart channel layers 1022 located between the source-drain doped layers 112 and in contact with the source-drain doped layers 112, the channel layers 1022 being suspended above the fin 101; a metal gate structure 116 on the fin 101 and surrounding the channel layer 1022; doped ions are located in the fin 101 below the metal gate structure 116, which are used to raise the threshold voltage of the parasitic device.
In this embodiment, the transistor is an NMOS, the doped ions in the fin 101 are boron, aluminum or gallium, and the doped ions are located at a channel position of the parasitic device during operation, so that the fermi level of the semiconductor tends to change at the bottom of the conduction band, and the fermi potential of the semiconductor increases, i.e. the larger the difference between the center of the semiconductor forbidden band and the fermi level, the harder the inversion layer is generated.
In other embodiments, the transistor is a PMOS, the doped ion in the fin is phosphorus or arsenic, the doped ion is located at a channel position when the parasitic device works, the fermi level of the semiconductor tends to change at the top of the valence band, the fermi potential of the semiconductor increases, that is, the larger the difference between the center of the forbidden band of the semiconductor and the fermi level is, the more difficult the inversion layer is generated, when the semiconductor structure works, the threshold voltage of the PMOS is increased, the parasitic device in the fin is difficult to turn on, and the electrical performance of the transistor is improved.
In this embodiment, the material of the substrate 100 is a silicon substrate. In other embodiments, the substrate material is silicon, germanium, silicon carbide, gallium arsenide, or indium gallium oxide, and the substrate can also be a silicon-on-insulator substrate or a germanium-on-insulator substrate. Components such as PMOS transistors, CMOS transistors, NMOS transistors, resistors, capacitors, inductors, or the like can also be formed within the substrate 100. The surface of the substrate 100 may further be formed with an interface layer, and the material of the interface layer may be silicon oxide, silicon nitride, silicon oxynitride, or the like.
The substrate further comprises: and the isolation layer 103 is positioned on the substrate 100 exposed by the fin portion 101. The isolation layer 103 is used to isolate adjacent devices.
In this embodiment, the material of the isolation layer 103 is silicon oxide. In other embodiments, the material of the isolation layer 103 is silicon nitride or silicon oxynitride.
In this embodiment, the number of the channel layers 1022 is plural. In other embodiments, the number of channel layers may be one.
In this embodiment, the material of the channel layer 1022 is Si.
The transistor further includes: and a sidewall 105 on the sidewall of the metal gate structure 116.
In this embodiment, the material of the sidewall 105 is silicon nitride. In other embodiments, the material of the sidewall may be one or more of silicon oxide, silicon carbide, silicon carbonitride, silicon oxynitride, boron nitride, and boron carbonitride.
In this embodiment, the sidewall 105 has a single-layer structure. In other embodiments, the sidewall may be a stacked structure.
In this embodiment, the thickness of the sidewall 105 is 2nm to 8nm according to the actual process requirement. The thickness of the sidewall 105 refers to: and the dimension of the side wall 105 in the direction perpendicular to the side wall 105.
The transistor further includes: and an inner sidewall layer 111 located between the metal gate structure 116 and the source/drain doped layer 112. The inner sidewall layer 111 is used to reduce the capacitive coupling effect between the metal gate structure 116 and the source/drain doped layer 112, thereby reducing parasitic capacitance and improving the electrical performance of the transistor structure.
In this embodiment, the inner side wall layer 111 is made of a material with a low K dielectric constant, and the material of the inner side wall layer 111 is SiN. In other embodiments, the material of the inner sidewall layer may be a low K dielectric constant material such as SiON, siBCN, or SiCN.
It should be noted that, the width of the inner sidewall 111 should not be too large or too small, if the width of the inner sidewall 111 is too large, the space of the metal gate structure 116 is too small, so that the metal gate structure 116 cannot well control the channel layer 1022; if the width of the sidewall layer 111 is too small, it is not beneficial to reduce the capacitive coupling effect between the metal gate structure 116 and the source-drain doped layer 112, thereby reducing the parasitic capacitance. In this embodiment, the width of the inner sidewall layer 111 is 2nm to 8nm in the direction perpendicular to the sidewall of the metal gate structure 116.
In this embodiment, the semiconductor device is NMOS (Negative channel Metal Oxide Semiconductor), and the material of the source-drain doped layer 112 is phosphorus doped silicon carbide or phosphorus doped silicon. In this embodiment, by doping phosphorus ions into the silicon carbide or the silicon phosphide, the phosphorus ions replace the positions of silicon atoms in the crystal lattice, and the more the phosphorus ions are doped, the higher the concentration of the polyions and the stronger the conductivity. In other embodiments, the doped ion may also be arsenic.
In other embodiments, the semiconductor device is PMOS (Positive Channel Metal Oxide Semiconductor). The source-drain doped layer is made of boron-doped silicon germanium. In this embodiment, by doping boron ions in the silicon germanium, the more boron ions are doped, the higher the concentration of the polyton is, and the stronger the conductivity is. In other embodiments, the doped ions may also be aluminum or gallium.
In this embodiment, the metal gate structure 116 includes a gate dielectric layer 1161 and a metal gate layer 1162 disposed on the gate dielectric layer 1161. The metal gate layer 1162 entirely surrounds the channel layer 1022.
In this embodiment, the gate dielectric layer 1161 is a high-K dielectric layer, and the material of the high-K dielectric layer is a dielectric material with a relative dielectric constant greater than that of silicon oxide. The high-K dielectric layer is made of HfO 2 、ZrO 2 HfSiO, hfSiON, hfTaO, hfTiO, hfZrO or Al 2 O 3 One or more of them.
The material of the metal gate layer 1162 is magnesium-tungsten alloy, and the material of the metal gate layer 1162 is magnesium-tungsten alloy, al, cu, ag, au, pt, ni or Ti.
The transistor may be formed by the forming method described in the foregoing embodiment, or may be formed by another forming method. For a specific description of the transistor in this embodiment, reference may be made to the corresponding description in the foregoing embodiment, which is not repeated here.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.

Claims (20)

1. A method of forming a transistor, comprising:
providing a substrate, wherein the substrate comprises a substrate, a discrete fin part protruding out of the substrate and one or more channel laminated layers positioned on the fin part, and the channel laminated layers comprise a sacrificial layer and a channel layer positioned on the sacrificial layer;
forming a gate structure on the fin, the gate structure crossing the channel stack, the gate structure covering a portion of a top wall and a portion of a side wall of the channel stack;
etching the channel lamination layers at two sides of the gate structure, and forming grooves at two sides of the gate structure respectively;
ion doping is carried out on the fin parts positioned below the grid electrode structure through the bottoms of the grooves so as to increase the threshold voltage of the parasitic device;
and forming a source-drain doped layer in the groove, wherein the step of forming the source-drain doped layer comprises annealing treatment, and ions doped at the bottom of the groove are diffused to the position of the channel through the annealing treatment.
2. The method of claim 1, wherein ion doping is performed in the fin by ion implantation.
3. The method of forming a transistor according to claim 1 or 2, wherein the ion doping process parameters are: the included angle between the implantation direction and the side wall of the grid structure is 10-45 degrees, the implantation energy is 1.0 KeV-50 KeV, and the implantation dosage is 1.0E13atm/cm 2-1.0E15 atm/cm2.
4. The method of forming a transistor of claim 1, wherein the type of dopant ions is different from the type of transistor.
5. The method of forming a transistor of claim 1, wherein the transistor is PMOS and the doped ion is phosphorus or arsenic;
or,
the transistor is NMOS, and the doped ions are boron, aluminum or gallium.
6. The method of forming a transistor of claim 1, further comprising: and after the groove is formed, forming a side wall layer covering the side wall of the groove and the side wall of the gate structure before ion doping is carried out on the fin part below the gate structure.
7. The method of claim 6, wherein the sidewall layer is SiN, siON, siBCN or SiCN.
8. The method of forming a transistor of claim 6, wherein the step of forming a sidewall layer comprises: forming a side wall material layer which conformally covers the groove and the grid structure;
and removing the side wall material layers at the top of the grid structure and the bottom of the groove to form the side wall layer.
9. The method of claim 8, wherein the sidewall material layer is formed by an atomic layer deposition process or a low pressure chemical vapor deposition process.
10. The method of forming a transistor of claim 8,
taking the direction perpendicular to the side wall of the grid structure as the transverse direction, the forming method of the transistor further comprises the following steps: after the groove is formed, before the side wall material layer is formed, the sacrificial layer with partial width on the side wall of the groove is transversely etched, and a side wall groove which is formed by the channel layer and the sacrificial layer in a surrounding mode or by the channel layer, the sacrificial layer and the fin part in a surrounding mode is formed;
in the step of forming the side wall material layer, the side wall material layer is further filled in the side wall groove to form an inner side wall layer.
11. The method of forming a transistor of claim 10, wherein in the step of forming a sidewall recess, a width of the sacrificial layer on a sidewall of the recess is 2nm to 8nm.
12. The method of claim 10, wherein a wet etching process is used to remove a portion of the sacrificial layer on the sidewall of the recess to form a sidewall recess.
13. The method of forming a transistor of claim 10, wherein the channel layer is Si, the sacrificial layer is SiGe, and the step of forming sidewall recesses comprises: and transversely etching the sacrificial layer on the side wall of the groove by adopting HCl solution.
14. A transistor, comprising:
a substrate;
a plurality of discrete fins located on the substrate;
the source-drain doping layer is separated on the fin part;
one or more channel layers which are arranged between the source-drain doping layers and are in contact with the source-drain doping layers, wherein the channel layers are suspended above the fin parts;
a metal gate structure located on the fin and surrounding the channel layer;
and doped ions are positioned at channel positions in the fin part below the metal gate structure, and the doped ions are used for improving the threshold voltage of the parasitic device.
15. The transistor of claim 14, wherein the type of dopant ions is different from the type of transistor.
16. The transistor of claim 14 wherein the transistor is PMOS and the doped ion is phosphorus or arsenic;
or,
the transistor is NMOS, and the doped ions are boron, aluminum or gallium.
17. The transistor of claim 14, wherein the material of the channel layer is silicon.
18. The transistor of claim 14, wherein the transistor further comprises: and the inner side wall layer is positioned between the metal gate structure and the source-drain doped layer.
19. The transistor of claim 18 wherein the material of the inner sidewall layer is SiN, siON, siBCN or SiCN.
20. The transistor of claim 18, wherein the width of said inner sidewall layer is between 2nm and 8nm in a direction perpendicular to the sidewalls of said metal gate structure.
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