CN111755513B - Semiconductor structure and forming method thereof - Google Patents
Semiconductor structure and forming method thereof Download PDFInfo
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- CN111755513B CN111755513B CN201910236722.XA CN201910236722A CN111755513B CN 111755513 B CN111755513 B CN 111755513B CN 201910236722 A CN201910236722 A CN 201910236722A CN 111755513 B CN111755513 B CN 111755513B
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- 238000000034 method Methods 0.000 title claims abstract description 118
- 239000004065 semiconductor Substances 0.000 title claims abstract description 96
- 239000010410 layer Substances 0.000 claims abstract description 621
- 229910052751 metal Inorganic materials 0.000 claims abstract description 364
- 239000002184 metal Substances 0.000 claims abstract description 364
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 174
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 174
- 239000000463 material Substances 0.000 claims abstract description 90
- 239000000758 substrate Substances 0.000 claims abstract description 64
- 239000011229 interlayer Substances 0.000 claims abstract description 46
- 238000009792 diffusion process Methods 0.000 claims abstract description 18
- 238000000231 atomic layer deposition Methods 0.000 claims description 12
- 229910052732 germanium Inorganic materials 0.000 claims description 10
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 8
- PEUPIGGLJVUNEU-UHFFFAOYSA-N nickel silicon Chemical compound [Si].[Ni] PEUPIGGLJVUNEU-UHFFFAOYSA-N 0.000 claims description 5
- 238000004518 low pressure chemical vapour deposition Methods 0.000 claims description 4
- 150000002736 metal compounds Chemical class 0.000 claims description 4
- UGACIEPFGXRWCH-UHFFFAOYSA-N [Si].[Ti] Chemical compound [Si].[Ti] UGACIEPFGXRWCH-UHFFFAOYSA-N 0.000 claims description 3
- 150000001875 compounds Chemical class 0.000 claims description 3
- 229910003481 amorphous carbon Inorganic materials 0.000 claims description 2
- 238000005530 etching Methods 0.000 description 31
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 28
- 150000002500 ions Chemical class 0.000 description 26
- 229910052710 silicon Inorganic materials 0.000 description 24
- 239000010703 silicon Substances 0.000 description 24
- 229910052581 Si3N4 Inorganic materials 0.000 description 14
- 230000009286 beneficial effect Effects 0.000 description 14
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 12
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 12
- 229910052814 silicon oxide Inorganic materials 0.000 description 12
- 239000004020 conductor Substances 0.000 description 8
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 8
- 229910010271 silicon carbide Inorganic materials 0.000 description 8
- 238000001039 wet etching Methods 0.000 description 8
- 230000015572 biosynthetic process Effects 0.000 description 7
- 239000003989 dielectric material Substances 0.000 description 6
- 239000011810 insulating material Substances 0.000 description 6
- 238000002513 implantation Methods 0.000 description 5
- 229910052582 BN Inorganic materials 0.000 description 4
- PZNSFCLAULLKQX-UHFFFAOYSA-N Boron nitride Chemical compound N#B PZNSFCLAULLKQX-UHFFFAOYSA-N 0.000 description 4
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 4
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 4
- 239000013078 crystal Substances 0.000 description 4
- 238000001312 dry etching Methods 0.000 description 4
- 230000005669 field effect Effects 0.000 description 4
- 229910052738 indium Inorganic materials 0.000 description 4
- 239000012212 insulator Substances 0.000 description 4
- 238000002955 isolation Methods 0.000 description 4
- 229910044991 metal oxide Inorganic materials 0.000 description 4
- 150000004706 metal oxides Chemical class 0.000 description 4
- 238000005280 amorphization Methods 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 229910018072 Al 2 O 3 Inorganic materials 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 2
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 2
- 229910004129 HfSiO Inorganic materials 0.000 description 2
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 description 2
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- 229910001080 W alloy Inorganic materials 0.000 description 2
- HMDDXIMCDZRSNE-UHFFFAOYSA-N [C].[Si] Chemical compound [C].[Si] HMDDXIMCDZRSNE-UHFFFAOYSA-N 0.000 description 2
- NTCVORQAIAUAJB-UHFFFAOYSA-N [Mg].[W] Chemical compound [Mg].[W] NTCVORQAIAUAJB-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- 229910052787 antimony Inorganic materials 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 239000000969 carrier Substances 0.000 description 2
- 230000002349 favourable effect Effects 0.000 description 2
- 229910052733 gallium Inorganic materials 0.000 description 2
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 229920000831 ionic polymer Polymers 0.000 description 2
- 230000006911 nucleation Effects 0.000 description 2
- 238000010899 nucleation Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 239000002356 single layer Substances 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- 229910021341 titanium silicide Inorganic materials 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000002699 waste material Substances 0.000 description 2
- VHUUQVKOLVNVRT-UHFFFAOYSA-N Ammonium hydroxide Chemical compound [NH4+].[OH-] VHUUQVKOLVNVRT-UHFFFAOYSA-N 0.000 description 1
- 235000011114 ammonium hydroxide Nutrition 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 230000001627 detrimental effect Effects 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
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- General Physics & Mathematics (AREA)
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Abstract
A semiconductor structure and a method for forming the same, the method for forming the same includes: providing a substrate, a gate structure positioned on the substrate, source-drain doped layers positioned in the substrate at two sides of the gate structure and an interlayer dielectric layer covering the side wall of the gate structure and the source-drain doped layers; forming an opening exposing the source-drain doping layer in the interlayer dielectric layer, wherein the bottom of the opening comprises a central area and an edge area; forming a first metal layer in the edge area, and forming a second metal layer in the central area, wherein the material diffusion capacity of the second metal layer is larger than that of the first metal layer; and processing the first metal layer and the second metal layer to form a first metal silicide layer and a second metal silicide layer respectively, wherein the resistivity of the second metal silicide layer is smaller than that of the first metal layer silicide layer. According to the invention, under the condition that the source-drain doped layer is not easy to pass through, the contact resistance between the source-drain doped layer and a contact hole plug formed subsequently is reduced, and the electrical property of the semiconductor structure is optimized.
Description
Technical Field
Embodiments of the present disclosure relate to semiconductor manufacturing, and more particularly, to a semiconductor structure and a method for forming the same.
Background
In semiconductor manufacturing, with the trend of very large scale integrated circuits, the feature size of integrated circuits is continuously reduced, and in order to adapt to smaller feature sizes, the channel length of Metal-Oxide-semiconductor field effect transistors (MOSFETs) is also continuously shortened. However, as the channel length of the device is shortened, the distance between the source and the drain of the device is also shortened, so that the control capability of the gate structure on the channel is further and further reduced, and the difficulty of pinching off (pin off) the channel by the gate voltage is further and further increased, so that the phenomenon of subthreshold leakage (subthreshold leakage), namely the so-called short-channel effect (SCE), is more likely to occur.
Accordingly, to reduce the impact of short channel effects, semiconductor processes are gradually beginning to transition from planar MOSFETs to three-dimensional transistors with higher efficiency, such as fin field effect transistors (finfets). In the FinFET, the gate structure can control the ultrathin body (fin part) from at least two sides, and compared with a planar MOSFET, the gate structure has stronger control capability on a channel and can well inhibit short channel effect; and finfets have better compatibility with existing integrated circuit fabrication than other devices.
Disclosure of Invention
The problem to be solved by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same, which are used for optimizing the performance of the semiconductor structure.
In order to solve the above problems, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate, wherein the substrate comprises a substrate, a gate structure positioned on the substrate, source-drain doped layers positioned in the substrate at two sides of the gate structure and an interlayer dielectric layer covering the side wall of the gate structure and the source-drain doped layers, and the interlayer dielectric layer exposes the top wall of the gate structure; forming an opening exposing the source-drain doped layer in the interlayer dielectric layer, wherein the bottom of the opening comprises a central area and an edge area surrounding the central area; forming a first metal layer at the bottom of the opening; removing the first metal layer in the central area of the bottom of the opening to form an opening; forming a second metal layer in the opening, wherein the material diffusion capacity of the second metal layer is larger than that of the first metal layer, and the resistivity of the second metal layer corresponding to silicide is smaller than that of the first metal layer corresponding to silicide; processing the first metal layer and the second metal layer to form a metal silicide layer, wherein the first metal layer and the second metal layer correspond to the first metal silicide layer and the second metal silicide layer respectively; after forming the metal silicide layer, forming a contact hole plug in the opening.
Optionally, the material of the first metal layer includes: ti.
Optionally, the thickness of the first metal layer is 2 nm to 8 nm.
Optionally, an atomic layer deposition or a low-pressure chemical vapor deposition process is adopted to form the first metal layer at the bottom of the opening.
Optionally, the width of the second metal layer is 10 nm to 20 nm in a direction perpendicular to the sidewall of the gate structure.
Optionally, the material of the second metal layer includes: ni.
Optionally, the thickness of the second metal layer is 2 nm to 8 nm.
Optionally, the second metal layer is formed in the opening by atomic layer deposition or low pressure chemical vapor deposition.
Optionally, the step of forming the opening includes: forming a sacrificial layer on the side wall of the opening; removing the first metal layer exposed by the sacrificial layer by taking the sacrificial layer as a mask to form the opening surrounded by the first metal layer and the source-drain doping layer; the method for forming the semiconductor structure further comprises the following steps: removing the sacrificial layer after forming the opening and before forming the second metal layer; or after the metal silicide layer is formed, removing the sacrificial layer.
Optionally, the material of the sacrificial layer includes: low-K material, metal compound, al compound, amorphous carbon, and amorphous germanium.
Optionally, in a direction perpendicular to the sidewall of the gate structure, a ratio of the length of the first metal layer to the length of the second metal layer is 2 to 3.
Optionally, a self-aligned metal silicide process is used to process the first metal layer and the second metal layer to form the first metal silicide layer and the second metal silicide layer respectively.
Optionally, the substrate is a substrate with a fin portion; the gate structure spans the fin and covers part of the top wall and the side wall of the fin; the source-drain doped layer is located in the fin portions at two sides of the gate structure.
Correspondingly, the embodiment of the invention also provides a semiconductor structure, which comprises: a substrate, a gate structure located on the substrate; the source-drain doping layers are positioned in the substrate at two sides of the grid structure; the interlayer dielectric layer covers the gate structure and the source-drain doping layer, and the top surface of the gate structure is exposed; the contact hole plug penetrates through the interlayer dielectric layer and is used for being electrically connected with the source-drain doped layer, and the contact hole plug comprises a central area and an edge area surrounding the central area; the metal silicide layer is positioned between the source-drain doping layer and the contact hole plug and comprises a first metal silicide layer and a second metal silicide layer; the first metal silicide layer is positioned between the source-drain doping layer and the edge area of the contact hole plug; the second metal silicide layer is positioned between the source-drain doping layer and the central area of the contact hole plug; the resistance value of the second metal silicide layer is lower than that of the first metal silicide layer, and the material diffusion capacity of the second metal silicide layer corresponding to the metal is larger than that of the first metal silicide corresponding to the metal.
Optionally, the first metal silicide layer includes: titanium silicon compound.
Optionally, the thickness of the first metal silicide layer is 2 nm to 16 nm.
Optionally, the second metal silicide layer includes: nickel silicon compound.
Optionally, the thickness of the second metal silicide layer is 2 nm to 16 nm.
Optionally, in a direction perpendicular to the sidewall of the gate structure, a ratio of the length of the first metal silicide layer to the length of the second metal silicide layer is 2 to 3.
Optionally, the width of the second metal silicide layer is 10 nm to 20 nm in a direction perpendicular to the sidewall of the gate structure.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following advantages:
the bottom of the opening comprises a central area and an edge area surrounding the central area, wherein the edge area is closer to a channel area below the grid structure than the central area; forming a first metal layer at the bottom of the opening; removing the first metal layer in the central area of the bottom of the opening to form an opening; a second metal layer is formed in the opening. The material diffusion capacity of the second metal layer is larger than that of the first metal layer, and compared with the situation that the second metal layer is singly used for forming the metal silicide layer, the material of the second metal layer in the central area is not easy to diffuse into a channel region below the grid structure in the process that the second metal layer is used for forming the second metal silicide layer, so that the source-drain doped layer is not easy to pass through, and the grid structure is easier to control a channel. The second metal silicide layer has a resistivity less than that of the first metal silicide layer and a lower resistance than that of the first metal silicide layer alone. In summary, the second metal silicide layer is formed in the central area of the bottom of the opening, and the first metal silicide layer is formed in the edge area, so that the contact resistance of the contact hole plug and the source-drain doped layer is reduced and the electrical performance of the semiconductor structure is optimized under the condition that the source-drain doped layer is not easy to pass through.
Drawings
FIG. 1 is a schematic diagram of a semiconductor structure;
fig. 2 to 10 are schematic structural views corresponding to steps in another embodiment of a method for forming a semiconductor structure according to the present invention.
Detailed Description
As can be seen from the background art, the semiconductor structure formed at present still has the problem of poor performance. The reason for the poor performance of the semiconductor structure is analyzed by combining a semiconductor structure.
Referring to fig. 1, a schematic structural diagram of a semiconductor structure is shown.
Referring to fig. 1, the semiconductor structure includes: a substrate 1; a fin 2 located on the substrate 1; a gate structure 3 straddling the fin 2, wherein the gate structure 3 covers partial top wall and side wall of the fin 2; the source-drain doped layer 4 is positioned in the fin part 2 at two sides of the grid structure 3; the metal silicide 5 is positioned on the source-drain doped layer 4; an interlayer dielectric layer (not shown) covering the gate structure 3 and the source-drain doped layer 4, and exposing the top surface of the gate structure 3; a contact hole plug 6, which is located on the metal silicide 5 and contacts with the metal silicide 5, wherein the top surface of the contact hole plug 6 is higher than the top surface of the interlayer dielectric layer; and the dielectric layer 7 is positioned on the interlayer dielectric layer and covers the side wall of the contact hole plug 6, and the top surface of the contact hole plug 6 is exposed.
The metal silicide layer 5 is used for reducing the contact resistance between the source-drain doped layer 4 and the contact hole plug 6. If the material of the metal silicide layer 5 is a nickel-silicon compound, during the formation of the nickel-silicon compound, the metal nickel is easy to diffuse into the channel region below the gate structure 3, and the source-drain doped layers 4 on both sides of the gate structure 3 are penetrated during the operation of the semiconductor structure, so that the gate structure 3 cannot control the channel well, and the electrical performance of the semiconductor structure is not high. If the material of the metal silicide layer 5 is titanium silicide, the resistivity of the titanium silicide is high, and the contact resistance between the source-drain doped layer 4 and the contact hole plug 6 cannot be well reduced, so that the electrical performance of the semiconductor structure is poor.
In order to solve the technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate, wherein the substrate comprises a substrate, a gate structure positioned on the substrate, source-drain doped layers positioned in the substrate at two sides of the gate structure and an interlayer dielectric layer covering the side wall of the gate structure and the source-drain doped layers, and the interlayer dielectric layer exposes the top wall of the gate structure; forming an opening exposing the source-drain doped layer in the interlayer dielectric layer, wherein the bottom of the opening comprises a central area and an edge area surrounding the central area; forming a first metal layer at the bottom of the opening; removing the first metal layer in the central area of the bottom of the opening to form an opening; forming a second metal layer in the opening, wherein the material diffusion capacity of the second metal layer is larger than that of the first metal layer, and the resistivity of the second metal layer corresponding to silicide is smaller than that of the first metal layer corresponding to silicide; processing the first metal layer and the second metal layer to form a metal silicide layer, wherein the first metal layer and the second metal layer correspond to the first metal silicide layer and the second metal silicide layer respectively; after forming the metal silicide layer, forming a contact hole plug in the opening.
The bottom of the opening comprises a central area and an edge area surrounding the central area, wherein the edge area is closer to a channel area below the grid structure than the central area; forming a first metal layer at the bottom of the opening; removing the first metal layer in the central area of the bottom of the opening to form an opening; a second metal layer is formed in the opening. The material diffusion capacity of the second metal layer is larger than that of the first metal layer, and compared with the situation that the second metal layer is singly used for forming the metal silicide layer, the material of the second metal layer in the central area is not easy to diffuse into a channel region below the grid structure in the process that the second metal layer is used for forming the second metal silicide layer, so that the source-drain doped layer is not easy to pass through, and the grid structure is easier to control a channel. The second metal silicide layer has a resistivity less than that of the first metal silicide layer and a lower resistance than that of the first metal silicide layer alone. In summary, the second metal silicide layer is formed in the central area of the bottom of the opening, and the first metal silicide layer is formed in the edge area, so that the contact resistance of the contact hole plug and the source-drain doped layer is reduced and the electrical performance of the semiconductor structure is optimized under the condition that the source-drain doped layer is not easy to pass through.
In order to make the above objects, features and advantages of the embodiments of the present invention more comprehensible, a detailed description of specific embodiments of the present invention is provided below with reference to the accompanying drawings.
Fig. 2 to 10 are schematic structural views corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention.
Referring to fig. 2, a base is provided, the base includes a substrate 100, a gate structure 103 located on the substrate 100, source-drain doped layers 104 located in the substrate 100 at two sides of the gate structure 103, and an interlayer dielectric layer 105 covering sidewalls of the gate structure 103 and the source-drain doped layers 104, and the interlayer dielectric layer 105 exposes a top wall of the gate structure 103.
The substrate 100 provides a process basis for the subsequent formation of semiconductor structures.
In this embodiment, the semiconductor structure is a fin field effect transistor (FinFET), and the substrate 100 is a substrate 100 having a fin 100 a. In other embodiments, the semiconductor structure formed may also be a planar structure, and correspondingly, the substrate is a planar substrate.
In this embodiment, the material of the substrate 100 is silicon. In other embodiments, the material of the substrate may also be germanium, silicon carbide, gallium arsenide, or indium gallium, and the substrate may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate. The substrate 100 may also have an interface layer formed on the surface thereof, and the interface layer may be made of silicon oxide, silicon nitride, silicon oxynitride, or the like.
The gate structure 103 spans across the fin 100a and covers portions of the top and side walls of the fin 100 a. The gate structure 103 is used to control the opening and closing of the channel when the semiconductor structure is in operation.
In this embodiment, the gate structure 103 is a metal gate structure.
In this embodiment, the gate structure 103 is a stacked structure, and includes a gate dielectric layer 1031 conformally covering a portion of the top surface and a portion of the sidewall of the fin portion 100a, and a gate layer 1032 on the gate dielectric layer 1031. In other embodiments, the gate structure may also be a single layer structure, i.e., the gate structure includes only a gate layer.
The gate dielectric layer 1031 is made of a high-k dielectric layer, and the material of the high-k dielectric layer is a dielectric material with a relative dielectric constant greater than that of silicon oxide. In this embodiment, the gate dielectric layer 1031 is made of HfO 2 . In other embodiments, the material of the gate dielectric layer may also be selected from ZrO 2 HfSiO, hfSiON, hfTaO, hfTiO, hfZrO or Al 2 O 3 One or more of them.
The gate layer 1032 serves as an electrode for making electrical connection with an external circuit. In this embodiment, the material of the gate layer 1032 is magnesium-tungsten alloy. In other embodiments, the material of the gate layer may also be W, al, cu, ag, au, pt, ni or Ti.
In other embodiments, the gate structure may also be a polysilicon gate structure. Correspondingly, the gate structure comprises a gate oxide layer and a gate layer positioned on the gate oxide layer.
The substrate further comprises a side wall layer 108, the side wall 108 is used for protecting the side wall of the gate structure 103 in the process of removing the interlayer dielectric layer 105 on the source-drain doped layer 104 by subsequent etching, and the side wall 108 is also used for defining the position of the source-drain doped layer 104.
The source-drain doped layer 104 is located in the fin portion 100a at two sides of the gate structure 103. The source-drain doped layer 104 provides stress for a channel under the gate structure 103 when the semiconductor structure works, so as to improve the mobility of carriers.
In this embodiment, the semiconductor structure is used to form the PMOS (Positive Channel Metal Oxide Semiconductor) transistor, i.e., the material of the source/drain doped layer 104 is P-type ion doped silicon germanium. In this embodiment, by doping P-type ions in silicon germanium, the P-type ions replace the positions of silicon atoms in the crystal lattice, and the more P-type ions are doped, the higher the concentration of the polynomials is, and the stronger the conductivity is. Specifically, the P-type ions include B, ga or In.
In other embodiments, the semiconductor structure is used to form NMOS (Negative channel Metal Oxide Semiconductor) transistors, i.e., the material of the source-drain doped layer is silicon carbide or silicon phosphide doped with N-type ions, respectively. By doping N-type ions in silicon carbide or silicon phosphide, the N-type ions replace the positions of silicon atoms in a crystal lattice, the more N-type ions are doped, the higher the concentration of the polyions is, and the higher the conductivity is. Specifically, the N-type ions include P, as or Sb.
It should be noted that the substrate further includes: an etch stop layer (Contact Etch Stop Layer, CESL) (not shown) is located on the source drain doped layer 104. The etching stop layer is used for defining the etching stop position of the etching process in the subsequent process of etching the interlayer dielectric layer 105 to form an opening, so that the probability of over-etching the source-drain doped layer 104 by the etching process is reduced while the opening is ensured to be formed by etching.
The material of the etching stop layer adopts a material with low K dielectric constant.
The material of the etching stop layer comprises one or more of silicon nitride, silicon oxynitride, silicon carbide, silicon nitride carbide, boron nitride silicon and boron nitride carbon silicon. In this embodiment, the material of the etching stop layer is silicon nitride.
An amorphous region is formed in the top of the source-drain doped layer 104, and the amorphous region is formed by using a pre-amorphization implantation (PAI) process. The PAI process includes ion implantation using ions selected from silicon, germanium, or a combination thereof to amorphize the top of the source drain doped layer 104, although amorphous silicidation implantation processes are known to slow down the stress hysteresis reaction (stress-retarded reaction) and increase the nucleation density such that the subsequently formed first and second metal layers on top of the source drain doped layer are processed to form more uniform and thicker first and second metal silicide layers. The ions are selected without changing the conductivity of the source-drain doped layer 104.
Specific implanted ions include: one or both of Ge and Si.
The interlayer dielectric layer 105 is used to achieve electrical isolation between adjacent semiconductor structures, and thus, the material of the interlayer dielectric layer 105 is an insulating material.
The interlayer dielectric layer 105 exposes the top wall of the gate structure 103.
Specifically, the material of the interlayer dielectric layer 105 is silicon oxide. Silicon oxide is a dielectric material with common process and low cost, has high process compatibility, is beneficial to reducing the process difficulty and the process cost for forming the interlayer dielectric layer 105, and has simple removal process. In other embodiments, the material of the interlayer dielectric layer may be one or more of silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride and silicon oxycarbonitride.
It should be noted that the substrate further includes: a dielectric layer 106 is located on the interlayer dielectric layer 105. The dielectric layer 106 and the interlayer dielectric layer 105 provide a process basis for the subsequent formation of contact plugs connected to the source/drain doped layer 104.
The dielectric layer 106 is used for realizing electrical isolation between adjacent devices, and the material of the dielectric layer 106 is an insulating material.
In this embodiment, the material of the dielectric layer 106 is silicon oxide. Silicon oxide is a dielectric material with common process and low cost, has high process compatibility, is beneficial to reducing the process difficulty and the process cost for forming the dielectric layer 106, and has simple removal process. In other embodiments, the material of the dielectric layer may be another insulating material such as silicon nitride or silicon oxynitride.
Referring to fig. 3, an opening 107 exposing the source-drain doped layer 104 is formed in the interlayer dielectric layer 105, and the bottom of the opening 107 includes a central region and an edge region surrounding the central region.
The central region is further from the channel region than the edge regions. The subsequent center region is used to form a second metal silicide layer and the edge region is used to form a first metal silicide layer.
The openings 107 provide a spatial location for subsequent contact plug formation.
The step of forming the opening 107 includes: forming an open mask layer (not shown) on the dielectric layer 106; and removing the interlayer dielectric layer 105 and the dielectric layer 106 on the source-drain doped layer 104 by taking the opening mask layer as a mask to form an opening 107 exposing the source-drain doped layer 104.
In this embodiment, a dry etching process is used to remove the interlayer dielectric layer 105 and the dielectric layer 106 on the source-drain doped layer 104, so as to form an opening 107. The dry etching process is an anisotropic etching process, has good etching profile control, reduces damage to other film structures, is favorable for enabling the morphology of the opening 107 to meet the process requirements, and is also favorable for improving the removal efficiency of the interlayer dielectric layer 105 and the dielectric layer 106.
It should be noted that, in the process of etching the interlayer dielectric layer 105, the etching stop layer defines the position where the etching process is stopped, so that the probability of over-etching the source/drain doped layer 104 caused by the etching process is reduced while the opening 107 is formed by etching is ensured.
Specifically, the opening 107 penetrates the dielectric layer 106, the interlayer dielectric layer 105, and the etching stop layer.
Note that the pre-amorphization implantation (PAI) process may also be performed after the formation of the opening 107.
Referring to fig. 4, a first metal layer 109 is formed at the bottom of the opening 107.
The first metal layer 109 provides for the subsequent formation of a first metal silicide layer. The first metal silicide layer is used for reducing the contact resistance between the source-drain doped layer 104 and a contact hole plug formed later.
In this embodiment, the materials of the first metal layer 109 include: ti.
In this embodiment, the first metal layer 109 is formed using an atomic layer deposition process (Atomic Layer Deposition, ALD). The atomic layer deposition process has a better conformal coverage capability, which is beneficial to ensuring that the first metal layer 109 can be conformally covered on the bottom surface and the side wall of the opening 107 in the step of forming the first metal layer 109, and is beneficial to improving the thickness uniformity of the first metal layer 109 by adopting the atomic layer deposition process. In other embodiments, the first metal layer may also be formed using a chemical vapor deposition process (chemical vapor deposition, CVD).
The first metal layer 109 is preferably not too thick or too thin. If the first metal layer 109 is too thick, the process time for forming the first metal layer 109 is too long, and the first metal 109 that is not reacted to form the first metal silicide is removed in the subsequent process, which results in resource waste. If the first metal layer 109 is too thin, the thickness of the first metal silicide layer formed by the self-aligned metal silicide process (self-alignment silicide processes) is too thin, so that the contact resistance cannot be reduced, and the electrical performance of the semiconductor structure is poor. In this embodiment, the thickness of the first metal layer 109 is 2 nm to 8 nm.
Referring to fig. 5 to 7, the first metal layer 109 is removed from the bottom central region of the opening 107, thereby forming an opening 101.
The openings 101 provide for the subsequent formation of a second metal layer material having a greater diffusivity than the first metal layer material.
In this embodiment, the width of the opening 101 is not too large or too small in the direction perpendicular to the sidewall of the gate structure 103. If the width of the opening 101 is too small, the width of the second metal layer formed in the direction perpendicular to the sidewall of the gate structure 103 is too small, which is not beneficial to reducing the resistance of the contact plug and the source-drain doped layer formed in the subsequent process. If the width of the opening 101 is too large, the width of the second metal layer formed in the direction perpendicular to the sidewall of the gate structure 103 is too large, because the diffusion capability of the second metal layer material is greater than that of the first metal layer material, if the width of the second metal layer is too large, the second metal layer material is easy to diffuse into the channel in the process of forming the second metal silicide layer by processing the second metal layer, so that the source-drain doped layer 104 is easy to pass through, and the performance of the semiconductor structure is poor. In this embodiment, the width of the opening 101 is 10 nm to 20 nm, perpendicular to the sidewall direction of the gate structure 103.
Note that, for the source-drain doped layer 104 at both ends of the fin portion 100a in the extending direction, only one end is close to the channel region, and the opening 101 exposes a portion of the source-drain doped layer 104 away from the channel region. The openings 101 expose portions of the source-drain doped layer 104 away from the channel region so that more area can be used to form a second metal layer in a subsequent process. In other embodiments, the openings may expose only the source-drain doped layer in the central region.
The step of forming the opening 101 includes:
as shown in fig. 5 and 6, a sacrificial layer 111 (shown in fig. 6) is formed on the sidewalls of the opening 107. The sacrificial layer 111 exposes the central region in preparation for subsequent etching of the first metal layer 109 to form openings using the sacrificial layer 111 as a mask.
The materials of the sacrificial layer 111 and the first metal layer 109 and the source-drain doped layer 104 are different, so that the sacrificial layer 111, the first metal layer 109 and the source-drain doped layer 104 have an etching selectivity ratio, and in the subsequent process of removing the sacrificial layer 111, the etched rate of the first metal layer 109 and the source-drain doped layer 104 is small.
Specifically, the material of the sacrificial layer 111 is one or more of low-K material, metal compound, al oxide, ti compound and amorphous germanium. In this embodiment, the material of the sacrificial layer 111 is amorphous germanium.
The step of forming the sacrificial layer 111 includes: forming a sacrificial material layer 113 conformally covering the first metal layer 109 (as shown in fig. 5); the sacrificial material layer 113 on the source drain doped layer 104 and on the dielectric layer 106 is removed, forming a sacrificial layer 111 on the sidewalls of the opening 107.
In this embodiment, a maskless etching process is used to remove the sacrificial material layer 113 on the source-drain doped layer 104 and the dielectric layer 106, so that a Mask is not required in the step of forming the sacrificial layer 111, and the process cost is reduced.
As shown in fig. 7, the first metal layer 109 exposed by the sacrificial layer 111 is removed by using the sacrificial layer 111 as a mask, so as to form an opening 101 surrounded by the first metal layer 109 and the source/drain doped layer 104.
In this embodiment, the first metal layer 109 exposed by the sacrificial layer 111 is removed by a dry etching process.
Specifically, the dry etching process has the characteristic of anisotropic etching, which is beneficial to ensuring that the damage to other film structures is small while the sacrificial material layer 113 on the source-drain doped layer 104 and the dielectric layer 106 is completely removed, and the first metal layer 109 is not easy to be laterally etched, so that the first metal layer 109 is not easy to be too short in the direction perpendicular to the side wall of the gate structure 103, and further the second metal layer is not easy to be too long in the direction perpendicular to the side wall of the gate structure 103, so that the material in the second metal layer is not easy to diffuse into the channel region in the subsequent process of performing the self-aligned metal silicide process, and the source-drain doped layer 104 is not easy to pass through, thereby optimizing the electrical performance of the semiconductor structure.
In other embodiments, a wet etching process may be further used to remove the first metal layer exposed by the sacrificial layer. The wet etching process has higher etching rate, simple operation and low process cost.
Specifically, the opening 101 is surrounded by the first metal layer 109, the etching stop layer, and the source-drain doped layer 104.
Referring to fig. 8, a second metal layer 110 is formed in the opening 101, wherein a material diffusion capability of the second metal layer 110 is greater than a material diffusion capability of the first metal layer 109, and a resistivity of the second metal layer 110 corresponding to silicide is less than a resistivity of the first metal layer 109 corresponding to silicide.
The bottom of the opening 107 in this embodiment of the present invention includes a central region, and an edge region surrounding the central region, the edge region being closer to the channel region under the gate structure 103 than the central region; forming a first metal layer 109 at the bottom of the opening 107; removing the first metal layer 109 in the bottom central area of the opening 107 to form an opening 112; a second metal layer 110 is formed in the opening 112. The material diffusion capability of the second metal layer 110 is greater than that of the first metal layer 109, and compared with the case where the metal silicide layer is formed by using the second metal layer 110 alone, the material of the second metal layer 110 located in the central region is not easy to diffuse into the channel region under the gate structure 103 during the process of forming the second metal silicide layer by using the second metal layer 110, so that the source-drain doped layer 104 is not easy to pass through, and the gate structure 103 is easier to control the channel. The second metal silicide layer has a resistivity less than that of the first metal silicide layer and a lower resistance than that of the first metal silicide layer formed by the reaction of only the first metal layer 109. In summary, the second metal silicide layer is formed in the bottom central area of the opening 107, and the first metal silicide layer is formed in the edge area, so that the contact resistance between the contact hole plug and the source/drain doped layer 104 is reduced and the electrical performance of the semiconductor structure is optimized under the condition that the source/drain doped layer 104 is not easy to pass through.
In this embodiment, the materials of the second metal layer 110 include: ni.
The second metal layer 110 is not too thick or too thin. If the second metal layer 110 is too thick, the process time for forming the second metal layer 110 is too long, and the second metal 109 that is not reacted to form the second metal silicide is removed in the subsequent process, which results in resource waste. If the second metal layer 110 is too thin, the thickness of the first metal silicide layer formed by the self-aligned metal silicide process is too thin, which makes the electrical performance of the semiconductor structure poor. In this embodiment, the thickness of the second metal layer 110 is 2 nm to 8 nm.
In this embodiment, the second metal layer 110 is formed by an atomic layer deposition process. The atomic layer deposition process has a better conformal coverage capability, which is beneficial to ensuring that the second metal layer 110 can be conformally covered on the bottom surface and the side wall of the opening 107 in the step of forming the second metal layer 110, and is beneficial to improving the thickness uniformity of the second metal layer 110 by adopting the atomic layer deposition process. In other embodiments, the second metal layer may also be formed using a chemical vapor deposition process.
In this embodiment, the width of the opening 101 is 10 nm to 20 nm, perpendicular to the sidewall direction of the gate structure 103. Accordingly, the width of the second metal layer 110 perpendicular to the sidewall direction of the gate structure 103 is 10 nm to 20 nm.
It should be noted that, in the direction perpendicular to the sidewall of the gate structure 103, the length ratio of the first metal layer 109 to the second metal layer 110 should not be too large or too small. The first metal layer 109 and the second metal layer 110 are processed to form a metal silicide layer, where the metal silicide layer includes a first metal silicide layer and a second metal silicide layer, and the resistance value of the second metal silicide layer is lower than that of the first metal silicide layer, and if the ratio is too large, that is, the second metal layer 110 is too short, the second metal silicide layer formed subsequently is too short, which correspondingly results in too large resistance between the source-drain doped layer 104 and the contact hole plug formed subsequently, which is not beneficial to reducing the contact resistance between the source-drain doped layer 104 and the contact hole plug formed subsequently, and is not beneficial to optimizing the electrical performance of the semiconductor structure. If the ratio is too small, that is, the length of the second metal layer 110 is too long, the second metal layer 110 is too close to the channel region, which may cause the material in the second metal layer 110 to be easily diffused into the channel region during the subsequent self-aligned process, which may easily cause the punch-through of the source/drain doped layer 104. In this embodiment, the ratio of the lengths of the first metal layer 109 and the second metal layer 110 is 2 to 3 in the direction perpendicular to the sidewall of the gate structure 103.
In this embodiment, after forming the opening 101, the sacrificial layer 111 is removed; after the sacrificial layer 111 is removed, a second metal layer 110 is formed in the opening 101.
In this embodiment, a wet etching process is used to remove the sacrificial layer 111. The wet etching process has higher etching rate, simple operation and low process cost.
Specifically, the wet etching solution is a hot HCl solution.
In other embodiments, the method for forming the semiconductor structure may further be: and the second metal layer conformally covers the dielectric layer, the sacrificial layer and the source-drain doping layer exposed by the sacrificial layer, and the sacrificial layer is removed after the metal silicide layer is formed subsequently.
Referring to fig. 9, the first metal layer 109 and the second metal layer 110 are processed to form a metal silicide layer 114, and the first metal layer 109 and the second metal layer 110 correspond to the first metal silicide layer 1141 and the second metal silicide layer 1142, respectively.
The metal silicide layer 114 is used to reduce the contact resistance between the subsequently formed contact plug and the source drain doped layer 104.
In this embodiment, the first metal layer 109 and the second metal layer 110 are processed by a salicide process to form the first metal silicide layer 1141 and the second metal silicide layer 1142, respectively.
The first metal layer 109 and the second metal layer 110 are further formed on the sidewalls of the gate structure 103 and the dielectric layer 106, and the method for forming the semiconductor structure further includes: after forming the metal silicide layer 114, the first metal layer 109 and the second metal layer 110 that are not reacted with the source drain doped layer 104 are removed. In other embodiments, because the first metal layer is TI, TI is a material with weak diffusion capability, the first metal layer may also be retained, and the first metal layer is used to prevent the material subsequently formed on the first metal layer from diffusing into the gate structure and the source-drain doped layer, which is detrimental to the electrical performance of the semiconductor structure.
In this embodiment, a wet etching process is used to remove the first metal layer 109 and the second metal layer 110 that do not react with the source/drain doped layer 104. The wet etching process has higher etching rate, simple operation and low process cost.
Specifically, the wet etching solution is a mixture of ammonia water and hydrogen peroxide.
As shown in fig. 10, a contact hole plug 115 is formed in the opening 107 (shown in fig. 3).
The contact hole plugs 115 are used to make electrical connection between the semiconductor structure and the semiconductor structure in addition to making electrical connection within the semiconductor structure.
In this embodiment, the conductive material is W. In other embodiments, the material of the conductive material may also be Al, cu, ag, au, or the like.
The step of forming the contact hole plugs 115 includes: and filling conductive material into the opening 107, removing the conductive material higher than the conductive material in the opening 107, and taking the conductive material in the opening 107 as a contact hole plug 115.
Correspondingly, the embodiment of the invention also provides a semiconductor structure. Referring to fig. 10, a schematic structure diagram of an embodiment of the semiconductor structure of the present invention is shown.
The semiconductor structure includes: a substrate 100, a gate structure 103, located on the substrate 100; source-drain doped layers 104 located in the substrate 100 at two sides of the gate structure 103; an interlayer dielectric layer 105 covering the gate structure 103 and the source-drain doped layer 104, wherein the interlayer dielectric layer 105 exposes the top surface of the gate structure 103; a contact hole plug 115 penetrating the interlayer dielectric layer 105 and electrically connected to the source/drain doped layer 104, wherein the contact hole plug 115 includes a central region and an edge region surrounding the central region; a metal silicide layer 114 located between the source-drain doped layer 104 and the contact hole plug 115, wherein the metal silicide layer 114 includes a first metal silicide layer 1141 and a second metal silicide layer 1142; the first metal silicide layer 1141 is located between the source-drain doped layer 104 and the edge region of the contact hole plug 115; the second metal silicide layer 1142 is located between the source-drain doped layer 104 and the central region of the contact hole plug 115; the resistance value of the second metal silicide layer 1142 is lower than the resistance value of the first metal silicide layer 1141, and the material diffusion capability of the second metal silicide corresponding to the metal is greater than the material diffusion capability of the first metal silicide layer 1141 corresponding to the metal.
The contact plug 115 of the present embodiment includes a central region, and an edge region surrounding the central region, the edge region being closer to a channel region under the gate structure 103 than the central region; the first metal silicide layer 1141 is formed by a first metal layer treatment, and the second metal silicide layer 1142 is formed by a second metal layer treatment. The material diffusion capability of the second metal layer is greater than that of the first metal layer, and compared with the case where the metal silicide layer is the second metal silicide layer 1142, in this embodiment, the second metal layer material that diffuses into the channel region under the gate structure 103 is less, so that the source-drain doped layer 104 is not easy to pass through, and the gate structure 103 is easier to control the channel. The second metal silicide layer 1142 has a resistivity smaller than that of the first metal silicide layer 1141, and has a lower resistance than that of the case where only the first metal silicide layer 1141 is used. In summary, the second metal silicide layer 1142 is located in the central region, and the first metal silicide layer 1141 is located in the edge region, so that the contact resistance between the contact hole plug and the 115 source/drain doped layer 104 is reduced and the electrical performance of the semiconductor structure is optimized under the condition that the source/drain doped layer 104 is not easy to pass through.
In this embodiment, the first metal silicide layer 1141 includes: titanium silicon compound.
It should be noted that the first metal silicide layer 1141 is not too thick or too thin. If the first metal silicide layer 1141 is too thick, the semiconductor structure may work, which may cause the source-drain doped layer 104 to not provide enough stress for the channel, and the performance of the semiconductor structure may be poor. If the first metal silicide layer 1141 is too thin, it cannot function to reduce the contact resistance, so that the electrical performance of the semiconductor structure is poor. In this embodiment, the thickness of the first metal silicide layer 1141 is 2 nm to 16 nm.
In this embodiment, the second metal silicide layer 1142 includes: nickel silicon compound.
It should be noted that the second metal silicide layer 1142 is not too thick or too thin. If the second metal silicide layer 1142 is too thick, the semiconductor structure may work, which may cause the source-drain doped layer 104 to not provide enough stress for the channel, and the performance of the semiconductor structure may be poor. If the second metal silicide layer 1142 is too thin, it cannot function to reduce the contact resistance, so that the electrical performance of the semiconductor structure is poor. In this embodiment, the thickness of the second metal silicide layer 1142 is 2 nm to 16 nm.
It should be noted that, in the direction perpendicular to the sidewall of the gate structure 103, the width of the second metal silicide layer 1142 is not too large or too small. If the width of the second metal silicide layer 1142 is too small, the width of the second metal silicide layer 1142 in the direction perpendicular to the sidewall of the gate structure 103 is too small, which is disadvantageous for reducing the resistance of the contact plug 115 and the source/drain doped layer 104. If the width of the second metal silicide layer 1142 is too large, the diffusion capability of the second metal layer material corresponding to the second metal silicide layer 1142 is greater than the diffusion capability of the first metal layer material corresponding to the first metal silicide layer 1141, and if the width of the second metal layer is too large, the second metal layer material is easy to diffuse into the channel during the process of forming the second metal silicide layer 1142 by processing the second metal layer, which results in easy punch-through of the source-drain doped layer 104 and poor performance of the semiconductor structure. In this embodiment, the width of the second metal silicide layer 1142 is 10 nm to 20 nm in the direction perpendicular to the sidewall of the gate structure 103.
It should be noted that, in the direction perpendicular to the sidewall of the gate structure 103, the length ratio of the first metal silicide layer 1141 and the second metal silicide layer 1142 should not be too large or too small. The resistance of the second metal silicide layer 1142 is lower than that of the first metal silicide layer 1141, and if the ratio is too large, that is, the second metal silicide layer 1142 is too short, it is not beneficial to reduce the contact resistance between the contact hole plug 115 and the source-drain doped layer 104, and is not beneficial to optimize the electrical performance of the semiconductor structure. The second metal silicide layer 1142 is formed by processing the second metal layer, and if the ratio is too small, that is, the length of the second metal silicide layer 1142 is too long, the second metal silicide layer 1142 is too close to the channel region, which may cause the second metal layer 1142 to be easily diffused into the channel region during the process of forming the second metal silicide layer 1142, which may easily cause the punch-through of the source/drain doped layer 104. In this embodiment, the ratio of the length of the first metal silicide layer 1141 to the length of the second metal silicide layer 1142 is 2 to 3 in the direction perpendicular to the sidewall of the gate structure 103.
Note that, for the source-drain doped layer 104 at both ends of the fin portion 100a in the extending direction, only one end is close to the channel region, so that the first metal silicide layer 1141 is only located on a partial area of the source-drain doped layer 104 close to the channel region, and the second metal silicide layer 1142 is formed on the remaining source-drain doped layer 104. The second metal silicide layer 1142 formed on the source/drain doped layer 104 away from the channel region may reduce the contact resistance of the source/drain doped layer 104 and the contact hole plug 115. In other embodiments, for the source-drain doped layers at two ends of the fin extension direction, a second metal silicide layer may be formed on the source-drain doped layer in the central region, and a first metal silicide layer may be formed on the source-drain doped layer in the edge region.
The substrate 100 provides a process basis for forming semiconductor structures.
In this embodiment, the semiconductor structure is exemplified by a fin field effect transistor (FinFET), and the substrate 100 is a substrate 100 having a fin 100 a. In other embodiments, the semiconductor structure may also be a planar structure, and correspondingly, the substrate is a planar substrate.
In this embodiment, the material of the substrate 100 is silicon. In other embodiments, the material of the substrate may also be germanium, silicon carbide, gallium arsenide, or indium gallium, and the substrate may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate. The substrate 100 may also have an interface layer formed on the surface thereof, and the interface layer may be made of silicon oxide, silicon nitride, silicon oxynitride, or the like.
The gate structure 103 spans across the fin 100a and covers portions of the top and side walls of the fin 100 a. The gate structure 103 is used to control the opening and closing of the channel when the semiconductor structure is in operation.
In this embodiment, the gate structure 103 is a metal gate structure.
In this embodiment, the gate structure 103 is a stacked structure, and includes a gate dielectric layer 1031 conformally covering a portion of the top surface and a portion of the sidewall of the fin portion 100a, and a gate layer 1032 on the gate dielectric layer 1031. In other embodiments, the gate structure may also be a single layer structure, i.e., the gate structure includes only a gate layer.
The gate dielectric layer 1031 is made of a high-k dielectric layer, and the material of the high-k dielectric layer is a dielectric material with a relative dielectric constant greater than that of silicon oxide. In this embodiment, the gate dielectricThe material of layer 1031 is HfO 2 . In other embodiments, the material of the gate dielectric layer may also be selected from ZrO 2 HfSiO, hfSiON, hfTaO, hfTiO, hfZrO or Al 2 O 3 One or more of them.
The gate layer 1032 serves as an electrode for making electrical connection with an external circuit. In this embodiment, the material of the gate layer 1032 is magnesium-tungsten alloy. In other embodiments, the material of the gate layer may also be W, al, cu, ag, au, pt, ni or Ti.
In other embodiments, the gate structure may also be a polysilicon gate structure. Correspondingly, the gate structure comprises a gate oxide layer and a gate layer positioned on the gate oxide layer.
The substrate also includes a sidewall layer 108.
The material of the sidewall layer 108 is not described herein.
The source-drain doped layer 104 is located in the fin portion 100a at two sides of the gate structure 103. The source-drain doped layer 104 provides stress for a channel under the gate structure 103 when the semiconductor structure works, so as to improve the mobility of carriers.
In this embodiment, the semiconductor structure is used to form the PMOS (Positive Channel Metal Oxide Semiconductor) transistor, i.e., the material of the source/drain doped layer 104 is P-type ion doped silicon germanium. In this embodiment, by doping P-type ions in silicon germanium, the P-type ions replace the positions of silicon atoms in the crystal lattice, and the more P-type ions are doped, the higher the concentration of the polynomials is, and the stronger the conductivity is. Specifically, the P-type ions include B, ga or In.
In other embodiments, the semiconductor structure is used to form NMOS (Negative channel Metal Oxide Semiconductor) transistors, i.e., the material of the source-drain doped layer is silicon carbide or silicon phosphide doped with N-type ions, respectively. By doping N-type ions in silicon carbide or silicon phosphide, the N-type ions replace the positions of silicon atoms in a crystal lattice, the more N-type ions are doped, the higher the concentration of the polyions is, and the higher the conductivity is. Specifically, the N-type ions include P, as or Sb.
It should be noted that the substrate further includes: an etch stop layer (Contact Etch Stop Layer, CESL) (not shown) is located on the source drain doped layer 104.
The material of the etching stop layer adopts a material with low K dielectric constant.
The material of the etching stop layer comprises one or more of silicon nitride, silicon oxynitride, silicon carbide, silicon nitride carbide, boron nitride silicon and boron nitride carbon silicon. In this embodiment, the material of the etching stop layer is silicon nitride.
An amorphous region is formed in the top of the source-drain doped layer 104, and the amorphous region is formed by using a pre-amorphization implantation (PAI) process. The PAI process includes ion implantation using ions selected from silicon, germanium, or a combination thereof to amorphize the top of the source drain doped layer 104, although amorphous silicon implantation processes are known to slow down the stress-lag reaction (stress-retarded reaction) and increase the nucleation density so that the first and second metal silicide layers 1141 and 1142 are more uniformly thicker. The ions are selected without changing the conductivity of the source-drain doped layer 104.
Specific implanted ions include: one or both of Ge and Si.
The interlayer dielectric layer 105 is used to achieve electrical isolation between adjacent semiconductor structures, and thus, the material of the interlayer dielectric layer 105 is an insulating material.
The interlayer dielectric layer 105 exposes the top wall of the gate structure 103.
Specifically, the material of the interlayer dielectric layer 105 is silicon oxide. Silicon oxide is a dielectric material with common process and low cost, has high process compatibility, is beneficial to reducing the process difficulty and the process cost for forming the interlayer dielectric layer 105, and has simple removal process. In other embodiments, the material of the interlayer dielectric layer may be one or more of silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride and silicon oxycarbonitride.
It should be noted that the substrate further includes: a dielectric layer 106 is located on the interlayer dielectric layer 105.
The dielectric layer 106 is used for realizing electrical isolation between adjacent devices, and the material of the dielectric layer 106 is an insulating material.
In this embodiment, the material of the dielectric layer 106 is silicon oxide. Silicon oxide is a dielectric material with common process and low cost, has high process compatibility, is beneficial to reducing the process difficulty and the process cost for forming the dielectric layer 106, and has simple removal process. In other embodiments, the material of the dielectric layer may be another insulating material such as silicon nitride or silicon oxynitride.
The contact hole plugs 115 are used to make electrical connection between the semiconductor structure and the semiconductor structure in addition to making electrical connection within the semiconductor structure.
In this embodiment, the conductive material is W. In other embodiments, the material of the conductive material may also be Al, cu, ag, au, or the like.
The semiconductor structure may be formed by the forming method described in the foregoing embodiments, or may be formed by other forming methods. For a specific description of the semiconductor structure in this embodiment, reference may be made to the corresponding description in the foregoing embodiment, which is not repeated here.
Although the embodiments of the present invention are disclosed above, the embodiments of the present invention are not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the embodiments of the invention, and the scope of the embodiments of the invention should be pointed out in the appended claims.
Claims (21)
1. A method of forming a semiconductor structure, comprising:
providing a substrate, wherein the substrate comprises a substrate, a gate structure positioned on the substrate, source-drain doped layers positioned in the substrate at two sides of the gate structure and an interlayer dielectric layer covering the side wall of the gate structure and the source-drain doped layers, and the interlayer dielectric layer exposes the top wall of the gate structure;
Forming an opening exposing the source-drain doped layer in the interlayer dielectric layer, wherein the bottom of the opening comprises a central area and an edge area surrounding the central area;
forming a first metal layer at the bottom of the opening;
removing the first metal layer in the central area of the bottom of the opening to form an opening;
forming a second metal layer in the opening, wherein the material diffusion capacity of the second metal layer is larger than that of the first metal layer, and the resistivity of the second metal layer corresponding to silicide is smaller than that of the first metal layer corresponding to silicide;
processing the first metal layer and the second metal layer to form a metal silicide layer, wherein the first metal layer and the second metal layer correspond to the first metal silicide layer and the second metal silicide layer respectively;
after forming the metal silicide layer, forming a contact hole plug in the opening.
2. The method of forming a semiconductor structure of claim 1, wherein the material of the first metal layer comprises: ti.
3. The method of forming a semiconductor structure of claim 1, wherein the first metal layer has a thickness of 2 nm to 8 nm.
4. The method of claim 1, wherein the first metal layer is formed at the bottom of the opening using atomic layer deposition or low pressure chemical vapor deposition.
5. The method of claim 1, wherein the second metal layer has a width of 10 nm to 20 nm perpendicular to a sidewall direction of the gate structure.
6. The method of forming a semiconductor structure of claim 1, wherein the material of the second metal layer comprises: ni.
7. The method of forming a semiconductor structure of claim 1, wherein the second metal layer has a thickness of 2 nm to 8 nm.
8. The method of claim 1, wherein the second metal layer is formed in the opening using atomic layer deposition or a low pressure chemical vapor deposition process.
9. The method of forming a semiconductor structure of claim 1, wherein forming the opening comprises:
forming a sacrificial layer on the side wall of the opening;
removing the first metal layer exposed by the sacrificial layer by taking the sacrificial layer as a mask to form the opening surrounded by the first metal layer and the source-drain doping layer;
The method for forming the semiconductor structure further comprises the following steps: removing the sacrificial layer after forming the opening and before forming the second metal layer; or after the metal silicide layer is formed, removing the sacrificial layer.
10. The method of forming a semiconductor structure of claim 9, wherein the material of the sacrificial layer comprises: low-K material, metal compound, amorphous carbon, and amorphous germanium.
11. The method of forming a semiconductor structure of claim 10, wherein the metal compound is an Al compound.
12. The method of forming a semiconductor structure of claim 1, wherein a ratio of a length of the first metal layer to a length of the second metal layer in a direction perpendicular to sidewalls of the gate structure is 2 to 3.
13. The method of forming a semiconductor structure of claim 1, wherein the first metal layer and the second metal layer are processed using a self-aligned metal silicide process to form the first metal silicide layer and the second metal silicide layer, respectively.
14. The method of forming a semiconductor structure of claim 1, wherein the substrate is a substrate having a fin;
The gate structure spans the fin and covers part of the top wall and the side wall of the fin;
the source-drain doped layer is located in the fin portions at two sides of the gate structure.
15. A semiconductor structure, comprising:
the substrate is provided with a plurality of holes,
a gate structure located on the substrate;
the source-drain doping layers are positioned in the substrate at two sides of the grid structure;
the interlayer dielectric layer covers the gate structure and the source-drain doping layer, and the top surface of the gate structure is exposed;
the contact hole plug penetrates through the interlayer dielectric layer and is used for being electrically connected with the source-drain doped layer, and the contact hole plug comprises a central area and an edge area surrounding the central area;
the metal silicide layer is positioned between the source-drain doping layer and the contact hole plug and comprises a first metal silicide layer and a second metal silicide layer; the first metal silicide layer is positioned between the source-drain doping layer and the edge area of the contact hole plug; the second metal silicide layer is positioned between the source-drain doping layer and the central area of the contact hole plug; the resistance value of the second metal silicide layer is lower than that of the first metal silicide layer, and the material diffusion capacity of the second metal silicide layer corresponding to the metal is larger than that of the first metal silicide corresponding to the metal.
16. The semiconductor structure of claim 15, wherein the first metal silicide layer comprises: titanium silicon compound.
17. The semiconductor structure of claim 15, wherein the first metal silicide layer has a thickness of 2 nm to 16 nm.
18. The semiconductor structure of claim 15, wherein the second metal silicide layer comprises: nickel silicon compound.
19. The semiconductor structure of claim 15, wherein the second metal silicide layer has a thickness of 2 nm to 16 nm.
20. The semiconductor structure of claim 15, wherein a ratio of a length of the first metal silicide layer to a length of the second metal silicide layer in a direction perpendicular to sidewalls of the gate structure is 2 to 3.
21. The semiconductor structure of claim 15, wherein the width of the second metal silicide layer is 10 nm to 20 nm in a direction perpendicular to the sidewalls of the gate structure.
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| US6486067B1 (en) * | 1999-10-29 | 2002-11-26 | Taiwan Semiconductor Manufacturing Company | Method for improving the electrical isolation between the contact and gate in a self-aligned contact MOSFET device structure |
| CN104681603A (en) * | 2013-12-03 | 2015-06-03 | 上海华虹宏力半导体制造有限公司 | Longitudinal bipolar transistor in BCD (Bipolar complementary metal-oxide-semiconductor double-diffusion metal-oxide-semiconductor) technology |
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| US20170194454A1 (en) * | 2016-01-06 | 2017-07-06 | International Business Machines Corporation | NiPt AND Ti INTERSECTING SILICIDE PROCESS AND STRUCTURE |
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| CN104681603A (en) * | 2013-12-03 | 2015-06-03 | 上海华虹宏力半导体制造有限公司 | Longitudinal bipolar transistor in BCD (Bipolar complementary metal-oxide-semiconductor double-diffusion metal-oxide-semiconductor) technology |
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