CN111755513B - Semiconductor structure and forming method thereof - Google Patents

Abstract

A semiconductor structure and a method for forming the same, the method for forming the same includes: providing a substrate, a gate structure positioned on the substrate, source-drain doped layers positioned in the substrate at two sides of the gate structure and an interlayer dielectric layer covering the side wall of the gate structure and the source-drain doped layers; forming an opening exposing the source-drain doping layer in the interlayer dielectric layer, wherein the bottom of the opening comprises a central area and an edge area; forming a first metal layer in the edge area, and forming a second metal layer in the central area, wherein the material diffusion capacity of the second metal layer is larger than that of the first metal layer; and processing the first metal layer and the second metal layer to form a first metal silicide layer and a second metal silicide layer respectively, wherein the resistivity of the second metal silicide layer is smaller than that of the first metal layer silicide layer. According to the invention, under the condition that the source-drain doped layer is not easy to pass through, the contact resistance between the source-drain doped layer and a contact hole plug formed subsequently is reduced, and the electrical property of the semiconductor structure is optimized.

Description

Semiconductor structures and methods of forming them

technical field

Embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular, to a semiconductor structure and a method for forming the same.

Background technique

In semiconductor manufacturing, with the development trend of ultra-large-scale integrated circuits, the feature size of integrated circuits continues to decrease. In order to adapt to smaller feature sizes, Metal-Oxide-Semiconductor Field-Effect Transistors , MOSFET) channel length has been shortened accordingly. However, as the channel length of the device shortens, the distance between the source and the drain of the device also shortens, so the ability of the gate structure to control the channel becomes worse, and the gate voltage pinches off the channel. The difficulty of the channel is also increasing, making the phenomenon of subthreshold leakage (subthreshold leakage), the so-called short-channel effect (SCE: short-channel effects) more likely to occur.

Therefore, in order to reduce the impact of the short channel effect, the semiconductor process gradually begins to transition from planar MOSFETs to three-dimensional transistors with higher efficiency, such as Fin Field Effect Transistors (FinFETs). In FinFET, the gate structure can control the ultra-thin body (fin) from at least two sides. Compared with the planar MOSFET, the gate structure has a stronger ability to control the channel and can well suppress the short channel effect; Moreover, compared with other devices, FinFET has better compatibility with existing integrated circuit manufacturing.

Contents of the invention

The problem solved by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same to optimize the performance of the semiconductor structure.

In order to solve the above problems, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a base, the base includes a substrate, a gate structure on the substrate, and gate structures located on both sides of the gate structure. The source-drain doped layer in the substrate and the interlayer dielectric layer covering the sidewall of the gate structure and the source-drain doped layer, and the interlayer dielectric layer exposes the top wall of the gate structure; forming an opening exposing the source-drain doped layer in the interlayer dielectric layer, the bottom of the opening includes a central region, and an edge region surrounding the central region; forming a first metal layer at the bottom of the opening; removing the The first metal layer in the central area of the bottom of the opening forms an opening; a second metal layer is formed in the opening, the material diffusion capacity of the second metal layer is greater than the material diffusion capacity of the first metal layer, and the The resistivity of the second metal layer corresponding to the silicide is smaller than the resistivity of the first metal layer corresponding to the silicide; the first metal layer and the second metal layer are processed to form a metal silicide layer, and the first The metal layer and the second metal layer respectively correspond to the first metal silicide layer and the second metal silicide layer; after forming the metal silicide layer, a contact hole plug is formed in the opening.

Optionally, the material of the first metal layer includes: Ti.

Optionally, the thickness of the first metal layer is 2 nm to 8 nm.

Optionally, the first metal layer is formed on the bottom of the opening by atomic layer deposition or low pressure chemical vapor deposition.

Optionally, perpendicular to the direction of the sidewall of the gate structure, the width of the second metal layer is 10 nm to 20 nm.

Optionally, the material of the second metal layer includes: Ni.

Optionally, the thickness of the second metal layer is 2 nanometers to 8 nanometers.

Optionally, the second metal layer is formed in the opening by atomic layer deposition or low pressure chemical vapor deposition.

Optionally, the step of forming the opening includes: forming a sacrificial layer on the sidewall of the opening; using the sacrificial layer as a mask to remove the first metal layer exposed by the sacrificial layer, forming the The opening surrounded by the first metal layer and the source-drain doped layer; the method for forming the semiconductor structure further includes: removing the sacrificial layer after forming the opening and before forming the second metal layer; or , after forming the metal silicide layer, removing the sacrificial layer.

Optionally, the material of the sacrificial layer includes: one or more of low-K materials, metal compounds, Al compounds, amorphous carbon and amorphous germanium.

Optionally, in a direction perpendicular to the sidewall of the gate structure, the ratio of the length of the first metal layer to the length of the second metal layer is 2 to 3.

Optionally, a salicide process is used to process the first metal layer and the second metal layer to form the first metal silicide layer and the second metal silicide layer respectively.

Optionally, the substrate is a substrate with a fin; the gate structure spans the fin and covers part of the top wall and side wall of the fin; the source-drain doped layer is located on the fin in the fins on both sides of the gate structure.

Correspondingly, an embodiment of the present invention also provides a semiconductor structure, including: a substrate, a gate structure located on the substrate; source and drain doped layers located in the substrate on both sides of the gate structure an interlayer dielectric layer covering the gate structure and the source-drain doped layer, and the interlayer dielectric layer exposes the top surface of the gate structure; a contact hole plug penetrates the interlayer dielectric layer , and is used for electrical connection with the source-drain doped layer, the contact hole plug includes a central region, and an edge region surrounding the central region; a metal silicide layer is located between the source-drain doped layer and the contact Between the hole plugs, the metal silicide layer includes a first metal silicide layer and a second metal silicide layer; the first metal silicide layer is located at the edge of the source-drain doped layer and the contact hole plug Between regions; the second metal silicide layer is located between the source-drain doped layer and the central region of the contact hole plug; the resistance value of the second metal silicide layer is lower than that of the first metal silicide The resistance value of the material layer, and the material diffusion capacity of the second metal silicide layer corresponding to the metal is greater than the material diffusion capacity of the first metal silicide layer corresponding to the metal.

Optionally, the first metal silicide layer includes: titanium silicon compound.

Optionally, the thickness of the first metal silicide layer is 2 nm to 16 nm.

Optionally, the second metal silicide layer includes: nickel silicon compound.

Optionally, the thickness of the second metal silicide layer is 2 nm to 16 nm.

Optionally, in a direction perpendicular to the sidewall of the gate structure, the ratio of the length of the first metal silicide layer to the length of the second metal silicide layer is 2 to 3.

Optionally, in a direction perpendicular to the sidewall of the gate structure, the width of the second metal silicide layer is 10 nanometers to 20 nanometers.

Compared with the prior art, the technical solutions of the embodiments of the present invention have the following advantages:

The bottom of the opening in the embodiment of the present invention includes a central region and an edge region surrounding the central region, the edge region is closer to the channel region below the gate structure than the central region; A metal layer; removing the first metal layer in the central area of the bottom of the opening to form an opening; forming a second metal layer in the opening. The material diffusion ability of the second metal layer is greater than the material diffusion ability of the first metal layer. Compared with the case where the second metal layer is used alone to form the metal silicide layer, the second metal layer located in the central region forms a second metal silicide layer. In the process of the metal silicide layer, the material of the second metal layer is not easy to diffuse into the channel region under the gate structure, so that the source-drain doped layer is not easy to penetrate, and the gate structure is easier to control the channel. The resistivity of the second metal silicide layer is smaller than the resistivity of the first metal silicide layer, and has a lower resistance value than the case where only the first metal layer is used to react to form the metal silicide layer . To sum up, the second metal silicide layer is formed in the central area of the bottom of the opening, and the first metal silicide layer is formed in the edge area, which ensures that the contact hole plug and contact holes are reduced when the source-drain doped layer is not easy to penetrate. The contact resistance of the source-drain doped layer optimizes the electrical performance of the semiconductor structure.

Description of drawings

Fig. 1 is a structural schematic diagram of a semiconductor structure;

2 to 10 are structural diagrams corresponding to each step in another embodiment of the method for forming a semiconductor structure according to the embodiment of the present invention.

Detailed ways

It can be seen from the background art that the semiconductor structures formed so far still have the problem of poor performance. The reasons for the poor performance of the semiconductor structure are analyzed in conjunction with a semiconductor structure.

Referring to FIG. 1 , a schematic structural diagram of a semiconductor structure is shown.

Referring to FIG. 1, the semiconductor structure includes: a substrate 1; a fin 2 located on the substrate 1; a gate structure 3 spanning the fin 2, and the gate structure 3 covers the fin part of the top wall and sidewall of part 2; doped source and drain layer 4, located in the fin part 2 on both sides of the gate structure 3; metal silicide 5 is located on the doped source and drain layer 4; layer An interlayer dielectric layer (not shown in the figure), covering the gate structure 3 and the source-drain doped layer 4, and the interlayer dielectric layer exposes the top surface of the gate structure 3; a contact hole plug 6, Located on the metal silicide 5 and in contact with the metal silicide 5, the top surface of the contact hole plug 6 is higher than the top surface of the interlayer dielectric layer; a dielectric layer 7 is located on the interlayer dielectric layer, covering the sidewall of the contact plug 6 and exposing the top surface of the contact plug 6 .

The metal silicide layer 5 is used to reduce the contact resistance between the source-drain doped layer 4 and the contact hole plug 6 . If the material of the metal silicide layer 5 is a nickel-silicon compound, during the process of forming the nickel-silicon compound, the metal nickel is easy to diffuse into the channel region below the gate structure 3, which will cause gate The source-drain doped layer 4 on both sides of the electrode structure 3 penetrates through, so that the gate structure 3 cannot control the channel well, so that the electrical performance of the semiconductor structure is not high. If the material of the metal silicide layer 5 is a titanium-silicon compound, the resistivity of the titanium-silicon compound is relatively high, and the contact resistance between the source-drain doped layer 4 and the contact hole plug 6 cannot be well reduced. poor electrical performance.

In order to solve the above technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a base, the base includes a substrate, a gate structure on the substrate, and a gate structure located on both sides of the gate structure. The source-drain doped layer in the substrate and the interlayer dielectric layer covering the sidewall of the gate structure and the source-drain doped layer, and the interlayer dielectric layer exposes the top wall of the gate structure; Forming an opening exposing the source-drain doped layer in the interlayer dielectric layer, the bottom of the opening includes a central region, and an edge region surrounding the central region; forming a first metal layer at the bottom of the opening; removing The first metal layer in the central area of the bottom of the opening forms an opening; a second metal layer is formed in the opening, and the material diffusion capacity of the second metal layer is greater than the material diffusion capacity of the first metal layer, And the resistivity corresponding to the silicide of the second metal layer is smaller than the resistivity corresponding to the silicide of the first metal layer; the first metal layer and the second metal layer are processed to form a metal silicide layer, the The first metal layer and the second metal layer respectively correspond to the first metal silicide layer and the second metal silicide layer; after forming the metal silicide layer, a contact hole plug is formed in the opening.

The bottom of the opening in the embodiment of the present invention includes a central region and an edge region surrounding the central region, the edge region is closer to the channel region below the gate structure than the central region; A metal layer; removing the first metal layer in the central area of the bottom of the opening to form an opening; forming a second metal layer in the opening. The material diffusion ability of the second metal layer is greater than the material diffusion ability of the first metal layer. Compared with the case where the second metal layer is used alone to form the metal silicide layer, the second metal layer located in the central region forms a second metal silicide layer. In the process of the metal silicide layer, the material of the second metal layer is not easy to diffuse into the channel region under the gate structure, so that the source-drain doped layer is not easy to penetrate, and the gate structure is easier to control the channel. The resistivity of the second metal silicide layer is smaller than the resistivity of the first metal silicide layer, and has a lower resistance value than the case where only the first metal layer is used to react to form the metal silicide layer . To sum up, the second metal silicide layer is formed in the central area of the bottom of the opening, and the first metal silicide layer is formed in the edge area, which ensures that the contact hole plug and contact holes are reduced when the source-drain doped layer is not easy to penetrate. The contact resistance of the source-drain doped layer optimizes the electrical performance of the semiconductor structure.

In order to make the above objects, features and advantages of the embodiments of the present invention more comprehensible, specific embodiments of the embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings.

2 to 10 are structural schematic diagrams corresponding to each step in an embodiment of a method for forming a semiconductor structure according to an embodiment of the present invention.

Referring to FIG. 2 , a base is provided, and the base includes a substrate 100, a gate structure 103 on the substrate 100, a source-drain doped layer 104 in the substrate 100 on both sides of the gate structure 103 And the interlayer dielectric layer 105 covering the sidewalls of the gate structure 103 and the source-drain doped layer 104 , and the interlayer dielectric layer 105 exposes the top wall of the gate structure 103 .

The substrate 100 provides a process basis for subsequent formation of semiconductor structures.

In this embodiment, the formed semiconductor structure is a Fin Field Effect Transistor (FinFET) as an example, and the substrate 100 is a substrate 100 having a fin portion 100a. In other embodiments, the formed semiconductor structure may also be a planar structure, and correspondingly, the substrate is a planar substrate.

In this embodiment, the material of the substrate 100 is silicon. In other embodiments, the material of the substrate may also be germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium, and the substrate may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate. An interface layer can also be formed on the surface of the substrate 100, and the material of the interface layer is silicon oxide, silicon nitride, or silicon oxynitride.

The gate structure 103 spans the fin portion 100a and covers part of the top wall and the side wall of the fin portion 100a. The gate structure 103 is used to control the opening and closing of the channel when the semiconductor structure is working.

In this embodiment, the gate structure 103 is a metal gate structure.

In this embodiment, the gate structure 103 is a stacked structure, including a gate dielectric layer 1031 conformally covering part of the top surface and part of the sidewall of the fin 100 a and a gate layer 1032 on the gate dielectric layer 1031 . In other embodiments, the gate structure may also be a single-layer structure, that is, the gate structure only includes a gate layer.

The material of the gate dielectric layer 1031 is a high-k dielectric layer, and the material of the high-k dielectric layer refers to a dielectric material with a relative dielectric constant greater than that of silicon oxide. In this embodiment, the material of the gate dielectric layer 1031 is HfO ₂ . In other embodiments, the material of the gate dielectric layer may also be selected from one or more of ZrO ₂ , HfSiO, HfSiON, HfTaO, HfTiO, HfZrO or Al ₂ O ₃ .

The gate layer 1032 is used as an electrode for realizing electrical connection with an external circuit. In this embodiment, the material of the gate layer 1032 is magnesium-tungsten alloy. In other embodiments, the material of the gate layer may also be W, Al, Cu, Ag, Au, Pt, Ni or Ti, etc.

In other embodiments, the gate structure may also be a polysilicon gate structure. Correspondingly, the gate structure includes a gate oxide layer and a gate layer on the gate oxide layer.

The substrate further includes a sidewall layer 108, and the sidewall 108 is used to protect the sidewall of the gate structure 103 during subsequent etching to remove the interlayer dielectric layer 105 on the source-drain doped layer 104. Playing a protective role, the sidewall 108 is also used to define the position of the source-drain doped layer 104 .

The source-drain doped layer 104 is located in the fin portion 100 a on both sides of the gate structure 103 . The source-drain doped layer 104 provides stress to the channel under the gate structure 103 when the semiconductor structure is working, and improves the mobility of carriers.

In this embodiment, the semiconductor structure is used to form a PMOS (Positive Channel Metal Oxide Semiconductor) transistor, that is, the material of the source-drain doped layer 104 is silicon germanium doped with P-type ions. In this embodiment, by doping P-type ions in silicon germanium, the P-type ions replace the positions of silicon atoms in the crystal lattice. The more P-type ions doped, the higher the concentration of multiple children and the better the conductivity. powerful. Specifically, the P-type ions include B, Ga or In.

In other embodiments, the semiconductor structure is used to form an NMOS (Negative channel Metal Oxide Semiconductor) transistor, that is, the material of the doped source and drain layers is silicon carbide or silicon phosphide doped with N-type ions. By doping N-type ions in silicon carbide or silicon phosphide, N-type ions replace the positions of silicon atoms in the crystal lattice. The more N-type ions doped, the higher the concentration of many children and the better the conductivity. powerful. Specifically, the N-type ions include P, As or Sb.

It should be noted that, the substrate further includes: an etch stop layer (Contact Etch Stop Layer, CESL) (not shown in the figure), located on the source-drain doped layer 104 . The etch stop layer is used to define the etching stop position of the etching process during the subsequent process of etching the interlayer dielectric layer 105 to form an opening, so as to ensure that the etching forms an opening while reducing the impact of the etching process on the opening. The probability of over-etching caused by the source-drain doped layer 104 is discussed above.

The material of the etching stop layer is a material with a low K dielectric constant.

The material of the etching stop layer includes one or more of silicon nitride, silicon oxynitride, silicon carbide, silicon carbide nitride, boron nitride, silicon boron nitride and silicon boron nitride. In this embodiment, the material of the etching stop layer is silicon nitride.

It should be noted that an amorphous region is formed on the top of the source-drain doped layer 104 , and the amorphous region is formed by a pre-amorphization implantation (PAI) process. The PAI process includes ion implantation using ions selected from silicon, germanium, or a combination thereof, so that the top of the source-drain doped layer 104 is amorphized, although it is known that the amorphous silicon implantation process can be used to slow down the stress-retarded reaction. reaction) and increase the density of crystal nucleus formation, so that the first metal silicide layer and the second metal layer that are subsequently formed on the top surface of the source-drain doped layer are processed to form a more uniform and thicker first metal silicide layer and the second metal silicide layer Two metal silicide layers. The ions are selected without changing the conductivity of the source-drain doped layer 104 .

Specific implanted ions include: one or two of Ge or Si.

The interlayer dielectric layer 105 is used to realize electrical isolation between adjacent semiconductor structures, therefore, the material of the interlayer dielectric layer 105 is an insulating material.

The interlayer dielectric layer 105 exposes the top wall of the gate structure 103 .

Specifically, the material of the interlayer dielectric layer 105 is silicon oxide. Silicon oxide is a commonly used dielectric material with low cost, and has high process compatibility, which is beneficial to reduce the process difficulty and process cost of forming the interlayer dielectric layer 105, and the silicon oxide removal process is simple. In other embodiments, the material of the interlayer dielectric layer may also be one or more of silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride and silicon oxycarbonitride.

It should be noted that the substrate further includes: a dielectric layer 106 located on the interlayer dielectric layer 105 . The dielectric layer 106 and the interlayer dielectric layer 105 provide a process basis for subsequent formation of contact hole plugs connected to the source-drain doped layer 104 .

The dielectric layer 106 is used to realize electrical isolation between adjacent devices, and the material of the dielectric layer 106 is an insulating material.

In this embodiment, the material of the dielectric layer 106 is silicon oxide. Silicon oxide is a commonly used dielectric material with low cost, and has high process compatibility, which is beneficial to reduce the process difficulty and process cost of forming the dielectric layer 106, and the silicon oxide removal process is simple. In other embodiments, the material of the dielectric layer may also be other insulating materials such as silicon nitride or silicon oxynitride.

Referring to FIG. 3 , an opening 107 exposing the source-drain doped layer 104 is formed in the interlayer dielectric layer 105 , the bottom of the opening 107 includes a central region, and an edge region surrounding the central region.

The central region is farther from the channel region than the edge regions. The subsequent central area is used to form a second metal silicide layer, and the edge area is used to form a first metal silicide layer.

The opening 107 provides a space for subsequent formation of contact hole plugs.

The step of forming the opening 107 includes: forming an opening mask layer (not shown in the figure) on the dielectric layer 106; using the opening mask layer as a mask to remove the layer on the source-drain doped layer 104 The inter-dielectric layer 105 and the dielectric layer 106 form an opening 107 exposing the source-drain doped layer 104 .

In this embodiment, a dry etching process is used to remove the interlayer dielectric layer 105 and the dielectric layer 106 on the source-drain doped layer 104 to form the opening 107 . The dry etching process is an anisotropic etching process, which has good controllability of the etching profile, reduces damage to other film structures, and is conducive to making the shape of the opening 107 meet the process requirements, and is also conducive to The removal efficiency of the interlayer dielectric layer 105 and the dielectric layer 106 is improved.

It should be noted that, in the process of etching the interlayer dielectric layer 105, the etching stop layer defines the etching stop position of the etching process, so as to ensure that the etching forms the opening 107 while reducing the etching process. The process causes the possibility of over-etching the source-drain doped layer 104 .

Specifically, the opening 107 penetrates through the dielectric layer 106 , the interlayer dielectric layer 105 and the etch stop layer.

It should be noted that the aforementioned pre-amorphization implantation (PAI) process may also be performed after the opening 107 is formed.

Referring to FIG. 4 , a first metal layer 109 is formed at the bottom of the opening 107 .

The first metal layer 109 prepares for the subsequent formation of a first metal silicide layer. The first metal silicide layer is used to reduce the contact resistance between the source-drain doped layer 104 and the subsequently formed contact hole plug.

In this embodiment, the material of the first metal layer 109 includes: Ti.

In this embodiment, the first metal layer 109 is formed by using an atomic layer deposition process (Atomic Layer Deposition, ALD). The atomic layer deposition process has better conformal coverage ability, which is beneficial to ensure that in the step of forming the first metal layer 109, the first metal layer 109 can conformally cover the bottom surface and sidewall of the opening 107 , by using the atomic layer deposition process, it is also beneficial to improve the thickness uniformity of the first metal layer 109 . In other embodiments, the first metal layer may also be formed by chemical vapor deposition (CVD).

It should be noted that the first metal layer 109 should neither be too thick nor too thin. If the first metal layer 109 is too thick, the process time for forming the first metal layer 109 is too long, and the subsequent process will remove the unreacted first metal 109 to form the first metal silicide, resulting in waste of resources. If the first metal layer 109 is too thin, the thickness of the first metal silicide layer formed by subsequent self-alignment silicide processes (self-alignment silicide processes) is too thin, so that the contact resistance cannot be reduced. The role of making the electrical performance of the semiconductor structure is not good. In this embodiment, the thickness of the first metal layer 109 is 2 nm to 8 nm.

Referring to FIG. 5 to FIG. 7 , the first metal layer 109 at the bottom central area of the opening 107 is removed to form the opening 101 .

The opening 101 is a preparation for subsequent formation of a second metal layer, and the diffusion capacity of the material of the second metal layer is greater than that of the material of the first metal layer.

In this embodiment, the width of the opening 101 should not be too large or too small in the direction perpendicular to the sidewall of the gate structure 103 . If the width of the opening 101 is too small, the width of the subsequent formation of the second metal layer in the direction perpendicular to the sidewall of the gate structure 103 is too small, which is not conducive to reducing the subsequent formation of contact hole plugs and source-drain doped layers. The resistance. If the width of the opening 101 is too large, the width of the subsequent second metal layer formed in the direction perpendicular to the sidewall of the gate structure 103 is too large, because the diffusion capacity of the material of the second metal layer is greater than that of the first metal layer. If the width of the second metal layer is too large, the material of the second metal layer will easily diffuse into the groove during the subsequent processing of the second metal layer to form the second metal silicide layer. In the channel, the source-drain doped layer 104 is easy to punch through, resulting in poor performance of the semiconductor structure. In this embodiment, the width of the opening 101 perpendicular to the direction of the sidewall of the gate structure 103 is 10 nanometers to 20 nanometers.

It should be noted that, for the source-drain doped layer 104 at both ends of the extending direction of the fin portion 100a, only one end is close to the channel region, and the opening 101 exposes part of the source-drain layer far away from the channel region. Doped layer 104. The opening 101 exposes a portion of the source-drain doped layer 104 away from the channel region, so that more regions can be used to form the second metal layer in a subsequent process. In other embodiments, the opening may only expose the source-drain doped layer in the central region.

The steps of forming the opening 101 include:

As shown in FIGS. 5 and 6 , a sacrificial layer 111 (as shown in FIG. 6 ) is formed on the sidewall of the opening 107 . The sacrificial layer 111 exposes the central region to prepare for subsequent etching of the first metal layer 109 using the sacrificial layer 111 as a mask to form openings.

The material of the sacrificial layer 111 is different from that of the first metal layer 109 and the source-drain doped layer 104, so the sacrificial layer 111 and the first metal layer 109 and the source-drain doped layer 104 have an etching selectivity ratio , during the subsequent process of removing the sacrificial layer 111 , the etching rates of the first metal layer 109 and the source-drain doped layer 104 are small.

Specifically, the material of the sacrificial layer 111 is low-K material, one or more of metal compound, Al oxide, Ti compound and amorphous germanium. In this embodiment, the material of the sacrificial layer 111 is amorphous germanium.

The step of forming the sacrificial layer 111 includes: forming a sacrificial material layer 113 conformally covering the first metal layer 109 (as shown in FIG. 5 ); removing the source-drain doped layer 104 and the dielectric layer 106 The sacrificial material layer 113 is formed on the sacrificial layer 111 on the sidewall of the opening 107 .

In this embodiment, the sacrificial material layer 113 located on the source-drain doped layer 104 and the dielectric layer 106 is removed by using a maskless etching process, and no light is used in the step of forming the sacrificial layer 111. Mask (Mask), which reduces the process cost.

As shown in FIG. 7 , the first metal layer 109 exposed by the sacrificial layer 111 is removed by using the sacrificial layer 111 as a mask to form a metal layer surrounded by the first metal layer 109 and the source-drain doped layer 104. Hole 101.

In this embodiment, the first metal layer 109 exposed by the sacrificial layer 111 is removed by a dry etching process.

Specifically, the dry etching process has the characteristics of anisotropic etching, which is beneficial to ensure that the sacrificial material layer 113 located on the source-drain doped layer 104 and the dielectric layer 106 is completely removed, while other The damage to the film layer structure is small, and it is not easy to etch the first metal layer 109 laterally, so that the first metal layer 109 is not easy to be too short in the direction perpendicular to the sidewall of the gate structure 103, so that the first metal layer 109 is not easy to be too short. The second metal layer is not easy to be too long in the direction perpendicular to the sidewall of the gate structure 103, so that the material in the second metal layer is not easy to diffuse into the channel region during the subsequent salicide process, The source-drain doped layer 104 is not easy to punch through, which optimizes the electrical performance of the semiconductor structure.

In other embodiments, a wet etching process may also be used to remove the first metal layer exposed by the sacrificial layer. The wet etching process has a high etching rate, simple operation and low process cost.

Specifically, the opening 101 is surrounded by the first metal layer 109 , the etch stop layer and the source-drain doped layer 104 .

Referring to FIG. 8, a second metal layer 110 is formed in the opening 101, the material diffusion capacity of the second metal layer 110 is greater than the material diffusion capacity of the first metal layer 109, and the second metal layer 110 The resistivity corresponding to the silicide is smaller than the resistivity of the first metal layer 109 corresponding to the silicide.

The bottom of the opening 107 in the embodiment of the present invention includes a central region and an edge region surrounding the central region, the edge region is closer to the channel region below the gate structure 103 than the central region; in the opening 107 A first metal layer 109 is formed at the bottom; the first metal layer 109 at the bottom central area of the opening 107 is removed to form an opening 112 ; and a second metal layer 110 is formed in the opening 112 . The material diffusion ability of the second metal layer 110 is greater than the material diffusion ability of the first metal layer 109. Compared with the case where the second metal layer 110 is used alone to form a metal silicide layer, the second metal layer located in the central region 110 In the process of forming the second metal silicide layer, the material of the second metal layer 110 is not easy to diffuse into the channel region under the gate structure 103, so that the source-drain doped layer 104 is not easy to penetrate through, and the gate structure 103 Easier to control channels. The resistivity of the second metal silicide layer is smaller than the resistivity of the first metal silicide layer, and has a lower resistivity than the case where only the first metal layer 109 is used to react to form the metal silicide layer. value. To sum up, the second metal silicide layer is formed in the central area of the bottom of the opening 107, and the first metal silicide layer is formed in the edge area, which ensures that the contact hole insertion is reduced when the source-drain doped layer 104 is not easy to penetrate. The contact resistance between the plug and the source-drain doped layer 104 optimizes the electrical performance of the semiconductor structure.

In this embodiment, the material of the second metal layer 110 includes: Ni.

It should be noted that the second metal layer 110 should neither be too thick nor too thin. If the second metal layer 110 is too thick, the process time for forming the second metal layer 110 is too long, and the subsequent process will remove the unreacted second metal 109 to form the second metal silicide, resulting in waste of resources. If the second metal layer 110 is too thin, the thickness of the first metal silicide layer formed by the subsequent salicide process is too thin, so that it cannot play the role of reducing the contact resistance, so that the semiconductor structure Poor electrical performance. In this embodiment, the thickness of the second metal layer 110 is 2 nm to 8 nm.

In this embodiment, the second metal layer 110 is formed by an atomic layer deposition process. The atomic layer deposition process has better conformal coverage ability, which is beneficial to ensure that in the step of forming the second metal layer 110, the second metal layer 110 can conformally cover the bottom surface and sidewall of the opening 107 , by using the atomic layer deposition process, it is also beneficial to improve the thickness uniformity of the second metal layer 110 . In other embodiments, a chemical vapor deposition process may also be used to form the second metal layer.

It should be noted that, in this embodiment, the width of the opening 101 perpendicular to the direction of the sidewall of the gate structure 103 is 10 nm to 20 nm. Correspondingly, the width of the second metal layer 110 perpendicular to the sidewall direction of the gate structure 103 is 10 nm to 20 nm.

It should be noted that, in the direction perpendicular to the sidewall of the gate structure 103 , the length ratio between the first metal layer 109 and the second metal layer 110 should not be too large or too small. The first metal layer 109 and the second metal layer 110 are processed to form a metal silicide layer, and the metal silicide layer includes a first metal silicide layer and a second metal silicide layer, and the second metal silicide layer The resistance value of the layer is lower than the resistance value of the first metal silicide layer. If the ratio is too large, that is to say, the second metal layer 110 is too short, it will cause the subsequent formation of the second metal silicide layer to be too short. Correspondingly, the resistance between the source-drain doped layer 104 and the subsequently formed contact hole plug is too large, which is not conducive to reducing the contact resistance between the source-drain doped layer 104 and the subsequently formed contact hole plug, and is not conducive to optimization. Electrical properties of semiconductor structures. If the ratio is too small, that is, the length of the second metal layer 110 is too long, and the second metal layer 110 is too close to the channel region, the material in the second metal layer 110 will be automatically During the alignment process, it is easy to diffuse into the channel region, which easily leads to the breakthrough of the source-drain doped layer 104 . In this embodiment, the length ratio between the first metal layer 109 and the second metal layer 110 is 2 to 3 in a direction perpendicular to the sidewall of the gate structure 103 .

It should be noted that, in this embodiment, after the opening 101 is formed, the sacrificial layer 111 is removed; after the sacrificial layer 111 is removed, the second metal layer 110 is formed in the opening 101 .

In this embodiment, the sacrificial layer 111 is removed by a wet etching process. The wet etching process has a high etching rate, simple operation and low process cost.

Specifically, the wet etching solution is hot HCl solution.

In other embodiments, the method for forming the semiconductor structure may also be: the second metal layer conformally covers the dielectric layer, the sacrificial layer, and the source-drain doped layer exposed by the sacrificial layer, and subsequently forms the After removing the metal silicide layer, the sacrificial layer is removed.

Referring to FIG. 9, the first metal layer 109 and the second metal layer 110 are processed to form a metal silicide layer 114, and the first metal layer 109 and the second metal layer 110 respectively correspond to the first metal silicide layer 1141 and the second metal silicide layer 1142 .

The metal silicide layer 114 is used to reduce the contact resistance between the subsequently formed contact hole plug and the source-drain doped layer 104 .

In this embodiment, the first metal silicide layer 109 and the second metal layer 110 are processed by a self-aligned metal silicide process to form the first metal silicide layer 1141 and the second metal silicide layer respectively. 1142.

It should be noted that the first metal layer 109 and the second metal layer 110 are also formed on the sidewall of the gate structure 103 and the dielectric layer 106, and the method for forming the semiconductor structure further includes: After the metal silicide layer 114 is formed, the first metal layer 109 and the second metal layer 110 that have not reacted with the source-drain doped layer 104 are removed. In other embodiments, because the first metal layer is TI, and Ti is a material with weak diffusion ability, the first metal layer can also be retained, and the first metal layer is used to prevent subsequent formation on the The material on the first metal layer diffuses into the gate structure and the source-drain doped layer, which damages the electrical performance of the semiconductor structure.

In this embodiment, a wet etching process is used to remove the first metal layer 109 and the second metal layer 110 that have not reacted with the source-drain doped layer 104 . The wet etching process has a high etching rate, simple operation and low process cost.

Specifically, the wet etching solution is a mixture of ammonia water and hydrogen peroxide.

As shown in FIG. 10, a contact hole plug 115 is formed in the opening 107 (shown in FIG. 3).

The contact hole plug 115 is not only used to realize the electrical connection within the semiconductor structure, but also used to realize the electrical connection between the semiconductor structures.

In this embodiment, the material of the conductive material is W. In other embodiments, the material of the conductive material may also be Al, Cu, Ag or Au.

The step of forming the contact hole plug 115 includes: filling the opening 107 with conductive material, removing the conductive material higher than the opening 107 , and the conductive material located in the opening 107 as the contact hole plug 115 .

Correspondingly, the embodiment of the present invention also provides a semiconductor structure. Referring to FIG. 10 , it shows a schematic structural view of an embodiment of the semiconductor structure of the present invention.

The semiconductor structure includes: a substrate 100, a gate structure 103 located on the substrate 100; a source-drain doped layer 104 located in the substrate 100 on both sides of the gate structure 103; an interlayer dielectric A layer 105 covers the gate structure 103 and the source-drain doped layer 104, and the interlayer dielectric layer 105 exposes the top surface of the gate structure 103; a contact hole plug 115 penetrates the interlayer Dielectric layer 105, and used for electrical connection with the source-drain doped layer 104, the contact hole plug 115 includes a central region, and an edge region surrounding the central region; a metal silicide layer 114, located at the source Between the drain doped layer 104 and the contact hole plug 115, the metal silicide layer 114 includes a first metal silicide layer 1141 and a second metal silicide layer 1142; the first metal silicide layer 1141 is located in the between the source-drain doped layer 104 and the edge region of the contact hole plug 115; the second metal silicide layer 1142 is located between the source-drain doped layer 104 and the center region of the contact hole plug 115; the The resistance value of the second metal silicide layer 1142 is lower than the resistance value of the first metal silicide layer 1141, and the material diffusion capacity of the metal corresponding to the second metal silicide layer is greater than that of the first metal silicide layer 1141. The material diffusion capacity of metals.

The contact hole plug 115 in the embodiment of the present invention includes a central region and an edge region surrounding the central region, and the edge region is closer to the channel region below the gate structure 103 than the central region; the second A metal silicide layer 1141 is formed by processing the first metal layer, and the second metal silicide layer 1142 is formed by processing the second metal layer. The material diffusion ability of the second metal layer is greater than the material diffusion ability of the first metal layer. Compared with the case where the metal silicide layer is the second metal silicide layer 1142, in this embodiment, diffusion to the gate structure The material of the second metal layer in the channel region below 103 is less, so that the source-drain doped layer 104 is not easy to penetrate, and the gate structure 103 is easier to control the channel. The resistivity of the second metal silicide layer 1142 is smaller than the resistivity of the first metal silicide layer 1141 , and has a lower resistance than the case of using only the first metal silicide layer 1141 . To sum up, the second metal silicide layer 1142 is located in the central area, and the first metal silicide layer 1141 is located in the edge area, which ensures that the source-drain doped layer 104 is not easy to penetrate, and the contact hole plug is reduced. The contact resistance with the source-drain doped layer 104 at 115 optimizes the electrical performance of the semiconductor structure.

In this embodiment, the first metal silicide layer 1141 includes: titanium silicon compound.

It should be noted that the first metal silicide layer 1141 should neither be too thick nor too thin. If the first metal silicide layer 1141 is too thick, the source-drain doped layer 104 may not be able to provide sufficient stress for the channel when the semiconductor structure is working, and the performance of the semiconductor structure is poor. If the first metal silicide layer 1141 is too thin, it will not be able to reduce the contact resistance, resulting in poor electrical performance of the semiconductor structure. In this embodiment, the thickness of the first metal silicide layer 1141 is 2 nm to 16 nm.

In this embodiment, the second metal silicide layer 1142 includes: nickel silicon compound.

It should be noted that the second metal silicide layer 1142 should neither be too thick nor too thin. If the second metal silicide layer 1142 is too thick, the source-drain doped layer 104 may not be able to provide sufficient stress for the channel when the semiconductor structure is working, and the performance of the semiconductor structure is poor. If the second metal silicide layer 1142 is too thin, it cannot reduce the contact resistance, and the electrical performance of the semiconductor structure is not good. In this embodiment, the thickness of the second metal silicide layer 1142 is 2 nm to 16 nm.

It should be noted that, in the direction perpendicular to the sidewall of the gate structure 103 , the width of the second metal silicide layer 1142 should not be too large or too small. If the width of the second metal silicide layer 1142 is too small, the width of the second metal silicide layer 1142 in the direction perpendicular to the sidewall of the gate structure 103 is too small, which is not conducive to the reduced contact hole plug 115. and the resistance of the source-drain doped layer 104 . If the width of the second metal silicide layer 1142 is too large, the diffusion capacity of the material of the second metal layer corresponding to the second metal silicide layer 1142 is greater than that of the first metal layer corresponding to the first metal silicide layer 1141 Diffusion ability of the material, if the width of the second metal layer is too large, the material of the second metal layer will easily diffuse into the channel during the process of processing the second metal layer to form the second metal silicide layer 1142 , causing the source-drain doped layer 104 to easily punch through, resulting in poor performance of the semiconductor structure. In this embodiment, in a direction perpendicular to the sidewall of the gate structure 103 , the width of the second metal silicide layer 1142 is 10 nm to 20 nm.

It should be noted that, in the direction perpendicular to the sidewall of the gate structure 103 , the length ratio between the first metal silicide layer 1141 and the second metal silicide layer 1142 should not be too large or too small. The resistance value of the second metal silicide layer 1142 is lower than the resistance value of the first metal silicide layer 1141, if the ratio is too large, that is, the second metal silicide layer 1142 is too short, It is not conducive to reducing the contact resistance between the contact hole plug 115 and the source-drain doped layer 104, and is not conducive to optimizing the electrical performance of the semiconductor structure. The second metal silicide layer 1142 is formed by processing the second metal layer. If the ratio is too small, that is to say, the length of the second metal silicide layer 1142 is too long, the second metal silicide layer 1142 Too close to the channel region will cause the material of the second metal layer to easily diffuse into the channel region during the process of forming the second metal silicide layer 1142 , which will easily lead to the breakthrough of the source-drain doped layer 104 . In this embodiment, the ratio of the length of the first metal silicide layer 1141 to the length of the second metal silicide layer 1142 is 2 to 3 in a direction perpendicular to the sidewall of the gate structure 103 .

It should be noted that, for the doped source and drain layers 104 at both ends of the extending direction of the fin portion 100a, only one end is close to the channel region. Therefore, the first metal silicide layer 1141 is only located in the doped source and drain layers. A second metal silicide layer 1142 is formed on the remaining source-drain doped layer 104 in a part of the region close to the channel region on the layer 104 . The second metal silicide layer 1142 formed on the source-drain doped layer 104 away from the channel region can reduce the contact resistance between the source-drain doped layer 104 and the contact hole plug 115 . In other embodiments, for the source-drain doped layers at both ends of the fin extension direction, a second metal silicide layer may be formed on the source-drain doped layer in the central region, and a second metal silicide layer may be formed on the source-drain doped layer in the edge region. The first metal silicide layer.

The substrate 100 provides a process basis for forming a semiconductor structure.

In this embodiment, the semiconductor structure is a Fin Field Effect Transistor (FinFET) as an example, and the substrate 100 is a substrate 100 having a fin portion 100a. In other embodiments, the semiconductor structure may also be a planar structure, and correspondingly, the substrate is a planar substrate.

In this embodiment, the material of the substrate 100 is silicon. In other embodiments, the material of the substrate may also be germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium, and the substrate may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate. An interface layer can also be formed on the surface of the substrate 100, and the material of the interface layer is silicon oxide, silicon nitride, or silicon oxynitride.

The gate structure 103 spans the fin portion 100a and covers part of the top wall and the side wall of the fin portion 100a. The gate structure 103 is used to control the opening and closing of the channel when the semiconductor structure is working.

In this embodiment, the gate structure 103 is a metal gate structure.

In this embodiment, the gate structure 103 is a stacked structure, including a gate dielectric layer 1031 conformally covering part of the top surface and part of the sidewall of the fin 100 a and a gate layer 1032 on the gate dielectric layer 1031 . In other embodiments, the gate structure may also be a single-layer structure, that is, the gate structure only includes a gate layer.

The material of the gate dielectric layer 1031 is a high-k dielectric layer, and the material of the high-k dielectric layer refers to a dielectric material with a relative dielectric constant greater than that of silicon oxide. In this embodiment, the material of the gate dielectric layer 1031 is HfO ₂ . In other embodiments, the material of the gate dielectric layer may also be selected from one or more of ZrO ₂ , HfSiO, HfSiON, HfTaO, HfTiO, HfZrO or Al ₂ O ₃ .

The gate layer 1032 is used as an electrode for realizing electrical connection with an external circuit. In this embodiment, the material of the gate layer 1032 is magnesium-tungsten alloy. In other embodiments, the material of the gate layer may also be W, Al, Cu, Ag, Au, Pt, Ni or Ti, etc.

In other embodiments, the gate structure may also be a polysilicon gate structure. Correspondingly, the gate structure includes a gate oxide layer and a gate layer on the gate oxide layer.

The substrate also includes a sidewall layer 108 .

The materials of the side wall layer 108 will not be repeated here.

The source-drain doped layer 104 is located in the fin portion 100 a on both sides of the gate structure 103 . The source-drain doped layer 104 provides stress to the channel under the gate structure 103 when the semiconductor structure is working, and improves the mobility of carriers.

In this embodiment, the semiconductor structure is used to form a PMOS (Positive Channel Metal Oxide Semiconductor) transistor, that is, the material of the source-drain doped layer 104 is silicon germanium doped with P-type ions. In this embodiment, by doping P-type ions in silicon germanium, the P-type ions replace the positions of silicon atoms in the crystal lattice. The more P-type ions doped, the higher the concentration of multiple children and the better the conductivity. powerful. Specifically, the P-type ions include B, Ga or In.

In other embodiments, the semiconductor structure is used to form an NMOS (Negative channel Metal Oxide Semiconductor) transistor, that is, the material of the doped source and drain layers is silicon carbide or silicon phosphide doped with N-type ions. By doping N-type ions in silicon carbide or silicon phosphide, N-type ions replace the positions of silicon atoms in the crystal lattice. The more N-type ions doped, the higher the concentration of many children and the better the conductivity. powerful. Specifically, the N-type ions include P, As or Sb.

It should be noted that, the substrate further includes: an etch stop layer (Contact Etch Stop Layer, CESL) (not shown in the figure), located on the source-drain doped layer 104 .

The material of the etching stop layer is a material with a low K dielectric constant.

The material of the etching stop layer includes one or more of silicon nitride, silicon oxynitride, silicon carbide, silicon carbide nitride, boron nitride, silicon boron nitride and silicon boron nitride. In this embodiment, the material of the etching stop layer is silicon nitride.

It should be noted that an amorphous region is formed on the top of the source-drain doped layer 104 , and the amorphous region is formed by a pre-amorphization implantation (PAI) process. The PAI process includes ion implantation using ions selected from silicon, germanium, or a combination thereof, so that the top of the source-drain doped layer 104 is amorphized, although it is known that the amorphous silicon implantation process can be used to slow down the stress-retarded reaction. reaction) and increase the density of crystal nucleus formation, so that the first metal silicide layer 1141 and the second metal silicide layer 1142 are more uniform and thicker. The ions are selected without changing the conductivity of the source-drain doped layer 104 .

Specific implanted ions include: one or two of Ge or Si.

The interlayer dielectric layer 105 is used to realize electrical isolation between adjacent semiconductor structures, therefore, the material of the interlayer dielectric layer 105 is an insulating material.

The interlayer dielectric layer 105 exposes the top wall of the gate structure 103 .

Specifically, the material of the interlayer dielectric layer 105 is silicon oxide. Silicon oxide is a commonly used dielectric material with low cost, and has high process compatibility, which is beneficial to reduce the process difficulty and process cost of forming the interlayer dielectric layer 105, and the silicon oxide removal process is simple. In other embodiments, the material of the interlayer dielectric layer may also be one or more of silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride and silicon oxycarbonitride.

It should be noted that the substrate further includes: a dielectric layer 106 located on the interlayer dielectric layer 105 .

The dielectric layer 106 is used to realize electrical isolation between adjacent devices, and the material of the dielectric layer 106 is an insulating material.

In this embodiment, the material of the dielectric layer 106 is silicon oxide. Silicon oxide is a commonly used dielectric material with low cost, and has high process compatibility, which is beneficial to reduce the process difficulty and process cost of forming the dielectric layer 106, and the silicon oxide removal process is simple. In other embodiments, the material of the dielectric layer may also be other insulating materials such as silicon nitride or silicon oxynitride.

The contact hole plug 115 is not only used to realize the electrical connection within the semiconductor structure, but also used to realize the electrical connection between the semiconductor structures.

In this embodiment, the material of the conductive material is W. In other embodiments, the material of the conductive material may also be Al, Cu, Ag or Au.

The semiconductor structure may be formed using the forming methods described in the foregoing embodiments, or may be formed using other forming methods. For the specific description of the semiconductor structure described in this embodiment, reference may be made to the corresponding description in the preceding embodiments, and details will not be repeated here in this embodiment.

Although the embodiments of the present invention are disclosed above, the embodiments of the present invention are not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the embodiments of the present invention. Therefore, the protection scope of the embodiments of the present invention should be defined by the claims.

Claims (21)

1. A method for forming a semiconductor structure, comprising: A base is provided, the base includes a substrate, a gate structure on the substrate, a source-drain doped layer in the substrate on both sides of the gate structure and covering the side walls of the gate structure and an interlayer dielectric layer of the source-drain doped layer, and the interlayer dielectric layer exposes the top wall of the gate structure; forming an opening exposing the source-drain doped layer in the interlayer dielectric layer, the bottom of the opening includes a central region, and an edge region surrounding the central region; forming a first metal layer at the bottom of the opening; removing the first metal layer in the central area of the bottom of the opening to form an opening; A second metal layer is formed in the opening, the material diffusion capacity of the second metal layer is greater than the material diffusion capacity of the first metal layer, and the resistivity of the second metal layer corresponding to silicide is smaller than the The first metal layer corresponds to the resistivity of the silicide; Processing the first metal layer and the second metal layer to form a metal silicide layer, the first metal layer and the second metal layer correspond to the first metal silicide layer and the second metal silicide layer respectively; After forming the metal silicide layer, a contact hole plug is formed in the opening. 2. The method for forming a semiconductor structure according to claim 1, wherein the material of the first metal layer comprises: Ti. 3. The method for forming a semiconductor structure according to claim 1, wherein the thickness of the first metal layer is 2 nm to 8 nm. 4. The method for forming a semiconductor structure according to claim 1, wherein the first metal layer is formed at the bottom of the opening by atomic layer deposition or low pressure chemical vapor deposition. 5 . The method for forming a semiconductor structure according to claim 1 , wherein the width of the second metal layer is 10 nanometers to 20 nanometers perpendicular to the sidewall direction of the gate structure. 6. The method for forming a semiconductor structure according to claim 1, wherein the material of the second metal layer comprises: Ni. 7. The method for forming a semiconductor structure according to claim 1, wherein the second metal layer has a thickness of 2 nm to 8 nm. 8. The method for forming a semiconductor structure according to claim 1, wherein the second metal layer is formed in the opening by atomic layer deposition or low pressure chemical vapor deposition. 9. The method for forming a semiconductor structure according to claim 1, wherein the step of forming the opening comprises: forming a sacrificial layer on sidewalls of the opening; Using the sacrificial layer as a mask to remove the first metal layer exposed by the sacrificial layer to form the opening surrounded by the first metal layer and the source-drain doped layer; The method for forming the semiconductor structure further includes: removing the sacrificial layer after forming the opening and before forming the second metal layer; or removing the sacrificial layer after forming the metal silicide layer. 10 . The method for forming a semiconductor structure according to claim 9 , wherein the material of the sacrificial layer comprises one or more of low-K materials, metal compounds, amorphous carbon and amorphous germanium. 11 . 11. The method for forming a semiconductor structure according to claim 10, wherein the metal compound is an Al compound. 12. The method for forming a semiconductor structure according to claim 1, wherein, in a direction perpendicular to the sidewall of the gate structure, the ratio of the length of the first metal layer to the length of the second metal layer is 2 to 3. 13. The method for forming a semiconductor structure according to claim 1, wherein the first metal layer and the second metal layer are processed by a salicide process to form the first metal layer and the second metal layer respectively. a metal silicide layer and the second metal silicide layer. 14. The method for forming a semiconductor structure according to claim 1, wherein the substrate is a substrate with fins; The gate structure spans the fin and covers part of the top and side walls of the fin; The source-drain doped layer is located in the fins on both sides of the gate structure. 15. A semiconductor structure, characterized in that, comprising: substrate, a gate structure located on the substrate; a source-drain doped layer located in the substrate on both sides of the gate structure; an interlayer dielectric layer covering the gate structure and the source-drain doped layer, and the interlayer dielectric layer exposes the top surface of the gate structure; a contact hole plug that penetrates the interlayer dielectric layer and is used for electrical connection with the source-drain doped layer, the contact hole plug includes a central region, and an edge region surrounding the central region; A metal silicide layer, located between the source-drain doped layer and the contact hole plug, the metal silicide layer includes a first metal silicide layer and a second metal silicide layer; the first metal silicide layer , located between the source-drain doped layer and the edge region of the contact hole plug; the second metal silicide layer, located between the source-drain doped layer and the center region of the contact hole plug; the second The resistance value of the metal silicide layer is lower than the resistance value of the first metal silicide layer, and the material diffusion ability of the second metal silicide layer corresponding to the metal is greater than the material diffusion ability of the first metal silicide layer corresponding to the metal . 16. The semiconductor structure of claim 15, wherein the first metal silicide layer comprises: titanium silicon compound. 17. The semiconductor structure according to claim 15, wherein the thickness of the first metal silicide layer is 2 nm to 16 nm. 18. The semiconductor structure of claim 15, wherein the second metal silicide layer comprises: nickel silicon compound. 19. The semiconductor structure according to claim 15, wherein the thickness of the second metal silicide layer is 2 nm to 16 nm. 20. The semiconductor structure according to claim 15, wherein in a direction perpendicular to the sidewall of the gate structure, the ratio of the length of the first metal silicide layer to the length of the second metal silicide layer is 2 to 3. 21 . The semiconductor structure according to claim 15 , wherein, in a direction perpendicular to the sidewall of the gate structure, the width of the second metal silicide layer is 10 nanometers to 20 nanometers.

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