KR102554708B1 - Semiconductor device - Google Patents

Abstract

The present invention relates to a semiconductor device, and more particularly, to a substrate including a first active region and a second active region; a first active pattern and a second active pattern on each of the first and second active regions; a first gate electrode and a second gate electrode crossing the first and second active patterns, respectively; and a first gate insulating pattern interposed between the first active pattern and the first gate electrode and a second gate insulating pattern interposed between the second active pattern and the second gate electrode. The first gate insulating pattern includes a first dielectric pattern and a first ferroelectric pattern on the first dielectric pattern, the second gate insulating pattern includes a second dielectric pattern, and the transistor on the first active region The threshold voltage is different from the threshold voltage of the transistor on the second active region.

Description

Semiconductor device {Semiconductor device}

The present invention relates to a semiconductor device, and more particularly, to a semiconductor device including a field effect transistor and a manufacturing method thereof.

The semiconductor device includes an integrated circuit composed of MOS field effect transistors (Metal Oxide Semiconductor (MOS) FET). As the size and design rules of semiconductor devices are gradually reduced, the scale down of MOS field effect transistors is also gradually accelerating. As the size of MOS field effect transistors decreases, operating characteristics of semiconductor devices may deteriorate. Accordingly, various methods for forming a semiconductor device with better performance while overcoming limitations due to high integration of semiconductor devices are being studied.

An object to be solved by the present invention is to provide a semiconductor device including transistors having different threshold voltages.

According to the concept of the present invention, a semiconductor device includes a substrate including a first active region and a second active region; a first active pattern and a second active pattern on each of the first and second active regions; a first gate electrode and a second gate electrode crossing the first and second active patterns, respectively; and a first gate insulating pattern interposed between the first active pattern and the first gate electrode, and a second gate insulating pattern interposed between the second active pattern and the second gate electrode. The first gate insulating pattern includes a first dielectric pattern and a first ferroelectric pattern on the first dielectric pattern, the second gate insulating pattern includes a second dielectric pattern, and the transistor on the first active region A threshold voltage may be different from a threshold voltage of a transistor on the second active region.

According to another concept of the present invention, a semiconductor device includes a substrate including a first active region and a second active region; a first active pattern and a second active pattern on each of the first and second active regions; a first gate electrode and a second gate electrode crossing the first and second active patterns, respectively; and a first gate insulating pattern interposed between the first active pattern and the first gate electrode, and a second gate insulating pattern interposed between the second active pattern and the second gate electrode. The first gate insulating pattern includes a first dielectric pattern and a first ferroelectric pattern on the first dielectric pattern, and the second gate insulating pattern includes a first dielectric pattern and a second ferroelectric pattern on the first dielectric pattern. At least one of a ferroelectric material, an impurity concentration, and a thickness of the first ferroelectric pattern may be different from that of the second ferroelectric pattern.

According to another concept of the present invention, a semiconductor device includes a substrate including a first active region and a second active region; a first active pattern and a second active pattern on each of the first and second active regions; a first gate electrode and a second gate electrode crossing the first and second active patterns, respectively; a gate spacer on a sidewall of each of the first and second gate electrodes; a first dielectric pattern and a first ferroelectric pattern interposed between the first gate electrode and the gate spacer; and a second dielectric pattern interposed between the second gate electrode and the gate spacer.

In the semiconductor device according to the present invention, a threshold voltage swing characteristic of a transistor may be improved and an operating voltage may be reduced. A semiconductor device according to the present invention may provide transistors having different threshold voltages according to regions by using a ferroelectric pattern of a gate insulating pattern.

1 is a plan view illustrating a semiconductor device according to example embodiments.
2A is a cross-sectional view taken along lines A-A' and B-B' of FIG. 1, FIG. 2B is a cross-sectional view taken along lines C-C' and D-D' of FIG. 1, and FIG. 2C is a cross-sectional view of FIG. It is a cross-sectional view taken along the line E-E', and FIG. 2d is a cross-sectional view taken along the line F-F' in FIG.
3, 5, 7, and 9 are plan views illustrating a method of manufacturing a semiconductor device according to example embodiments.
4, 6a, and 8a are cross-sectional views taken along lines A-A' of FIGS. 3, 5, and 7, respectively.
6B, 8B, and 10B are cross-sectional views taken along line BB′ of FIGS. 5, 7, and 9, respectively.
6c, 8c, and 10c are cross-sectional views taken along line C-C′ of FIGS. 5, 7, and 9, respectively.
10A is a cross-sectional view taken along lines A-A' and B-B' of FIG. 9, FIG. 10B is a cross-sectional view taken along lines C-C' and D-D' of FIG. 1, and FIG. 10C is a cross-sectional view of FIG. It is a cross-sectional view taken along line E-E', and FIG. 10D is a cross-sectional view taken along line F-F' in FIG.
11 to 15 are cross-sectional views taken along lines -A' and BB' of FIG. 1 to describe a semiconductor device according to embodiments of the present invention.
16 is a plan view for explaining a semiconductor device according to example embodiments.
17A is a cross-sectional view taken along lines A-A' and B-B' of FIG. 16, FIG. 17B is a cross-sectional view taken along line C-C' of FIG. 16, and FIG. 17C is a cross-sectional view taken along line D-D' of FIG. It is a cross-section along

1 is a plan view illustrating a semiconductor device according to example embodiments. 2A is a cross-sectional view taken along lines A-A' and B-B' of FIG. 1, FIG. 2B is a cross-sectional view taken along lines C-C' and D-D' of FIG. 1, and FIG. 2C is a cross-sectional view of FIG. It is a cross-sectional view taken along the line E-E', and FIG. 2d is a cross-sectional view taken along the line F-F' in FIG.

Referring to FIGS. 1 and 2A to 2D , a substrate 100 including a first PMOSFET region PR1 , a second PMOSFET region PR2 , a first NMOSFET region NR1 , and a second NMOSFET region NR2 this can be provided. The substrate 100 may be a semiconductor substrate including silicon, germanium, silicon-germanium, or the like, or a compound semiconductor substrate. For example, the substrate 100 may be a silicon substrate.

In an embodiment, the first and second PMOSFET regions PR1 and PR2 and the first and second NMOSFET regions NR1 and NR2 may be logic cell regions in which logic transistors constituting a logic circuit of a semiconductor device are disposed. can For example, logic transistors constituting a logic circuit may be disposed on the logic cell region of the substrate 100 . The first and second PMOSFET regions PR1 and PR2 and the first and second NMOSFET regions NR1 and NR2 may include some of the logic transistors.

First and second PMOSFET regions PR1 and PR2 and first and second NMOSFET regions NR1 and NR2 may be defined by the second trench TR2 formed on the upper surface of the substrate 100 . A second trench TR2 may be positioned between the first PMOSFET region PR1 and the first NMOSFET region NR1 and between the second PMOSFET region PR2 and the second NMOSFET region NR2. The first PMOSFET region PR1 and the first NMOSFET region NR1 may be spaced apart from each other in the first direction D1 with the second trench TR2 therebetween. The second PMOSFET region PR2 and the second NMOSFET region NR2 may be spaced apart from each other in the first direction D1 with the second trench TR2 therebetween. The first PMOSFET region PR1 and the second PMOSFET region PR2 may be spaced apart from each other in the second direction D2. The first NMOSFET region NR1 and the second NMOSFET region NR2 may be spaced apart from each other in the second direction D2.

First active patterns AP1 may be provided on the first and second PMOSFET regions PR1 and PR2 . Second active patterns AP2 may be provided on the first and second NMOSFET regions NR1 and NR2 . The first and second active patterns AP1 and AP2 may extend in the second direction D2. The first and second active patterns AP1 and AP2 are parts of the substrate 100 and may be vertically protruding portions. A first trench TR1 may be defined between the first active patterns AP1 adjacent to each other and between the second active patterns AP2 adjacent to each other. The first trench TR1 may be shallower than the second trench TR2.

An isolation layer ST may fill the first and second trenches TR1 and TR2 . The device isolation layer ST may include a silicon oxide layer. Upper portions of the first and second active patterns AP1 and AP2 may vertically protrude from the device isolation layer ST (see FIG. 2C ). Each of upper portions of the first and second active patterns AP1 and AP2 may have a fin shape. The device isolation layer ST may not cover upper portions of the first and second active patterns AP1 and AP2 . The device isolation layer ST may cover lower sidewalls of the first and second active patterns AP1 and AP2 .

First source/drain patterns SD1 may be provided on upper portions of the first active patterns AP1 . The first source/drain patterns SD1 may be impurity regions of a first conductivity type (eg, p-type). A first channel region CH1 may be interposed between the pair of first source/drain patterns SD1. Second source/drain patterns SD2 may be provided on upper portions of the second active patterns AP2 . The second source/drain patterns SD2 may be impurity regions of a second conductivity type (eg, n-type). A second channel region CH2 may be interposed between the pair of second source/drain patterns SD2.

The first and second source/drain patterns SD1 and SD2 may be epitaxial patterns formed through a selective epitaxial growth process. Top surfaces of the first and second source/drain patterns SD1 and SD2 may be positioned at a higher level than top surfaces of the first and second channel regions CH1 and CH2 . For example, the first source/drain patterns SD1 may include a semiconductor element (eg, SiGe) having a lattice constant greater than that of the semiconductor element of the substrate 100 . Thus, the first source/drain patterns SD1 may provide compressive stress to the first channel regions CH1. For example, the second source/drain patterns SD2 may include the same semiconductor element (eg, Si) as the substrate 100 .

A first gate electrode GE1 and a second gate electrode GE2 may be provided to cross the first and second active patterns AP1 and AP2 and extend in the first direction D1 . The first gate electrode GE1 may cross the first PMOSFET region PR1 and the first NMOSFET region NR1. The second gate electrode GE2 may cross the second PMOSFET region PR2 and the second NMOSFET region NR2. The first gate electrode GE1 and the second gate electrode GE2 may be spaced apart from each other in the second direction D2.

Each of the first and second gate electrodes GE1 and GE2 may vertically overlap the first and second channel regions CH1 and CH2 . Each of the first and second gate electrodes GE1 and GE2 may surround the top surface and both sidewalls of each of the first and second channel regions CH1 and CH2 (see FIG. 2C ).

A pair of gate spacers GS may be disposed on both sidewalls of each of the first and second gate electrodes GE1 and GE2 . The gate spacers GS may extend in the first direction D1 along the first and second gate electrodes GE1 and GE2 . Top surfaces of the gate spacers GS may be higher than top surfaces of the first and second gate electrodes GE1 and GE2 . Top surfaces of the gate spacers GS may be coplanar with a top surface of the first interlayer insulating layer 110 to be described later. The gate spacers GS may include at least one of SiCN, SiCON, and SiN. As another example, the gate spacers GS may include a multi-layer made of at least two of SiCN, SiCON, and SiN.

Gate capping patterns GP may be provided on the first and second gate electrodes GE1 and GE2, respectively. The gate capping patterns GP may extend in the first direction D1 along the first and second gate electrodes GE1 and GE2 . The gate capping patterns GP may include a material having etch selectivity with respect to the first and second interlayer insulating layers 110 and 120 to be described later. Specifically, the gate capping patterns GP may include at least one of SiON, SiCN, SiCON, and SiN.

A first gate insulating pattern GI1 may be interposed between the first gate electrode GE1 and the first active pattern AP1 and between the first gate electrode GE1 and the second active pattern AP2. A first gate insulating pattern GI1 may be interposed between the first gate electrode GE1 and the spacers GS. A second gate insulating pattern GI2 may be interposed between the second gate electrode GE2 and the first active pattern AP1 and between the second gate electrode GE2 and the second active pattern AP2. A second gate insulating pattern GI2 may be interposed between the second gate electrode GE2 and the spacers GS.

The first and second gate insulating patterns GI1 and GI2 may extend along bottom surfaces of the first and second gate electrodes GE1 and GE2 , respectively. Each of the first and second gate insulating patterns GI1 and GI2 may cover the upper surface and both sidewalls of the first channel region CH1 . Each of the first and second gate insulating patterns GI1 and GI2 may cover the upper surface and both sidewalls of the second channel region CH2 . The first and second gate insulating patterns GI1 and GI2 may cover the top surface of the device isolation layer ST below the first and second gate electrodes GE1 and GE2 (see FIG. 2C ).

The first gate insulating pattern GI1 may include a dielectric pattern DE and a ferroelectric pattern FE on the dielectric pattern DE. A thickness of the ferroelectric pattern FE may be greater than or equal to a thickness of the dielectric pattern DE.

The dielectric pattern DE according to the present invention may function as a positive capacitor (positive capacitor). The dielectric pattern DE may include a silicon oxide layer, a high dielectric constant layer, or a multilayer in which a silicon oxide layer and a high dielectric constant layer are sequentially stacked. For example, the high-k film may include hafnium oxide, hafnium silicon oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, lithium oxide, aluminum oxide, and lead. It may include at least one of scandium tantalum oxide and lead zinc niobate.

The ferroelectric pattern FE according to the present invention may function as a negative capacitor (negative capacitor). For example, when an external voltage is applied to the ferroelectric pattern FE, a negative capacitance effect due to a phase change from an initial polar state to another state due to movement of dipoles inside the ferroelectric pattern FE ( negative capacitance effect). In this case, the total capacitance of the transistor of the present invention including the ferroelectric pattern FE may increase, and accordingly, the sub-threshold swing characteristics of the transistor may be improved and the operating voltage may be reduced.

The ferroelectric pattern FE may include hafnium oxide doped with (or containing) at least one of zirconium (Zr), silicon (Si), aluminum (Al), and lanthanum (La). By doping hafnium oxide with at least one of zirconium (Zr), silicon (Si), aluminum (Al), and lanthanum (La) in a predetermined ratio, at least a portion of the ferroelectric pattern FE has an orthorhombic crystal structure ) can have. When at least a portion of the ferroelectric pattern FE has an orthorhombic crystal structure, a negative capacitance effect may occur. A volume ratio of a portion having an orthorhombic crystal structure in the ferroelectric pattern FE may be 10% to 50%.

When the ferroelectric pattern FE includes zirconium-doped hafnium oxide (ZrHfO), the ratio of Zr atoms (Zr/(Hf+Zr)) among all Zr and Hf atoms may be 45 at% to 55 at%. there is. When the ferroelectric pattern FE includes silicon-doped hafnium oxide (SiHfO), the ratio of Si atoms (Si/(Hf+Si)) among all Si and Hf atoms may be 4 at% to 6 at%. there is. When the ferroelectric pattern FE includes aluminum-doped hafnium oxide (AlHfO), the ratio of Al atoms (Al/(Hf+Al)) among all Al and Hf atoms may be 5 at% to 10 at%. there is. When the ferroelectric pattern FE includes hafnium oxide (LaHfO) doped with lanthanum, the ratio of La atoms (La/(Hf+La)) among all La and Hf atoms may be 5 at% to 10 at% there is.

The second gate insulating pattern GI2 may include a dielectric pattern DE. The second gate insulating pattern GI2 may include a dielectric pattern DE. In other words, the second gate insulating pattern GI2 may not include the ferroelectric pattern FE.

Each of the first and second gate electrodes GE1 and GE2 may include a first work function metal pattern WF1, a second work function metal pattern WF2, and an electrode pattern EL that are sequentially stacked. there is. The first work function metal pattern WF1 may be provided on the ferroelectric pattern FE. In other words, the ferroelectric pattern FE may be interposed between the first work function metal pattern WF1 and the first and second channel regions CH1 and CH2.

The first work function metal pattern WF1 may include a metal nitride layer, for example, a titanium nitride layer (TiN) or a tantalum nitride layer (TaN). The second work function metal pattern WF2 may include metal carbide doped with (or containing) aluminum or silicon. For example, the second work function metal pattern WF2 may include TiAlC, TaAlC, TiSiC, or TaSiC. The electrode pattern EL may have lower resistance than the first work function metal pattern WF1 and the second work function metal pattern WF2 . For example, the electrode pattern EL may include at least one low-resistance metal among aluminum (Al), tungsten (W), titanium (Ti), and tantalum (Ta).

The thickness of the first work function metal pattern WF1 on the first and second PMOSFET regions PR1 and PR2 shown in FIG. 2A is the thickness of the first and second NMOSFET regions NR1 and NR2 shown in FIG. 2 . It may be thicker than the thickness of the 1 work function metal pattern WF1. The thickness of the second work function metal pattern WF2 on the first and second NMOSFET regions NR1 and NR2 shown in FIG. 2 is the first and second work function metal pattern WF2 on the first and second PMOSFET regions PR1 and PR2 shown in FIG. 2A. It may be thicker than the thickness of the 1 work function metal pattern WF1.

A first interlayer insulating film 110 may be provided on the substrate 100 . The first interlayer insulating layer 110 may cover the gate spacers GS and the first and second source/drain patterns SD1 and SD2 . A top surface of the first interlayer insulating layer 110 may be substantially coplanar with top surfaces of the gate capping patterns GP and top surfaces of the gate spacers GS. A second interlayer insulating layer 120 covering the gate capping patterns GP may be disposed on the first interlayer insulating layer 110 . For example, the first and second interlayer insulating films 110 and 120 may include a silicon oxide film.

Active contacts AC adjacent to both sides of each of the first and second gate electrodes GE1 and GE2 may be provided. The active contacts AC may be electrically connected to the first and second source/drain patterns SD1 and SD2 through the first and second interlayer insulating layers 110 and 120 . The active contacts AC may include at least one of metal materials such as aluminum, copper, tungsten, molybdenum, and cobalt.

A silicide layer (not shown) may be interposed between the first and second source/drain patterns SD1 and SD2 and the active contact AC. The active contact AC may be electrically connected to the first and second source/drain patterns SD1 and SD2 through the silicide layer. The silicide layer may include metal-silicide, and for example, may include at least one of titanium-silicide, tantalum-silicide, tungsten-silicide, nickel-silicide, and cobalt-silicide.

Gate contacts GC electrically connected to the first and second gate electrodes GE1 and GE2 on the second isolation layer ST2 through the second interlayer insulating layer 120 and the gate capping pattern GP. ) can be placed. The gate contacts GC may include the same metal material as the active contacts AC.

According to example embodiments, a ferroelectric pattern FE may be provided between the gate electrode and the channel region. The ferroelectric pattern FE may generate a negative capacitance effect by including an orthorhombic crystal structure. As a result, the threshold voltage swing characteristics of the transistor may be improved and the operating voltage may be reduced.

According to example embodiments, the second gate insulating pattern GI2 includes only the dielectric pattern DE, and the first gate insulating pattern GI1 includes not only the dielectric pattern DE but also the ferroelectric pattern FE. can be included with Thus, the threshold voltage of the transistor on the first PMOSFET region PR1 may be different from the threshold voltage of the transistor on the second PMOSFET region PR2. The threshold voltage of the transistor on the first NMOSFET region NR1 may be different from the threshold voltage of the transistor on the second NMOSFET region NR2. As a result, by changing the layers constituting the gate insulating pattern differently according to the region, the threshold voltage of the transistor can be set differently according to the region.

3, 5, 7, and 9 are plan views illustrating a method of manufacturing a semiconductor device according to example embodiments. 4, 6a, and 8a are cross-sectional views taken along lines A-A' of FIGS. 3, 5, and 7, respectively. 6B, 8B, and 10B are cross-sectional views taken along line BB′ of FIGS. 5, 7, and 9, respectively. 6c, 8c, and 10c are cross-sectional views taken along line C-C′ of FIGS. 5, 7, and 9, respectively. 10A is a cross-sectional view taken along lines A-A' and B-B' of FIG. 9, FIG. 10B is a cross-sectional view taken along lines C-C' and D-D' of FIG. 1, and FIG. 10C is a cross-sectional view of FIG. It is a cross-sectional view taken along line E-E', and FIG. 10D is a cross-sectional view taken along line F-F' in FIG.

3 and 4, a substrate 100 including a first PMOSFET region PR1, a second PMOSFET region PR2, a first NMOSFET region NR1, and a second NMOSFET region NR2 is provided. can By patterning the substrate 100 , first and second active patterns AP1 and AP2 may be formed. First active patterns AP1 may be formed on the first and second PMOSFET regions PR1 and PR2, and second active patterns AP1 may be formed on the first and second NMOSFET regions NR1 and NR2. AP2) can be formed. A first trench TR1 may be formed between the first active patterns AP1 and between the second active patterns AP2 .

The substrate 100 is patterned to form a second trench TR2 between the first PMOSFET region PR1 and the first NMOSFET region NR1 and between the second PMOSFET region PR2 and the second NMOSFET region NR2. It can be. The second trench TR2 may be formed deeper than the first trench TR1.

An isolation layer ST may be formed on the substrate 100 to fill the first and second trenches TR1 and TR2 . The device isolation layer ST may include an insulating material such as a silicon oxide layer. The device isolation layer ST may be recessed until upper portions of the first and second active patterns AP1 and AP2 are exposed. Thus, upper portions of the first and second active patterns AP1 and AP2 may protrude vertically above the isolation layer ST.

5 and 6A to 6C , a first sacrificial pattern PP1 and a second sacrificial pattern PP2 crossing the first and second active patterns AP1 and AP2 may be formed. The first sacrificial pattern PP1 may cross the first PMOSFET region PR1 and the first NMOSFET region NR1, and the second sacrificial pattern PP2 may cross the second PMOSFET region PR2 and the second NMOSFET region ( NR2) can be crossed. The first and second sacrificial patterns PP1 and PP2 may be formed in a line shape or bar shape extending in the first direction D1 .

Specifically, forming the first and second sacrificial patterns PP1 and PP2 includes forming a sacrificial layer on the entire surface of the substrate 100 and forming hard mask patterns MA on the sacrificial layer. and patterning the sacrificial layer using hard mask patterns MA as an etch mask. The sacrificial layer may include a polysilicon layer.

A pair of gate spacers GS may be formed on both sidewalls of each of the first and second sacrificial patterns PP1 and PP2 . Gate spacers GS may also be formed on both sidewalls of each of the first and second active patterns AP1 and AP2 . Both sidewalls of each of the first and second active patterns AP1 and AP2 may be exposed portions that are not covered by the device isolation layer ST and the sacrificial patterns PP.

Forming the gate spacers GS may include conformally forming a gate spacer layer on the entire surface of the substrate 100 and anisotropically etching the gate spacer layer. The gate spacer layer may include at least one of SiCN, SiCON, and SiN. As another example, the gate spacer layer may be a multi-layer including at least two of SiCN, SiCON, and SiN.

Referring to FIGS. 7 and 8A to 8C , first source/drain patterns SD1 may be formed on each of the first active patterns AP1. A pair of first source/drain patterns SD1 may be formed on both sides of each of the first and second sacrificial patterns PP1 and PP2 .

Specifically, first recess regions may be formed by etching upper portions of the first active patterns AP1 using the hard mask patterns MA and the gate spacers GS as an etch mask. While the upper portions of the first active patterns AP1 are etched, the gate spacers GS on both sidewalls of each of the first active patterns AP1 may be removed together. While the upper portions of the first active patterns AP1 are being etched, the device isolation layer ST between the first active patterns AP1 may be recessed.

By performing a selective epitaxial growth process using the inner walls of the first recess regions of the first active patterns AP1 as a seed layer, the first source/drain patterns ( SD1) can be formed. As the first source/drain patterns SD1 are formed, a first channel region CH1 may be defined between the pair of first source/drain patterns SD1. For example, the selective epitaxial growth process may include a chemical vapor deposition (CVD) process or a molecular beam epitaxy (MBE) process. The first source/drain patterns SD1 may include a semiconductor element (eg, SiGe) having a lattice constant greater than that of the semiconductor element of the substrate 100 . Each of the first source/drain patterns SD1 may be formed of multiple semiconductor layers.

For example, impurities may be implanted in-situ during a selective epitaxial growth process for forming the first source/drain patterns SD1 . As another example, impurities may be implanted into the first source/drain patterns SD1 after the first source/drain patterns SD1 are formed. The first source/drain patterns SD1 may be doped to have a first conductivity type (eg, p-type).

Second source/drain patterns SD2 may be formed on each of the second active patterns AP2 . A pair of second source/drain patterns SD2 may be formed on both sides of each of the sacrificial patterns PP.

Specifically, second recess regions may be formed by etching upper portions of the second active patterns AP2 using the hard mask patterns MA and the gate spacers GS as an etch mask. Second source/drain patterns SD2 may be formed by performing a selective epitaxial growth process using inner walls of the second recess regions of the second active patterns AP2 as seed layers. As the second source/drain patterns SD2 are formed, a second channel region CH2 may be defined between the pair of second source/drain patterns SD2. For example, the second source/drain patterns SD2 may include the same semiconductor element (eg, Si) as the substrate 100 . The second source/drain patterns SD2 may be doped to have a second conductivity type (eg, n-type).

The first source/drain patterns SD1 and the second source/drain patterns SD2 may be sequentially formed through different processes. In other words, the first source/drain patterns SD1 and the second source/drain patterns SD2 may not be formed at the same time.

9 and 10A to 10D , the first interlayer insulating layer 110 covers the first and second source/drain patterns SD1 and SD2, the hard mask patterns MA, and the gate spacers GS. ) can be formed. For example, the first interlayer insulating film 110 may include a silicon oxide film.

The first interlayer insulating layer 110 may be planarized until top surfaces of the first and second sacrificial patterns PP1 and PP2 are exposed. Planarization of the first interlayer insulating layer 110 may be performed using an etch back or chemical mechanical polishing (CMP) process. During the planarization process, all of the hard mask patterns MA may be removed. As a result, the top surface of the first interlayer insulating layer 110 may be coplanar with the top surfaces of the first and second sacrificial patterns PP1 and PP2 and the top surfaces of the gate spacers GS.

The first and second sacrificial patterns PP1 and PP2 may be replaced with the first and second gate electrodes GE1 and GE2, respectively. Specifically, the exposed first and second sacrificial patterns PP1 and PP2 may be selectively removed. By removing the first and second sacrificial patterns PP1 and PP2 , a first empty space ET1 and a second empty space ET2 may be formed, respectively.

A first gate insulating pattern GI1 and a first gate electrode GE1 may be formed in the first empty space ET1. Forming the first gate insulating pattern GI1 may include sequentially forming a dielectric pattern DE and a ferroelectric pattern FE partially filling the first empty space ET1 . The dielectric pattern DE may include a silicon oxide layer, a high dielectric constant layer, or a multilayer in which a silicon oxide layer and a high dielectric constant layer are sequentially stacked. The ferroelectric pattern FE may be formed using hafnium oxide doped with (or containing) at least one of zirconium (Zr), silicon (Si), aluminum (Al), and lanthanum (La). Forming the first gate electrode GE1 means sequentially forming the first work function metal pattern WF1, the second work function metal pattern WF2, and the electrode pattern EL on the ferroelectric pattern FE. can include

A second gate insulating pattern GI2 and a second gate electrode GE2 may be formed in the second empty space ET2 . Forming the second gate insulating pattern GI2 may include forming a dielectric pattern DE partially filling the first empty space ET1 . Forming the second gate electrode GE2 means sequentially forming the first work function metal pattern WF1, the second work function metal pattern WF2, and the electrode pattern EL on the dielectric pattern DE. can include

After the first and second gate electrodes GE1 and GE2 are formed in the first and second empty spaces ET1 and ET2, a planarization process is performed until the upper surface of the first interlayer insulating film 110 is exposed. It can be.

Referring back to FIGS. 1 and 2A to 2D , a second interlayer insulating film 120 may be formed on the first interlayer insulating film 110 . The second interlayer insulating layer 120 may include a silicon oxide layer or a low-k oxide layer. For example, the low-k oxide layer may include a silicon oxide layer doped with carbon such as SiCOH. The second interlayer insulating film 120 may be formed by a CVD process.

Active contacts AC electrically connected to the first and second source/drain patterns SD1 and SD2 may be formed through the second interlayer insulating layer 120 and the first interlayer insulating layer 110 . Gate contacts GC electrically connected to the first and second gate electrodes GE1 and GE2 on the second isolation layer ST2 through the second interlayer insulating layer 120 and the gate capping pattern GP. ) can be formed.

11 to 16 are cross-sectional views taken along lines -A' and BB' of FIG. 1 to describe a semiconductor device according to example embodiments. In this embodiment, detailed descriptions of technical features overlapping with those previously described with reference to FIGS. 1 and 2A to 2D will be omitted, and differences will be described in detail.

1 and 11, the top of the first work function metal pattern WF1 is chamfered so that the top surface WF1t of the first work function metal pattern WF1 is the top surface ELt of the electrode pattern EL. can be lower than The second work function metal pattern WF2 may cover the top surface WF1t of the first work function metal pattern WF1 . As the upper portion of the first work function metal pattern WF1 is chamfered, the width of the upper portion of the electrode pattern EL may be increased.

1 and 12 , the first gate insulating pattern GI1 may include a dielectric pattern DE and a first ferroelectric pattern FE1, and the second gate insulating pattern GI2 may include a dielectric pattern DE. ) and a second ferroelectric pattern FE2.

The first ferroelectric pattern FE1 and the second ferroelectric pattern FE2 may include different ferroelectric materials. For example, the first ferroelectric pattern FE1 may include hafnium oxide doped with zirconium, and the second ferroelectric pattern FE2 may include hafnium oxide doped with aluminum.

The first ferroelectric pattern FE1 and the second ferroelectric pattern FE2 may include the same ferroelectric material. However, the impurity concentration in the first ferroelectric pattern FE1 and the impurity concentration in the second ferroelectric pattern FE2 may be different from each other. For example, the first ferroelectric pattern FE1 and the second ferroelectric pattern FE2 may include hafnium oxide doped with zirconium, and in this case, Zr/(Hf+Zr) of the first ferroelectric pattern FE1 is 45 at %, and Zr/(Hf+Zr) of the second ferroelectric pattern FE2 may be 55 at%.

The first ferroelectric pattern FE1 and the second ferroelectric pattern FE2 may have substantially the same thickness as each other. Alternatively, the first ferroelectric pattern FE1 and the second ferroelectric pattern FE2 may have different thicknesses.

1 and 13 , the first gate insulating pattern GI1 may include a dielectric pattern DE, a first ferroelectric pattern FE1 and a second ferroelectric pattern FE2, and the second gate insulating pattern (GI2) may include a dielectric pattern (DE) and a second ferroelectric pattern (FE2). The second ferroelectric pattern FE2 of the first gate insulating pattern GI1 may be interposed between the first work function metal pattern WF1 and the first ferroelectric pattern FE1. Descriptions of the first ferroelectric pattern FE1 and the second ferroelectric pattern FE2 may be substantially the same as those previously described with reference to FIG. 12 .

Referring to FIGS. 1 and 14 , each of the first and second gate insulating patterns GI1 and GI2 may include a dielectric pattern DE and a ferroelectric pattern FE. The ferroelectric pattern FE of the first gate insulating pattern GI1 and the ferroelectric pattern FE of the second gate insulating pattern GI2 may include the same ferroelectric material. Concentrations of impurities in the ferroelectric pattern FE of the first gate insulating pattern GI1 and concentrations of impurities in the ferroelectric pattern FE of the second gate insulating pattern GI2 may be equal to each other.

The ferroelectric pattern FE of the first gate insulating pattern GI1 may have a first thickness T1, and the ferroelectric pattern FE of the second gate insulating pattern GI2 may have a second thickness T2. there is. The first thickness T1 may be greater than the second thickness T2.

1 and 15 , the first gate electrode GE1 may further include a barrier pattern BM interposed between the first gate insulating pattern GI1 and the first work function metal pattern WF1. . The second gate electrode GE2 may further include a barrier pattern BM interposed between the second gate insulating pattern GI2 and the first work function metal pattern WF1. The barrier pattern BM may prevent diffusion of a metal element between the first work function metal pattern WF1 and the gate insulating patterns GI1 and GI2. For example, the barrier pattern BM may include TiN, TaC, TaN, TiSiN, TaTiN, TaSiN, or a combination thereof (multilayer).

16 is a plan view for explaining a semiconductor device according to example embodiments. 17A is a cross-sectional view taken along lines A-A' and B-B' of FIG. 16, FIG. 17B is a cross-sectional view taken along line C-C' of FIG. 16, and FIG. 17C is a cross-sectional view taken along line D-D' of FIG. It is a cross-section along In this embodiment, detailed descriptions of technical features overlapping with those previously described with reference to FIGS. 1 and 2A to 2D will be omitted, and differences will be described in detail.

Referring to FIGS. 16 and 17A to 17C , a substrate 100 including a first active region AR1 and a second active region AR2 may be provided. Active patterns AP may be provided on the first and second active regions AR1 and AR2 . For example, the first and second active regions AR1 and AR2 may be logic cell regions. Logic transistors constituting a logic circuit may be disposed on the logic cell region.

An element isolation layer ST may be provided on the substrate 100 . The device isolation layer ST may define active patterns AP on the substrate 100 . The active patterns AP may have a line shape or a bar shape extending in the second direction D2 .

The device isolation layer ST may fill a trench TR between a pair of adjacent active patterns AP. A top surface of the device isolation layer ST may be lower than top surfaces of the active patterns AP.

Source/drain patterns SD and a channel pattern CHP interposed between a pair of adjacent source/drain patterns SD may be provided on the active pattern AP. The channel pattern CHP may include sequentially stacked first to third semiconductor patterns SP1 , SP2 , and SP3 . The first to third semiconductor patterns SP1 , SP2 , and SP3 may be spaced apart from each other in a third direction D3 perpendicular to the upper surface of the substrate 100 . The first to third semiconductor patterns SP1 , SP2 , and SP3 may vertically overlap each other. Each of the source/drain patterns SD may directly contact one sidewall of each of the first to third semiconductor patterns SP1 , SP2 , and SP3 . In other words, the first to third semiconductor patterns SP1 , SP2 , and SP3 may connect a pair of adjacent source/drain patterns SD.

The first to third semiconductor patterns SP1 , SP2 , and SP3 of the channel pattern CHP may have the same thickness or different thicknesses. For example, the first to third semiconductor patterns SP1 , SP2 , and SP3 of the channel pattern CHP may have different maximum lengths in the second direction D2 . For example, the maximum length of the first semiconductor pattern SP1 in the second direction D2 may be the first length. The maximum length of the second semiconductor pattern SP2 in the second direction D2 may be the second length. The first length may be greater than the second length.

The first to third semiconductor patterns SP1 , SP2 , and SP3 of the channel pattern CHP may include at least one of silicon (Si), germanium (Ge), and silicon-germanium (SiGe). The channel pattern CHP is illustrated as including first to third semiconductor patterns SP1 , SP2 , and SP3 , but the number of semiconductor patterns is not particularly limited.

Each of the source/drain patterns SD is an epitaxial pattern formed by using the first to third semiconductor patterns SP1 , SP2 , and SP3 of the channel pattern CHP and the active pattern AP as a seed layer. can For example, the source/drain pattern SD may have a maximum width in the second direction D2 at a middle portion thereof (see FIG. 17A ). A width of the source/drain pattern SD in the second direction D2 may increase from an upper portion thereof toward the middle portion. A width of the source/drain pattern SD in the second direction D2 may decrease from the middle portion to a lower portion thereof. The source/drain patterns SD may be p-type impurity regions or n-type impurity regions. For example, the source/drain patterns SD may include SiGe or Si.

A first gate electrode GE1 extending in the first direction D1 crossing the channel pattern CHP on the first active region AR1 and crossing the channel pattern CHP on the second active region AR2 A second gate electrode GE2 extending in the first direction D1 may be provided. The first and second gate electrodes GE1 and GE2 may be spaced apart from each other in the second direction D2. Each of the first and second gate electrodes GE1 and GE2 may vertically overlap the channel pattern CHP. A pair of gate spacers GS may be disposed on both sidewalls of each of the first and second gate electrodes GE1 and GE2 . Gate capping patterns GP may be provided on the first and second gate electrodes GE1 and GE2, respectively.

Each of the first and second gate electrodes GE1 and GE2 may include a first work function metal pattern WF1, a second work function metal pattern WF2, and an electrode pattern EL that are sequentially stacked. there is. The first work function metal pattern WF1 may surround each of the first to third semiconductor patterns SP1 , SP2 , and SP3 (see FIG. 17B ). In other words, the first work function metal pattern WF1 may surround the top and bottom surfaces and both sidewalls of each of the first to third semiconductor patterns SP1 , SP2 , and SP3 . That is, the transistors according to the present embodiment may be gate-all-around type field effect transistors.

A first gate insulating pattern GI1 may be provided between the first to third semiconductor patterns SP1 , SP2 , and SP3 and the first gate electrode GE1 . A second gate insulating pattern GI2 may be provided between the first to third semiconductor patterns SP1 , SP2 , and SP3 and the second gate electrode GE2 . The first gate insulating pattern GI1 may include a dielectric pattern DE and a ferroelectric pattern FE, and the second gate insulating pattern GI2 may include a dielectric pattern DE. The second gate insulating pattern GI2 may not include the ferroelectric pattern FE.

Each of the first and second gate insulating patterns GI1 and GI2 may surround the first to third semiconductor patterns SP1 , SP2 and SP3 . Each of the first and second gate insulating patterns GI1 and GI2 may be interposed between an upper portion of the active pattern AP and the first work function metal pattern WF1. Each of the first and second gate insulating patterns GI1 and GI2 may be interposed between the device isolation layer ST and the first work function metal pattern WF1.

A detailed description of the dielectric pattern DE, the ferroelectric pattern FE, the first work function metal pattern WF1, the second work function metal pattern WF2, and the electrode pattern EL is shown in FIGS. 1 and 2A to 2A It may be substantially the same as that described with reference to FIG. 2d.

A first space SA1 may be defined between the first semiconductor pattern SP1 and the second semiconductor pattern SP2 on the first active region AR1. In other words, a first space SA1 may be defined between a pair of vertically adjacent semiconductor patterns SP1 , SP2 , and SP3 .

The dielectric pattern DE, the ferroelectric pattern FE, and the first work function metal pattern WF1 may fill the first space SA1. The dielectric pattern DE and the ferroelectric pattern FE may conformally fill the first space SA1 . The first work function metal pattern WF1 may completely fill the remaining area of the first space SA1 except for the first gate insulating pattern GI1. The second work function metal pattern WF2 and the electrode pattern EL may not fill the first space SA1. The first gate insulating pattern GI1 in the first space SA1 may contact the source/drain pattern SD (see FIG. 17A ). In other words, the first gate insulating pattern GI1 in the first space SA1 may be interposed between the first gate electrode GE1 and the source/drain pattern SD.

A second space SA2 may be defined on the uppermost semiconductor pattern on the first active region AR1, that is, on the third semiconductor pattern SP3. The second space SA2 may be a space surrounded by a pair of gate spacers GS, a gate capping pattern GP, and a third semiconductor pattern SP3.

The dielectric pattern DE, the ferroelectric pattern FE, the first work function metal pattern WF1 , the second work function metal pattern WF2 , and the electrode pattern EL may fill the second space SA2 . The shapes of the dielectric pattern DE, the ferroelectric pattern FE, the first work function metal pattern WF1, the second work function metal pattern WF2, and the electrode pattern EL filling the second space SA2 are as described above. It may be similar to that described with reference to FIGS. 1 and 2A to 2D.

A first interlayer insulating film 110 and a second interlayer insulating film 120 may be provided on the entire surface of the substrate 100 . Active contacts AC connected to the source/drain patterns SD may be provided through the first and second interlayer insulating layers 110 and 120 .

Although the embodiments of the present invention have been described with reference to the accompanying drawings, the present invention may be implemented in other specific forms without changing its technical spirit or essential features. Therefore, it should be understood that the embodiments described above are illustrative in all respects and not restrictive.

Claims (20)

a substrate including a first active region and a second active region;
a first active pattern and a second active pattern on each of the first and second active regions;
a device isolation layer filling the trench defining the first and second active patterns;
a first gate electrode and a second gate electrode crossing the first and second active patterns, respectively; and
A first gate insulating pattern interposed between the first active pattern and the first gate electrode and a second gate insulating pattern interposed between the second active pattern and the second gate electrode,
The first gate insulating pattern includes a first dielectric pattern and a first ferroelectric pattern on the first dielectric pattern;
The second gate insulating pattern includes a second dielectric pattern,
The threshold voltage of the transistor on the first active region is different from the threshold voltage of the transistor on the second active region;
An upper portion of each of the first and second active patterns protrudes vertically above the isolation layer,
The first ferroelectric pattern is provided on an upper surface and both sidewalls of the upper portion of the first active pattern.
According to claim 1,
wherein the first ferroelectric pattern includes hafnium oxide containing at least one of zirconium (Zr), silicon (Si), aluminum (Al), and lanthanum (La).
According to claim 2,
The semiconductor device of claim 1 , wherein a volume ratio of a portion having an orthorhombic crystal structure in the first ferroelectric pattern is 10% to 50%.
According to claim 1,
The first and second dielectric patterns include a silicon oxide layer, a high dielectric constant layer, or a multilayer in which a silicon oxide layer and a high dielectric constant layer are sequentially stacked.
According to claim 1,
Each of the first and second gate electrodes includes a first work function metal pattern, a second work function metal pattern, and an electrode pattern sequentially stacked,
The first work function metal pattern includes a metal nitride layer,
The second work function metal pattern includes a metal carbide containing aluminum or silicon.
According to claim 5,
The upper surface of the first work function metal pattern is lower than the upper surface of the electrode pattern,
The second work function metal pattern covers the upper surface of the first work function metal pattern.
According to claim 1,
The second gate insulating pattern includes only the second dielectric pattern.
According to claim 1,
The second gate insulating pattern further includes a second ferroelectric pattern on the second dielectric pattern,
The ferroelectric material of the first ferroelectric pattern is different from the ferroelectric material of the second ferroelectric pattern.
According to claim 1,
The second gate insulating pattern further includes a second ferroelectric pattern on the second dielectric pattern,
A thickness of the first ferroelectric pattern is different from a thickness of the second ferroelectric pattern.
delete a substrate including a first active region and a second active region;
a first active pattern and a second active pattern on each of the first and second active regions;
a first gate electrode and a second gate electrode crossing the first and second active patterns, respectively; and
A first gate insulating pattern interposed between the first active pattern and the first gate electrode and a second gate insulating pattern interposed between the second active pattern and the second gate electrode,
The first gate insulating pattern includes a first dielectric pattern and a first ferroelectric pattern on the first dielectric pattern;
The second gate insulating pattern includes a first dielectric pattern and a second ferroelectric pattern on the first dielectric pattern;
At least one of the ferroelectric material and the impurity concentration of the first ferroelectric pattern is different from that of the second ferroelectric pattern.
According to claim 11,
A threshold voltage of a transistor on the first active region is different from a threshold voltage of a transistor on the second active region.
According to claim 11,
The first and second ferroelectric patterns include hafnium oxide doped with at least one of zirconium (Zr), silicon (Si), aluminum (Al), and lanthanum (La).
According to claim 11,
The first gate insulating pattern further includes a third ferroelectric pattern on the first ferroelectric pattern.
According to claim 11,
Further comprising a device isolation layer filling the trench defining the first and second active patterns,
An upper portion of each of the first and second active patterns protrudes vertically above the device isolation layer,
the first ferroelectric pattern is provided on an upper surface and both sidewalls of the upper portion of the first active pattern;
The second ferroelectric pattern is provided on an upper surface and both sidewalls of the upper portion of the second active pattern.
a substrate including a first active region and a second active region;
a first active pattern and a second active pattern on each of the first and second active regions;
a first gate electrode and a second gate electrode crossing the first and second active patterns, respectively;
a gate spacer on a sidewall of each of the first and second gate electrodes;
a first dielectric pattern and a first ferroelectric pattern interposed between the first gate electrode and the gate spacer; and
A second dielectric pattern interposed between the second gate electrode and the gate spacer,
The first gate electrode includes a work function metal pattern including a metal nitride film and an electrode pattern,
The first ferroelectric pattern is interposed between a sidewall of the work function metal and the first dielectric pattern.
According to claim 16,
A threshold voltage of a transistor on the first active region is different from a threshold voltage of a transistor on the second active region.
According to claim 16,
One sidewall of the second dielectric pattern directly contacts the gate spacer;
A sidewall opposite to the second dielectric pattern directly contacts the second gate electrode.
According to claim 16,
Further comprising a second ferroelectric pattern interposed between the second gate electrode and the gate spacer,
The ferroelectric material of the first ferroelectric pattern is different from the ferroelectric material of the second ferroelectric pattern.
According to claim 16,
Further comprising a second ferroelectric pattern interposed between the second gate electrode and the gate spacer,
A thickness of the first ferroelectric pattern is different from a thickness of the second ferroelectric pattern.

Images