CN116504784A

CN116504784A - Semiconductor device with a semiconductor device having a plurality of semiconductor chips

Info

Publication number: CN116504784A
Application number: CN202211221577.6A
Authority: CN
Inventors: 申东石; 刘贤琯; 李善英; 车知勳; 黄炅渊
Original assignee: Samsung Electronics Co Ltd
Current assignee: Samsung Electronics Co Ltd
Priority date: 2022-01-18
Filing date: 2022-10-08
Publication date: 2023-07-28

Abstract

A semiconductor device is disclosed. The semiconductor device includes: a substrate including an active pattern; a channel pattern on the active pattern and including a semiconductor pattern; a source/drain pattern connected to the semiconductor pattern; a gate electrode on the semiconductor pattern; and a gate dielectric layer between the gate electrode and the semiconductor pattern. The inner spacer of the gate dielectric layer includes a horizontal portion between the high-k dielectric layer and the second semiconductor pattern, a vertical portion between the high-k dielectric layer and the source/drain pattern, and a corner portion between the horizontal portion and the vertical portion. The first thickness of the horizontal portion is less than the second thickness of the vertical portion. The second thickness of the vertical portion is less than the third thickness of the corner portion.

Description

Semiconductor device with a semiconductor device having a plurality of semiconductor chips

The present application claims priority from korean patent application No. 10-2022-0007410 filed on 1 month 18 of 2022 and korean patent application No. 10-2022-0039763 filed on 3 months 30 of 2022, the disclosures of which are incorporated herein by reference in their entirety.

Technical Field

The present disclosure relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device including a field effect transistor and a method of manufacturing the same.

Background

The semiconductor device includes an integrated circuit including a Metal Oxide Semiconductor Field Effect Transistor (MOSFET). As the size and design rules of semiconductor devices have been progressively reduced, the size of MOSFETs has also been progressively reduced. The reduced size of the MOSFET may deteriorate the operation properties of the semiconductor device. Accordingly, various researches have been conducted to develop a method of manufacturing a semiconductor device having excellent performance while overcoming limitations caused by high integration of the semiconductor device.

Disclosure of Invention

It is an aspect to provide a semiconductor device having improved electrical properties.

Another aspect is to provide a method of manufacturing a semiconductor device having improved electrical properties.

According to aspects of some embodiments, a semiconductor apparatus may include: a substrate including an active pattern; a channel pattern on the active pattern, the channel pattern including a plurality of semiconductor patterns vertically stacked and spaced apart from each other; source/drain patterns connected to the plurality of semiconductor patterns; a gate electrode on the plurality of semiconductor patterns; and a gate dielectric layer between the gate electrode and the plurality of semiconductor patterns. The gate electrode may include a first portion between a first semiconductor pattern and a second semiconductor pattern that are adjacent semiconductor patterns among the plurality of semiconductor patterns. The gate dielectric layer may include a high-k dielectric layer surrounding a first portion of the gate electrode and an internal spacer on the high-k dielectric layer. The inner spacer may include: a horizontal portion having a first thickness between the high-k dielectric layer and the second semiconductor pattern; a vertical portion having a second thickness between the high-k dielectric layer and the source/drain pattern; and a corner portion having a third thickness between the horizontal portion and the vertical portion. The first thickness may be less than the second thickness, and the second thickness may be less than the third thickness.

According to another aspect of some embodiments, a semiconductor device may include: a substrate including an active pattern; a channel pattern on the active pattern, the channel pattern including a plurality of semiconductor patterns vertically stacked and spaced apart from each other; a pair of source/drain patterns on the active pattern, the plurality of semiconductor patterns being between the pair of source/drain patterns; a gate electrode on the plurality of semiconductor patterns; and a gate dielectric layer between the gate electrode and the plurality of semiconductor patterns. The gate electrode may include a portion between a first semiconductor pattern and a second semiconductor pattern that are adjacent semiconductor patterns among the plurality of semiconductor patterns. The gate dielectric layer may include a high-k dielectric layer surrounding portions of the gate electrode and an internal spacer on the high-k dielectric layer. The internal region may be defined by the pair of source/drain patterns, the first semiconductor pattern, and the second semiconductor pattern. The inner spacer may be within the inner region, the inner spacer may include an inner gate space, the portion of the high-k dielectric layer and the gate electrode may be within the inner gate space, the inner region may have a first side, and the inner gate space may have a second side adjacent to the first side.

According to yet another aspect of some embodiments, a semiconductor device may include: a substrate including an active region; a device isolation layer defining an active pattern on the active region; a channel pattern and a source/drain pattern on the active pattern, the channel pattern including a plurality of semiconductor patterns vertically stacked and spaced apart from each other; a gate electrode on the plurality of semiconductor patterns; a gate dielectric layer between the plurality of semiconductor patterns and the gate electrode; a gate spacer on sidewalls of the gate electrode; a gate cap pattern on a top surface of the gate electrode; an interlayer dielectric layer on the gate cap pattern; an active contact penetrating the interlayer dielectric layer and electrically connected to the source/drain pattern; a metal-semiconductor compound layer between the active contact and the source/drain pattern; a gate contact penetrating the interlayer dielectric layer and the gate cap pattern and electrically connected to the gate electrode; a first metal layer on the interlayer dielectric layer, the first metal layer including a power line and a plurality of first lines electrically connected to the active contact and the gate contact, respectively; and a second metal layer on the first metal layer. The second metal layer may include a plurality of second wires electrically connected to the first metal layer. The gate electrode may include a portion between the first semiconductor pattern and the second semiconductor pattern, which are adjacent semiconductor patterns among the plurality of semiconductor patterns. The source/drain pattern may include a protrusion protruding toward the portion of the gate electrode. The protrusion of the source/drain pattern may have a first convex sidewall directed toward the portion of the gate electrode. The portion of the gate electrode may have a second convex sidewall directed toward the first convex sidewall of the protrusion.

According to yet another aspect of some embodiments, a method of manufacturing a semiconductor device may include: forming a stack pattern including a plurality of active layers and a plurality of sacrificial layers alternately stacked with each other on a substrate; forming a sacrificial pattern extending in a first direction on the stacked pattern; etching the stacked pattern using the sacrificial pattern as a mask to form a pair of recesses correspondingly adjacent to sides of the sacrificial pattern; forming a pair of source/drain patterns in the pair of recesses, an active layer between the pair of source/drain patterns forming a plurality of semiconductor patterns constituting a channel pattern; removing the sacrificial pattern and the sacrificial layer to expose the plurality of semiconductor patterns; forming a gate dielectric layer on the exposed plurality of semiconductor patterns; and forming a gate electrode on the gate dielectric layer. The plurality of semiconductor patterns may include a first semiconductor pattern and a second semiconductor pattern adjacent to each other. The step of forming the gate dielectric layer may include forming a first dielectric layer in an inner region defined by the pair of source/drain patterns, the first semiconductor pattern, and the second semiconductor pattern; partially etching the first dielectric layer to form an internal gate space provided by the internal spacer; and forming a high-k dielectric layer in the internal gate space.

Drawings

Fig. 1 to 3 illustrate conceptual diagrams showing logic units of a semiconductor device according to some embodiments;

fig. 4 illustrates a plan view showing a semiconductor device according to some embodiments;

FIGS. 5A, 5B, 5C and 5D show cross-sectional views taken along lines A-A ', B-B', C-C 'and D-D' of FIG. 4, respectively;

fig. 6 shows an enlarged view showing an example of the portion M depicted in fig. 5A;

fig. 7A to 12C illustrate cross-sectional views of methods of manufacturing a semiconductor device according to some embodiments;

fig. 13 to 17 show enlarged views of a method of forming the portion M depicted in fig. 11A;

fig. 18 and 19 show enlarged views showing an example of the portion M depicted in fig. 5A; and

fig. 20A, 20B, 20C, and 20D illustrate cross-sectional views taken along lines A-A ', B-B', C-C ', and D-D', respectively, of fig. 4 showing a semiconductor device according to some embodiments.

Detailed Description

Fig. 1 to 3 illustrate conceptual diagrams showing logic units of a semiconductor device according to some embodiments.

Referring to fig. 1, a single height unit SHC may be provided. For example, the substrate 100 may have the first power lines m1_r1 and the second power lines m1_r2 disposed thereon. The first power line m1_r1 may be a path for providing the source voltage VSS (e.g., a ground voltage). The second power line m1_r2 may be a path for providing the drain voltage VDD (e.g., a power supply voltage).

The single-height unit SHC may be defined between the first power line m1_r1 and the second power line m1_r2. The single-height unit SHC may include one first active region AR1 and one second active region AR2. One of the first active region AR1 and the second active region AR2 may be a PMOSFET region, and the other of the first active region AR1 and the second active region AR2 may be an NMOSFET region. For example, the single-height unit SHC may have a Complementary Metal Oxide Semiconductor (CMOS) structure disposed between the first power line m1_r1 and the second power line m1_r2.

Each of the first active region AR1 and the second active region AR2 may have a first width WI1 in the first direction D1. The first height HE1 may be defined to indicate a length of the single-height unit SHC in the first direction D1. The first height HE1 may be substantially the same as a distance (e.g., pitch) between the first power line m1_r1 and the second power line m1_r2.

The single-height unit SHC may constitute one logic unit. In this description, a logic unit may refer to a logic device, such as AND, OR, XOR, XNOR or an inverter, that performs a specific function. For example, the logic unit may include transistors for constituting the logic device, and may further include wirings connecting the transistors to each other.

Referring to fig. 2, a dual height unit DHC may be provided. For example, the substrate 100 may have the first power line m1_r1, the second power line m1_r2, and the third power line m1_r3 disposed thereon. The first power line m1_r1 may be disposed between the second power line m1_r2 and the third power line m1_r3. The third power line m1_r3 may be a path for providing the source voltage VSS.

The dual height unit DHC may be defined between the second power line m1_r2 and the third power line m1_r3. The dual height unit DHC may include two first active areas AR1 and two second active areas AR2.

One of the two second active regions AR2 may be adjacent to the second power line m1_r2. The other of the two second active regions may be adjacent to the third power line m1_r3. Two first active regions AR1 may be adjacent to the first power lines m1_r1. The first power line m1_r1 may be disposed between two first active regions AR1 when viewed in a plane.

The second height HE2 may be defined to indicate a length of the dual height unit DHC in the first direction D1. The second height HE2 may be about twice the first height HE1 of fig. 1. The two first active areas AR1 of the dual height cell DHC may collectively operate as one active area.

In the present disclosure, the dual height unit DHC shown in fig. 2 may be defined as a multiple height unit. Although not shown, the multiple height unit may include a triple height unit having a unit height about three times that of the single height unit SHC.

Referring to fig. 3, the substrate 100 may have a first single-height unit SHC1, a second single-height unit SHC2, and a dual-height unit DHC disposed two-dimensionally thereon. The first single-height unit SHC1 may be positioned between the first power line m1_r1 and the second power line m1_r2. The second single-height unit SHC2 may be positioned between the first power line m1_r1 and the third power line m1_r3. The second single-height unit SHC2 may be adjacent to the first single-height unit SHC1 in the first direction D1.

The dual height unit DHC may be positioned between the second power line m1_r2 and the third power line m1_r3. The dual height unit DHC may be adjacent to each of the first single height unit SHC1 and the second single height unit SHC2 in the second direction D2.

The separation structure DB may be disposed between the first single-height unit SHC1 and the double-height unit DHC and between the second single-height unit SHC2 and the double-height unit DHC. The separation structure DB may electrically separate the active region of the dual height unit DHC from the active region of each of the first single height unit SHC1 and the second single height unit SHC 2.

Fig. 4 illustrates a plan view showing a semiconductor device according to some embodiments. Fig. 5A, 5B, 5C and 5D show cross-sectional views taken along lines A-A ', B-B', C-C 'and D-D' of fig. 4, respectively. Fig. 6 shows an enlarged view showing an example of the portion M depicted in fig. 5A. The semiconductor device shown in fig. 4 and 5A to 5D may be a specific example of the single-height unit SHC depicted in fig. 1.

Referring to fig. 4 and 5A to 5D, a single-height unit SHC may be disposed on the substrate 100. The single-height unit SHC may have logic transistors constituting a logic circuit provided thereon. The substrate 100 may be a compound semiconductor substrate or a semiconductor substrate including silicon, germanium, or silicon-germanium. For example, in some embodiments, the substrate 100 may be a silicon substrate.

The substrate 100 may include a first active region AR1 and a second active region AR2. Each of the first active region AR1 and the second active region AR2 may extend in the second direction D2. For example, the first active region AR1 may be an NMOSFET region and the second active region AR2 may be a PMOSFET region.

The first and second active patterns AP1 and AP2 may be defined by a trench TR formed on an upper portion of the substrate 100 (best shown in fig. 5C and 5D). The first active pattern AP1 may be disposed on the first active area AR1, and the second active pattern AP2 may be disposed on the second active area AR2. The first active pattern AP1 and the second active pattern AP2 may extend in the second direction D2. The first active pattern AP1 and the second active pattern AP2 may be vertically (i.e., in the third direction D3) protruding portions of the substrate 100.

The device isolation layer ST may be disposed on the substrate 100. The device isolation layer ST may fill the trench TR. The device isolation layer ST may include a silicon oxide layer. The device isolation layer ST may not cover any one of the first channel pattern CH1 and the second channel pattern CH2, which will be discussed below.

The first channel pattern CH1 may be disposed on the first active pattern AP 1. The second channel pattern CH2 may be disposed on the second active pattern AP 2. Each of the first and second channel patterns CH1 and CH2 may include a first semiconductor pattern SP1, a second semiconductor pattern SP2, and a third semiconductor pattern SP3 sequentially stacked. The first, second, and third semiconductor patterns SP1, SP2, and SP3 may be spaced apart from each other in the vertical direction or the third direction D3.

Each of the first, second, and third semiconductor patterns SP1, SP2, and SP3 may include silicon (Si), germanium (Ge), or silicon-germanium (SiGe). For example, each of the first, second, and third semiconductor patterns SP1, SP2, and SP3 may include crystalline silicon.

A plurality of first source/drain patterns SD1 (best shown in fig. 5A) may be disposed on the first active pattern AP 1. A plurality of first recesses RS1 may be formed on an upper portion of the first active pattern AP 1. The first source/drain pattern SD1 may be disposed in the corresponding first recess RS 1. The first source/drain pattern SD1 may be an impurity region of a first conductivity type (e.g., n-type). The first channel pattern CH1 may be interposed between a pair of first source/drain patterns SD 1. For example, the pair of first source/drain patterns SD1 may be connected to each other through the stacked first, second and third semiconductor patterns SP1, SP2 and SP3.

A plurality of second source/drain patterns SD2 (best shown in fig. 5B) may be disposed on the second active pattern AP 2. A plurality of second recesses RS2 may be formed on an upper portion of the second active pattern AP 2. The second source/drain pattern SD2 may be disposed in the corresponding second recess RS 2. The second source/drain pattern SD2 may be an impurity region of a second conductivity type (e.g., p-type). The second channel pattern CH2 may be interposed between a pair of second source/drain patterns SD 2. For example, the pair of second source/drain patterns SD2 may be connected to each other through the stacked first, second and third semiconductor patterns SP1, SP2 and SP 3.

The first source/drain pattern SD1 and the second source/drain pattern SD2 may be epitaxial patterns formed through a Selective Epitaxial Growth (SEG) process. For example, in some embodiments, each of the first and second source/drain patterns SD1 and SD2 may have a top surface higher than that of the third semiconductor pattern SP 3. For another example, in some embodiments, at least one selected from the first source/drain pattern SD1 and the second source/drain pattern SD2 may have a top surface at substantially the same level as that of the third semiconductor pattern SP 3.

In an embodiment, the first source/drain pattern SD1 may include the same semiconductor element (e.g., si) as that of the substrate 100. The second source/drain pattern SD2 may include a semiconductor element (e.g., siGe) having a lattice constant greater than that of the semiconductor element of the substrate 100. Accordingly, the pair of second source/drain patterns SD2 may provide compressive stress to the second channel pattern CH2 therebetween.

Each of the first and second source/drain patterns SD1 and SD2 may have a non-uniform embossed shape at sidewalls thereof. For example, each of the first and second source/drain patterns SD1 and SD2 may have a wavy profile at sidewalls thereof. The sidewalls of each of the first and second source/drain patterns SD1 and SD2 may protrude toward first, second and third portions PO1, PO2 and PO3 of the gate electrode GE, which will be discussed below.

The plurality of gate electrodes GE may be disposed to extend in the first direction D1 while crossing the first and second channel patterns CH1 and CH2. The gate electrode GE may be arranged in the second direction D2 at a first pitch. Each of the gate electrodes GE may vertically overlap a corresponding one of the first and second channel patterns CH1 and CH2.

The gate electrode GE may include a first portion PO1 interposed between the first semiconductor pattern SP1 and one of the first and second active patterns AP1 and AP2, a second portion PO2 interposed between the first and second semiconductor patterns SP1 and SP2, a third portion PO3 interposed between the second and third semiconductor patterns SP2 and SP3, and a fourth portion PO4 on the third semiconductor pattern SP 3.

Referring back to fig. 5D, the gate electrode GE may be disposed on the top surface TS, the bottom surface BS, and the two sidewalls SW of each of the first, second, and third semiconductor patterns SP1, SP2, and SP 3. In this sense, the transistor according to the embodiment shown in fig. 4 and 5A to 5D may be a three-dimensional field effect transistor (e.g., MBCFET or GAAFET) in which the gate electrode GE three-dimensionally surrounds the first channel pattern CH1 and the second channel pattern CH 2.

Referring back to fig. 4 and 5A to 5D, a pair of gate spacers GS may be disposed on both sidewalls of the fourth portion PO4 of the gate electrode GE. The gate spacer GS may extend along the gate electrode GE in the first direction D1. The gate spacer GS may have a top surface higher than that of the gate electrode GE. The top surface of the gate spacer GS may be coplanar with a top surface of the first interlayer dielectric layer 110, which will be discussed below. In an embodiment, the gate spacer GS may include at least one selected from SiCN, siCON, and SiN. Alternatively, the gate spacer GS may include a multilayer formed of two or more of SiCN, siCON, and SiN. For example, the gate spacer GS may include a first spacer and a second spacer.

The gate cap pattern GP may be disposed on the gate electrode GE. The gate cap pattern GP may extend along the gate electrode GE in the first direction D1. The gate cap pattern GP may include a material having an etch selectivity with respect to the first and second interlayer dielectric layers 110 and 120, which will be discussed below. For example, the gate cap pattern GP may include at least one selected from SiON, siCN, siCON and SiN.

The gate dielectric layer GI may be disposed between the gate electrode GE and the first channel pattern CH1 and between the gate electrode GE and the second channel pattern CH 2. The gate dielectric layer GI may cover the top surface TS, the bottom surface BS, and the two sidewalls SW of each of the first, second, and third semiconductor patterns SP1, SP2, and SP 3. The gate dielectric layer GI may cover a top surface of the device isolation layer ST under the gate electrode GE.

In an embodiment, as shown in fig. 6, the gate dielectric layer GI may include an internal spacer IS and a high-k dielectric layer HK. In an embodiment, the inner spacer IS may include a first dielectric layer IL1 and a second dielectric layer IL2. Each of the first dielectric layer IL1 and the second dielectric layer IL2 may include a dielectric material including silicon (Si). Each of the first dielectric layer IL1 and the second dielectric layer IL2 may include a silicon oxide layer, a silicon oxynitride layer, or a silicon nitride layer.

The high-k dielectric layer HK may include a high-k dielectric material having a dielectric constant greater than that of the silicon oxide layer. For example, the high-k dielectric layer HK may include at least one selected from hafnium oxide, hafnium silicon oxide, lanthanum oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, lithium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate.

In an embodiment, the semiconductor device may include a negative capacitance field effect transistor using a negative capacitor. For example, the high-k dielectric layer HK may include a ferroelectric material layer exhibiting ferroelectric properties, a paraelectric material layer exhibiting paraelectric properties, or a combination thereof.

The ferroelectric material layer may have a negative capacitance and the paraelectric material layer may have a positive capacitance. For example, when two or more capacitors are connected in series, and when each capacitor has a positive capacitance, the total capacitance may be reduced to be smaller than the capacitance of each capacitor. Conversely, when at least one of the two or more capacitors connected in series has a negative capacitance, the total capacitance may have a positive value that increases to be greater than the absolute value of the capacitance of each capacitor.

When a ferroelectric material layer having a negative capacitance is connected in series to a paraelectric material layer having a positive capacitance, the total capacitance of the ferroelectric material layer and paraelectric material layer connected in series can be increased. The increase in total capacitance may be used to allow transistors comprising the ferroelectric material layer to have a Subthreshold Swing (SS) of less than about 60 mV/decade at room temperature.

The ferroelectric material layer may have ferroelectric properties. The ferroelectric material layer may include, for example, at least one selected from hafnium oxide, hafnium zirconium oxide, barium strontium titanium oxide, and lead zirconium titanium oxide. For example, hafnium zirconium oxide may be a material in which hafnium oxide is doped with zirconium (Zr). As another example, hafnium zirconium oxide may be a compound of hafnium (Hf), zirconium (Zr) and oxygen (O).

The ferroelectric material layer may further include impurities doped therein. For example, the impurity may include at least one selected from aluminum (Al), titanium (Ti), niobium (Nb), lanthanum (La), yttrium (Y), magnesium (Mg), silicon (Si), calcium (Ca), cerium (Ce), dysprosium (Dy), erbium (Er), gadolinium (Gd), germanium (Ge), scandium (Sc), strontium (Sr), and tin (Sn). The type of impurities included in the ferroelectric material layer may vary according to the ferroelectric material included in the ferroelectric material layer.

When the ferroelectric material layer includes hafnium oxide, the ferroelectric material layer may include at least one of impurities such as gadolinium (Gd), silicon (Si), zirconium (Zr), aluminum (Al), and yttrium (Y).

When the impurity is aluminum (Al), the ferroelectric material layer may include about 3 to about 8 atomic percent aluminum. In this description, the ratio of the impurities may be a ratio of aluminum to the sum of hafnium and aluminum.

When the impurity is silicon (Si), the ferroelectric material layer may include about 2 to about 10 atomic percent silicon. When the impurity is yttrium (Y), the ferroelectric material layer may include about 2 to about 10 atomic percent yttrium. When the impurity is gadolinium (Gd), the ferroelectric material layer may include about 1 to 7 atomic percent gadolinium. When the impurity is zirconium (Zr), the ferroelectric material layer may include about 50 to about 80 atomic percent zirconium.

The paraelectric material layer may have paraelectric properties. The paraelectric material layer may include, for example, at least one selected from silicon oxide and high-k metal oxide. The metal oxide included in the paraelectric material layer may include, for example, at least one selected from hafnium oxide, zirconium oxide, and aluminum oxide, but the inventive concept is not limited thereto.

The ferroelectric material layer and the paraelectric material layer may comprise the same material. The ferroelectric material layer may have ferroelectric properties, while the paraelectric material layer may not have ferroelectric properties. For example, when the ferroelectric material layer and the paraelectric material layer include hafnium oxide, the hafnium oxide included in the ferroelectric material layer may have a crystal structure different from that of the hafnium oxide included in the paraelectric material layer.

The ferroelectric material layer may have a thickness exhibiting ferroelectric properties. The thickness of the ferroelectric material layer may be in the range of, for example, about 0.5nm to about 10nm, but the embodiment is not limited thereto. Because the ferroelectric material has its own critical thickness exhibiting ferroelectric properties, the thickness of the ferroelectric material layer may depend on the ferroelectric material.

For example, the high-k dielectric layer may comprise a layer of ferroelectric material. For another example, the high-k dielectric layer HK may include a plurality of ferroelectric material layers spaced apart from each other. The high-k dielectric layer HK may have a stacked structure in which a plurality of ferroelectric material layers and a plurality of paraelectric material layers are alternately stacked.

Referring back to fig. 4 and 5A to 5D, the gate electrode GE may include a first metal pattern and a second metal pattern on the first metal pattern. The first metal pattern may be disposed on the gate dielectric layer GI to be adjacent to the first, second and third semiconductor patterns SP1, SP2 and SP 3. The first metal pattern may include a work function metal controlling a threshold voltage of the transistor. The thickness and composition of the first metal pattern may be adjusted to achieve a threshold voltage of the transistor. For example, the first portion PO1, the second portion PO2, and the third portion PO3 of the gate electrode GE may be formed of a first metal pattern as a work function metal.

The first metal pattern may include a metal nitride layer. For example, the first metal pattern may include nitrogen (N) and at least one metal selected from titanium (Ti), tantalum (Ta), aluminum (Al), tungsten (W), and molybdenum (Mo). In addition, the first metal pattern may further include carbon (C). The first metal pattern may include a plurality of stacked work function metal layers.

The second metal pattern may include a metal having a resistance smaller than that of the first metal pattern. For example, the second metal pattern may include at least one metal selected from tungsten (W), aluminum (Al), titanium (Ti), and tantalum (Ta). For example, the fourth portion PO4 of the gate electrode GE may include a first metal pattern and a second metal pattern on the first metal pattern.

A first interlayer dielectric layer 110 (best shown in fig. 5C) may be disposed on the substrate 100. The first interlayer dielectric layer 110 may cover the gate spacer GS and the first and second source/drain patterns SD1 and SD2. The first interlayer dielectric layer 110 may have a top surface substantially coplanar with a top surface of the gate cap pattern GP and a top surface of the gate spacer GS. The first interlayer dielectric layer 110 may have a second interlayer dielectric layer 120 disposed thereon to cover the gate cap pattern GP. A third interlayer dielectric layer 130 may be disposed on the second interlayer dielectric layer 120. A fourth interlayer dielectric layer 140 may be disposed on the third interlayer dielectric layer 130. For example, the first to fourth interlayer dielectric layers 110 to 140 may include a silicon oxide layer.

As shown in fig. 4, the single-height unit SHC may have a first boundary BD1 and a second boundary BD2 opposite to each other in the second direction D2. The first and second boundaries BD1 and BD2 may extend in the first direction D1. The single-height unit SHC may have a third boundary BD3 and a fourth boundary BD4 opposite to each other in the first direction D1. The third and fourth boundaries BD3 and BD4 may extend in the second direction D2.

The single-height unit SHC may be provided on both sides thereof with a pair of separation structures DB opposite to each other in the second direction D2. For example, the pair of separation structures DB may be disposed on the first and second boundaries BD1 and BD2 of the single-height unit SHC, respectively. The separation structure DB may extend in the first direction D1 in parallel with the gate electrode GE. The pitch between the separation structure DB and the gate electrode GE adjacent thereto may be the same as the first pitch.

The separation structure DB may penetrate the first and second interlayer dielectric layers 110 and 120 to extend into the first and second active patterns AP1 and AP 2. The separation structure DB may penetrate an upper portion of each of the first and second active patterns AP1 and AP 2. The separation structure DB may electrically separate the active region of the single-height cell SHC from the active region of the adjacent cell.

The active contact AC may be disposed to penetrate the first and second interlayer dielectric layers 110 and 120 and be electrically connected to the first and second source/drain patterns SD1 and SD2, respectively. A pair of active contacts AC may be disposed on both sides of the gate electrode GE. That is, one active contact AC may be disposed on either side of the gate electrode GE. The active contact AC may have a bar shape extending in the first direction D1 when viewed in a plane, as shown in fig. 4.

The active contact AC may be a self-aligned contact. For example, the active contacts AC may be formed in a self-aligned manner using the gate cap pattern GP and the gate spacer GS. For example, the active contact AC may cover at least a portion of the sidewall of the gate spacer GS. Although not shown, the active contact AC may cover a portion of the top surface of the gate cap pattern GP.

A metal-semiconductor compound layer SC (such as a silicide layer) may be interposed between the active contact AC and the first source/drain pattern SD1 and between the active contact AC and the second source/drain pattern SD 2. The active contact AC may be electrically connected to one of the first source/drain pattern SD1 and the second source/drain pattern SD2 through the metal-semiconductor compound layer SC. For example, the metal-semiconductor compound layer SC may include at least one selected from titanium silicide, tantalum silicide, tungsten silicide, nickel silicide, and cobalt silicide.

The gate contact GC may be disposed to penetrate the second interlayer dielectric layer 120 and the gate cap pattern GP and be electrically connected to the corresponding gate electrode GE. The gate contact GC may be disposed between the first active region AR1 and the second active region AR2 when viewed in a plane. For example, the gate contact GC may be disposed on the second active pattern AP2 (see fig. 5B).

In an embodiment, referring to fig. 5B, the upper dielectric pattern UIP may fill an upper portion of each active contact AC, which is adjacent to the gate contact GC. The upper dielectric pattern UIP may have a lower bottom surface than the bottom surface of the gate contact GC. For example, the upper dielectric pattern UIP may cause the active contact AC adjacent to the gate contact GC to have a lower top surface than the bottom surface of the gate contact GC. Accordingly, it is possible to prevent an electrical short circuit from occurring due to contact between the gate contact GC and the active contact AC adjacent thereto.

Each of the active contact AC and the gate contact GC may include a conductive pattern FM and a barrier pattern BM surrounding the conductive pattern FM. For example, the conductive pattern FM may include at least one metal selected from aluminum, copper, tungsten, molybdenum, and cobalt. The barrier pattern BM may cover sidewalls and bottom surfaces of the conductive pattern FM. The barrier pattern BM may include a metal layer and a metal nitride layer. The metal layer may include at least one selected from titanium, tantalum, tungsten, nickel, cobalt, and platinum. The metal nitride layer may include at least one selected from a titanium nitride (TiN) layer, a tantalum nitride (TaN) layer, a tungsten nitride (WN) layer, a nickel nitride (NiN) layer, a cobalt nitride (CoN) layer, and a platinum nitride (PtN) layer.

The first metal layer M1 may be disposed in the third interlayer dielectric layer 130. For example, the first metal layer M1 may include a first power line m1_r1, a second power line m1_r2, and a first wiring m1_i. The lines m1_r1, m1_r2, and m1_i of the first metal layer M1 may extend in parallel in the second direction D2.

For example, the first power line m1_r1 and the second power line m1_r2 may be disposed on the third boundary BD3 and the fourth boundary BD4 of the single-height unit SHC, respectively. The first power line m1_r1 may extend in the second direction D2 along the third boundary BD 3. The second power line m1_r2 may extend in the second direction D2 along the fourth boundary BD 4.

The first wiring m1_i of the first metal layer M1 may be disposed between the first power line m1_r1 and the second power line m1_r2 of the first metal layer M1. The first wirings m1_i of the first metal layer M1 may be arranged at a second pitch along the first direction D1. The second pitch may be smaller than the first pitch. Each of the first wirings m1_i may have a line width smaller than that of each of the first and second power lines m1_r1 and m1_r2.

The first metal layer M1 may further include a first via VI1. The first via VI1 may be disposed under the lines m1_r1, m1_r2, and m1_i of the first metal layer M1, respectively. The first via VI1 may electrically connect the active contact AC to one of the lines m1_r1, m1_r2, and m1_i of the first metal layer M1. The first via VI1 may electrically connect the gate contact GC to one of the lines m1_r1, m1_r2, and m1_i of the first metal layer M1.

The wiring of the first metal layer M1 and the first via VI1 thereunder may be formed through a separate process. For example, the wiring of the first metal layer M1 and the first via VI1 thereunder may be formed by a single damascene process. The semiconductor device according to the present embodiment can be manufactured using a sub-20 nm process.

The second metal layer M2 may be disposed in the fourth interlayer dielectric layer 140. The second metal layer M2 may include a plurality of second wirings m2_i. The second wirings m2_i of the second metal layer M2 may each have a linear or bar shape extending in the first direction D1. For example, the second wiring m2_i may extend in parallel in the first direction D1.

The second metal layer M2 may further include a second via VI2 correspondingly disposed under the second wiring m2_i. The wiring of the first metal layer M1 may be electrically connected to a corresponding wiring in the second metal layer M2 through the second via VI2. For example, the wiring of the second metal layer M2 and the second via VI2 thereunder may be simultaneously formed through a dual damascene process.

The first metal layer M1 and the second metal layer M2 may have wirings including the same conductive material or different conductive materials. For example, the wirings of the first and second metal layers M1 and M2 may include at least one metal material selected from aluminum, copper, tungsten, molybdenum, ruthenium, and cobalt. Although not shown, other metal layers (e.g., M3, M4, M5, etc. (not shown)) may be additionally stacked on the fourth interlayer dielectric layer 140. Each stacked metal layer may include wiring for wiring between cells.

Referring to fig. 6, the internal spacers IS on the first channel pattern CH1 will be described in detail below. Referring to fig. 6, the first source/drain pattern SD1 may include protrusions PRP protruding toward the first, second and third portions PO1, PO2 and PO3 of the gate electrode GE, respectively. The protrusion PRP of the first source/drain pattern SD1 may have a first convex sidewall CSW1. The first convex sidewall CSW1 may protrude toward a corresponding one of the first portion PO1, the second portion PO2, and the third portion PO 3.

Each of the first portion PO1, the second portion PO2, and the third portion PO3 of the gate electrode GE may have a second convex sidewall CSW2. The second convex sidewall CSW2 may protrude toward the corresponding first convex sidewall CSW1 of the first source/drain pattern SD 1.

In an embodiment, each of the first, second and third portions PO1, PO2 and PO3 may not have concave sidewalls corresponding to the first convex sidewalls CSW1 of the first source/drain pattern SD 1. This may be caused by the fact that: the internal spacers IS provide an internal gate space IGE in which each of the first, second and third portions PO1, PO2 and PO3 has a second convex sidewall CSW2.

In an embodiment, the first portion PO1, the second portion PO2, and the third portion PO3 may have different widths from each other. For example, the maximum width of the first portion PO1 in the second direction D2 may be larger than the maximum width of the second portion PO2 in the second direction D2. The maximum width of the second portion PO2 in the second direction D2 may be greater than the maximum width of the third portion PO3 in the second direction D2.

The first source/drain pattern SD1 may include a first semiconductor layer SEL1 and a second semiconductor layer SEL2 on the first semiconductor layer SEL 1. In an embodiment, when the first source/drain pattern SD1 has n-type conductivity, the first semiconductor layer SEL1 may include the same semiconductor material (e.g., silicon (Si)) as that of the second semiconductor layer SEL2. The concentration of the n-type impurity (e.g., phosphorus or arsenic) in the second semiconductor layer SEL2 may be greater than that in the first semiconductor layer SEL 1.

In an embodiment, when the first source/drain pattern SD1 has p-type conductivity, the first semiconductor layer SEL1 may include the same semiconductor material (e.g., silicon-germanium (SiGe)) as that of the second semiconductor layer SEL 2. The germanium concentration in the second semiconductor layer SEL2 may be greater than that in the first semiconductor layer SEL 1. In addition, the concentration of the p-type impurity (e.g., boron) in the second semiconductor layer SEL2 may be greater than the concentration of the p-type impurity in the first semiconductor layer SEL 1.

The first semiconductor layer SEL1 may directly contact the first, second, and third semiconductor patterns SP1, SP2, and SP 3. The first semiconductor layer SEL1 may include a protrusion PRP. The first semiconductor layer SEL1 may be directly covered by an internal spacer IS to be discussed below. In some embodiments, the first semiconductor layer SEL1 may be in direct contact with the internal spacer IS, and the first, second and third portions PO1, PO2 and PO3 of the gate electrode GE may be spaced apart from the first semiconductor layer SEL1 across the internal spacer IS.

The pair of first source/drain patterns SD1 may be provided with an internal region IRG therebetween. The first portion PO1, the second portion PO2, and the third portion PO3 of the gate electrode GE may be disposed in the corresponding internal region IRG. An internal spacer IS and a high-k dielectric layer HK may also be disposed in each internal region IRG.

The inner spacer IS may partially fill the inner region IRG. The internal spacers IS may provide an internal gate space IGE. The internal gate space IGE may have a high-k dielectric layer HK disposed therein and a corresponding one of the first portion PO1, the second portion PO2, and the third portion PO 3.

The length of the internal region IRG in the second direction D2 may gradually decrease and then increase in the third direction D3. The inner region IRG may have a first side SI1 as a concave surface corresponding to the first convex sidewall CSW 1.

The length of the internal gate space IGE in the second direction D2 may be gradually increased and then decreased in the third direction D3. The internal gate space IGE may have a second side SI2 as a convex surface corresponding to the second convex sidewall CSW 2.

For example, the internal spacers IS may cause the second side SI2 of the internal gate space IGE to have a profile (e.g., a convex profile) that IS opposite to the profile (e.g., a concave profile) of the first side SI1 of the internal region IRG.

The second portion PO2 of the gate electrode GE and the gate dielectric layer GI surrounding the second portion PO2 will be representatively described below. The gate dielectric layer GI may be disposed between the second portion PO2 and the first semiconductor pattern SP1, between the second portion PO2 and the second semiconductor pattern SP2, and between the second portion PO2 and the first source/drain pattern SD 1.

The gate dielectric layer GI may include an internal spacer IS and a high-k dielectric layer HK. The inner spacer IS may include a first dielectric layer IL1 and a second dielectric layer IL2 on the first dielectric layer IL 1. The first dielectric layer IL1 may directly cover the first semiconductor pattern SP1, the second semiconductor pattern SP2, and the first source/drain pattern SD1. In some embodiments, the first dielectric layer IL1 may directly contact the first semiconductor pattern SP1, the second semiconductor pattern SP2, and the first source/drain pattern SD1. A high-k dielectric layer HK may be disposed between the inner spacer IS and the second portion PO 2. The high-k dielectric layer HK may directly cover the surface of the second portion PO2 of the gate electrode GE. In some embodiments, the high-k dielectric layer HK may be in direct contact with the surface of the second portion PO2 of the gate electrode GE.

Each of the first dielectric layer IL1 and the second dielectric layer IL2 may include a dielectric material including silicon (Si). Each of the first dielectric layer IL1 and the second dielectric layer IL2 may include a silicon oxide layer, a silicon oxynitride layer, or a silicon nitride layer. In an embodiment, all of the first dielectric layer IL1 and the second dielectric layer IL2 may include a silicon oxide layer. When the first dielectric layer IL1 and the second dielectric layer IL2 include the same material (e.g., silicon oxide layer), there may be no boundary (different from that shown in the example of fig. 6) between the first dielectric layer IL1 and the second dielectric layer IL2. For example, the first dielectric layer IL1 and the second dielectric layer IL2 may be integrally connected as one silicon oxide layer constituting the internal spacer IS.

In an embodiment, the first dielectric layer IL1 may include a silicon nitride layer, and the second dielectric layer IL2 may include a silicon oxide layer. In this case, a distinct boundary (as shown in the example of fig. 6) can be found between the first dielectric layer IL1 and the second dielectric layer IL 2.

The thickness of the internal spacer IS may be the sum of the thickness of the first dielectric layer IL1 and the thickness of the second dielectric layer IL 2. The inner spacer IS may have a first thickness TK1 as a thickness in a vertical direction as the third direction DR 3. The first thickness TK1 may represent a thickness of the inner spacer IS on the top surface TSR of the high-k dielectric layer HK or on the bottom surface of the high-k dielectric layer HK. The first thickness TK1 may be less than the thickness of the high-k dielectric layer HK.

The inner spacer IS may have a second thickness TK2 as a thickness in a horizontal direction as the second direction D2. The second thickness TK2 may represent a thickness of the inner spacer IS on the first side surface SSR1 of the high-k dielectric layer HK. The second thickness TK2 may be greater or less than the thickness of the high-k dielectric layer HK.

The third thickness TK3 may be defined to indicate a thickness at a corner of the inner spacer IS. The high-k dielectric layer HK may include a curved first corner COR1 between the top surface TSR and the first side surface SSR 1. The inner spacer IS may have a third thickness TK3 on the first corner COR1 of the high-k dielectric layer HK. For example, the point FAP may be defined to indicate a position where the first source/drain pattern SD1 meets the bottom surface of the second semiconductor pattern SP 2. The third thickness TK3 may be the same distance between the point FAP and the first corner COR1 of the high-k dielectric layer HK. The third thickness TK3 may be greater than the thickness of the high-k dielectric layer HK.

Various elements may be described using terms such as "first," "second," "third," etc., but these elements should not be limited by these terms. As used herein, the terms "first" and "second" may describe corresponding components or elements regardless of importance or order, and are used only to distinguish one component or element from another component or element without limiting the components or elements. The use of such ordinal numbers should not be construed as limiting the meaning of the terms. For example, a "first" component may be referred to as a "second" component, and similarly, a "second" component may also be referred to as a "first" component, without departing from the scope of the disclosure.

The inner spacer IS may include a horizontal portion TPO on a top surface TSR or a bottom surface of the high-k dielectric layer HK, a vertical portion SPO on a first side surface SSR1 of the high-k dielectric layer HK, and a corner portion CPO on a first corner COR1 of the high-k dielectric layer HK. The corner portion CPO may be located between the horizontal portion TPO and the vertical portion SPO. The horizontal portion TPO may have a first thickness TK1, the vertical portion SPO may have a second thickness TK2, and the corner portion CPO may have a third thickness TK3.

The first thickness TK1, the second thickness TK2, and the third thickness TK3 may be different from each other. The second thickness TK2 may be greater than the first thickness TK1 and the third thickness TK3 may be greater than the second thickness TK2. The ratio of the second thickness TK2 to the first thickness TK1 (TK 2/TK 1) may be in the range of about 1.5 to about 3. The ratio of the third thickness TK3 to the first thickness TK1 (TK 3/TK 1) may be in the range of about 2.5 to about 5.

According to the embodiment shown in fig. 6, the high-k dielectric layer HK may have a uniform thickness. Conversely, the thickness of the vertical portion SPO of the inner spacer IS (e.g., TK 2) may be greater than the thickness of the horizontal portion TPO of the inner spacer IS (e.g., TK 1). Specifically, the thickness (e.g., TK 3) of the corner portion CPO of the inner spacer IS may be greater than the thickness (e.g., TK 2) of the vertical portion SPO of the inner spacer IS. According to some embodiments, the internal spacers IS may have a variable thickness depending on the position, and thus the internal gate space IGE may be provided to have a shape different from that of the internal region IRG.

The fourth portion PO4 of the gate electrode GE and the gate dielectric layer GI surrounding the fourth portion PO4 will be described below. The gate dielectric layer GI may be disposed between the fourth portion PO4 and the third semiconductor pattern SP3 and between the fourth portion PO4 and the gate spacer GS. The gate dielectric layer GI may include an internal spacer IS and a high-k dielectric layer HK.

The inner spacer IS may have a fourth thickness TK4 as a thickness in the vertical direction as the third direction D3. The fourth thickness TK4 may represent the thickness of the inner spacer IS on the bottom surface BSR of the high-k dielectric layer HK. The fourth thickness TK4 may be substantially the same as the first thickness TK 1.

The inner spacer IS may have a fifth thickness TK5 as a thickness in a horizontal direction as the second direction D2. The fifth thickness TK5 may represent the thickness of the inner spacer IS on the second side surface SSR2 of the high-k dielectric layer HK. The fifth thickness TK5 may be substantially the same as the second thickness TK 2.

The inner spacer IS may have a sixth thickness TK6 at its corners. The high-k dielectric layer HK may include a curved second corner COR2 between the bottom surface BSR and the second side surface SSR 2. The sixth thickness TK6 may represent the thickness of the inner spacer IS on the second corner COR2 of the high-k dielectric layer HK. The sixth thickness TK6 may be the same as a distance between the second corner COR2 and a position where the third semiconductor pattern SP3 meets the gate spacer GS. The sixth thickness TK6 may be substantially the same as the third thickness TK 3.

The internal spacers IS shown in fig. 6 may be applied to NMOSFETs as well as PMOSFETs. In an embodiment, the internal spacer IS of fig. 6 may be applicable only to NMOSFETs and not to PMOSFETs. In another embodiment, the internal spacers IS may be applicable only to PMOSFETs and not to NMOSFETs. In another embodiment, the internal spacers IS may be applied to all of the PMOSFET and the NMOSFET.

According to some embodiments, the second thickness TK2 of the vertical portion SPO of the inner spacer IS may be greater than the first thickness TK1 of the horizontal portion TPO of the inner spacer IS, and thus may be able to reduce leakage current of the transistor. Further, by making the inner spacer IS have the greatly increased third thickness TK3 at the corner portion CPO susceptible to the leakage current, the leakage current can be effectively reduced. In addition, by having the internal spacer IS having a significantly increased thickness only at the corner portion CPO, a relatively small capacitance may be provided between the first source/drain pattern SD1 and the first, second and third portions PO1, PO2 and PO3 of the gate electrode GE. As a result, according to various embodiments, the thickness of the internal spacers may be selectively increased to improve the electrical properties of the semiconductor device.

Fig. 7A to 12C illustrate cross-sectional views of methods of manufacturing a semiconductor device according to some embodiments. Fig. 7A, 8A, 9A, 10A, 11A and 12A show cross-sectional views taken along the line A-A' of fig. 4. Fig. 9B, 10B, 11B and 12B show cross-sectional views taken along line C-C' of fig. 4. Fig. 7B, 8B, 9C, 10C, 11C, and 12C illustrate cross-sectional views taken along line D-D' of fig. 4.

Referring to fig. 7A and 7B, a substrate 100 including a first active region AR1 and a second active region AR2 may be provided. The active layer ACL and the sacrificial layer SAL alternately stacked on the substrate 100 may be formed. The active layer ACL may include one of silicon (Si), germanium (Ge), and silicon-germanium (SiGe), and the sacrificial layer SAL may include the other of silicon (Si), germanium (Ge), and silicon-germanium (SiGe). For example, in some embodiments, when the active layer ACL includes silicon (Si), the sacrificial layer SAL may include one of germanium (Ge) and silicon-germanium (SiGe). In other embodiments, when the active layer ACL includes silicon-germanium (SiGe), the sacrificial layer SAL may include one of silicon (Si) and germanium (Ge). In other embodiments, when the active layer ACL includes germanium (Ge), the sacrificial layer SAL may include one of silicon (Si) and silicon-germanium (SiGe).

The sacrificial layer SAL may include a material having etching selectivity with respect to the active layer ACL. For example, the active layer ACL may include silicon (Si), and the sacrificial layer SAL may include silicon-germanium (SiGe). Each sacrificial layer SAL may have a germanium concentration of about 10at% to about 30 at%.

A mask pattern may be formed on the first active region AR1 and the second active region AR2 of the substrate 100. The mask patterns may each have a linear or stripe shape extending in the second direction D2.

A patterning process in which a mask pattern is used as an etching mask may be performed to form trenches TR defining the first and second active patterns AP1 and AP2 and the corresponding stack patterns STP. The first active pattern AP1 may be formed on the first active region AR 1. The second active pattern AP2 may be formed on the second active region AR 2.

A stack pattern STP may be formed on each of the first active pattern AP1 and the second active pattern AP2. The stack pattern STP may include active layers ACL and sacrificial layers SAL that are alternately stacked. During the patterning process, a stack pattern STP may be formed together with the first active pattern AP1 and the second active pattern AP2.

The device isolation layer ST may be formed to fill the trench TR. For example, a dielectric layer may be formed on the entire surface of the substrate 100 to cover the first and second active patterns AP1 and AP2 and the stack pattern STP. The dielectric layer may be recessed until the stack pattern STP is exposed, and thus the device isolation layer ST may be formed.

The device isolation layer ST may include a dielectric material such as a silicon oxide layer. The stack pattern STP may be exposed upward from the device isolation layer ST. For example, the stack pattern STP may vertically protrude upward from the device isolation layer ST.

Referring to fig. 8A and 8B, a sacrificial pattern PP may be formed on the substrate 100 to cross the stack pattern STP. Each of the sacrificial patterns PP may be formed to have a linear or bar shape extending in the first direction D1. The sacrificial pattern PP may be arranged at a first pitch along the second direction D2.

For example, the formation of the sacrificial pattern PP may include forming a sacrificial layer on the entire surface of the substrate 100, forming a hard mask pattern MP on the sacrificial layer, and patterning the sacrificial layer using the hard mask pattern MP as an etching mask. The sacrificial layer may include polysilicon.

A pair of gate spacers GS may be formed on each of the sacrificial patterns PP. In some embodiments, as shown in fig. 8A, a gate spacer GS may be formed on each sidewall of each sacrificial pattern PP. The forming of the gate spacer GS may include conformally forming a gate spacer layer on the entire surface of the substrate 100 and anisotropically etching the gate spacer layer. In an embodiment, the gate spacer GS may have a multi-layered structure including at least two layers.

Referring to fig. 9A to 9C, a first recess RS1 may be formed in the stack pattern STP on the first active pattern AP 1. The second recess RS2 may be formed in the stack pattern STP on the second active pattern AP 2. During the formation of the first and second recesses RS1 and RS2, the device isolation layer ST may be made more recessed on both sides of each of the first and second active patterns AP1 and AP2 (see fig. 9B).

For example, the hard mask pattern MP and the gate spacer GS may be used as an etching mask to etch the stack pattern STP on the first active pattern AP1, thereby forming the first recess RS1. The first recess RS1 may be formed between a pair of sacrificial patterns PP. The forming of the first recess RS1 may include additionally performing a selective etching process on the exposed sacrificial layer SAL. The selective etching process may retract each sacrificial layer SAL to form a recess region IDE. Accordingly, the first recess RS1 may have a wave-shaped inner sidewall. The second recess RS2 in the stack pattern STP on the second active pattern AP2 may be formed by the same method as that used to form the first recess RS1, and thus a repeated description thereof is omitted for brevity.

The active layer ACL may be formed into the first, second, and third semiconductor patterns SP1, SP2, and SP3 sequentially stacked between adjacent first recesses RS1. The first channel pattern CH1 may be composed of a first semiconductor pattern SP1, a second semiconductor pattern SP2, and a third semiconductor pattern SP3 between adjacent first recesses RS1. The second channel pattern CH2 may be composed of a first semiconductor pattern SP1, a second semiconductor pattern SP2, and a third semiconductor pattern SP3 between adjacent second recesses RS 2.

Referring to fig. 10A to 10C, the first source/drain pattern SD1 may be formed in the first recess RS1 accordingly. For example, a Selective Epitaxial Growth (SEG) process in which the inner wall of the first recess RS1 is used as a seed layer may be performed to form an epitaxial layer filling the first recess RS 1. The epitaxial layer may be grown from the seed, or from the first, second, and third semiconductor patterns SP1, SP2, and SP3 exposed by the first recess RS1 and the substrate 100. For example, the SEG process may include Chemical Vapor Deposition (CVD) or Molecular Beam Epitaxy (MBE).

In an embodiment, the first source/drain pattern SD1 may include the same semiconductor element (e.g., si) as that of the substrate 100. During formation of the first source/drain pattern SD1, an impurity (e.g., phosphorus, arsenic, or antimony) may be implanted in situ to make the first source/drain pattern SD1 have n-type conductivity. Alternatively or additionally, after the first source/drain pattern SD1 is formed, impurities may be implanted into the first source/drain pattern SD1.

The second source/drain pattern SD2 may be formed in the second recess RS2 accordingly. For example, a Selective Epitaxial Growth (SEG) process in which the inner sidewall of the second recess RS2 is used as a seed layer may be performed to form the second source/drain pattern SD2.

In an embodiment, the second source/drain pattern SD2 may include a semiconductor element (e.g., siGe) having a lattice constant greater than that of the semiconductor element of the substrate 100. During formation of the second source/drain pattern SD2, an impurity (e.g., boron, gallium, or indium) may be implanted in situ to make the second source/drain pattern SD2 have p-type conductivity. Alternatively or additionally, after the second source/drain pattern SD2 is formed, impurities may be implanted into the second source/drain pattern SD 2.

Referring to fig. 11A to 11C, a first interlayer dielectric layer 110 may be formed to cover the first and second source/drain patterns SD1 and SD2, the hard mask pattern MP, and the gate spacer GS. For example, the first interlayer dielectric layer 110 may include a silicon oxide layer.

The first interlayer dielectric layer 110 may be planarized until the top surface of the sacrificial pattern PP is exposed. An etch back or Chemical Mechanical Polishing (CMP) process may be performed to planarize the first interlayer dielectric layer 110. The hard mask pattern MP may be entirely removed during the planarization process. As a result, the first interlayer dielectric layer 110 may have a top surface coplanar with the top surface of the sacrificial pattern PP and the top surface of the gate spacer GS.

The exposed sacrificial pattern PP may be selectively removed. The removal of the sacrificial pattern PP may form an external region ORG exposing the first and second channel patterns CH1 and CH2 (see fig. 11C). The removal of the sacrificial pattern PP may include performing a wet etching process using an etchant that selectively etches polysilicon.

The sacrificial layer SAL exposed through the outer region ORG may be selectively removed to form the inner region IRG (see fig. 11C). For example, an etching process of selectively etching the sacrificial layer SAL may be performed to remove only the sacrificial layer SAL while leaving the first, second, and third semiconductor patterns SP1, SP2, and SP3. For silicon-germanium where the germanium concentration is relatively high, the etching process may have a high etch rate. For example, the etching process may have a high etch rate for silicon-germanium with a germanium concentration greater than about 10 at%.

The etching process may remove the sacrificial layer SAL on the first active region AR1 and the second active region AR 2. The etching process may be a wet etching process. The etching material used for the etching process can rapidly etch the sacrificial layer SAL having a relatively high germanium concentration.

Referring back to fig. 11C, since the sacrificial layer SAL is selectively removed, only the first, second, and third semiconductor patterns SP1, SP2, and SP3 may remain on each of the first and second active patterns AP1 and AP 2. Removing the sacrificial layer SAL may form the first, second, and third internal regions IRG1, IRG2, and IRG3.

For example, a first internal region IRG1 may be formed between the first semiconductor pattern SP1 and one of the first and second active patterns AP1 and AP2, a second internal region IRG2 may be formed between the first and second semiconductor patterns SP1 and SP2, and a third internal region IRG3 may be formed between the second and third semiconductor patterns SP2 and SP 3.

Referring again to fig. 11A to 11C, a gate dielectric layer GI may be formed on the exposed first, second, and third semiconductor patterns SP1, SP2, and SP 3. The gate dielectric layer GI may surround each of the first, second, and third semiconductor patterns SP1, SP2, and SP 3. The gate dielectric layer GI may be formed in each of the first, second, and third internal regions IRG1, IRG2, and IRG3. The gate dielectric layer GI may be formed in the outer region ORG.

Fig. 13 to 17 show enlarged views illustrating a method of forming the portion M depicted in fig. 11A. Referring to fig. 13, as described above, the sacrificial pattern PP may be selectively removed to form the external region ORG. The sacrificial layer SAL exposed through the outer region ORG may be selectively removed to form first to third inner regions IRG1 to IRG3. Each of the first to third internal regions IRG1 to IRG3 may be located between a pair of first source/drain patterns SD 1.

The indented area IDE shown in fig. 9A may allow the first source/drain pattern SD1 to include protrusions PRP. The protrusion PRP may have a first convex sidewall CSW1. For example, the second internal region IRG2 may expose the first convex sidewall CSW1 of the first source/drain pattern SD 1. The second internal region IRG2 may expose a top surface of the first semiconductor pattern SP1 and a bottom surface of the second semiconductor pattern SP 2.

As the distance from the substrate 100 in the third direction D3 increases, the length L of each of the first to third internal regions IRG1 to IRG3 in the second direction D2 may gradually decrease and then increase. Each of the first, second, and third internal regions IRG1, IRG2, and IRG3 may have a first side SI1 as a concave surface corresponding to the first convex sidewall CSW1.

Referring to fig. 14, the first dielectric layer IL1 may be conformally formed in the first to third internal regions IRG1 to IRG3 and the external region ORG. The first dielectric layer IL1 may be formed by a deposition process such as Atomic Layer Deposition (ALD) or Chemical Vapor Deposition (CVD). The first dielectric layer IL1 may be formed to partially fill the first to third internal regions IRG1 to IRG3, but not completely fill the first to third internal regions IRG1 to IRG3. Accordingly, the first dielectric layer IL1 may define an internal gate space IGE in each of the first to third internal regions IRG1 to IRG3. For example, the first dielectric layer IL1 may include a silicon oxide layer, a silicon oxynitride layer, or a silicon nitride layer.

Referring to fig. 15, the first dielectric layer IL1 may be partially and selectively etched. The etching of the first dielectric layer IL1 may include performing a wet etching process using an etching solution that selectively etches only the first dielectric layer IL1. For example, an etching material may be provided through the internal gate space IGE to etch the first dielectric layer IL1. In an embodiment, as shown in fig. 15, the etching process may be continued until surfaces of the first, second, and third semiconductor patterns SP1, SP2, and SP3 are exposed.

After the etching process, the first dielectric layer IL1 may remain on the surface of the first source/drain pattern SD 1. For example, a relatively large amount of the first dielectric layer IL1 may remain in the space between the first source/drain pattern SD1 and the first to third semiconductor patterns SP1 to SP 3. The remaining first dielectric layer IL1 may provide the internal gate space IGE that expands more than the internal gate space IGE of fig. 14. In other words, the etching process may expand the internal gate space IGE from the size shown in fig. 14 to the size shown in fig. 15.

Referring to fig. 16, the second dielectric layer IL2 may be conformally formed in the first to third internal regions IRG1 to IRG3 and the external region ORG. A second dielectric layer IL2 may be formed on the first dielectric layer IL1. For example, the second dielectric layer IL2 may include a silicon oxide layer, a silicon oxynitride layer, or a silicon nitride layer. The first dielectric layer IL1 and the second dielectric layer IL2 may constitute an internal spacer IS.

The internal spacer IS may include a horizontal portion TPO on one of the first to third semiconductor patterns SP1 to SP3, a vertical portion SPO on the first convex sidewall CSW1 of the first source/drain pattern SD1, and a corner portion CPO between the horizontal portion TPO and the vertical portion SPO. The horizontal portion TPO may have a first thickness TK1, the vertical portion SPO may have a second thickness TK2, and the corner portion CPO may have a third thickness TK3, as shown in fig. 16. The second thickness TK2 may be greater than the first thickness TK1 and the third thickness TK3 may be greater than the second thickness TK2.

The internal spacers IS in each of the first to third internal regions IRG1 to IRG3 may define an internal gate space IGE. The first side SI1 of each of the first to third internal regions IRG1 to IRG3 may be concave, and the second side SI2 of the internal gate space IGE may be convex. Since the corner portion CPO of the internal spacer IS formed relatively thick as compared to the horizontal portion TPO and the vertical portion SPO, the second side SI2 of the internal gate space IGE may protrude opposite to the first side SI1 of each of the first to third internal regions IRG1 to IRG 3.

Referring to fig. 17, a high-k dielectric layer HK may be formed in the outer region ORG and the first to third inner regions IRG1 to IRG 3. A high-k dielectric layer HK may be formed in the internal gate space IGE. The internal spacers IS and the high-k dielectric layer HK may constitute a gate dielectric layer GI.

In an embodiment, the high-k dielectric layer HK may be conformally formed. For example, the thickness of the high-k dielectric layer HK in the horizontal direction may be substantially the same as the thickness of the high-k dielectric layer HK in the vertical direction.

According to various embodiments, since the horizontal portion TPO of the internal spacer IS has a relatively small thickness TK1, each of the first, second, and third internal regions IRG1, IRG2, and IRG3 may be provided therein with an internal gate space IGE, which IS a space sufficiently filled with a gate electrode GE to be discussed below. In various embodiments, the vertical portion SPO and the corner portion CPO may be formed to have relatively large thicknesses TK2 and TK3, respectively, compared to the first thickness TK1, and thus may be able to reduce leakage current of the transistor and improve electrical properties of the device.

Referring back to fig. 12A to 12C, a gate electrode GE may be formed on the gate dielectric layer GI. The gate electrode GE may include first, second, PO2, and third portions PO1, second, PO2, and PO3 formed in the first, second, and third internal regions IRG1, IRG2, and IRG3, respectively, and may further include a fourth portion PO4 formed in the external region ORG. The first portion PO1, the second portion PO2, and the third portion PO3 may fill the corresponding internal gate space IGE of fig. 17. The gate electrode GE may be recessed to have a reduced height. A gate cap pattern GP may be formed on the recessed gate electrode GE.

Referring back to fig. 5A to 5D, a second interlayer dielectric layer 120 may be formed on the first interlayer dielectric layer 110. The second interlayer dielectric layer 120 may include a silicon oxide layer. The active contact AC may be formed to penetrate the second interlayer dielectric layer 120 and the first interlayer dielectric layer 110 and be electrically connected to the first source/drain pattern SD1 and the second source/drain pattern SD2. The gate contact GC may be formed to penetrate the second interlayer dielectric layer 120 and the gate cap pattern GP and be electrically connected to the gate electrode GE.

The forming of the active contact AC and the gate contact GC may include forming a barrier pattern BM and a conductive pattern FM on the barrier pattern BM. The barrier pattern BM may be conformally formed, and may include a metal layer and a metal nitride layer. The conductive pattern FM may include a low resistance metal.

The separation structure DB may be formed on the first and second boundaries BD1 and BD2 (see fig. 4) of the single-height unit SHC. The separation structure DB may extend from the second interlayer dielectric layer 120 through the gate electrode GE into the active pattern AP1 or AP2 (see, e.g., fig. 5A). The separation structure DB may include a dielectric material such as a silicon oxide layer or a silicon nitride layer.

A third interlayer dielectric layer 130 may be formed on the active contact AC and the gate contact GC. The first metal layer M1 may be formed in the third interlayer dielectric layer 130. A fourth interlayer dielectric layer 140 may be formed on the third interlayer dielectric layer 130. The second metal layer M2 may be formed in the fourth interlayer dielectric layer 140.

Various embodiments are discussed below. In the following embodiments, detailed descriptions of technical features repeated from those discussed above with reference to fig. 1 to 6 will be omitted for brevity, and differences thereof will be discussed in detail.

Fig. 18 and 19 show enlarged views showing an example of the portion M depicted in fig. 5A.

Referring to fig. 18, the internal spacer IS may include a first dielectric layer IL1, a second dielectric layer IL2, and a third dielectric layer IL3. The first dielectric layer IL1 and the third dielectric layer IL3 may be conformally formed to each have a uniform thickness. The second dielectric layer IL2 may have a thickness that is variable according to the position. The first and third dielectric layers IL1 and IL3 may include, for example, a silicon oxide layer. The second dielectric layer IL2 may include a silicon nitride layer or a silicon oxynitride layer.

The second dielectric layer IL2 may be omitted on the horizontal portion TPO of the inner spacer IS. The first dielectric layer IL1 and the third dielectric layer IL3 of the horizontal portion TPO may contact each other. In some embodiments, the first dielectric layer IL1 and the third dielectric layer IL3 may comprise the same material (e.g., a silicon oxide layer), and thus no distinct boundary (other than the boundary shown in fig. 18) may be found between the first dielectric layer IL1 and the third dielectric layer IL3 on the horizontal portion TPO. Note that boundaries are shown on the horizontal portion TPO in fig. 18, which is merely for convenience in showing the first dielectric layer IL1 and the third dielectric layer IL3 on the horizontal portion TPO.

On the vertical portion SPO of the inner spacer IS, a second dielectric layer IL2 may be disposed between the first dielectric layer IL1 and the third dielectric layer IL3. For example, the second dielectric layer IL2 of the vertical portion SPO may have a thickness smaller than that of the third dielectric layer IL3 of the vertical portion SPO.

On the corner portion CPO of the inner spacer IS, the second dielectric layer IL2 may be disposed between the first dielectric layer IL1 and the third dielectric layer IL3. The second dielectric layer IL2 of the corner portion CPO may have a relatively large thickness compared to the thickness of the second dielectric layer IL2 in the vertical portion SPO or the horizontal portion TPO. The thickness of the second dielectric layer IL2 on the corner portion CPO may be greater than the thickness of the third dielectric layer IL3 on the corner portion CPO.

The inner spacer IS may have a maximum thickness TK3 at the corner portion CPO where the second dielectric layer IL2 has the maximum thickness. The horizontal portion TPO from which the second dielectric layer IL2 is omitted may have the minimum thickness TK1. In an embodiment, the second dielectric layer IL2 may be omitted on the vertical portion SPO. For example, the second dielectric layer IL2 may be disposed only on the corner portion CPO.

Referring to fig. 19, the third dielectric layer IL3 may be omitted from the internal spacer IS of fig. 18. For example, the inner spacer IS may include a first dielectric layer IL1 and a second dielectric layer IL2. The first dielectric layer IL1 may be conformally formed to have a uniform thickness. The second dielectric layer IL2 may have a thickness that is variable according to the position. The first dielectric layer IL1 may include, for example, a silicon oxide layer. The second dielectric layer IL2 may include a silicon nitride layer or a silicon oxynitride layer.

The second dielectric layer IL2 may be omitted on the horizontal portion TPO of the inner spacer IS. The first dielectric layer IL1 of the horizontal portion TPO may be directly interposed between the high-k dielectric layer HK and each of the first to third semiconductor patterns SP1 to SP 3.

On the vertical portion SPO of the inner spacer IS, a second dielectric layer IL2 may be disposed between the high-k dielectric layer HK and the first dielectric layer IL 1. For example, the second dielectric layer IL2 of the vertical portion SPO may have a thickness smaller than that of the first dielectric layer IL1 of the vertical portion SPO.

On the corner portion CPO of the inner spacer IS, a second dielectric layer IL2 may be disposed between the high-k dielectric layer HK and the first dielectric layer IL 1. The second dielectric layer IL2 of the corner portion CPO may have a relatively large thickness compared to the thicknesses of the second dielectric layers IL2 of the horizontal portion TPO and the vertical portion SPO. The thickness of the second dielectric layer IL2 on the corner portion CPO may be greater than the thickness of the first dielectric layer IL1 on the corner portion CPO.

Referring to fig. 4 and 20A to 20D, a device isolation layer ST may define first and second active patterns AP1 and AP2 on an upper portion of a substrate 100. The first active pattern AP1 may be defined on the first active area AR1, and the second active pattern AP2 may be defined on the second active area AR 2.

The device isolation layer ST may cover a lower sidewall of each of the first and second active patterns AP1 and AP2. An upper portion of each of the first and second active patterns AP1 and AP2 may protrude upward from the device isolation layer (see fig. 20D) and be defined by a first trench TR1, and an upper portion of each of the first and second active patterns AP1 and AP2 may be defined by a second trench TR2 formed on an upper portion of the substrate 100.

The first active pattern AP1 may include first source/drain patterns SD1 and first channel patterns CH1 between the first source/drain patterns SD1 on an upper portion thereof. The second active pattern AP2 may include second source/drain patterns SD2 and second channel patterns CH2 between the second source/drain patterns SD2 on an upper portion thereof.

Referring back to fig. 20D, each of the first and second channel patterns CH1 and CH2 may not include any of the first, second and third semiconductor patterns SP1, SP2 and SP3 discussed above with reference to fig. 5A to 5D. Each of the first channel pattern CH1 and the second channel pattern CH2 may have a semiconductor pillar shape protruding upward from the device isolation layer ST. Each of the first and second active patterns AP1 and AP2 may have a fin shape protruding from the device isolation layer ST.

The gate electrode GE may be disposed on a top surface and both sidewalls of each of the first and second channel patterns CH1 and CH 2. In this sense, the transistor according to the embodiment shown in fig. 20A to 20D may be a three-dimensional field effect transistor (e.g., finFET) in which the gate electrode GE three-dimensionally surrounds the first channel pattern CH1 and the second channel pattern CH 2.

The first interlayer dielectric layer 110 and the second interlayer dielectric layer 120 may be disposed on the entire surface of the substrate 100. The active contact AC may be disposed to penetrate the first and second interlayer dielectric layers 110 and 120 and be connected to the first and second source/drain patterns SD1 and SD2, respectively. The gate contact GC may be disposed to penetrate the second interlayer dielectric layer 120 and the gate cap pattern GP and be connected to the gate electrode GE.

A third interlayer dielectric layer 130 may be disposed on the second interlayer dielectric layer 120. A fourth interlayer dielectric layer 140 may be disposed on the third interlayer dielectric layer 130. The first metal layer M1 may be disposed in the third interlayer dielectric layer 130. The second metal layer M2 may be disposed in the fourth interlayer dielectric layer 140. The detailed description of the first and second metal layers M1 and M2 may be substantially the same as that discussed above with reference to fig. 4 and 5A to 5D.

The enlarged view of the portion N depicted in fig. 20A may be substantially the same as the view including the fourth portion PO4 of the gate electrode GE depicted in fig. 6 and the gate dielectric layer GI surrounding the fourth portion PO 4. Referring back to fig. 6 and 20A, the gate dielectric layer GI on the first channel pattern CH1 may include an internal spacer IS and a high-k dielectric layer HK.

The inner spacer IS on the second corner COR2 of the high-k dielectric layer HK may have a relatively large thickness TK6. Accordingly, it may be possible to prevent leakage current that easily occurs in the corner between the bottom surface and the sidewall of the gate electrode GE.

The three-dimensional field effect transistor may include an internal spacer configured such that the gate dielectric layer may prevent leakage current of the gate. The inner spacer may have an increased thickness at corner portions thereof susceptible to leakage current. Accordingly, it may be possible to prevent gate leakage current and improve electrical properties of the device.

The internal spacers of the various embodiments may include a horizontal portion having a relatively small thickness, and thus may provide sufficient internal gate space. Accordingly, the gate electrode can stably fill the internal gate space.

Although some embodiments have been discussed with reference to the accompanying drawings, it will be understood that various changes in form and detail may be made therein without departing from the spirit and scope of the features of the various embodiments. Accordingly, it will be understood that the above-described embodiments are merely illustrative in all respects and not restrictive.

Claims

1. A semiconductor device, the semiconductor device comprising:

a substrate including an active pattern;

a channel pattern on the active pattern, the channel pattern including a plurality of semiconductor patterns vertically stacked and spaced apart from each other;

source/drain patterns connected to the plurality of semiconductor patterns;

a gate electrode on the plurality of semiconductor patterns; and

a gate dielectric layer between the gate electrode and the plurality of semiconductor patterns,

wherein the gate electrode includes a first portion between a first semiconductor pattern and a second semiconductor pattern which are adjacent semiconductor patterns among the plurality of semiconductor patterns,

Wherein the gate dielectric layer comprises: a high-k dielectric layer surrounding a first portion of the gate electrode; and an internal spacer on the high-k dielectric layer,

wherein the inner spacer comprises: a horizontal portion having a first thickness between the high-k dielectric layer and the second semiconductor pattern; a vertical portion having a second thickness between the high-k dielectric layer and the source/drain pattern; and a corner portion between the horizontal portion and the vertical portion, the corner portion having a third thickness,

wherein the first thickness is smaller than the second thickness, and

wherein the second thickness is less than the third thickness.

2. The semiconductor device according to claim 1, wherein a ratio of the second thickness to the first thickness is in a range of 1.5 to 3.

3. The semiconductor device according to claim 1, wherein a ratio of the third thickness to the first thickness is in a range of 2.5 to 5.

4. The semiconductor device according to claim 1, wherein,

the first thickness is smaller than the thickness of the high-k dielectric layer, and

the third thickness is greater than the thickness of the high-k dielectric layer.

5. The semiconductor device of claim 1, wherein the inner spacer comprises a first dielectric layer and a second dielectric layer,

Wherein the first dielectric layer comprises a silicon oxide layer, an

Wherein the second dielectric layer comprises a silicon nitride layer or a silicon oxynitride layer.

6. The semiconductor device of claim 5, wherein the second dielectric layer is omitted on the horizontal portion.

7. The semiconductor device of claim 5, wherein the inner spacer further comprises a third dielectric layer,

wherein the third dielectric layer comprises a silicon oxide layer, an

Wherein the second dielectric layer is between the first dielectric layer and the third dielectric layer.

8. The semiconductor device of claim 1, wherein the internal spacers directly cover the first semiconductor pattern, the second semiconductor pattern, and the source/drain pattern.

9. The semiconductor device of claim 1, wherein the source/drain pattern comprises a protrusion protruding toward the first portion of the gate electrode,

wherein the protrusion of the source/drain pattern has a first convex sidewall directed to the first portion of the gate electrode, an

Wherein the first portion of the gate electrode has a second convex sidewall directed toward the first convex sidewall of the protrusion.

10. The semiconductor device according to claim 1, wherein the gate electrode further comprises: a second portion on an uppermost semiconductor pattern of the plurality of semiconductor patterns,

Wherein an inner spacer between the second portion and the uppermost semiconductor pattern has a fourth thickness,

wherein the inner spacer between the second portion and the gate spacer has a fifth thickness,

wherein an inner spacer between the second portion and an inner corner of the uppermost semiconductor pattern contact gate spacer has a sixth thickness

Wherein the fourth thickness is smaller than the fifth thickness, and

wherein the fifth thickness is less than the sixth thickness.

11. A semiconductor device, the semiconductor device comprising:

a substrate including an active pattern;

a pair of source/drain patterns on the active pattern, the plurality of semiconductor patterns being between the pair of source/drain patterns;

a gate electrode on the plurality of semiconductor patterns; and

wherein the gate electrode includes a portion between a first semiconductor pattern and a second semiconductor pattern which are adjacent semiconductor patterns among the plurality of semiconductor patterns,

wherein the gate dielectric layer comprises: a high-k dielectric layer surrounding the portion of the gate electrode; and

An internal spacer on the high-k dielectric layer,

wherein an inner region is defined by the pair of source/drain patterns, the first semiconductor pattern and the second semiconductor pattern,

wherein the inner spacer is disposed within the inner region,

wherein the inner spacer includes an inner gate space,

wherein the high-k dielectric layer and the portion of the gate electrode are in the internal gate space,

wherein the inner region has a first side, and

wherein the internal gate space has a second side adjacent to the first side.

12. The semiconductor device of claim 11, wherein the inner spacer comprises:

a horizontal portion between the high-k dielectric layer and the second semiconductor pattern;

a vertical portion between the high-k dielectric layer and one of the pair of source/drain patterns; and

corner portions, between the horizontal portion and the vertical portion,

wherein the thickness of the vertical portion is greater than the thickness of the horizontal portion, and

wherein the thickness of the corner portion is greater than the thickness of the vertical portion.

13. The semiconductor device of claim 11, wherein each of the pair of source/drain patterns comprises a protrusion protruding toward the portion of the gate electrode,

Wherein the protrusion has a first convex sidewall directed toward the portion of the gate electrode, an

Wherein the portion of the gate electrode has a second convex sidewall directed toward the first convex sidewall of the protrusion.

14. The semiconductor device of claim 13, wherein,

a first side of the inner region is concave corresponding to the first convex side wall, and

the second side of the interior region is convex corresponding to the second convex sidewall.

15. The semiconductor device of claim 11, wherein the inner spacer comprises a first dielectric layer and a second dielectric layer,

wherein the first dielectric layer comprises a silicon oxide layer, an

16. A semiconductor device, the semiconductor device comprising:

a substrate including an active region;

a device isolation layer defining an active pattern on the active region;

a channel pattern and a source/drain pattern on the active pattern, the channel pattern including a plurality of semiconductor patterns vertically stacked and spaced apart from each other;

a gate electrode on the plurality of semiconductor patterns;

a gate dielectric layer between the plurality of semiconductor patterns and the gate electrode;

a gate spacer on sidewalls of the gate electrode;

A gate cap pattern on a top surface of the gate electrode;

an interlayer dielectric layer on the gate cap pattern;

an active contact penetrating the interlayer dielectric layer and electrically connected to the source/drain pattern;

a metal-semiconductor compound layer between the active contact and the source/drain pattern;

a gate contact penetrating the interlayer dielectric layer and the gate cap pattern and electrically connected to the gate electrode;

a first metal layer on the interlayer dielectric layer, the first metal layer including a power line and a plurality of first lines electrically connected to the active contact and the gate contact, respectively; and

a second metal layer on the first metal layer,

wherein the second metal layer includes a plurality of second wires electrically connected to the first metal layer,

wherein the source/drain pattern includes a protrusion protruding toward the portion of the gate electrode,

wherein the protrusion of the source/drain pattern has a first convex sidewall directed to the portion of the gate electrode, and

17. The semiconductor device of claim 16, wherein the gate dielectric layer comprises:

a high-k dielectric layer surrounding the portion of the gate electrode; and

an internal spacer on the high-k dielectric layer,

wherein the inner spacer covers the first convex sidewall, an

Wherein the high-k dielectric layer covers the second convex sidewall.

18. The semiconductor device of claim 17, wherein the inner spacer comprises:

a horizontal portion having a first thickness between the high-k dielectric layer and the second semiconductor pattern;

a vertical portion having a second thickness between the high-k dielectric layer and the source/drain pattern; and

a corner portion, between the horizontal portion and the vertical portion, the corner portion having a third thickness,

wherein the first thickness is smaller than the second thickness, and

wherein the second thickness is less than the third thickness.

19. The semiconductor device according to claim 18, wherein a ratio of the second thickness to the first thickness is in a range of 1.5 to 3.

20. The semiconductor device according to claim 18, wherein a ratio of the third thickness to the first thickness is in a range of 2.5 to 5.