CN114765131A - Method for forming semiconductor structure - Google Patents

Method for forming semiconductor structure Download PDF

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Publication number
CN114765131A
CN114765131A CN202110032936.2A CN202110032936A CN114765131A CN 114765131 A CN114765131 A CN 114765131A CN 202110032936 A CN202110032936 A CN 202110032936A CN 114765131 A CN114765131 A CN 114765131A
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layer
forming
gate
groove
mask
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涂武涛
王彦
邱晶
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Priority to CN202110032936.2A priority Critical patent/CN114765131A/en
Publication of CN114765131A publication Critical patent/CN114765131A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823821—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823857—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

A method for forming a semiconductor structure, the method comprising: providing a substrate, wherein the substrate comprises a first area and a second area, and the substrate comprises a substrate, a fin part, an isolation layer, a pseudo gate structure and an interlayer dielectric layer, the fin part is separated from the substrate, the isolation layer is positioned on the fin part and exposed out of the substrate, the pseudo gate structure is positioned on the isolation layer and stretches across the fin part, and the interlayer dielectric layer covers the side wall of the pseudo gate structure and exposes out of the top of the pseudo gate structure; removing the pseudo gate structure, and forming a gate opening in the interlayer dielectric layer; forming an annealing sacrificial layer in the gate opening; removing the annealing sacrificial layer; forming a mask layer with a first groove, wherein the extending direction of the first groove is the same as that of the fin part, and the first groove exposes a part of a grid opening at the junction of the first area and the second area; a first blocking layer is formed in the first groove. Therefore, the removing process window of the annealing sacrificial layer at the junction of the first region and the second region is large, and residue is not easy to exist, so that the threshold voltage of the semiconductor structure can be better controlled by the first gate structure and the second gate structure.

Description

Method for forming semiconductor structure
Technical Field
The embodiment of the invention relates to the field of semiconductor manufacturing, in particular to a method for forming a semiconductor structure.
Background
In Semiconductor manufacturing, with the trend of ultra-large scale integrated circuits, the feature size of the integrated circuit is continuously reduced, and in order to adapt to smaller feature sizes, the channel length of a Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) is also continuously shortened correspondingly. However, as the channel length of the device is shortened, the distance between the source and the drain of the device is also shortened, so that the controllability of the gate structure to the channel is deteriorated, and the difficulty of the gate voltage to pinch off the channel is increased, so that a sub-threshold leakage (SCE) phenomenon, which is a so-called short-channel effect (SCE), is more likely to occur.
Therefore, in order to better accommodate the reduction of feature sizes, semiconductor processing is gradually beginning to transition from planar MOSFETs to three-dimensional transistors with higher power efficiency, such as fin field effect transistors (finfets). In the FinFET, the gate structure can control the ultrathin body (fin part) at least from two sides, and compared with a planar MOSFET, the gate structure has stronger control capability on a channel and can well inhibit a short-channel effect; the gate structure is also shifted from the original polysilicon gate structure to a metal gate structure in which a work function layer is capable of adjusting the threshold voltage of the semiconductor structure.
The threshold voltage is an important parameter of a transistor and has a significant impact on the performance of the transistor.
Disclosure of Invention
The embodiment of the invention provides a method for forming a semiconductor structure, so that the threshold voltage of the semiconductor structure meets the process requirement, and the electrical performance of the semiconductor structure is optimized.
To solve the above problems, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate, wherein the substrate comprises a first area and a second area which are adjacent to each other, and the substrate comprises a substrate, a fin part which is separated from the substrate, an isolation layer which is positioned on the fin part and exposed out of the substrate, a dummy gate structure which is positioned on the isolation layer and stretches across the fin part, and an interlayer dielectric layer which covers the side wall of the dummy gate structure and exposes out of the top of the dummy gate structure; removing the pseudo gate structure, and forming a gate opening in the interlayer dielectric layer; forming a gate dielectric layer which conformally covers the gate opening; forming an annealing sacrificial layer covering the gate dielectric layer in the gate opening; removing the annealing sacrificial layer; after removing the annealing sacrificial layer, forming a mask layer with a first groove in the gate opening and on the interlayer dielectric layer, wherein the extending direction of the first groove is the same as that of the fin part, and the first groove exposes part of the gate opening at the junction of the first area and the second area; a first blocking layer is formed in the first recess.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following advantages:
in the method for forming the semiconductor structure provided by the embodiment of the invention, the dummy gate structure is removed, a gate dielectric layer which conformally covers the gate opening is formed after the gate opening is formed in the interlayer dielectric layer, and the gate dielectric layer is repaired in the step of forming the annealing sacrificial layer after the gate dielectric layer is formed, so that the density of the gate dielectric layer is improved; after the annealing sacrificial layer is removed, a mask layer with a first groove is formed in the grid opening and on the interlayer dielectric layer, the extending direction of the first groove is the same as that of the fin portion, the grid opening at the junction of the first area and the second area is exposed out of the first groove, and a first blocking layer is formed in the first groove. In the embodiment of the invention, compared with the situation that after the dummy gate structure is formed, the blocking layer penetrating through the dummy gate structure at the junction of the first area and the second area is formed, then the dummy gate structure is removed to form the gate opening, the gate dielectric layer and the annealing sacrificial layer covering the gate dielectric layer are formed in the gate opening, and then the annealing sacrificial layer is removed, in the step of removing the annealing sacrificial layer, the blocking layer is not formed at the junction of the first area and the second area, so that the removing process window of the annealing sacrificial layer at the junction of the first area and the second area is larger, the removing process window is easy to remove and has less possibility of residue, the mask layer is removed subsequently, the first gate structure is formed in the gate opening of the first area, the second gate structure is formed in the gate opening of the second area, and the first gate structure and the second gate structure are not formed on the residual annealing sacrificial layer, the first grid structure and the second grid structure can better control the threshold voltage of the semiconductor structure, and the electrical reliability of the semiconductor structure is improved.
In an alternative scheme, in the step of forming the mask layer, the mask layer further has a second groove exposing a part of the gate opening, and an extending direction of the second groove is perpendicular to an extending direction of the fin portion. The mask layer formed in the embodiment of the invention is provided with the first groove and the second groove at the same time, namely the first groove and the second groove are formed by adopting an integrated (All in one, AIO) etching process. In addition, after the mask layer is formed and before the first blocking layer is formed, the fin part exposed out of the second groove is removed, a second opening is formed, and in the step of forming the first blocking layer in the first groove, a second blocking layer is formed in the second groove and the opening, namely the first blocking layer and the second blocking layer are formed simultaneously.
Drawings
Fig. 1 to 13 are schematic structural diagrams corresponding to respective steps in a method for forming a semiconductor structure;
fig. 14 to 32 are schematic structural views corresponding to steps in a method for forming a semiconductor structure according to an embodiment of the invention.
Detailed Description
As can be seen from the background art, the semiconductor structure formed at present still has a problem of poor electrical performance. The reason for the poor electrical performance of the semiconductor structure is analyzed in combination with a method for forming the semiconductor structure.
Referring to fig. 1 to 13, schematic structural diagrams corresponding to steps in a method for forming a semiconductor structure are shown.
As shown in fig. 1 and 2, fig. 1 is a top view, fig. 2 is a cross-sectional view of fig. 1 at aa, a substrate is provided, the substrate includes a substrate 1, a fin portion 2 discrete on the substrate 1, an isolation layer 4 located on the fin portion 2 exposed out of the substrate 1, a dummy gate structure 3 located on the isolation layer 4 and crossing the fin portion 2, and source and drain doping layers (not shown in the figure) located in the fin portion 2 at two sides of the dummy gate structure 3, and the substrate includes a first region I and a second region II which are adjacent to each other.
The pseudo gate structure 3 is formed by a Self-aligned Double Patterning (SADP) process, and specifically, the forming process of the pseudo gate structure 3 includes: forming a pseudo gate material layer covering the fin part 2 on the isolation layer 4; forming a core layer (mandrel) (not shown) on the dummy gate material layer; forming a side wall material layer (not shown in the figure) conformally covering the core layer and the pseudo gate material layer; removing the side wall material layers on the top of the core layer and the top of the pseudo gate material layer, and taking the rest side wall material layers positioned on the side wall of the core layer as side wall layers; removing the core layer; and patterning the pseudo gate material layer by taking the side wall layer as a mask to form the pseudo gate structure 3.
It should be noted that both ends of the core layer in the extending direction are located outside the first region I and the second region II, and both ends of the corresponding pseudo gate structure 3 in the extending direction are located outside the first region I and the second region II.
As shown in fig. 3 and 4, fig. 3 is a top view, fig. 4 is a cross-sectional view of fig. 3 at aa, an interlayer dielectric layer 5 covering the source-drain doped layer is formed, and the interlayer dielectric layer 5 exposes the top of the dummy gate structure 3; forming a mask layer (not shown in the figure) on the interlayer dielectric layer 5 and the dummy gate structure 3, wherein the mask layer is provided with an opening for exposing part of the dummy gate structure 3 on the isolation layer 4 at the junction of the first area I and the second area II; removing the dummy gate structure 3 exposed by the opening, and forming a blocking opening (P2 cut) (not shown in the figure) for cutting off a part of the dummy gate structure 3 on the isolation layer 4 at the junction of the first region I and the second region II in a direction perpendicular to the extending direction of the dummy gate structure 3; a blocking layer 6 is formed in the blocking opening.
It should be noted that the opening in the mask layer also exposes the dummy gate structure 3 outside the first region I and the second region II; in the process of forming the blocking opening, the pseudo gate structures 3 outside the first area I and the second area II are etched to form an external opening; in the process of forming the blocking layer 6 in the blocking opening, the external blocking layer 7 is formed in the external opening.
As shown in fig. 5 and 6, fig. 5 is a top view, and fig. 6 is a cross-sectional view at aa of fig. 5, where the dummy gate structure 3 is removed to form a gate opening 8.
As shown in fig. 7, forming a gate dielectric layer 9 conformally covering the gate opening 8; forming a cap layer (not shown in the figure) which conformally covers the gate dielectric layer 9 in the gate opening 8; forming an annealing sacrificial layer (not shown in the figure) covering the cap layer, wherein the forming process of the annealing sacrificial layer comprises annealing treatment (Anneal) for repairing the gate dielectric layer 9 and improving the density of the gate dielectric layer 9; and removing the annealing sacrificial layer.
As shown in fig. 8 and 9, fig. 8 is a top view, fig. 9 is a cross-sectional view at aa of fig. 8, and a first work function layer (not shown) is formed in the first region I; forming a second work function layer (not shown in the figure) in the second region II; a gate layer (not shown) is formed on the first work function layer and the second work function layer, the first work function layer and the gate layer serve as a first gate structure 10, and the second work function layer and the gate layer serve as a second gate structure 11.
As shown in fig. 10 and 11, fig. 10 is a top view, and fig. 11 is a cross-sectional view at aa of fig. 10, a shielding layer 12 is formed on the first gate structure 10, the second gate structure 11, the blocking layer 6 and the outer blocking layer 7, the shielding layer 12 has a recess 13 therein, and the recess 13 exposes a portion of the first gate structure 10 and the second gate structure 11.
As shown in fig. 12, the first gate structure 10 and the second gate structure 11 exposed by the recess 13 and the fin portion 2 are etched by using the shielding layer 12 as a mask to form a Single Diffusion Break (SDB) opening 14.
As shown in fig. 13, a single diffusion break layer 15 is formed in the single diffusion break opening 14.
The step of forming the annealing sacrificial layer includes annealing treatment, and the annealing treatment is used for repairing the gate dielectric layer 9, so that the quality and performance of the gate dielectric layer 9 are improved, and further the electrical performance and reliability performance of the formed semiconductor structure are improved. The blocking opening cuts off a part of the dummy gate structure 3 on the isolation layer 4 at the junction of the first region I and the second region II, because the isolation layer 4 is formed on the substrate 1 between the fins 2, the blocking opening is located on the isolation layer 4 between the fins 2, and the corresponding blocking layer 6 is located on the isolation layer 4 between the fins 2. As the integration level of the semiconductor structure is higher and higher, the spacing between adjacent fins 2 is smaller and smaller, and the blocking layer 6 is located between the fins 2, so that the spacing between the blocking layer 6 and the fins 2 is smaller and smaller, and the corresponding spacing between the outer blocking layer 7 and the fins 2 in the first region I and the second region II is smaller. In the step of removing the annealed sacrificial layer, since the removal window of the annealed sacrificial layer between the blocking layer 6 and the fin portion 2 is small, a residual annealed sacrificial layer 20 is liable to exist (as shown in fig. 7), and the residual annealed sacrificial layer 20 is also liable to exist between the outer blocking layer 7 and the fin portions 2 in the first region I and the second region II.
In the subsequent process of forming the first gate structure 10 and the second gate structure 11, the second gate structure 11 may be formed on the residual annealing sacrificial layer 20, and when the semiconductor structure operates, the residual annealing sacrificial layer 20 formed in the second region II may cause the threshold voltage of the second region II to not meet the process requirement, and in addition, may also cause the electrical reliability of the semiconductor structure to be poor.
In addition, it should be noted that, forming the blocking opening, forming the blocking layer 6 in the blocking opening, forming the single diffusion interruption opening 14, and forming the single diffusion interruption layer 15 in the single diffusion interruption opening 14, the blocking opening and the single diffusion interruption opening 14 are formed in different steps, which results in that the forming step of the semiconductor structure is complicated, which is not beneficial to improving the forming efficiency of the semiconductor structure, and the yield is not high.
In the process of etching the groove 13 to expose portions of the first gate structure 10, the second gate structure 11 and the fin portion 2 to form the single diffusion interruption opening 14, the gate layer, the first work function layer and the second work function layer need to be etched, which results in poor process controllability.
In order to solve the technical problem, in the method for forming the semiconductor structure provided by the embodiment of the invention, the dummy gate structure is removed, a gate dielectric layer which conformally covers the gate opening is formed after the gate opening is formed in the interlayer dielectric layer, and the gate dielectric layer is repaired in the step of forming the annealing sacrificial layer so as to improve the density of the gate dielectric layer after the gate dielectric layer is formed; after the annealing sacrificial layer is removed, a mask layer with a first groove is formed in the grid opening and on the interlayer dielectric layer, the extending direction of the first groove is the same as that of the fin portion, the grid opening at the junction of the first area and the second area is exposed out of the first groove, and a first blocking layer is formed in the first groove. In the embodiment of the invention, compared with the situation that after the dummy gate structure is formed, the blocking layer penetrating through the dummy gate structure at the junction of the first area and the second area is formed, then the dummy gate structure is removed, the gate opening is formed, the gate dielectric layer and the annealing sacrificial layer covering the gate dielectric layer are formed in the gate opening, and then the annealing sacrificial layer is removed, in the step of removing the annealing sacrificial layer, the blocking layer is not formed at the junction of the first area and the second area, so that the removing process window of the annealing sacrificial layer at the junction of the first area and the second area is larger, the removing process window is easy to remove, residues are not easy to exist, the mask layer is removed subsequently, the first gate structure is formed in the gate opening of the first area, the second gate structure is formed in the gate opening of the second area, and the first gate structure and the second gate structure are not formed on the residual annealing sacrificial layer, the first grid structure and the second grid structure can better control the threshold voltage of the semiconductor structure, and the electrical reliability of the semiconductor structure is improved.
Fig. 14 to 32 are schematic structural views corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention.
Referring to fig. 14 to 15, fig. 14 is a top view, and fig. 15 is a cross-sectional view at AA of fig. 14, which provides a base, where the base includes a first region I and a second region II, and the base includes a substrate 100, a fin 104 separated from the substrate 100, an isolation layer 101 on the fin 104 exposed from the substrate 100, a dummy gate structure 102 on the isolation layer 101 and crossing the fin 104, and an interlayer dielectric layer 103 covering sidewalls of the dummy gate structure 102 and exposing a top of the dummy gate structure 102.
The substrate provides a process foundation for the subsequent formation of a semiconductor structure. In this embodiment, the first region I is used to form an nmos (negative Channel Metal Oxide semiconductor), and the second region II is used to form a pmos (positive Channel Metal Oxide semiconductor). In other embodiments, the first region I is used to form a PMOS, and the second region II is used to form an NMOS. In other embodiments, the first region I and the second region II may form a PMOS or an NMOS simultaneously.
In the present embodiment, the subsequent formation of the semiconductor structure is exemplified by a fin field effect transistor (FinFET). In other embodiments, the substrate further includes a channel stack on the fin, the channel stack includes a sacrificial layer and a channel layer on the sacrificial layer, and accordingly, the subsequently formed semiconductor structure is a gate all around transistor (GAA).
In this embodiment, the substrate 100 is a silicon substrate. In other embodiments, the material of the substrate may also be other materials such as germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, and the substrate may also be another type of substrate such as a silicon-on-insulator substrate or a germanium-on-insulator substrate.
The fins 104 are located in the first region I and the second region II.
In this embodiment, the fin 104 is made of the same material as the substrate 100, and includes silicon.
The isolation layer 101 is used to electrically isolate the substrate 100 from a subsequently formed gate structure. The isolation layer 101 covers a portion of the sidewall of the fin 104.
In this embodiment, the material of the isolation layer 101 includes silicon oxide. The silicon oxide is a dielectric material with a common process and low cost, has high process compatibility, and is beneficial to reducing the process difficulty and the process cost for forming the isolation layer 101.
The dummy gate structure 102 is used to occupy process space for the subsequent formation of a gate structure.
In this embodiment, the dummy gate structure 102 adopts a Self-aligned Double Patterning (SADP) process. In other embodiments, the dummy gate structure may be formed by a self-aligned quadruple patterning (SAQP).
Specifically, the step of forming the dummy gate structure 102 includes: forming a dummy gate material layer covering the fin portion 104 on the isolation layer 101; forming a core layer (mandrel) (not shown) on the dummy gate material layer; forming a side wall material layer (not shown in the figure) which conformally covers the core layer and the pseudo gate material layer; removing the side wall material layers on the top of the core layer and the top of the pseudo gate material layer, and taking the rest side wall material layers positioned on the side wall of the core layer as side wall layers; removing the core layer; and patterning the pseudo gate material layer by taking the side wall layer as a mask to form the pseudo gate structure 102.
Because the side wall material layer covers the side wall and the end of the core layer, the side wall layer is annular, correspondingly, the dummy gate structure 102 is annular, the extending direction of the dummy gate structure 102 in the first region I and the second region II is perpendicular to the fin portion 104, and two ends of the dummy gate structure 102 along the extending direction are located outside the first region I and the second region II.
Two ends of the dummy gate structure 102 along the extending direction thereof are located outside the first region I and the second region II, so that the length of the dummy gate structure 102 can meet the requirements of the process. Accordingly, in the step of forming the core layer, the core layer crosses the first region I and the second region II in the extending direction of the core layer, and both ends of the core layer in the extending direction thereof are located outside the first region I and the second region II.
In this embodiment, the dummy gate structure 102 is a stacked structure, and includes a dummy gate oxide layer (not shown in the figure) and a dummy gate layer (not shown in the figure) on the dummy gate oxide layer. In other embodiments, the dummy gate structure may also be a single-layer structure.
Specifically, the dummy gate oxide layer comprises silicon oxide, and the dummy gate layer comprises polysilicon.
In the step of providing a substrate, the substrate further comprises: and source and drain doping layers (not shown) located in the fin portions 104 on two sides of the dummy gate structure 102.
When the semiconductor structure works, the source-drain doped layers are used for providing stress for the channel and improving the migration rate of current carriers in the channel.
In this embodiment, the first region I is used to form an NMOS, and the source-drain doping layer is silicon carbide or silicon phosphide doped with N-type ions. In this embodiment, the N-type ions include: phosphorus, arsenic or antimony. The second region II is used to form a PMOS. The source-drain doped layer is silicon germanium doped with P-type ions. In this embodiment, the P-type ions include: boron, gallium or indium.
It should be noted that, in the step of providing a substrate, the substrate further includes: and a sidewall layer (not shown) formed on the sidewall of the dummy gate structure 102. The source-drain doping layer and the subsequently formed gate structure are not easy to bridge, the capacitive coupling effect of the source-drain doping layer and the gate structure is reduced, and the electrical performance of the semiconductor structure is improved.
The material of the side wall layer comprises: SiON, SiBCN, SiCN, SiN. In this embodiment, the material of the sidewall layer is SiN.
The interlevel dielectric layer 103 serves to electrically isolate adjacent devices.
In this embodiment, the interlayer dielectric layer 103 is made of an insulating material. Specifically, the material of the interlayer dielectric layer 103 includes silicon oxide. The silicon oxide is a dielectric material with common process and low cost, has high process compatibility, and is beneficial to reducing the process difficulty and the process cost for forming the interlayer dielectric layer 103.
It should be noted that the interlayer dielectric layer 103 exposes the top of the dummy gate structure 102, so as to prepare for removing the dummy gate structure 102 subsequently.
Referring to fig. 16 and 17, the dummy gate structure 102 is removed, and a gate opening 105 is formed in the interlayer dielectric layer 103.
The gate opening 105 provides for the subsequent formation of a gate structure.
In this embodiment, the dummy gate structure 102 is removed by a wet etching process. The wet etching process has the advantages of high etching rate, simple operation and low process cost.
In this embodiment, the dummy gate structure 102 includes a dummy gate oxide layer and a dummy gate layer. The material of the pseudo gate oxide layer is silicon oxide, and the material of the pseudo gate layer is polycrystalline silicon. Specifically, in the step of removing the dummy gate structure 102, the etching solution used includes ammonia water and a tetramethylammonium hydroxide solution.
It should be noted that, because two ends of a portion of the dummy gate structure 102 in a direction perpendicular to the extending direction of the fin 104 are located outside the first region I and the second region II, in the step of forming the gate opening 105, the gate opening 105 is also formed outside the first region I and the second region II.
Referring to fig. 18, a gate dielectric layer 106 is formed conformally covering the gate opening 105.
The gate dielectric layer 106 is used to electrically isolate the fin 104 from a subsequently formed gate structure. The gate dielectric layer 106 is made of a high-k dielectric material. Wherein, the high-k dielectric material is a dielectric material with a relative dielectric constant larger than that of silicon oxide.
In this embodiment, the gate dielectric layer 106 is made of HfO2. In other embodiments, the material of the gate dielectric layer 106 may also be selected from ZrO2、HfSiO、HfSiON、HfTaO, HfTiO, HfZrO or Al2O3One or more of them.
In this embodiment, the gate dielectric Layer 106 is formed by an Atomic Layer Deposition (ALD) process. The atomic layer deposition process can accurately control the thickness of the gate dielectric layer 106, and the atomic layer deposition process has good gap filling performance and step coverage, so that the gate dielectric layer 106 can conformally cover the bottom and the side wall of the gate opening 105, and the fin portion 104 and a subsequently formed gate structure can be better electrically isolated. In other embodiments, the gate dielectric layer may also be formed by a Chemical Vapor Deposition (CVD) process.
The method for forming the semiconductor structure further comprises the following steps: after forming the gate dielectric layer 106 conformally covering the gate opening 105, a capping layer 107 conformally covering the gate opening 105 is formed.
After the cap layer 107 is formed, an annealing sacrificial layer is formed in the gate opening 105, and the forming process of the annealing sacrificial layer includes annealing treatment for repairing the gate dielectric layer 106 and improving the density of the gate dielectric layer 106. In the step of removing the annealed sacrificial layer, the cap layer 107 is used to protect the gate dielectric layer 106 from being damaged.
In addition, after the annealing sacrificial layer is subsequently removed, a work function layer is formed on the cap layer 107, the cap layer 107 is formed between the gate dielectric layer 106 and the work function layer, the cap layer 107 prevents metal ions in the work function layer from being easily diffused into the gate dielectric layer 106, and meanwhile, the cap layer 107 also prevents oxygen ions in the gate dielectric layer 106 from being easily diffused into the work function layer, so that the problem of increase of oxygen vacancy content in the gate dielectric layer 106 is not easily caused.
In this embodiment, the capping layer 107 is made of TiN. In other embodiments, the material of the cap layer may also be TiSiN or TaN.
In this embodiment, the cap layer 107 is formed by an atomic layer deposition process. In other embodiments, the cap layer may be formed by a physical vapor deposition process.
With continued reference to fig. 18, after the gate dielectric layer 106 is formed, an annealed sacrificial layer 108 is formed in the gate opening 106.
The step of forming the annealed sacrificial layer 108 includes an annealing treatment, which is used to repair the gate dielectric layer 106, improve the density of the gate dielectric layer 106, facilitate the improvement of the quality and performance of the gate dielectric layer 106, and improve the electrical performance and reliability performance of the formed semiconductor structure, such as Positive Bias Temperature Instability (PBTI) of NMOS; in addition, the capping layer 107 is closer to the fin 104 than a subsequently formed work function layer, and the annealing process is also used for adsorbing oxygen in the capping layer 107, which is beneficial to improving the stability and reliability of the threshold voltage of the semiconductor structure.
The etching difficulty of the annealing sacrificial layer 108 is smaller than that of the cap layer 107, so that in the subsequent step of removing the annealing sacrificial layer 108, the cap layer 107 can protect the gate dielectric layer 106.
In this embodiment, the material of the annealed sacrificial layer 108 includes: amorphous silicon (a-Si).
The step of forming an annealed sacrificial layer 108 covering the gate opening 106 comprises: forming a sacrificial material layer (not shown) in the gate opening 106 to cover the gate dielectric layer 106; and annealing the sacrificial material layer to form the annealed sacrificial layer 108.
In this embodiment, the sacrificial material layer is formed by a chemical vapor deposition process.
It should be noted that, in the step of forming the annealing sacrificial layer 108, the first work function layer matched with the first region I, the second work function layer matched with the second region II, and the gate layer on the first work function layer and the second work function layer are not formed in the first region I, that is, in the step of forming the annealing sacrificial layer 108, the high temperature of the annealing process does not affect the first work function layer, the second work function layer, and the gate layer to be formed subsequently, so that performance deviation does not occur easily in the first work function layer, the second work function layer, and the gate layer to be formed subsequently.
Referring to fig. 19, the annealed sacrificial layer 108 is removed.
In the method for forming the semiconductor structure provided by the embodiment of the invention, the dummy gate structure 102 is removed, the gate dielectric layer 106 which conformally covers the gate opening 105 is formed after the gate opening 105 is formed in the interlayer dielectric layer 103, and the gate dielectric layer 106 is repaired in the step of forming the annealing sacrificial layer 108 after the gate dielectric layer 106 is formed, so that the density of the gate dielectric layer 108 is improved; after removing the annealed sacrificial layer 108, a mask layer with a first groove is formed in the gate opening 105 and on the interlayer dielectric layer 103, the extending direction of the first groove is the same as the extending direction of the fin 104, the gate opening 105 at the junction of the first area I and the second area II is exposed by the first groove, and a first blocking layer is formed in the first groove. In the embodiment of the present invention, compared with the case where after the dummy gate structure is formed, the blocking layer penetrating through the dummy gate structure at the junction between the first region and the second region is formed, the dummy gate structure is removed, the gate opening is formed, the gate dielectric layer is formed in the gate opening, the gate dielectric layer is covered in the gate opening, after the gate dielectric layer is formed, the annealing sacrificial layer is formed in the gate opening, and then the annealing sacrificial layer is removed, in the step of removing the annealing sacrificial layer 108 in the embodiment of the present invention, the blocking layer is not formed at the junction between the first region I and the second region II, so that the process window for removing the annealing sacrificial layer 108 at the junction between the first region I and the second region II is large, and is easy to remove and difficult to have residue, and then the first gate structure is formed in the gate opening 105 of the first region I, and the second gate structure is formed in the gate opening 105 of the second region II, the first gate structure and the second gate structure are not formed on the residual annealing sacrificial layer 108, so that the first gate structure and the second gate structure can better control the threshold voltage of the semiconductor structure, and the electrical reliability of the semiconductor structure is improved.
The annealed sacrificial layer 108 is removed in preparation for subsequently forming a first gate structure in the first region I and a second gate structure in the second region II.
In this embodiment, the annealed sacrificial layer 108 is removed by a wet etching process. The wet etching process has isotropic etching characteristic, high etching rate, simple operation and low process cost. In other embodiments, the annealed sacrificial layer may be removed by a dry etching process.
In this embodiment, the material of the annealing sacrificial layer 108 includes amorphous silicon, the material of the cap layer 107 is TiN, the TiN is a metal material, in the step of removing the annealing sacrificial layer 108, the etched rate of the cap layer 107 is smaller than the etched rate of the annealing sacrificial layer 108, and in the process of removing the annealing sacrificial layer 108 by using a wet etching process, the cap layer 107 is not easily damaged, so that the top of the cap layer 107 can be used as a removal stop position of the annealing sacrificial layer 108, and the corresponding gate dielectric layer 106 covered by the cap layer 107 is not easily damaged.
It should be noted that the cap layer 107 can also be used as a work function layer for adjusting threshold voltages of NMOS and PMOS, and therefore, the cap layer 107 in the region for forming the first gate structure and the second gate structure later is not removed.
In this embodiment, after the annealing sacrificial layer 108 is removed, the film materials in the first region I and the second region II are the same and are both the gate dielectric layer 106 and the capping layer 107 located on the gate dielectric layer 106, and the annealing sacrificial layer 108 is not easy to have residue.
Referring to fig. 20 to 23, fig. 21 is a cross-sectional view at AA of fig. 20, fig. 23 is a cross-sectional view at AA of fig. 22, after removing the annealed sacrificial layer 108, a mask layer 110 (as shown in fig. 23) having a first recess 109 is formed in the gate opening 105 and on the interlayer dielectric layer 103, an extending direction of the first recess 109 is the same as an extending direction of the fin 104, and the first recess 109 exposes a portion of the gate opening 105 at a boundary between the first region I and the second region II.
The first recess 109 exposes a portion of the gate opening 105 at the boundary between the first region I and the second region II, so as to provide a process space for forming a first blocking layer in the gate opening 105 at the boundary between the first region I and the second region II.
A first blocking layer is formed in the first groove 109, and in a direction perpendicular to the extending direction of the fin 104, the mask layer 110 of the first region I on one side of the first groove 109 is replaced by a first gate structure, the mask layer 110 of the second region II on the other side of the first groove 109 is replaced by a second gate structure, the first blocking layer is used for blocking a portion of the first gate structure of the first region I and the second gate structure of the second region II, and the purpose of the first groove 109 is the same as that of an opening formed by a conventional gate cut (P2 cut) process.
In this embodiment, the mask layer 110 is a material that can function as a mask and is easy to remove, and damage to the gate opening 105 and the interlayer dielectric layer 103 can be reduced when the mask layer 110 is subsequently removed.
In this embodiment, the mask layer 110 includes a bottom anti-reflective coating (BARC). In other embodiments, the masking layer may also include a layer of fill material, or both a layer of fill material and an anti-reflective coating on the layer of fill material.
Specifically, the bottom anti-reflective coating material comprises: BARC (bottom-reflective coating) material, DARC (dielectric anti-reflective coating) material.
The layer of filler material comprises: an ODL (organic dielectric layer) material, or an SOC (spin on carbon) material.
The step of forming the mask layer 110 includes: forming the mask material layer 113 covering the first region I and the second region II; forming a photoresist layer 114 on the masking material layer 113; and etching the mask material layer 113 by taking the photoresist layer 114 as a mask, wherein the residual mask material layer 113 is taken as a mask layer 110.
In this embodiment, the mask material layer 113 is formed by a spin coating process.
Specifically, the mask material layer 113 is etched by using the photoresist layer 114 as a mask through a dry etching process to form the mask layer 110. The dry etching process has anisotropic etching characteristics, has good etching profile controllability, can obtain quite accurate pattern conversion, and is beneficial to enabling the appearance of the first groove 109 in the mask layer 110 to meet the process requirements.
In the step of etching the mask material layer 113 by using the photoresist layer 114 as a mask, the mask material layer 113 is made of a bottom anti-reflection coating and is a material layer easy to remove, so that the mask material layer 113 is not easy to remain in the exposed region of the photoresist layer 114, and the process controllability is high. Correspondingly, in the subsequent process of etching the cap layer 107 and the gate dielectric layer 106 in the exposed region of the photoresist layer 114, the cap layer 107 and the gate dielectric layer 106 should not have residues.
It should be noted that, the first groove 109 also exposes a portion of the interlayer dielectric layer 108 between the first region I and the second region II.
It should be noted that, in the step of forming the mask layer 110, the first groove 109 also exposes the gate opening 105 outside the first region I and the second region II (i.e., the end position of the gate opening 105 along the extending direction thereof). The gate opening 105 outside the first region I and the second region II provides for the subsequent formation of a first blocking layer.
It should be noted that, in the step of forming the mask layer 110, the mask layer 110 further has a second groove 112 exposing a portion of the gate opening 105, and an extending direction of the second groove 112 is perpendicular to an extending direction of the fin 104.
The second recess 112 provides for the subsequent removal of a portion of the fin 104 in the gate opening 105 to form an opening.
In this embodiment, a part of the second groove 112 is communicated with the first groove 109. In other embodiments, the second groove may not be communicated with the first groove according to process requirements.
The mask layer 110 formed in the embodiment of the present invention has the first recess 109 and the second recess 112 at the same time, that is, the first recess 109 and the second recess 112 are formed by using an All In One (AIO) etching process, which saves the cost of a mask (mask), is favorable for reducing the process flow of the semiconductor forming method, and increases the yield, compared with the case of sequentially forming the mask layer 110 having the first recess 109 and the mask layer 110 having the second recess 112. In addition, in the embodiment of the present invention, after the mask layer 110 is formed and before the first blocking layer is formed, the fin portion 104 exposed by the second groove 112 is removed, a second opening is formed, and in the step of forming the first blocking layer in the first groove 109, a second blocking layer is further formed in the second groove 112 and the opening, that is, the first blocking layer and the second blocking layer are formed simultaneously.
In the subsequent steps of forming the first blocking layer and the second blocking layer, the top of the mask layer 110 is used as a removal stop position, and the position of the top of the mask layer 110 determines the positions of the tops of the subsequent first blocking layer and the second blocking layer.
Specifically, the mask layer 110 covers the interlayer dielectric layer 108, that is, the height of the mask layer 110 is higher than that of the interlayer dielectric layer 108. The height of the mask layer 110 is higher than that of the interlayer dielectric layer 108, so that the heights of the first blocking layer formed in the first groove and the second blocking layer formed in the second groove are higher than that of the interlayer dielectric layer.
And subsequently, removing the mask layer 110 to form a third groove 111 surrounded by the interlayer dielectric layer 108, the first barrier layer, the second barrier layer and the cap layer. And subsequently, forming a first initial gate structure in the third groove 111 of the first region I, forming a second initial gate structure in the third groove 111 of the second region II, and performing planarization treatment on the first initial gate structure and the second initial gate structure by taking the top of the interlayer dielectric layer 108 as a planarization stop position to respectively form a first gate structure and a second gate structure. That is, the height of the mask layer 110 is higher than that of the interlayer dielectric layer 108, so as to prepare for the subsequent formation of the first initial gate structure and the second initial gate structure with higher heights, and thus prepare for the planarization treatment of the first initial gate structure and the second initial gate structure to respectively form the first gate structure and the second gate structure with higher flatness.
With continued reference to fig. 22 and 23, the method of forming a semiconductor structure further includes: after the mask layer 110 is formed, the cap layer 107 exposed by the first groove 109 and the second groove 112 is removed.
And removing the cap layer 107 exposed from the first groove 109 and the second groove 112, so as to prepare for subsequently removing the gate dielectric layer 106 exposed from the first groove 109 and the second groove 112.
In this embodiment, the cap layer 107 exposed by the first groove 109 and the second groove 112 is removed by using an isotropic dry etching process. The isotropic dry etching process has isotropic etching characteristics, and can remove the capping layer 107 exposed from the mask layer 110 and located on the top and the side wall of the fin 104 and the surface of the isolation layer 101, so that residues are not easy to exist.
It should be noted that in the step of removing the cap layer 107 exposed in the first groove 109 and the second groove 110, the etched rate of the cap layer 107 is greater than the etched rate of the gate dielectric layer 106, so that the top of the gate dielectric layer 106 can be used as a removal stop position, and thus the process controllability of the removal process of the cap layer 107 is relatively high, the gate dielectric layer 106 is not easily damaged, and when the semiconductor structure works, the gate dielectric layer 106 can better electrically isolate the fin portion 104 from the first gate structure and the second gate structure which are formed subsequently.
Referring to fig. 24 and 25, fig. 25 is a cross-sectional view at AA of fig. 24. The method for forming the semiconductor structure further comprises the following steps: after removing the cap layer 107 exposed by the first groove 109 and the second groove 112, and before forming the first blocking layer in the first groove 109, removing the gate dielectric layer 106 in the gate opening 105 exposed by the first groove 109 and the second groove 112 by using the mask layer 110 as a mask.
And removing the gate dielectric layer 106 exposed in the second groove 112 to expose the fin portion 104, so as to prepare for subsequently removing the fin portion 104 exposed in the second groove 112 and forming an opening.
And removing the gate dielectric layer 106 exposed by the first groove 109. Correspondingly, in this embodiment, the mask layer 110 is directly used as a mask to remove the gate dielectric layer 106 exposed by the second groove 112 and the first groove 109, and no additional film layer is formed, so that a mask (mask) can be omitted, and the process cost for removing the gate dielectric layer 106 is reduced.
In this embodiment, the gate dielectric layer 106 is removed by an isotropic etching process. Specifically, the isotropic etching process includes an isotropic dry etching process or a isotropic wet etching process.
With continued reference to fig. 24 and 25, the method of forming a semiconductor structure further includes: after the mask layer 110 is formed and before the first blocking layer is formed, the fin portion 104 exposed by the second groove 112 is removed by using the mask layer 110 as a mask, and an opening 115 is formed.
The opening 115 provides process space for subsequent formation of a second blocking layer.
Specifically, the opening 115 is surrounded by the isolation layer 101, the substrate 100, and the fin 104.
In this embodiment, the fin portion 104 exposed by the second groove 112 is removed by using the mask layer 110 as a mask through a dry etching process, so as to form an opening 115. The dry etching process has anisotropic etching characteristics, has good etching profile controllability, can obtain quite accurate pattern conversion, is beneficial to enabling the appearance of the opening 115 to meet the process requirements, and is also beneficial to improving the removal efficiency of the fin part 104 exposed out of the second groove 112.
In the step of removing the fin portion 104 exposed by the second groove 112 by using the mask layer 110 as a mask to form the opening 115, the etched rate of the fin portion 104 is greater than that of the isolation layer 101, so that the isolation layer 101 is less damaged, a formation region of the opening 105 is favorably defined, and the process controllability of the semiconductor structure is stronger; in the step of forming the opening 115, the etched rate of the fin portion 104 is greater than the etched rate of the gate dielectric layer 106, so that the sidewall of the gate dielectric layer 106 covered by the mask layer 110 is not easily damaged, and further, the space at the bottom of the first groove 109 and the second groove 112 is not expanded, which is beneficial to controlling the formation area of the first barrier layer and the second barrier layer, and thus the process controllability of the semiconductor structure is strong.
In this embodiment, the material of the fin 104 includes silicon, and the material of the isolation layer 101 includes silicon oxide. Accordingly, the gases used in the dry etching process include fluorine-based gases, such as: CF4、CHF3Or C2F6And the like.
It should be noted that the space formed by the opening 115 and the second groove 112 located above the opening corresponds to a Single Diffusion Break opening formed by a Single Diffusion Break process (SDB).
It should be noted that in the step of removing the fin 104 exposed by the second groove 112 by using the mask layer 110 as a mask, the isolation layer 101 exposed by the first groove 109 may also be damaged.
In this embodiment, after the opening 115 is formed, the photoresist layer 114 on the mask layer 110 is removed. Timely removal of the photoresist layer 114 is beneficial to prevent the photoresist layer 114 from contaminating the machine.
In this embodiment, the photoresist layer 114 is removed by an ashing process or a wet stripping process.
Referring to fig. 26 to 28, fig. 26 is a schematic view based on the cross section of fig. 25, and fig. 28 is a cross-sectional view at AA of fig. 27, wherein a first blocking layer 116 is formed in the first groove 109.
In this embodiment, the first blocking layer 116 is used to define the formation position of the first gate structure to be formed subsequently. In other cases, the first blocking layer is used to block the first gate structure and the second gate structure that are subsequently formed on both sides of the first blocking layer.
In the step of forming the first blocking layer 116 in the first groove 109, a second blocking layer 117 is also formed in the second groove 112 and the opening 115.
The second blocking layer 117 extends in a direction perpendicular to the fin portion 104, and the second blocking layer 117 is used to electrically isolate the fin portion 104 located at two sides thereof.
In the steps of forming the first blocking layer 116 in the first groove 109 and forming the second blocking layer 117 in the second groove 112 and the opening 115, both the first blocking layer 116 and the second blocking layer 117 penetrate through the gate dielectric layer 106.
Specifically, the forming steps of the first blocking layer 116 and the second blocking layer 117 include:
as shown in fig. 26, the dielectric material layer 118 is formed to cover the first recess 109, the second recess 112 and the opening 115, and the top of the dielectric material layer 118 is higher than the top of the mask layer 110.
The dielectric material layer 118 above the mask layer 110 is subsequently removed to form a first blocking layer and a second blocking layer.
In this embodiment, the dielectric material layer 118 is formed by a Flowable Chemical Vapor Deposition (FCVD) process. The flowable chemical vapor deposition process has good filling capability, is suitable for filling a space with a high aspect ratio, and is beneficial to reducing the probability of defects such as voids formed in the dielectric material layer 118, and correspondingly beneficial to improving the film forming quality of the first blocking layer 116 and the second blocking layer 117.
Specifically, the material of the dielectric material layer 118 includes: one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide nitride, boron nitride boron silicon and boron nitride silicon carbide. In this embodiment, the material of the dielectric material layer 118 includes silicon oxide.
As shown in fig. 27 and 28, the dielectric material layer 118 above the mask layer 110 is removed, the dielectric material layer 118 in the first groove 109 is remained to serve as a first blocking layer 116, and the dielectric material layer 118 in the second groove 112 and the opening 115 is remained to serve as a second blocking layer 117.
In this embodiment, a Chemical Mechanical Planarization (CMP) process is used to remove the dielectric material layer 118 above the mask layer 110. Chemical mechanical polishing is a global surface planarization technique that is advantageous for conforming the top surfaces of the first blocking layer 116 and the second blocking layer 117 to the top surface of the mask layer 110.
In the step of forming the first blocking layer 116 in the first groove 109, the first blocking layer 116 is also formed in the gate opening 105 outside the first region I and the second region II.
Referring to fig. 29 and 30, fig. 30 is a cross-sectional view at AA of fig. 29, the method of forming a semiconductor structure further comprising: after the first blocking layer 116 and the second blocking layer 117 are formed, the mask layer 110 is removed.
Removing the mask layer 110 provides for the subsequent formation of a first gate structure in the first region I and a second gate structure in the second region II.
In this embodiment, the mask layer 110 is removed, and a third groove 111 surrounded by the interlayer dielectric layer 108, the first barrier layer 116, the second barrier layer 117, and the capping layer 107 is formed.
The top of the mask layer 110 is higher than the top of the interlayer dielectric layer 108, and the corresponding third groove 111 exposes the top of the interlayer dielectric layer 108.
And subsequently, forming a first initial gate structure in the third groove 111 of the first region I, forming a second initial gate structure in the third groove 111 of the second region II, and performing planarization treatment on the first initial gate structure and the second initial gate structure by taking the top of the interlayer dielectric layer 108 as a planarization stop position to respectively form a first gate structure and a second gate structure. That is to say, the height of the mask layer 110 is higher than that of the interlayer dielectric layer 108 to prepare for forming the first initial gate structure and the second initial gate structure with higher heights in the following steps, so as to prepare for forming the first gate structure and the second gate structure respectively by performing planarization treatment on the first initial gate structure and the second initial gate structure, which is beneficial to improving the flatness of the tops of the first gate structure and the second gate structure.
In this embodiment, the material of the mask layer 110 includes a BARC material. The mask layer 110 is removed by an ashing process.
Referring to fig. 31 and 32, the method of forming the semiconductor structure further includes: after removing the mask layer 110, a first gate structure 119 is formed in the gate opening 105 of the first region I, and a second gate structure 120 is formed in the gate opening 105 of the second region II.
When the semiconductor structure is in operation, the first gate structure 119 is used for controlling the channel of the first region I to be turned on and off, and the second gate structure 120 is used for controlling the channel of the second region II to be turned on and off.
Forming a first gate structure in the first region I, and forming a second gate structure in the second region II, including: forming a first work function material layer in the gate opening 105 of the first and second regions I and II; forming a first shielding layer covering the first area I and exposing the second area II; removing the first work function material layer exposed from the first shielding layer in the second area II, and taking the remaining first work function material layer as a first work function layer; after the first work function layer is formed, removing the first shielding layer; forming a second work function layer covering the first region I and the second region II; after the second work function layer is formed, forming a gate layer on the second work function layer, wherein the first work function layer, the second work function layer and the gate layer located in the first region I are used as a first initial gate structure, and the second work function layer and the gate layer located in the second region II are used as a second initial gate structure; and with the top of the interlayer dielectric layer 108 as a planarization stop position, performing planarization treatment on the first initial gate structure and the second initial gate structure to form the first gate structure 119 and the second gate structure 120 respectively.
In this embodiment, the first region I is used to form an NMOS, and correspondingly, the material of the first work function layer includes: one or more of titanium aluminide, tantalum carbide, aluminum, and titanium carbide.
In this embodiment, the first work function layer is formed by an atomic layer deposition process.
In this embodiment, the second region II is used to form a PMOS, and correspondingly, the material of the second work function layer includes: one or more of titanium nitride, tantalum nitride, titanium carbide, tantalum silicon nitride, titanium silicon nitride, and tantalum carbide.
In this embodiment, the second work function layer is formed by an atomic layer deposition process.
In this embodiment, the material of the gate layer includes: one or more of magnesium tungsten alloy, tungsten, copper, nickel and titanium.
And the top of the interlayer dielectric layer is taken as a planarization stop position to planarize the first initial gate structure and the second initial gate structure, so that the improvement of the flatness of the tops of the first gate structure 119 and the second gate structure 120 is facilitated, the heights of the first gate structure 119 and the second gate structure 120 are controlled, and the process controllability of the semiconductor structure is improved.
In this embodiment, the planarization process is performed by Chemical Mechanical Planarization (CMP).
It should be further noted that after the first blocking layer 116 and the second blocking layer 117 are formed, after the first initial gate structure is formed in the third groove 111 of the first region I, the second initial gate structure is formed in the third groove 111 of the second region II, the first initial gate structure and the second initial gate structure higher than the interlayer dielectric layer 108 are removed, the remaining first initial gate structure is used as the first gate structure 119, and the remaining second initial gate structure is used as the second gate structure 120. Compared with the case that the first blocking layer is formed first, then the first gate structure and the second gate structure are formed, the first gate structure, the second gate structure and the fin portion are etched to form a single diffusion interruption opening for forming the second blocking layer, and the second blocking layer is formed in the single diffusion interruption opening, in this embodiment, etching operations on the gate layer, the first work function layer and the second work function layer are avoided, the gate layer, the first work function layer and the second work function layer which are remained do not exist at the bottom of the second blocking layer, and the forming processes of the first gate structure 119 and the second gate structure 120 are relatively high in controllability, so that the first gate structure 119 and the second gate structure 120 can better control the threshold voltage of the semiconductor structure, and the electrical reliability of the semiconductor structure is improved.
Although the embodiments of the present invention are disclosed above, the embodiments of the present invention are not limited thereto. Various changes and modifications may be effected therein by one of ordinary skill in the pertinent art without departing from the scope or spirit of the present embodiments, and it is intended that the scope of the present embodiments be defined by the appended claims.

Claims (19)

1. A method of forming a semiconductor structure, comprising:
providing a substrate, wherein the substrate comprises a first area and a second area which are adjacent to each other, and the substrate comprises a substrate, a fin part which is separated from the substrate, an isolation layer which is positioned on the fin part and exposed out of the substrate, a dummy gate structure which is positioned on the isolation layer and stretches across the fin part, and an interlayer dielectric layer which covers the side wall of the dummy gate structure and exposes out of the top of the dummy gate structure;
removing the pseudo gate structure, and forming a gate opening in the interlayer dielectric layer;
forming a gate dielectric layer which conformally covers the gate opening;
forming an annealing sacrificial layer covering the gate dielectric layer in the gate opening;
removing the annealing sacrificial layer;
after removing the annealing sacrificial layer, forming a mask layer with a first groove in the gate opening and on the interlayer dielectric layer, wherein the extending direction of the first groove is the same as that of the fin part, and the first groove exposes part of the gate opening at the junction of the first area and the second area;
a first blocking layer is formed in the first recess.
2. The method of claim 1, wherein in the step of forming the mask layer, the mask layer further has a second recess exposing a portion of the gate opening, and an extending direction of the second recess is perpendicular to an extending direction of the fin;
the method for forming the semiconductor structure further comprises the following steps: after the mask layer is formed and before the first blocking layer is formed, removing the fin part exposed out of the second groove by taking the mask layer as a mask to form an opening;
in the step of forming the first blocking layer in the first groove, a second blocking layer is also formed in the second groove and the opening.
3. The method of forming a semiconductor structure of claim 2, further comprising: after the mask layer is formed and before the opening is formed, removing the gate dielectric layer in the gate opening exposed by the first groove and the second groove by taking the mask layer as a mask;
and forming a first blocking layer in the first groove, and in the step of forming a second blocking layer in the second groove and the opening, the first blocking layer and the second blocking layer penetrate through the gate dielectric layer.
4. The method of forming a semiconductor structure of claim 3, further comprising: after forming a gate dielectric layer which conformally covers the gate opening and before forming the annealing sacrificial layer, forming a cap layer which conformally covers the gate opening;
in the step of removing the annealing sacrificial layer, the etched rate of the cap layer is smaller than that of the annealing sacrificial layer;
the method for forming the semiconductor structure further comprises the following steps: and after the mask layer is formed, removing the cap layer exposed by the first groove and the second groove before removing the gate dielectric layer in the gate opening exposed by the first groove and the second groove.
5. The method for forming the semiconductor structure according to claim 4, wherein in the step of removing the cap layer exposed by the first groove and the second groove, the etching rate of the cap layer is greater than that of the gate dielectric layer.
6. The method for forming the semiconductor structure according to claim 4, wherein the cap layer exposed by the first groove and the second groove is removed by an isotropic dry etching process.
7. The method for forming the semiconductor structure according to claim 2, wherein the fin portion exposed by the second groove is removed by a dry etching process with the mask layer as a mask to form the opening.
8. The method of forming a semiconductor structure of claim 2, wherein the step of forming the first blocking layer and the second blocking layer comprises:
forming a dielectric material layer covering the first groove, the second groove and the opening, wherein the top of the dielectric material layer is higher than the top of the mask layer;
and removing the dielectric material layer higher than the mask layer, wherein the residual dielectric material layer positioned in the first groove is used as a first blocking layer, and the residual dielectric material layer positioned in the second groove and the opening is used as a second blocking layer.
9. The method of claim 8, wherein the dielectric material layer is formed using a flowable chemical vapor deposition process.
10. The method of forming a semiconductor structure of claim 8, wherein a material of the dielectric layer comprises: one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, boron nitride boron silicon nitride, and boron nitride silicon carbide.
11. The method of claim 8, wherein the dielectric material layer above the mask layer is removed using a chemical mechanical planarization process.
12. The method of forming a semiconductor structure of claim 1, further comprising:
and removing the mask layer after the first blocking layer and the second blocking layer are formed.
13. The method of forming a semiconductor structure of claim 12, wherein the mask layer is removed using an ashing process.
14. The method of forming a semiconductor structure of claim 12, further comprising: and after removing the mask layer, forming a first gate structure in the gate opening of the first region, and forming a second gate structure in the gate opening of the second region.
15. The method of forming a semiconductor structure of claim 14, wherein forming a first gate structure in the gate opening of the first region and forming a second gate structure in the gate opening of the second region comprises:
forming a first work function material layer in the gate openings of the first and second regions;
forming a first shielding layer covering the first area and exposing the second area;
removing the first work function material layer in the second region exposed by the first shielding layer, and taking the remaining first work function material layer in the first region as a first work function layer;
after the first work function layer is formed, removing the first shielding layer;
after removing the first shielding layer, forming a second work function layer covering the first region and the second region;
after the second work function layer is formed, forming a gate layer on the second work function layer, wherein the first work function layer, the second work function layer and the gate layer in the first region are used as a first initial gate structure, and the second work function layer and the gate layer in the second region are used as a second initial gate structure;
and carrying out planarization treatment on the first initial gate structure and the second initial gate structure by taking the top of the interlayer dielectric layer as a planarization stop position to respectively form the first gate structure and the second gate structure.
16. The method of forming a semiconductor structure of claim 1, wherein the step of forming the mask layer comprises:
forming a layer of said masking material overlying said first and second regions;
forming a photoresist layer on the mask material layer;
and etching the mask material layer by taking the photoresist layer as a mask, wherein the rest mask material layer is taken as the mask layer.
17. The method of forming a semiconductor structure according to claim 1, wherein the material of the mask layer comprises: one or more of an ODL material, an SOC material, a BARC material, and a DARC material.
18. The method of forming a semiconductor structure of claim 1, wherein in the step of providing a substrate, the dummy gate structure is formed using a self-aligned double patterning process or a self-aligned quadruple patterning process.
19. The method of forming a semiconductor structure of claim 1, wherein forming an annealed sacrificial layer in the gate opening comprises:
forming a sacrificial material layer covering the gate dielectric layer in the gate opening;
and carrying out annealing treatment on the sacrificial material layer to form the annealing sacrificial layer.
CN202110032936.2A 2021-01-11 2021-01-11 Method for forming semiconductor structure Pending CN114765131A (en)

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