CN112151595B - Semiconductor structure and forming method thereof - Google Patents

Semiconductor structure and forming method thereof Download PDF

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Publication number
CN112151595B
CN112151595B CN201910579439.7A CN201910579439A CN112151595B CN 112151595 B CN112151595 B CN 112151595B CN 201910579439 A CN201910579439 A CN 201910579439A CN 112151595 B CN112151595 B CN 112151595B
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semiconductor
layer
forming
column
initial
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CN112151595A (en
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周飞
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H01L29/0688—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions characterised by the particular shape of a junction between semiconductor regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

A semiconductor structure and a method for forming the same, the method for forming the same includes: forming a substrate, wherein the substrate comprises a substrate, a source doping layer positioned on the substrate and a semiconductor column protruding out of the source doping layer, the semiconductor column is of a T-shaped structure, the semiconductor column comprises a first semiconductor column and a second semiconductor column positioned on the first semiconductor column, and the width of the second semiconductor column is larger than that of the first semiconductor column; forming a gate structure surrounding a portion of a sidewall of the first semiconductor pillar, the gate structure exposing the second semiconductor pillar; and forming a leakage doping layer on the top of the second semiconductor column. The embodiment of the invention is beneficial to improving the performance of the semiconductor structure.

Description

Semiconductor structure and forming method thereof
Technical Field
Embodiments of the present disclosure relate to semiconductor manufacturing, and more particularly, to a semiconductor structure and a method for forming the same.
Background
With the rapid development of semiconductor manufacturing technology, semiconductor devices are being developed toward higher element density and higher integration, and the development trend of semiconductor process nodes following moore's law is continuously decreasing. Transistors are currently being widely used as the most basic semiconductor devices, and therefore, as the element density and integration level of the semiconductor devices are improved, the channel length of the transistors has to be continuously shortened in order to accommodate the reduction of process nodes.
The reduction of the transistor channel length has the benefits of increasing the die density of the chip, increasing the switching speed, and the like. However, as the channel length is shortened, the distance between the source and the drain of the transistor is shortened, and the control capability of the gate to the channel is reduced, so that subthreshold leakage (subthreshold leakage) phenomenon, that is, so-called short-channel effects (SCE) is more likely to occur, and the channel leakage of the transistor is increased.
Accordingly, to better accommodate the demand for device scaling, semiconductor processes are increasingly beginning to transition from planar transistors to three-dimensional transistors with higher power, such as Gate-all-around (GAA) transistors. In the fully-enclosed gate transistor, the gate encloses the region where the channel is located from the periphery, and compared with a planar transistor, the gate of the fully-enclosed gate transistor has stronger control capability on the channel and can better inhibit the short channel effect. The fully-surrounding Gate transistors include a Lateral Gate-all-around (LGAA) transistor and a Vertical Gate-all-around (VGAA) transistor, wherein the channel of VGAA extends in a direction perpendicular to the surface of the substrate, which is beneficial to improving the area utilization efficiency of the semiconductor structure, and thus is beneficial to further realizing the reduction of the feature size.
Disclosure of Invention
The embodiment of the invention solves the problem of providing a semiconductor structure and a forming method thereof, and improves the performance of the semiconductor structure.
In order to solve the above problems, an embodiment of the present invention provides a method for forming a semiconductor structure, including: forming a substrate, wherein the substrate comprises a substrate, a source doping layer positioned on the substrate and a semiconductor column protruding out of the source doping layer, the semiconductor column is of a T-shaped structure, the semiconductor column comprises a first semiconductor column and a second semiconductor column positioned on the first semiconductor column, and the width of the second semiconductor column is larger than that of the first semiconductor column; forming a gate structure surrounding a portion of a sidewall of the first semiconductor pillar, the gate structure exposing the second semiconductor pillar; and forming a leakage doping layer on the top of the second semiconductor column.
Correspondingly, the embodiment of the invention also provides a semiconductor structure, which comprises: a substrate; a source doped layer located on the substrate; the semiconductor column protrudes out of the source doping layer, the semiconductor column is of a T-shaped structure, the semiconductor column comprises a first semiconductor column and a second semiconductor column positioned on the first semiconductor column, and the width of the second semiconductor column is larger than that of the first semiconductor column; a gate structure surrounding a portion of a sidewall of the first semiconductor pillar, the gate structure exposing the second semiconductor pillar; and the leakage doping layer is positioned at the top of the second semiconductor column.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following advantages:
the semiconductor column formed by the embodiment of the invention is of a T-shaped structure, the semiconductor column comprises a first semiconductor column and a second semiconductor column positioned on the first semiconductor column, and the width of the second semiconductor column is larger than that of the first semiconductor column, so that the width of the second semiconductor column is larger along the direction perpendicular to the side wall of the semiconductor column, the area of the drain doping layer is correspondingly increased after the drain doping layer is formed at the top of the second semiconductor column, and the contact performance of the contact hole plug and the source drain doping layer can be improved in the process of forming the contact hole plug electrically connected with the drain doping layer, and in addition, the embodiment of the invention can reduce the contact resistance of the contact hole plug and the drain doping layer by increasing the contact area of the contact hole plug and the drain doping layer; in summary, the embodiment of the invention improves the performance of the semiconductor structure by forming the semiconductor column with the T-shaped structure.
Drawings
FIG. 1 is a schematic diagram of a semiconductor structure;
fig. 2 to 14 are schematic structural views corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention.
Detailed Description
The devices formed at present still have the problem of poor performance. The reasons for poor device performance are now analyzed in conjunction with a schematic structural diagram of a semiconductor structure.
Referring to fig. 1, a schematic structural diagram of a semiconductor structure is shown.
The semiconductor structure includes: a substrate 1; a source doped layer 2 located on the substrate 1; a semiconductor pillar 3 protruding from the source doping layer 2; a drain doped layer 4 located on top of the semiconductor pillars 3; a gate structure 5 surrounding a portion of the sidewall of the semiconductor pillar 3 and exposing the drain doped layer 4.
In the semiconductor structure, the drain doped layer 4 is located on top of the semiconductor pillars 3. In the semiconductor field, the width dimension of the semiconductor pillar 3 is generally smaller, and since the dimension of the drain doped layer 4 is limited by the width dimension of the semiconductor pillar 3, the width dimension of the drain doped layer 4 is also generally smaller, and when a contact hole plug electrically connected with the drain doped layer 4 is formed subsequently, the process difficulty of forming the contact hole plug is greater, and the contact performance of the contact hole plug and the drain doped layer 4 is easily reduced, and meanwhile, the contact area of the contact hole plug and the drain doped layer 4 is also smaller, and the contact resistance of the contact hole plug and the drain doped layer 4 is also greater, thereby resulting in poor performance of the formed semiconductor structure.
In order to solve the technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, including: forming a substrate, wherein the substrate comprises a substrate, a source doping layer positioned on the substrate and a semiconductor column protruding out of the source doping layer, the semiconductor column is of a T-shaped structure, the semiconductor column comprises a first semiconductor column and a second semiconductor column positioned on the first semiconductor column, and the width of the second semiconductor column is larger than that of the first semiconductor column; forming a gate structure surrounding a portion of a sidewall of the first semiconductor pillar, the gate structure exposing the second semiconductor pillar; and forming a leakage doping layer on the top of the second semiconductor column.
The semiconductor column formed by the embodiment of the invention is of a T-shaped structure, the semiconductor column comprises a first semiconductor column and a second semiconductor column positioned on the first semiconductor column, and the width of the second semiconductor column is larger than that of the first semiconductor column, so that the width of the second semiconductor column is larger along the direction perpendicular to the side wall of the semiconductor column, the area of the drain doping layer is correspondingly increased after the drain doping layer is formed at the top of the second semiconductor column, and the contact performance of the contact hole plug and the source drain doping layer can be improved in the process of forming the contact hole plug electrically connected with the drain doping layer, and in addition, the embodiment of the invention can reduce the contact resistance of the contact hole plug and the drain doping layer by increasing the contact area of the contact hole plug and the drain doping layer; in summary, the embodiment of the invention improves the performance of the semiconductor structure by forming the semiconductor column with the T-shaped structure.
In order that the above objects, features and advantages of embodiments of the invention may be readily understood, a more particular description of the invention will be rendered by reference to specific embodiments thereof which are illustrated in the appended drawings.
Fig. 2 to 14 are schematic structural views corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention.
Referring to fig. 2 to 7, a base (not shown) is formed, the base including a substrate 100, a source doping layer 105 on the substrate 100, and a semiconductor pillar 110 protruding from the source doping layer 105 (as shown in fig. 7), the semiconductor pillar 110 having a T-shaped structure, the semiconductor pillar 110 including a first semiconductor pillar 10 (as shown in fig. 7) and a second semiconductor pillar 11 (as shown in fig. 7) on the first semiconductor pillar 10, the second semiconductor pillar 11 having a width larger than that of the first semiconductor pillar 10.
The substrate provides a process platform for subsequent process steps.
In this embodiment, the substrate 100 is a silicon substrate. In other embodiments, the material of the substrate may also be germanium, silicon carbide, gallium arsenide, or indium gallium, and the substrate may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate.
When forming the PMOS (Positive Channel Metal Oxide Semiconductor) transistor, the material of the source doped layer 105 is P-type ion doped silicon germanium. By doping P-type ions in silicon germanium, the more P-type ions are doped, the higher the concentration of the polytope is, and the stronger the conductivity is. Specifically, the P-type ions include B, ga or In.
When forming the NMOS (Negative channel Metal Oxide Semiconductor) transistor, the material of the source doped layer 105 is silicon carbide or silicon phosphide doped with N-type ions, respectively. By doping N-type ions in silicon carbide or silicon phosphide, the N-type ions replace the positions of silicon atoms in a crystal lattice, the more N-type ions are doped, the higher the concentration of the polyions is, and the higher the conductivity is. Specifically, the N-type ions include P, as or Sb.
In this embodiment, a first epitaxial layer (not labeled) is formed by an epitaxial growth method, and ions are doped in situ during the process of forming the first epitaxial layer, so as to form the source doped layer 105. In other embodiments, after in-situ self-doping in the process of forming the first epitaxial layer, ion doping may be performed on the first epitaxial layer continuously by means of ion implantation to form a source doped layer. The doped ions can achieve the effect of improving the carrier mobility of the transistor. In other embodiments, the first epitaxial layer may be doped with ions only by ion implantation.
In this embodiment, the semiconductor pillar 110 is formed in a T-shaped structure, and the semiconductor pillar 110 includes a first semiconductor pillar 10 and a second semiconductor pillar 11 located on the first semiconductor pillar 10, where the width of the second semiconductor pillar 11 is greater than the width of the first semiconductor pillar 10.
The semiconductor pillars 110 are used to provide a process platform for forming gate structures and drain doped layers. The first semiconductor column 10 is used for providing a channel region when the MOS device works subsequently, and the second semiconductor column 11 is used for providing a process basis for forming a drain doped layer subsequently.
In this embodiment, the material of the semiconductor pillar 110 is silicon. In other embodiments, the material of the semiconductor pillars may be germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, as desired.
When forming the PMOS transistor, the semiconductor pillar 110 is doped with N-type ions, wherein the N-type ions may be P ions, as ions or Sb ions; when forming an NMOS transistor, the semiconductor pillar 110 is doped with P-type ions, which may be B ions, ga ions, or In ions.
Along the direction perpendicular to the sidewall of the semiconductor pillar 110, the width of the second semiconductor pillar 11 is larger, the area of the leaky-doped layer is correspondingly increased after the leaky-doped layer is formed at the top of the second semiconductor pillar 11, and in the process of forming a contact hole plug electrically connected with the leaky-doped layer, the contact performance of the contact hole plug and the leaky-doped layer is improved, and in addition, the contact resistance of the contact hole plug and the leaky-doped layer can be reduced by increasing the contact area of the contact hole plug and the leaky-doped layer; in summary, the performance of the semiconductor structure is improved by forming the semiconductor pillars with the T-shaped structures.
The proportion of the height of the second semiconductor pillars 11 to the total height of the semiconductor pillars 110 should not be too small or too large. If the proportion of the height of the second semiconductor pillar 11 to the total height of the semiconductor pillar 110 is too small, the volume of the subsequently formed drain doped layer on top of the second semiconductor pillar 11 is correspondingly too small, which is easy to affect the carrier mobility of the device; if the proportion of the height of the second semiconductor pillar 11 to the total height of the semiconductor pillar 110 is too large, the height of the first semiconductor pillar 10 is correspondingly too small without changing the total height of the semiconductor pillar 110, which easily results in too little material for providing a channel region in the first semiconductor pillar 10, which easily affects the effective channel length of the device. For this purpose, in the present embodiment, the height of the second semiconductor pillars 11 is one fifth to one third of the total height of the semiconductor pillars 110.
Specifically, in this embodiment, the height of the second semiconductor pillar 11 is 3 nm to 8 nm, so that the contact performance of the subsequent drain doped layer and the contact hole plug can be significantly improved, and the performance of the semiconductor structure can be improved.
The width of the second semiconductor pillar 11 is not too small nor too large in the direction perpendicular to the sidewalls of the semiconductor pillar 110. If the width of the second semiconductor pillar 11 is too small, after the drain doped layer is formed on the top of the second semiconductor pillar 11, the width of the drain doped layer is too small, so that it is difficult to improve the contact performance between the drain doped layer and the subsequent contact plug; if the width of the second semiconductor pillars 11 is too large, the distance between the adjacent second semiconductor pillars 11 is too short, and even a short circuit occurs between the adjacent second semiconductor pillars 11, and thus a leakage current or the like is liable to occur. For this reason, in the present embodiment, the width of the second semiconductor pillar 11 is 1.5 to 3 times the width of the first semiconductor pillar 10.
Specifically, in this embodiment, the width of the second semiconductor pillar 11 is 8 nm to 20 nm, so that the effect of the second semiconductor pillar 11 for improving the contact performance of the subsequent drain doped layer and the contact plug is more remarkable, and the reliability of the semiconductor structure is improved.
In this embodiment, the step of forming the semiconductor pillar 110 includes:
referring to fig. 2 to 6, a protective layer 102 (shown in fig. 6) is formed on the source doping layer 105, a groove 300 (shown in fig. 6) is formed in the protective layer 102, the cross section of the groove 300 is T-shaped, the groove 300 includes a bottom groove 210 (shown in fig. 6) and a top groove 220 (shown in fig. 6) located on the bottom groove 210, the opening width of the top groove 220 is larger than the opening width of the bottom groove 210, and the top of the bottom groove 210 is communicated with the bottom of the top groove 220.
The protective layer 102 is used to provide a process platform for forming the recess 300.
To reduce the impact of the protective layer 102 on the semiconductor structure, the material of the protective layer 102 is silicon oxide, silicon nitride, silicon oxynitride, boron nitride, or silicon oxycarbonitride. The materials are all insulating materials, and the influence on the performance of the semiconductor structure is small. In this embodiment, the material of the protection layer 102 is silicon oxide. Silicon oxide is an insulating material commonly used in semiconductor technology, and has high technology compatibility.
The recess 300 is used to provide a spatial location for the formation of semiconductor pillars, and the recess 300 is also used to define the formation region and shape of the semiconductor pillars.
Specifically, the step of forming the recess 300 includes:
as shown in fig. 2, an initial protective layer 101 is formed on the source doping layer 105; as shown in fig. 3, an initial recess 200 exposing the source doping layer 105 is formed in the initial protection layer 101.
The initial recess 200 is used to subsequently form the recess 300.
Specifically, a portion of the initial recess 200 on a side near the source doped layer 105 is used as a bottom recess. Thus, the width of the initial groove 200 is equal to the width of the bottom groove.
In this embodiment, the initial protection layer 101 is etched by a dry etching process, so as to form the initial recess 200. The dry etching process has the characteristic of anisotropic etching, and has good profile control, so that the profile of the groove 200 can meet the process requirement.
As shown in fig. 4, a filling layer 103 is formed in the initial recess 200, and the top of the filling layer 103 is lower than the top of the initial protection layer 101.
The top of the filling layer 103 is lower than the top of the initial protection layer 101, so as to provide a process basis for the subsequent etching of the sidewalls of the initial recess 200 where the filling layer 103 is exposed.
To reduce the difficulty in forming and removing the filling layer 103, the influence of the filling layer 103 on the semiconductor structure is reduced, and the filling layer 103 is made of a material easy to form and remove.
For this purpose, the material of the filling layer 103 is BARC (Bottom Anti-reflective coating ) material, ODL (organic Dielectric layer, organic Dielectric layer) material, SOC (spin-on carbon) material, photoresist, DARC (Dielectric Anti-reflective Coating ) material or DUO (deep UV light absorbing oxide, deep ultraviolet light absorbing oxide) material. In this embodiment, the material of the filling layer 103 is BARC material.
In this embodiment, the step of forming the filling layer 103 includes: forming a filling material layer (not shown) filled in the initial recess 200, the filling material layer also covering the top of the initial protection layer 101; the filling material layer is removed from the top of the initial protection layer 101 and from a partial thickness of the initial recess 200, and the remaining filling material layer serves as the filling layer 103.
As shown in fig. 5, the sidewalls of the initial recess 200 exposed by the filling layer 103 are etched in a direction perpendicular to the sidewalls of the initial recess 200, so as to form the top recess 220, and the initial protection layer 101 remains as the protection layer 102.
In this embodiment, an isotropic etching process is used to etch the sidewalls of the initial recess 200 exposed by the filling layer 103. By using an isotropic etching process, the sidewalls of the initial recess 200 exposed by the filling layer 103 can be etched in a direction perpendicular to the sidewalls of the initial recess 200, so that the opening width of the top recess 220 is greater than the opening width of the initial recess 200.
In the isotropic etching process, the initial protection layer 101 is also etched in a direction normal to the surface of the substrate 100. The thickness of the initial protection layer 101 is greater along the normal direction of the surface of the substrate 100, and thus, after the isotropic etching process is performed, the top of the filling layer 103 is still lower than the top of the initial protection layer 101, so that the top recess 220 can be formed.
In this embodiment, the SiCoNi process may be used to etch the sidewalls of the initial recess 220 exposed by the filling layer 103.
The sicomini process is used as a low-strength high-precision chemical etching method, and generally comprises the following steps: firstly, generating etching gas; etching the material layer to be etched through the etching gas to form byproducts; performing an annealing process to sublimate and decompose the byproducts into gaseous products; and removing the gaseous product by means of air suction. In this embodiment, the etching gas of the sicon process includes a fluorocarbon-based gas and a hydrogen-containing fluorocarbon-based gas.
The sicon process is advantageous for precisely controlling the etching amount of the sidewalls of the initial recess 220, thereby precisely controlling the width of the subsequent second semiconductor pillars.
In other embodiments, hydrofluoric acid solution may be used to etch the exposed sidewalls of the initial recess of the filling layer. The hydrofluoric acid solution is adopted to easily realize isotropic etching, and is a solution commonly used for etching silicon oxide materials in the semiconductor process, so that the process cost is low and the process compatibility is high.
As shown in fig. 6, the filling layer 103 (shown in fig. 5) is removed, and the remaining initial grooves 200, which are in communication with the top grooves 220, serve as the bottom grooves 210.
In this embodiment, the material of the filling layer 103 is BARC material, and an ashing process may be used to remove the filling layer 103.
Referring to fig. 7, the semiconductor pillars 110 are formed in the recess 300, wherein a portion of the semiconductor pillars 110 located in the bottom recess 210 serves as the first semiconductor pillars 10, a portion of the semiconductor pillars 110 located in the top recess 220 serves as the second semiconductor pillars 11, and a width of the second semiconductor pillars 11 is greater than a width of the first semiconductor pillars 10.
Specifically, the semiconductor pillars 110 are formed in the recesses 300 using an epitaxial process, thereby improving the formation quality of the semiconductor pillars 110.
Referring to fig. 8, a drain doped layer 125 is formed on top of the second semiconductor pillar 11 (shown in fig. 7).
Along the direction perpendicular to the sidewall of the semiconductor pillar 110, the width of the second semiconductor pillar 11 is larger, after the drain doped layer 125 is formed on the top of the second semiconductor pillar 11, the area of the drain doped layer 125 is correspondingly increased, so that in the process of subsequently forming a contact hole plug electrically connected with the drain doped layer 125, the requirement on the alignment deviation (overlay) of the contact hole plug forming process is reduced, the process difficulty of forming the contact hole plug is correspondingly reduced, the process window is increased, and the contact performance between the contact hole plug and the drain doped layer 125 is improved, and in addition, the contact resistance between the contact hole plug and the drain doped layer 125 can be reduced by increasing the contact area between the contact hole plug and the drain doped layer 125; in summary, by forming the second semiconductor pillars 11 with a larger width, the performance of the semiconductor structure is improved.
The drain doped layer 125 is the same as the source doped layer 105 in the type of dopant ions and in the material.
When forming a PMOS transistor, the material of the drain doped layer 125 is P-type ion doped silicon germanium. By doping P-type ions in silicon germanium, the more P-type ions are doped, the higher the concentration of the polytope is, and the stronger the conductivity is. Specifically, the P-type ions include B, ga or In.
When forming an NMOS transistor, the material of the drain doped layer 125 is silicon carbide or silicon phosphide doped with N-type ions, respectively. By doping N-type ions in silicon carbide or silicon phosphide, the N-type ions replace the positions of silicon atoms in a crystal lattice, the more N-type ions are doped, the higher the concentration of the polyions is, and the higher the conductivity is. Specifically, the N-type ions include P, as or Sb.
In this embodiment, the step of forming the drain doped layer 125 includes: the second semiconductor pillar 11 (as shown in fig. 7) exposed from the protective layer 102 is ion-doped, and a portion of the second semiconductor pillar 11 doped with ions serves as the drain doped layer 125.
In this embodiment, the second semiconductor column 11 exposed from the protection layer 102 is ion doped to form the drain doped layer 125, so that no additional mask layer forming step is required, which is beneficial to simplifying the process steps and improving the process integration; in addition, the drain doped layer 125 is formed before the gate structure is formed, so that in the subsequent step of forming the gate dielectric layer, the step of removing the gate dielectric layer surrounding the second semiconductor pillar 11 is not required, which is also beneficial to simplifying the process flow and reducing the process difficulty.
In other embodiments, an epitaxial layer may be formed on top of the second semiconductor pillar exposed by the protective layer by using an epitaxial process, and the drain doped layer is formed by in-situ self-doping ions during the process of forming the epitaxial layer.
The present embodiment takes the case that the drain doped layer 125 is formed before the gate structure is formed. In other embodiments, a drain doped layer may also be formed on top of the second semiconductor pillar after the gate structure is formed.
Referring to fig. 9 in combination, after forming the semiconductor pillar 110 (as shown in fig. 7), the method further includes: and etching back a part of the protective layer 102, and remaining the protective layer 102 as an isolation layer 106.
Specifically, after the drain doped layer 125 is formed on top of the second semiconductor pillar 11, the isolation layer 106 is formed.
A gate structure is subsequently formed on the isolation layer 106, and the isolation layer 106 is used to isolate the gate structure from the source doped layer 105.
The isolation layer 106 is formed by etching back the protection layer 102 with a partial thickness, which is beneficial to saving the process flow and has high process integration.
In this embodiment, a dry etching process is used to etch back a portion of the protective layer 102. The dry etching process has the characteristic of anisotropic etching, has good section control, is favorable for accurately controlling the etching amount of the protective layer 102, and improves the etching efficiency.
Referring to fig. 10 to 13, a gate structure 120 (as shown in fig. 13) is formed, the gate structure 120 surrounding a portion of the sidewall of the first semiconductor pillar 10, the gate structure 120 exposing the second semiconductor pillar 11.
The gate structure 120 is used for controlling the on/off of the conducting channel when the MOS device is operated.
In this embodiment, the gate structure 120 is a metal gate structure. As shown in fig. 13, the gate structure 120 includes a work function layer 111 surrounding a portion of the sidewall of the first semiconductor pillar 10 and a gate electrode layer 112 surrounding the work function layer 111.
When the MOS device is an NMOS transistor, the material of the work function layer 111 includes one or more of titanium aluminide, tantalum carbide, aluminum, or titanium carbide; when the MOS device formed is a PMOS transistor, the material of the work function layer 111 includes one or more of titanium nitride, tantalum nitride, titanium carbide, tantalum silicon nitride, titanium silicon nitride, and tantalum carbide.
In this embodiment, the material of the gate electrode layer 112 is magnesium-tungsten alloy. In other embodiments, the material of the gate electrode layer may also be W, al, cu, ag, au, pt, ni or Ti.
Thus, in the step of forming the gate structure 120, the gate structure 120 surrounds a portion of the sidewall of the first semiconductor pillar 10 exposed by the isolation layer 106.
Accordingly, in this embodiment, the step of forming the gate structure 120 includes:
as shown in fig. 10, an initial work function layer 108 conformally covering the semiconductor pillar 110 exposed by the isolation layer 106, and an initial gate electrode layer 109 conformally covering the initial work function layer 108 are formed, wherein the initial work function layer 108 and the initial gate electrode layer 109 also extend onto a portion of the source doped layer 105 on one side of the semiconductor pillar 110. Specifically, the initial work function layer 108 and the initial gate electrode layer 109 extend onto the isolation layer 106 above the source doped layer 105 on one side of the semiconductor pillar 110.
The initial work function layer 108 provides for the subsequent formation of a work function layer; the initial gate electrode layer 109 provides for the subsequent formation of a gate electrode layer.
In this embodiment, the initial work function layer 108 and the gate electrode layer 109 are formed by a deposition process and an etching process that are sequentially performed, so that a part of the source doping layer 105 is exposed from the initial work function layer 108 and the gate electrode layer 109.
Specifically, the deposition process is an atomic layer deposition process.
As shown in fig. 11 and 12, a first dielectric layer 115 (as shown in fig. 12) is formed on the source doped layer 105, the first dielectric layer 115 covers a portion of the sidewalls of the semiconductor pillars 110, and the top of the first dielectric layer 115 is lower than the bottom of the drain doped layer 125.
The first dielectric layer 115 is used to achieve electrical isolation between adjacent devices.
Thus, the material of the first dielectric layer 115 is a dielectric material. In this embodiment, the material of the first dielectric layer 115 is silicon oxide. In other embodiments, the material of the first dielectric layer may be another dielectric material such as silicon nitride, silicon oxynitride, or the like.
Specifically, the step of forming the first dielectric layer 115 includes: forming an initial dielectric layer 126 (as shown in fig. 11), wherein the initial dielectric layer 126 covers the initial gate electrode layer 109 and the isolation layer 106; and removing part of the thickness of the initial dielectric layer 126 to form a first dielectric layer 115 covering part of the side wall of the initial gate electrode layer 109.
In this embodiment, a dry etching process is used to remove a portion of the thickness of the initial dielectric layer 126. The dry etching process has the characteristic of anisotropic etching, and the top surface position of the first dielectric layer 115 is easy to control by selecting the dry etching process.
As shown in fig. 13, the initial gate electrode layer 109 (as shown in fig. 12) and the initial work function layer 108 (as shown in fig. 12) exposed by the first dielectric layer 115 are removed, the initial gate electrode layer 109 is remained as a gate electrode layer 112, the initial work function layer 108 is remained as a work function layer 111, and the gate electrode layer 112 and the work function layer 111 are used to form a gate structure 120.
In this embodiment, the initial work function layer 108 and the initial gate electrode layer 109 are etched by a dry etching process. The dry etching process is beneficial to precisely controlling the etching amount of the first dielectric layer 115 and reducing the damage to other film layers.
Referring to fig. 10 in combination, the method for forming the semiconductor structure further includes: after forming the isolation layer 106, before forming the initial work function layer 108 and the initial gate electrode layer 109, further includes: a gate dielectric layer 107 conformally covering the exposed semiconductor pillars 110 of the isolation layer 106 is formed.
The gate dielectric layer 107 is used to electrically isolate the gate structure 120 from the semiconductor pillar 110.
The gate structure 120 formed later is a metal gate structure, so the material of the gate dielectric layer 107 is a high-k dielectric material; the high-k dielectric material refers to a dielectric material with a relative dielectric constant larger than that of silicon oxide. Specifically, the gate dielectric layer 107 is made of HfO 2 . In other embodiments, the gate dielectric layer material may also be selected from ZrO 2 、HfSiO、HfSiON、HfTaO, hfTiO, hfZrO or Al 2 O 3 Etc.
In other embodiments, the gate dielectric layer may further include a gate oxide layer, and a high-k dielectric layer disposed on the gate oxide layer, where a material of the gate oxide layer may be silicon oxide or silicon oxynitride, respectively.
In this embodiment, the gate dielectric layer 107 is formed by an atomic layer deposition process. In other embodiments, the gate dielectric layer may also be formed by a chemical vapor deposition process.
Thus, with continued reference to fig. 13, after the gate structure 120 is formed, the gate structure 120 exposes the gate dielectric layer 107 on the surface of the drain doped layer 125.
In this embodiment, by reserving the gate dielectric layer 107 on the surface of the drain doped layer 125, the gate dielectric layer 107 protects the drain doped layer 125, so as to better realize electrical isolation between the drain doped layer 125 and the gate structure 120.
After forming the gate structure 120, the subsequent process further includes:
referring to fig. 14, a second dielectric layer 127 is formed to cover the first dielectric layer 115 and the drain doped layer 125, and the second dielectric layer 127 and the first dielectric layer 115 form an interlayer dielectric layer (not labeled); a source contact plug 122 electrically connected to the source doped layer 105 is formed in the interlayer dielectric layer on one side of the gate structure 120, a drain contact plug 121 electrically connected to the drain doped layer 125 is formed in the second dielectric layer 127, a gate contact plug 123 is formed in the interlayer dielectric layer on the other side of the gate structure 120, and the gate contact plug 123 is electrically connected to the gate structure 120.
The area of the drain doped layer 125 is larger, which is beneficial to reducing the requirement of alignment deviation of the process of forming the drain contact hole plug 121 in the process of forming the drain contact hole plug 121, correspondingly reducing the process difficulty of forming the drain contact hole plug 121, increasing the process window, and simultaneously being beneficial to improving the contact performance of the drain contact hole plug 121 and the drain doped layer 125, and in addition, the embodiment can increase the contact area of the drain contact hole plug 122 and the drain doped layer 125 by increasing the area of the drain contact hole plug 121, thereby reducing the contact resistance of the drain contact hole plug 122 and the drain doped layer 125 and improving the performance of the semiconductor structure.
The second dielectric layer 127 is also used to isolate adjacent devices. The second dielectric layer 127 is further used to provide a process platform for forming the drain contact plug 121, the source contact plug 122, and the gate contact plug 123, and the second dielectric layer 127 is further used to realize isolation between adjacent contact plugs.
In this embodiment, the second dielectric layer 127 is made of the same material as the first dielectric layer 115. The material of the second dielectric layer 127 is silicon oxide.
In this embodiment, the drain contact plug 121 is made of tungsten.
In this embodiment, the materials of the source contact hole plug 122 and the gate contact hole plug 123 are the same as the materials of the drain contact hole plug 121, and will not be described here again.
Correspondingly, the invention further provides a semiconductor structure. Referring to fig. 14, a schematic structural diagram of an embodiment of a semiconductor structure of the present invention is shown.
The semiconductor structure includes: a substrate 100; a source doped layer 105 on the substrate 100; a semiconductor pillar 110 (as shown in fig. 7) protruding from the source doped layer 105, the semiconductor pillar 110 having a T-shaped structure, the semiconductor pillar 110 including a first semiconductor pillar 10 and a second semiconductor pillar 11 (as shown in fig. 7) located on the first semiconductor pillar 10, the second semiconductor pillar 11 having a width greater than that of the first semiconductor pillar 10; a gate structure 120, the gate structure 120 surrounding a portion of the sidewall of the first semiconductor pillar 10, the gate structure 120 exposing the second semiconductor pillar 11; and a drain doped layer 125 located on top of the second semiconductor pillar 11.
The width of the second semiconductor pillar 11 is greater than the width of the first semiconductor pillar 10, the width of the second semiconductor pillar 11 is greater along the direction perpendicular to the sidewall of the semiconductor pillar 110, the area of the drain doped layer 125 is also greater at the top of the second semiconductor pillar 11, and in the process of forming a contact hole plug electrically connected with the drain doped layer 125, the contact performance between the contact hole plug and the drain doped layer 125 is improved, and in this embodiment, the contact resistance between the contact hole plug and the drain doped layer 125 can be reduced by increasing the contact area between the contact hole plug and the drain doped layer 125; in summary, the performance of the semiconductor structure is improved by the semiconductor pillar 110 with the T-shaped structure.
The substrate 100 provides a process platform for the formation of semiconductor structures.
In this embodiment, the substrate 100 is a silicon substrate. In other embodiments, the material of the substrate may also be germanium, silicon carbide, gallium arsenide, or indium gallium, and the substrate may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate.
When forming a PMOS transistor, the source doped layer 105 is formed of silicon germanium doped with P-type ions. By doping P-type ions in silicon germanium, the more P-type ions are doped, the higher the concentration of the polytope is, and the stronger the conductivity is. Specifically, the P-type ions include B, ga or In.
When forming an NMOS transistor, the material of the source doped layer 105 is silicon carbide or silicon phosphide doped with N-type ions, respectively. By doping N-type ions in silicon carbide or silicon phosphide, the N-type ions replace the positions of silicon atoms in a crystal lattice, the more N-type ions are doped, the higher the concentration of the polyions is, and the higher the conductivity is. Specifically, the N-type ions include P, as or Sb.
The semiconductor pillars 110 provide a process platform for forming gate structures 120 and drain doped layers 125. The first semiconductor pillar 10 is used to provide a channel region when the MOS device is in operation, and the second semiconductor pillar 11 is used to provide a process basis for forming the drain doped layer 125.
In this embodiment, the material of the semiconductor pillar 110 is silicon. In other embodiments, the material of the semiconductor pillars may be germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, as desired.
When forming the PMOS transistor, the semiconductor pillar 110 is doped with N-type ions, wherein the N-type ions may be P ions, as ions or Sb ions; when forming an NMOS transistor, the semiconductor pillar 110 is doped with P-type ions, which may be B ions, ga ions, or In ions.
The proportion of the height of the second semiconductor pillars 11 to the total height of the semiconductor pillars 110 should not be too small or too large. If the proportion of the height of the second semiconductor pillar 11 to the total height of the semiconductor pillar 110 is too small, the volume of the drain doped layer 125 located on the top of the second semiconductor pillar 11 is correspondingly too small, so that the carrier mobility of the device is easily affected; if the proportion of the height of the second semiconductor pillar 11 to the total height of the semiconductor pillar 110 is too large, the proportion of the first semiconductor pillar 10 is too small, and the height of the first semiconductor pillar 10 is too small without changing the total height of the semiconductor pillar 110, which easily results in that the material of the first semiconductor pillar 10 used as a channel region is too small, which easily affects the effective channel length of the device. For this purpose, in the present embodiment, the height of the second semiconductor pillars 11 is one fifth to one third of the total height of the semiconductor pillars 110.
Specifically, in the present embodiment, the height of the second semiconductor pillar 11 is 3 nm to 8 nm.
The width of the second semiconductor pillar 11 is not too small nor too large in the direction perpendicular to the sidewalls of the semiconductor pillar 110. If the width of the second semiconductor pillar 11 is too small, the width of the drain doped layer 125 located at the top of the second semiconductor pillar 11 is too small, so that it is difficult to improve the contact performance between the drain doped layer 125 and the contact hole plug; if the width of the second semiconductor pillars 11 is too large, the distance between the adjacent second semiconductor pillars 11 is too short, and even a short circuit occurs between the adjacent second semiconductor pillars 11, and thus a leakage current or the like is liable to occur. For this reason, in the present embodiment, the width of the second semiconductor pillar 11 is 1.5 to 3 times the width of the first semiconductor pillar 10.
Specifically, in this embodiment, the width of the second semiconductor pillar 11 is 8 nm to 20 nm, so that the effect of the second semiconductor pillar 11 for improving the contact performance of the drain doped layer 125 and the contact plug is more remarkable, and the reliability of the semiconductor structure is improved.
The semiconductor structure further includes: an isolation layer 106 is located on the source doped layer 105 and surrounds a portion of the sidewall of the first semiconductor pillar 10 exposed by the gate structure 120.
The isolation layer 106 is used to isolate the gate structure 120 from the source doped layer 105.
In this embodiment, the material of the isolation layer 106 is silicon oxide. Silicon oxide is an insulating material commonly used in semiconductor technology, and has high technology compatibility. In other embodiments, the material of the isolation layer may also be silicon nitride, silicon oxynitride, boron nitride, or silicon oxycarbonitride.
The gate structure 120 is used for controlling the on/off of the conducting channel when the MOS device is operated.
In this embodiment, the gate structure 120 is a metal gate structure. The gate structure 120 includes a work function layer 111 surrounding a portion of the sidewall of the first semiconductor pillar 10 where the doped layer 104 is exposed, and a gate electrode layer 112 surrounding the work function layer 111.
Specifically, the gate structure 120 surrounds the exposed sidewalls of the first semiconductor pillars 10 of the isolation layer 106. Wherein the gate electrode layer 112 and the work function layer 111 also extend onto the source doped layer 105 on the side of the semiconductor pillar 110. Specifically, the gate electrode layer 112 and the work function layer 111 also extend onto the isolation layer 106 above the source doped layer 105 on the side of the semiconductor pillar 110.
When the semiconductor structure is an NMOS transistor, the material of the work function layer 111 includes one or more of titanium aluminide, tantalum carbide, aluminum, or titanium carbide; when the semiconductor structure is a PMOS transistor, the material of the work function layer 111 includes one or more of titanium nitride, tantalum nitride, titanium carbide, tantalum silicon nitride, titanium silicon nitride, and tantalum carbide.
In this embodiment, the material of the gate electrode layer 112 is magnesium-tungsten alloy. In other embodiments, the material of the gate electrode layer may also be W, al, cu, ag, au, pt, ni or Ti.
In this embodiment, the semiconductor structure further includes: and the gate dielectric layer 107 conformally covers the semiconductor column 110 exposed by the isolation layer 106.
The gate dielectric layer 107 is used to electrically isolate the gate structure 120 from the semiconductor pillar 110.
The gate structure 120 is a metal gate structure, so the gate dielectric layer 107 is made of a high-k dielectric material; the high-k dielectric material refers to a dielectric material with a relative dielectric constant larger than that of silicon oxide. Specifically, the gate dielectric layer 107 is made of HfO 2 . In other embodiments, the gate dielectric layer material may also be selected from ZrO 2 HfSiO, hfSiON, hfTaO, hfTiO, hfZrO or Al 2 O 3 Etc.
In other embodiments, the gate dielectric layer may further include a gate oxide layer, and a high-k dielectric layer disposed on the gate oxide layer, where a material of the gate oxide layer may be silicon oxide or silicon oxynitride, respectively.
In this embodiment, by reserving the gate dielectric layer 107 on the surface of the drain doped layer 125, the gate dielectric layer 107 protects the drain doped layer 125, so that the isolation between the drain doped layer 125 and the gate structure 120 is better achieved.
The drain doped layer 125 is the same as the source doped layer 105 in the type of dopant ions and in the material.
When forming a PMOS transistor, the material of the drain doped layer 125 is P-type ion doped silicon germanium. By doping P-type ions in silicon germanium, the more P-type ions are doped, the higher the concentration of the polytope is, and the stronger the conductivity is. Specifically, the P-type ions include B, ga or In.
When forming an NMOS transistor, the material of the drain doped layer 125 is silicon carbide or silicon phosphide doped with N-type ions, respectively. By doping N-type ions in silicon carbide or silicon phosphide, the N-type ions replace the positions of silicon atoms in a crystal lattice, the more N-type ions are doped, the higher the concentration of the polyions is, and the higher the conductivity is. Specifically, the N-type ions include P, as or Sb.
In this embodiment, the second semiconductor pillar 11 is doped with ions, and a portion of the second semiconductor pillar 11 doped with ions serves as the drain doped layer 125. In other embodiments, the drain doped layer may also be an epitaxial layer doped with ions, the epitaxial layer being located on top of the second semiconductor pillar.
In this embodiment, the semiconductor structure further includes: a first dielectric layer 115 on the substrate 100 exposed by the gate structure 120, wherein the first dielectric layer 115 exposes the second semiconductor pillar 11; a second dielectric layer 127 covering the first dielectric layer 115 and the drain doped layer 125, wherein the second dielectric layer 127 and the first dielectric layer 115 form an interlayer dielectric layer (not labeled); a source contact plug 122, located in the interlayer dielectric layer at one side of the gate structure 120 and electrically connected to the source doped layer 105; a drain contact plug 121 located in the second dielectric layer 127 and electrically connected to the drain doped layer 125; and a gate contact plug 123, which is located in the interlayer dielectric layer at the other side of the gate structure 120 and is electrically connected to the gate structure 120.
The first dielectric layer 115 is used to achieve electrical isolation between adjacent devices.
Thus, the material of the first dielectric layer 115 is a dielectric material. In this embodiment, the material of the first dielectric layer 115 is silicon oxide. In other embodiments, the material of the dielectric layer may be silicon nitride, silicon oxynitride, or other dielectric materials.
The second dielectric layer 127 is also used to isolate adjacent devices. The second dielectric layer 127 is further used to provide a process platform for forming the drain contact plug 121, the source contact plug 122, and the gate contact plug 123, and the second dielectric layer 127 is further used to realize isolation between adjacent contact plugs. In this embodiment, the second dielectric layer 127 is made of the same material as the first dielectric layer 115. The material of the second dielectric layer 127 is silicon oxide.
The drain contact hole plug 121 is used for electrically connecting the drain doped layer 125 with an external circuit or other interconnection structure; the source contact plug 122 is used to electrically connect the source doped layer 115 to an external circuit or other interconnect structure; the gate contact plugs 123 are used to electrically connect the gate structures 120 to external circuitry or other interconnect structures.
In this embodiment, the drain contact plug 121 is made of tungsten.
In this embodiment, the materials of the source contact hole plug 122 and the gate contact hole plug 123 are the same as the materials of the drain contact hole plug 121, and will not be described here again.
The semiconductor structure may be formed by the forming method described in the foregoing embodiments, or may be formed by other forming methods. For a specific description of the semiconductor structure in this embodiment, reference may be made to the corresponding description in the foregoing embodiment, which is not repeated here.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.

Claims (18)

1. A method of forming a semiconductor structure, comprising:
forming a substrate, comprising: providing a substrate; forming a source doping layer on the substrate; forming a protective layer on the source doping layer; forming a groove in the protective layer, wherein the cross section of the groove is T-shaped, the groove comprises a bottom groove and a top groove positioned on the bottom groove, the opening width of the top groove is larger than that of the bottom groove, and the top of the bottom groove is communicated with the bottom of the top groove; forming a semiconductor column in the groove, wherein the part of the semiconductor column in the bottom groove is used as a first semiconductor column, the part of the semiconductor column in the top groove is used as a second semiconductor column, the semiconductor column is of a T-shaped structure, the semiconductor column comprises a first semiconductor column and a second semiconductor column on the first semiconductor column, and the width of the second semiconductor column is larger than that of the first semiconductor column;
forming a drain doping layer on the top of the second semiconductor column;
after forming the source-drain doped layer, etching back the protective layer with partial thickness, wherein the rest protective layer is used as an isolation layer;
And forming a gate structure, wherein the gate structure surrounds part of the side wall of the first semiconductor column exposed by the protective layer, and the second semiconductor column is exposed by the gate structure.
2. The method of forming a semiconductor structure of claim 1, wherein the step of forming the recess comprises: forming an initial protection layer on the source doping layer;
forming an initial groove exposing the source doping layer in the initial protection layer; forming a filling layer in the initial groove, wherein the top of the filling layer is lower than the top of the initial protective layer;
etching the exposed initial groove side wall of the filling layer along the direction perpendicular to the initial groove side wall to form the top groove, and taking the remaining initial protective layer as the protective layer;
and removing the filling layer, and taking the remaining initial grooves communicated with the top grooves as the bottom grooves.
3. The method of forming a semiconductor structure of claim 1, wherein the semiconductor pillars are formed in the recesses using an epitaxial process.
4. The method of claim 2, wherein the exposed sidewalls of the initial recess of the fill layer are etched using an isotropic etch process.
5. The method of claim 4, wherein the exposed sidewalls of the initial recess of the filler layer are etched using a sicon process or a hydrofluoric acid solution.
6. The method of forming a semiconductor structure of claim 2, wherein the initial protective layer is etched using a dry etching process to form the initial recess.
7. The method of claim 1, wherein the material of the protective layer is silicon oxide, silicon nitride, silicon oxynitride, boron nitride, or silicon oxycarbonitride.
8. The method of forming a semiconductor structure of claim 1, wherein a dry etching process is used to etch back a portion of the protective layer.
9. The method of claim 2, wherein the material of the filling layer is BARC material, ODL material, SOC material, photoresist, DARC material, or DUO material.
10. The method of forming a semiconductor structure of claim 1, wherein a height of the second semiconductor pillar is one fifth to one third of a total height of the semiconductor pillar.
11. The method of forming a semiconductor structure of claim 1, wherein a width of the second semiconductor pillar is 1.5 times to 3 times a width of the first semiconductor pillar.
12. The method of forming a semiconductor structure of claim 1, wherein a width of the second semiconductor pillar is 8 nm to 20 nm.
13. The method of forming a semiconductor structure of claim 1, wherein the step of forming the drain doped layer comprises: and carrying out ion doping treatment on the second semiconductor column exposed by the protective layer, wherein part of the second semiconductor column doped with ions serves as the leakage doping layer.
14. A semiconductor structure, comprising:
a substrate;
a source doped layer located on the substrate;
the semiconductor column protrudes out of the source doping layer, the semiconductor column is of a T-shaped structure, the semiconductor column comprises a first semiconductor column and a second semiconductor column positioned on the first semiconductor column, and the width of the second semiconductor column is larger than that of the first semiconductor column;
a gate structure surrounding a portion of a sidewall of the first semiconductor pillar, the gate structure exposing the second semiconductor pillar;
the leakage doping layer is positioned at the top of the second semiconductor column;
the semiconductor structure further comprises an isolation layer which is positioned between the source doping layer and the gate structure in the direction perpendicular to the substrate and surrounds part of the side wall of the first semiconductor column exposed by the gate structure.
15. The semiconductor structure of claim 14, wherein a height of the second semiconductor pillar is one fifth to one third of a total height of the semiconductor pillar.
16. The semiconductor structure of claim 14, wherein a width of the second semiconductor pillar is 1.5 times to 3 times a width of the first semiconductor pillar.
17. The semiconductor structure of claim 14, wherein a width of the second semiconductor pillar is 8 nm to 20 nm.
18. The semiconductor structure of claim 14, wherein ions are doped in the second semiconductor pillars, and a portion of the second semiconductor pillars doped with ions serves as the leaky doped layer.
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Citations (2)

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CN101877317A (en) * 2009-04-29 2010-11-03 台湾积体电路制造股份有限公司 Non-planar transistors and methods of fabrication thereof
JP2014022386A (en) * 2012-07-12 2014-02-03 Ps4 Luxco S A R L Semiconductor device

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