CN111627819B - Semiconductor structure and forming method thereof - Google Patents

Semiconductor structure and forming method thereof Download PDF

Info

Publication number
CN111627819B
CN111627819B CN201910153187.1A CN201910153187A CN111627819B CN 111627819 B CN111627819 B CN 111627819B CN 201910153187 A CN201910153187 A CN 201910153187A CN 111627819 B CN111627819 B CN 111627819B
Authority
CN
China
Prior art keywords
layer
semiconductor
forming
doping
semiconductor structure
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201910153187.1A
Other languages
Chinese (zh)
Other versions
CN111627819A (en
Inventor
周飞
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
Original Assignee
Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Semiconductor Manufacturing International Shanghai Corp, Semiconductor Manufacturing International Beijing Corp filed Critical Semiconductor Manufacturing International Shanghai Corp
Priority to CN201910153187.1A priority Critical patent/CN111627819B/en
Publication of CN111627819A publication Critical patent/CN111627819A/en
Application granted granted Critical
Publication of CN111627819B publication Critical patent/CN111627819B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4908—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET for thin film semiconductor, e.g. gate of TFT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78642—Vertical transistors

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

A semiconductor structure and a method for forming the same, the method for forming the same includes: providing a substrate; forming a source doping layer on a substrate; forming a semiconductor column on the source doped layer; forming a drain doping layer at the top end of the semiconductor column; forming a gate structure surrounding a portion of the sidewall of the semiconductor pillar and exposing the drain doped layer, the gate structure including a work function layer covering the portion of the sidewall of the semiconductor pillar and a gate layer covering the work function layer; doping ions in the work function layer at a location near the drain doped layer that can increase the threshold voltage of the semiconductor structure. According to the embodiment of the invention, ions are doped in the work function layer, so that the voltage at the drain doping layer is reduced, the longitudinal electric field at the corresponding drain doping layer is reduced, namely the reliability of the semiconductor structure is improved, and the starting voltage at the source doping layer is lower because the work function layer is doped at the position close to the drain doping layer, so that the driving current of the semiconductor structure is higher, and the electrical property of the semiconductor structure is optimized.

Description

Semiconductor structure and forming method thereof
Technical Field
The present disclosure relates to semiconductor manufacturing, and more particularly, to a semiconductor structure and a method for forming the same.
Background
With the rapid development of semiconductor manufacturing technology, semiconductor devices are being developed toward higher element density and higher integration, and the development trend of semiconductor process nodes following moore's law is continuously decreasing. Transistors are currently being widely used as the most basic semiconductor devices, and therefore, as the element density and integration level of the semiconductor devices are improved, the channel length of the transistors has to be continuously shortened in order to accommodate the reduction of process nodes.
The reduction of the transistor channel length has the benefits of increasing the die density of the chip, increasing the switching speed, and the like. However, as the channel length is shortened, the distance between the source and the drain of the transistor is shortened, the control capability of the gate to the channel is reduced, so that the subthreshold leakage (subthreshold leakage) phenomenon, that is, short-channel effects (SCE) is more likely to occur, and the channel leakage current of the transistor is increased.
Accordingly, to better accommodate the demand for device scaling, semiconductor processes are increasingly beginning to transition from planar transistors to three-dimensional transistors with higher power, such as Gate-all-around (GAA) transistors. In the fully-enclosed gate transistor, the gate encloses the region where the channel is located from the periphery, and compared with a planar transistor, the gate of the fully-enclosed gate transistor has stronger control capability on the channel and can better inhibit the short channel effect. The fully-surrounding Gate transistors include a Lateral Gate-all-around (lga) transistor and a Vertical Gate-all-around (VGAA) transistor, wherein the channel of VGAA extends in a direction perpendicular to the substrate surface, which is advantageous for improving the area utilization efficiency of the semiconductor structure, and thus for achieving further feature size reduction.
Disclosure of Invention
The embodiment of the invention solves the problem of providing a semiconductor structure and a forming method thereof, and optimizes the electrical performance of the semiconductor structure.
In order to solve the above problems, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate; forming a source doping layer on the substrate; forming a semiconductor column on the source doped layer; forming a drain doping layer at the top end of the semiconductor column; forming a gate structure surrounding a portion of the sidewall of the semiconductor pillar and exposing the drain doped layer, the gate structure including a work function layer covering the semiconductor pillar portion sidewall and a gate layer covering the work function layer; doping ions in the work function layer at a position close to the leakage doping layer, wherein the doping ions can increase the threshold voltage of the semiconductor structure.
Correspondingly, the embodiment of the invention also provides a semiconductor structure, which comprises: a substrate; a source doped layer located on the substrate; a semiconductor pillar located on the source doped layer; the leakage doping layer is positioned at the top end of the semiconductor column; a gate structure surrounding a portion of the sidewall of the semiconductor pillar and exposing the drain doped layer, the gate structure including a work function layer covering the semiconductor pillar portion sidewall and a gate layer covering the work function layer; and the doping ions are positioned in the work function layer at a position close to the leakage doping layer, and can increase the threshold voltage of the semiconductor structure.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following advantages:
the substrate comprises a substrate, a source doping layer positioned on the substrate and a semiconductor column positioned on the source doping layer; forming a drain doping layer at the top end of the semiconductor column; the gate structure comprises a work function layer and a gate layer positioned on the work function layer, and the gate structure exposes the leakage doped layer; doping ions in the work function layer at a position close to the leakage doping layer, wherein the doping ions can increase the threshold voltage of the semiconductor structure. The source doping layer is connected with the substrate, so that the voltage of the source doping layer is lower, the voltage of the drain doping layer is higher than that of the source doping layer, the electric field of the drain doping layer is stronger, hot carriers in the corresponding drain doping layer are liable to damage the grid structure, the electric field intensity is positively correlated with the voltage intensity, the longitudinal electric field is arranged at the drain doping layer, the longitudinal voltage at the drain doping layer is equal to the longitudinal voltage loaded on the grid structure minus the threshold voltage of the semiconductor structure.
Drawings
FIG. 1 is a schematic diagram of a semiconductor structure;
fig. 2 to 14 are schematic structural views corresponding to steps in a first embodiment of a method for forming a semiconductor structure according to an embodiment of the present invention;
fig. 15 is a schematic view of a semiconductor structure according to a second embodiment of the method for forming a semiconductor structure according to the present invention.
Detailed Description
As can be seen from the background art, the devices formed at present still have the problem of poor performance. The reason for the poor performance of the device is analyzed by combining a forming method of a semiconductor structure.
Referring to fig. 1, a schematic structural diagram of a semiconductor structure is shown.
The semiconductor structure includes: a substrate 10; a source doped layer 11 on the substrate 10; a semiconductor pillar 13 located on the source doped layer 11; a leaky doped layer 12 positioned at the top end of the semiconductor column 13; an isolation layer 14 on the source doped layer 11 exposed from the semiconductor pillar 13, and the isolation layer 14 covers a portion of the sidewall of the semiconductor pillar 13; a gate structure 15 surrounding a portion of the sidewall of the semiconductor pillar 13, the gate structure 15 exposing the drain doped layer 12; a bottom contact hole plug 16 located on the source doping layer 11 and connected to the source doping layer 11; a gate contact plug 17 located on the gate structure 15 and connected to the gate structure 15; a top contact plug 18 is located on the drain doped layer 12 and is connected to the drain doped layer 12.
The source doped layer 11 is connected with the substrate 10, and when the semiconductor structure works, the voltage of the source doped layer 11 is lower, the voltage of the drain doped layer 12 is higher than that of the source doped layer 11, so that the electric field of the drain doped layer 12 is stronger, and hot carriers in the corresponding drain doped layer 12 are liable to damage the gate structure 15, so that the electrical performance of the semiconductor structure is not high.
In order to solve the technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate, a source doping layer positioned on the substrate and a semiconductor column positioned on the source doping layer; forming a drain doping layer at the top end of the semiconductor column; forming a gate structure surrounding a portion of a sidewall of the semiconductor pillar and exposing the drain doped layer, the gate structure including a work function layer and a gate layer on the work function layer, and the gate structure exposing the drain doped layer; doping ions in the work function layer at a position close to the leakage doping layer, wherein the doping ions can increase the threshold voltage of the semiconductor structure. The source doping layer is connected with the substrate, so that the voltage of the source doping layer is lower, the voltage of the drain doping layer is higher than that of the source doping layer, the electric field of the drain doping layer is stronger, hot carriers in the corresponding drain doping layer are liable to damage the grid structure, the electric field intensity is positively correlated with the voltage intensity, the longitudinal electric field is arranged at the drain doping layer, the longitudinal voltage at the drain doping layer is equal to the longitudinal voltage loaded on the grid structure minus the threshold voltage of the semiconductor structure.
In order to make the above objects, features and advantages of the embodiments of the present invention more comprehensible, a detailed description of specific embodiments of the present invention is provided below with reference to the accompanying drawings.
Fig. 2 to 14 are schematic structural views corresponding to each step in the first embodiment of the method for forming a semiconductor structure according to the embodiment of the present invention.
Referring to fig. 2, a substrate 100 is provided. The substrate 100 provides a process platform for the subsequent formation of semiconductor structures.
In this embodiment, the substrate 100 is a silicon substrate. In other embodiments, the substrate material may also be germanium, silicon carbide, gallium arsenide, or indium gallium, and the substrate may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate.
With continued reference to fig. 2, a source doped layer 101 is formed on the substrate 100.
The source doped layer 101 serves as the source of the semiconductor structure. The source doped layer 101 and a drain doped layer formed at the top end of the semiconductor pillar later form a source-drain doped layer of the semiconductor structure.
In this embodiment, the semiconductor structure is used to form a PMOS (Positive Channel Metal Oxide Semiconductor) transistor, i.e., the material of the source doped layer 101 is P-type ion doped silicon germanium. In this embodiment, by doping P-type ions in silicon germanium, the P-type ions replace the positions of silicon atoms in the crystal lattice, and the more P-type ions are doped, the higher the concentration of the polynomials is, and the stronger the conductivity is. Specifically, the P-type ions include B, ga or In.
In other embodiments, the semiconductor structure is used to form NMOS (Negative channel Metal Oxide Semiconductor) transistors, and the material of the source doped layer is silicon carbide or silicon phosphide doped with N-type ions, respectively. By doping N-type ions in silicon carbide or silicon phosphide, the N-type ions replace the positions of silicon atoms in a crystal lattice, the more N-type ions are doped, the higher the concentration of the polyions is, and the higher the conductivity is. Specifically, the N-type ions include P, as or Sb.
In this embodiment, the first epitaxial layer is formed by using an epitaxial growth method, and in-situ doping ions are used in the process of forming the first epitaxial layer to form the source doped layer 101. In other embodiments, after in-situ self-doping is adopted in the process of forming the first epitaxial layer, ion doping is further performed on the first epitaxial layer in an ion implantation manner to form a source doped layer. The doped ions can achieve the effect of improving the carrier mobility of the transistor. In other embodiments, the first epitaxial layer may be doped with ions only by ion implantation.
Referring to fig. 3, a semiconductor pillar 102 is formed on the source doping layer 101. The semiconductor pillars 102 are used to form channels during operation of the semiconductor structure.
In this embodiment, the material of the semiconductor pillar 102 is silicon. In other embodiments, the material of the semiconductor pillar may be germanium, silicon carbide, gallium arsenide, or indium gallium arsenide.
The step of forming the semiconductor pillars 102 includes: after forming the source doping layer 101, forming a semiconductor material pillar (not shown in the figure) on the source doping layer 101; forming a mask layer 103 on the semiconductor material pillars; and etching the semiconductor material column by taking the mask layer 103 as a mask to form a semiconductor column 102.
In this embodiment, a selective epitaxial growth method is used to form a semiconductor material column on the source doped layer 101, so that the formed semiconductor material column is a monocrystalline material with higher purity, and a channel region is prepared for the semiconductor column formed subsequently.
The semiconductor pillars 102 are not easily too short or too tall. If the semiconductor pillars 102 are too short, the channel region formed later is too short, short channel effect is easily generated, and the electrical performance of the semiconductor structure is not improved; if the semiconductor pillars 102 are too high, the semiconductor pillars 102 are prone to collapse, and the process of forming the semiconductor pillars 102 is too difficult. In this embodiment, the height of the semiconductor pillars 102 is 150 nm to 800 nm.
Referring to fig. 3 and 4, after forming the semiconductor pillars 102, further includes: an isolation layer 104 is formed on the source doped layer 101 where the semiconductor pillar 102 is exposed (as shown in fig. 4), the isolation layer 104 covering a portion of the sidewall of the semiconductor pillar 102.
The isolation layer 104 is used to electrically isolate the gate structure formed later from the source doped layer 101, so as to optimize the electrical performance of the semiconductor structure.
In this embodiment, the material of the isolation layer 104 is an insulating material. Specifically, the material of the isolation layer 104 includes one or more of silicon oxide, silicon nitride, silicon carbonitride oxide, silicon oxynitride, boron nitride, and boron carbonitride. In this embodiment, the material of the isolation layer 104 is silicon oxide. Silicon oxide is a dielectric material with common process and low cost, has high process compatibility, and is beneficial to reducing the process difficulty and the process cost for forming the isolation layer 104; in addition, the smaller dielectric constant of silicon oxide is also beneficial to improving the function of the subsequent isolation layer 104 for isolating adjacent devices.
The step of forming the isolation layer 104 includes: forming an isolation material layer (not shown in the figure) on the source doping layer 101 where the semiconductor pillars 102 are exposed, the isolation material layer covering the semiconductor pillars 102; flattening the isolation material layer until the mask layer 103 is exposed; and etching back the isolation material layer with the mask layer 103 as a mask to form the isolation layer 104 on the source doped layer 101 exposed by the semiconductor column 102.
In this embodiment, the isolation material layer is formed using a flowable chemical vapor deposition (Flowable Chemical Vapor Deposition, FCVD) process. The flowable chemical vapor deposition process has good filling capability, is beneficial to reducing the probability of forming defects such as cavities in the isolation material layer, and is correspondingly beneficial to improving the film forming quality of the isolation material layer.
The spacer layer 104 is not too thick or too thin. If the isolation layer 104 is too thick, the gate structure formed on the semiconductor pillar 102 is too short, which may result in poor effect of controlling the short channel effect of the gate structure, and is unfavorable for improving the electrical performance of the semiconductor structure. If the isolation layer 104 is too thin, the distance between the gate structure formed on the semiconductor pillar 102 and the source doped layer 101 is too short, which is likely to cause bridging between the gate structure and the source doped layer 101, and is not favorable for optimizing the electrical performance of the semiconductor structure. In this embodiment, the thickness of the isolation layer 104 is 5 nm to 15 nm.
Continuing to dope fig. 3 and 4, the method for forming the semiconductor structure further includes: after forming the semiconductor pillars 102, a protective material layer 105 (shown in fig. 3) is conformally covered over the semiconductor pillars 102 and the source doped layer 101 exposed by the semiconductor pillars 102, before forming the isolation material layer.
The isolation material layer is formed by adopting a flowable chemical vapor deposition process, the isolation material layer is rich in O and H, and the protection material layer 105 is used for making the surface of the semiconductor pillar 102 not easily oxidized in the process of forming the isolation layer 104.
The material of the protective material layer 105 is a dielectric material. Specifically, the material of the protective material layer 105 includes one or more of silicon oxide, silicon nitride, silicon carbonitride oxide, silicon oxynitride, boron nitride, and boron carbonitride. In this embodiment, the material of the protective material layer 105 is silicon oxide.
In this embodiment, the protective material layer 105 is formed by an atomic layer deposition process (Atomic Layer Deposition, ALD). The atomic layer deposition process has good deposition uniformity, is beneficial to improving the thickness uniformity and the film quality of the isolating film, is correspondingly beneficial to improving the film forming quality of the protective material layer 105, and is beneficial to accurately controlling the deposition thickness of the protective material layer 105 by adopting the atomic layer deposition process. In other embodiments, the sidewall material layer may also be formed using a chemical vapor deposition process (Chemical Vapor Deposition, CVD).
The protective material layer 105 is preferably not too thick or too thin. If the protective material layer 105 is too thick, the process time for forming the protective material layer 105 is too long, and the corresponding process for subsequently removing the protective material layer 105 exposing the isolation layer 104 (as shown in fig. 4) is too long, and the gate structure subsequently formed on the semiconductor pillar 102 is too short, which is easy to cause poor effect of controlling short channel effect of the gate structure, and is unfavorable for improving the electrical performance of the semiconductor structure. If the protective material layer 105 is too thin, the surface of the semiconductor pillar 102 is easily oxidized, resulting in poor uniformity of the semiconductor pillar 102, which cannot well improve the electrical performance of the semiconductor structure. In this embodiment, the thickness of the protective material layer 105 is 3 nm to 8 nm.
The method for forming the semiconductor structure further comprises the following steps: after the spacer 104 is formed, the protective material layer 105 exposed by the spacer 104 is removed, and a protective layer 106 is formed.
The removal of the protective material layer 105 exposing the isolation layer 104 provides for the subsequent formation of a gate structure surrounding the semiconductor pillar portion sidewalls.
In this embodiment, the materials of the isolation layer 104 and the protection material layer 105 are different, the isolation layer 104 and the protection material layer 105 have an etching selectivity, and a wet process is used to remove the protection material layer 105 exposed by the isolation layer 104. The wet etching process is isotropic etching, has higher etching rate, and is simple to operate and low in process cost.
The material of the passivation layer 106 is a dielectric material, so the passivation layer 106 located at the bottom end of the isolation layer 104 and between the isolation layer 104 and the semiconductor pillar 102 may not be removed.
Referring to fig. 5 to 12, a gate structure 109 (shown in fig. 12) is formed surrounding a portion of the sidewall of the semiconductor pillar 102, the gate structure 109 including a work function layer 1091 (shown in fig. 12) covering the portion of the sidewall of the semiconductor pillar 102 and a gate layer 1092 (shown in fig. 12) covering the work function layer 1091.
The gate structure 109 is used to control the opening and closing of the channel in the semiconductor pillar 102.
In this embodiment, the semiconductor structure is used to form an NMOS. Specifically, the material of the work function layer 1091 includes one or more of titanium aluminide, tantalum carbide, aluminum, or titanium carbide. In other embodiments, the semiconductor structure is used to form a PMOS. Specifically, the material of the work function layer includes one or more of titanium nitride, tantalum nitride, titanium carbide, tantalum silicon nitride, titanium silicon nitride, and tantalum carbide.
In this embodiment, the material of the gate layer 1092 is magnesium-tungsten alloy. In other embodiments, the material of the gate layer may also be W, al, cu, ag, au, pt, ni or Ti.
The step of forming the gate structure 109 includes:
as shown in fig. 6, a gate material structure 107 (shown in fig. 7) is conformally covered over the semiconductor pillars 102 and the source doped layer 101 where the semiconductor pillars 102 are exposed.
In this embodiment, the gate material structure 107 includes a work function material layer 1071 and a gate material layer 1072 on the work function material layer 1071.
The work function material layer 1071 provides for a subsequent formation of a work function layer, and the gate material layer 1072 provides for a subsequent formation of a gate layer.
In this embodiment, the gate material structure 107 is formed by an atomic layer deposition process, and the advantages of the atomic layer deposition process are not described herein.
As shown in fig. 7, a shielding layer (not shown) is formed to cover the gate material structure 107, and the gate material structure 107 is etched with the shielding layer as a mask; after etching the gate material structure 107, the masking layer is removed.
The masking layer reduces the probability of the gate material structure 107 being misetched that is covered by the masking layer during removal of the gate material structure 107 that is exposed by the masking layer.
Specifically, the step of forming the shielding layer includes: forming a layer of shielding material (not shown) overlying the gate material structure 107; forming a photoresist layer on the shielding material layer; and etching the shielding material layer by taking the photoresist layer as a mask to form a shielding layer.
In this embodiment, the material of the shielding layer is an organic material. The organic material is a material that is easy to remove so that damage to the gate material structure 107 is reduced when the masking layer is subsequently removed.
Specifically, the material of the shielding layer may be BARC (bottom anti-reflective coating ) material, ODL (organic dielectric layer, organic dielectric layer) material, photoresist, DARC (dielectric anti-reflective coating ) material, DUO (Deep UV Light Absorbing Oxide, deep ultraviolet light absorbing oxide) material, or APF (Advanced Patterning Film ) material.
In this embodiment, a spin coating process is used to form the shielding material layer.
In this embodiment, after the gate material structure 107 is etched, the shielding layer is removed. And removing the shielding layer to provide space for forming an interlayer dielectric layer subsequently.
In this embodiment, an ashing process or a dry etching process is used to remove the shielding layer.
As shown in fig. 8 to 11, after the shielding layer is removed, an interlayer dielectric layer 110 (as shown in fig. 11) is formed to cover a portion of the sidewalls of the semiconductor pillars 102.
The interlayer dielectric layer 110 provides for subsequent removal of the gate material structure 107 exposing the interlayer dielectric layer 110.
The interlayer dielectric layer 110 is used for realizing electrical isolation between adjacent devices, and the material of the interlayer dielectric layer 110 is an insulating material. In this embodiment, the material of the interlayer dielectric layer 110 is silicon oxide, and in other embodiments, the material of the interlayer dielectric layer may be another insulating material such as silicon nitride or silicon oxynitride.
The step of forming the interlayer dielectric layer 110 includes: forming an interlayer dielectric material layer 111 (as shown in fig. 8) covering the gate material structure 107, the interlayer dielectric material layer 111 exposing a top surface of the gate material structure 107 on the semiconductor pillar 102; and etching back part of the interlayer dielectric material layer 111 to form an interlayer dielectric layer 110 covering part of the side wall of the semiconductor column 102.
As shown in fig. 12, the gate material structure 107 above the interlayer dielectric layer 110 is removed, and a gate structure 109 is formed to cover a portion of the sidewall of the semiconductor pillar 102.
In this embodiment, a dry process is used to remove the gate material structure 107 exposing the interlayer dielectric layer 110. The dry etching process is beneficial to precisely controlling the thickness of the gate material structure 107 exposing the interlayer dielectric layer 110, and reducing the damage to other film structures. In other embodiments, a wet etching process may be further used to remove the gate material structure exposing the interlayer dielectric layer.
With continued reference to fig. 5, it should be noted that the method for forming the semiconductor structure further includes: after forming the isolation layer 104, a gate dielectric layer 108 is conformally covered over the semiconductor pillars 102 and the isolation layer 104 exposed by the semiconductor pillars 102, prior to forming the gate material structure 107.
The gate dielectric layer 108 is used to electrically isolate the gate material structure 107 from the semiconductor pillar 102.
In this embodiment, the gate structure is a metal gate junctionThe material of gate dielectric layer 108 thus includes HfO 2 、ZrO 2 HfSiO, hfSiON, hfTaO, hfTiO, hfZrO and Al 2 O 3 One or more of them. In other embodiments, when the gate structure is a polysilicon gate structure, the material of the gate dielectric layer includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride oxide, and amorphous carbon.
In this embodiment, the gate dielectric layer 108 is formed by an atomic layer deposition process, and the advantages of the atomic layer deposition process are not described herein. In other embodiments, the gate dielectric layer may also be formed by a chemical vapor deposition process.
With continued reference to fig. 8-10, a drain doped layer 112 is formed on top of the semiconductor pillars 102 (as shown in fig. 10).
The drain doped layer 112 and the source doped layer 101 provide stress to the channel during operation of the semiconductor structure, increasing the carrier mobility.
The step of forming the drain doped layer 112 includes: after forming the interlayer dielectric material layer 111, before forming the interlayer dielectric layer 110, removing the interlayer dielectric material layer 111 and the gate material structure 107 higher than the mask layer 103 by adopting a planarization process; after exposing the mask layer 103, removing the mask layer 103 to form a groove (not shown in the figure) surrounded by the semiconductor column 102 and the gate dielectric layer 108; a drain doped layer 112 is formed in the recess.
In this embodiment, the interlayer dielectric material layer 111 is planarized by Chemical-mechanical planarization (Chemical-Mechanical Planarization, CMP).
In this embodiment, a wet etching process is used to remove the mask layer 103. The gate material structure 107 exposing the interlayer dielectric layer 110 is removed by a wet process. The wet etching process is isotropic etching, has higher etching rate, and is simple to operate and low in process cost. In other embodiments, a dry etching process may also be used to remove the exposed mask layer.
Specifically, the mask layer 103 is exposed by removing with a phosphoric acid solution.
In this embodiment, the second epitaxial layer is formed by an epitaxial growth method, and in-situ doping ions are used in the process of forming the second epitaxial layer to form the drain doped layer 112. In other embodiments, after in-situ self-doping is adopted in the process of forming the second epitaxial layer, ion doping may be performed on the second epitaxial layer continuously by using an ion implantation method to form the drain doped layer 112. The doped ions can achieve the effect of improving the mobility of carriers in the channel. In other embodiments, the second epitaxial layer may be doped with ions only by ion implantation.
In this embodiment, the semiconductor structure is used to form PMOS (Positive Channel Metal Oxide Semiconductor), i.e., the material of the second epitaxial layer is silicon germanium. In this embodiment, by doping P-type ions in the second epitaxial layer, the P-type ions replace the silicon atoms in the lattice, and the more P-type ions are doped, the higher the concentration of the multimers and the stronger the conductivity. Specifically, the P-type ions include B, ga or In.
In other embodiments, the semiconductor structure is used to form NMOS (Negative channel Metal Oxide Semiconductor), i.e., the material of the second epitaxial layer is silicon carbide or silicon phosphide, respectively. By doping N-type ions in the second epitaxial layer, the N-type ions replace the positions of silicon atoms in the crystal lattice, and the more N-type ions are doped, the higher the concentration of the polytope and the stronger the conductivity. Specifically, the N-type ions include P, as or Sb.
In other embodiments, the step of forming the leakage doped layer may further include: removing the interlayer dielectric material layer higher than the semiconductor column by adopting a planarization process; and carrying out ion doping on the semiconductor column to form a leakage doping layer.
In other embodiments, the step of forming the leaky doped layer includes: after the isolation material layer is formed, before the isolation layer is formed, a planarization process is adopted to remove the isolation material layer higher than the mask layer; removing the mask layer exposed by the isolation material layer to form an isolation layer groove surrounded by the isolation material layer and the semiconductor column; and forming the leakage doping layer in the isolation layer groove.
Or removing the isolation material layer higher than the semiconductor column by adopting a planarization process after the isolation material layer is formed and before the isolation layer is formed; and carrying out ion doping on the semiconductor column to form the leakage doped layer.
The drain doped layer is formed before the gate material structure is formed, so that the situation that doping ions are mistakenly introduced into the gate material structure in the process of forming the drain doped layer, and the opening and the disconnection of a channel cannot be well controlled by the subsequently formed gate structure can be avoided.
With continued reference to fig. 12, the gate structure 109 exposes the drain doped layer 112.
It should be noted that the distance between the gate structure 109 and the bottom of the drain doped layer 112 should not be too large or too small. If the distance is too large, the gate structure 109 on the semiconductor pillar 102 is too short, which is easy to cause poor effect of controlling the short channel effect of the gate structure 109, and is unfavorable for improving the electrical performance of the semiconductor structure. If the distance is too short, bridging between the gate structure 109 and the drain doped layer 112 may occur, which is detrimental to optimizing the electrical performance of the semiconductor structure. In this embodiment, the distance between the gate structure 109 and the bottom of the drain doped layer 112 is 6 nm to 10 nm.
Referring to fig. 13, dopant ions that increase the threshold voltage of the semiconductor structure are doped in the work function layer 1091 near the drain doped layer 112.
The source doped layer 101 is connected with the substrate 100, so that the voltage of the source doped layer 101 is lower, the voltage of the drain doped layer 112 is higher than the voltage of the source doped layer 101, the electric field of the drain doped layer 112 is stronger, hot carriers in the corresponding drain doped layer 112 are liable to damage the gate structure 109, the magnitude of the electric field strength is positively correlated with the voltage strength, a longitudinal electric field is arranged at the drain doped layer 112, the longitudinal voltage at the drain doped layer 112 is equal to the longitudinal voltage loaded on the gate structure 109 minus the threshold voltage of the semiconductor structure, and doping ions capable of increasing the threshold voltage of the semiconductor structure are doped in the work function layer 1091, so that the voltage at the drain doped layer 112 is reduced, the longitudinal electric field at the corresponding drain doped layer 112 is reduced, the reliability of the semiconductor structure is improved, and the starting voltage at the drain doped layer 101 is lower only at the position close to the drain doped layer 112 in the layer 1091, so that the driving current of the semiconductor structure is higher, and the work function performance of the semiconductor structure is optimized.
In this embodiment, after the gate structure 109 is formed, the work function layer 1091 is doped with a dopant ion capable of increasing the threshold voltage of the semiconductor structure by ion implantation. In other embodiments, ions may be doped in the work function layer by way of ion diffusion.
Ions are doped in the work function layer 1091, so that the fermi level of the work function layer 1091 tends to change on the top of the valence band or tends to change on the bottom of the conduction band, the fermi potential of the work function layer 1091 increases, so that an inversion layer of a semiconductor structure is more difficult to generate, the threshold voltage of the semiconductor structure is improved, the longitudinal voltage loaded on the drain doped layer 112 decreases, the longitudinal electric field at the corresponding drain doped layer 112 decreases, hot carriers in the drain doped layer 112 are not easy to damage the gate structure 109, and the electrical performance of the semiconductor structure is optimized.
Doping in the work function layer 1091 at a location near the drain doped layer 112 increases the threshold voltage of the semiconductor structure, that is, the ion doping concentration at the drain doped layer 112 is higher than the ion doping concentration at the source doped layer 101, and thus the turn-on voltage at the source doped layer 101 is lower, resulting in a higher drive current of the semiconductor structure.
In this embodiment, when the semiconductor structure is used to form PMOS, the process parameters of the ion doping include: the doping ions comprise one or more of Al, ti and Ta; the implantation dose is 1.0E16 atoms per square centimeter to 1.0E19 atoms per square centimeter, the implantation energy is 0.8Kev to 12Kev, and the included angle between the direction of ion implantation and the normal line of the substrate is 7 degrees to 25 degrees.
It should be noted that the implantation dose should not be too large or too small. If the implantation dosage is too large, the inversion layer of the semiconductor structure is more difficult to generate, and the threshold voltage of the semiconductor structure is too high, so that the semiconductor structure is more difficult to open; if the implant dose is too small, the threshold voltage of the semiconductor structure is not significantly increased, and the electric field at the drain doped layer 112 cannot be reduced, resulting in the gate structure 109 being easily damaged by hot carriers. In this example, the implant dose is 1.0E16 atoms per square centimeter to 1.0E19 atoms per square centimeter.
The implantation energy should not be too large or too small. If the implantation energy is too large, dopant ions will enter the work function layer 1091 near the source doping layer 101, so that the ion doping concentration at the source doping layer 101 is higher, and the driving current of the semiconductor structure is lower; in addition, if the implantation energy is higher, the doped ions enter the semiconductor column 102, that is, enter the channel region, so that the effect of increasing the threshold voltage of the semiconductor structure is not easily achieved; if the implantation energy is too low, the dopant ions are too concentrated on the top surface of the work function layer 1091, so that the dopant ions cannot play a role in adjusting the fermi level of the work function layer 1091, and the threshold voltage of the semiconductor structure is not significantly increased. In this embodiment, the implantation energy is 0.8Kev to 12Kev.
It should be noted that, the angle between the direction of ion implantation and the normal line of the substrate 100 should not be too large or too small. If the implantation angle is too large, too many dopant ions are implanted into the gate layer 1092, and thus too few dopant ions are implanted into the work function layer 1191, the electric field at the drain doped layer 112 cannot be reduced, and the gate structure 109 is easily damaged under the action of hot carriers. If the implantation angle is too small, dopant ions are likely to enter the work function layer 1091 near the source doping layer 101, resulting in an increase in the turn-on voltage at the source doping layer 101 and a lower drive current of the semiconductor structure. In this embodiment, the angle between the direction of ion implantation and the normal line of the substrate 100 is 7 degrees to 25 degrees.
In other embodiments, the semiconductor structure is used to form an NMOS transistor, and the process parameters of the ion doping include: the dopant ions include one or more of F, N, H, C and O; the implantation dose is 1.0E14 atoms per square centimeter to 9.0E16 atoms per square centimeter, the implantation energy is 0.5Kev to 10Kev, and the included angle between the direction of ion implantation and the normal line of the substrate is 7 degrees to 25 degrees.
Referring to fig. 14, after the doping ions, a dielectric layer 113 covering the inter-layer dielectric layer 110 and the drain doped layer 112 is formed; after forming the dielectric layer 113, forming a bottom contact plug 114 connected to the source doping layer 101; forming a gate contact plug 115 connected to the gate structure 109; a top contact plug 116 is formed in connection with the drain doped layer 112.
The dielectric layer 113 is used for realizing electrical isolation between adjacent devices, and the material of the dielectric layer 113 is an insulating material.
In this embodiment, the material of the dielectric layer 113 is silicon oxide. In other embodiments, the material of the dielectric layer may be another insulating material such as silicon nitride or silicon oxynitride.
The bottom contact plugs 114, gate contact plugs 115, and top contact plugs 116 are used to make electrical connection between the semiconductor structure and the semiconductor structure in addition to making electrical connection within the semiconductor structure.
The step of forming the bottom contact plug 114 includes: the dielectric layer 113, the interlayer dielectric layer 110, the isolation layer 104 and the protection layer 106 are etched until a first via hole exposing the source doped layer 101 is formed, and a conductive material is filled in the first via hole, wherein the conductive material in the first via hole is used as a bottom contact hole plug 114.
In this embodiment, the conductive material is W. In other embodiments, the material of the conductive material may also be Al, cu, ag, au, or the like.
The formation method of the gate contact plug 115 and the top contact plug 116 is similar to that of the bottom contact plug 114, and will not be described here.
As shown in fig. 15, the present invention further provides a second method for forming a semiconductor structure, which specifically includes the following steps:
the embodiments of the present invention are the same as the first embodiment, and will not be described in detail herein. The present embodiment is different from the first embodiment in that: after the gate layer 2092 is formed, ions are doped in the work function layer 2091 at a position close to the drain doped layer 212 by annealing.
The doping ions enter the work function layer 2091 by annealing, so that the activity of the ions in the work function layer 2091 is reduced, the fermi level of the work function layer 2091 tends to change at the valence band top, the fermi potential of the work function layer 2091 is increased, the inversion layer of the semiconductor structure is more difficult to generate, the threshold voltage of the semiconductor structure is increased, the longitudinal voltage loaded on the drain doping layer 212 is reduced, correspondingly, the longitudinal electric field at the drain doping layer 212 is reduced, hot carriers in the drain doping layer 212 are not easy to damage the gate structure 209, and because the ions doped by annealing are mainly concentrated at the position, close to the drain doping layer 212, in the work function layer 2091, the opening voltage at the source doping layer 201 is lower, so that the driving current of the semiconductor structure is higher, and the electrical performance of the semiconductor structure is optimized in total.
For example, when the material of the work function layer 2091 is TiAl, by doping one or both of F and H in the work function layer 2091, such that the fermi level in the work function layer 2091 tends to change toward the valence band top, the fermi potential of the work function layer 2091 increases, making the inversion layer of the semiconductor structure more difficult to generate, and increasing the threshold voltage of the semiconductor structure.
The ions doped by annealing are mainly concentrated in the work function layer 2091 near the drain doped layer 212, that is, the ion doped concentration at the drain doped layer 212 is higher than the ion doped concentration at the source doped layer 201, so that the turn-on voltage at the source doped layer 201 is lower, and the driving current of the semiconductor structure is higher.
The semiconductor structure is used for forming an NMOS transistor, and the ion doping process parameters comprise: the doping ions comprise one or more of F and H, and the ion doped reaction gas correspondingly comprises F 2 And H 2 Wherein F is one or more of 2 The flow rate is 10sccm to 800sccm, or H 2 The flow rate is 10sccm to 800sccm; the process temperature is 850-1050 ℃; the chamber pressure is 0.5 times to 10 times standard atmospheric pressure.
F in the chamber 2 Or H 2 The flow rate of (2) should not be too large or too small. If the gas flow is too small, the rate of diffusion of the F ions or H ions into the work function layer 2091 is easily caused, so that the required process time is too long, which is not beneficial to improving the formation efficiency of the semiconductor structure; if the gas flow is too large, it is easy to cause F ions or H ions to diffuse into the work function layer 2091 near the source doping layer 201, resulting in an increase in the turn-on voltage at the source doping layer 201 and a lower drive current of the semiconductor structure. In the present embodiment, F 2 The flow rate is 10sccm to 800sccm, or H 2 The flow rate is 10sccm to 800sccm.
It should be noted that the process temperature should not be too low or too high. If the process temperature is too low, the diffusion rate of ions in the work function layer 2091 is too slow, so that the required process time is too long, which is not beneficial to improving the formation efficiency of the semiconductor structure; if the process temperature is too high, the effect of enhancing ion diffusion is not significant enough, and the electrical parameters of the transistor may be deviated, thereby reducing the electrical performance of the transistor. For this reason, in the present embodiment, the process temperature is in the range of 850 degrees celsius to 1050 degrees celsius.
It should be noted that the chamber pressure should not be too high or too low. If the chamber pressure is too high, it is likely to cause F ions or H ions to diffuse into the work function layer 2091 near the source doping layer 201, resulting in an increase in the on-voltage at the source doping layer 201 and a lower drive current of the semiconductor structure. If the chamber pressure is too low, the rate of diffusion of the F ions or H ions into the work function layer 2091 is likely to result in too long a process time, which is detrimental to improving the formation efficiency of the semiconductor structure. In this embodiment, the chamber pressure is 0.5 times to 10 times the normal atmospheric pressure.
For a specific description of the semiconductor structure in this embodiment, reference may be made to the corresponding description in the first embodiment, which is not repeated here.
Correspondingly, the embodiment of the invention also provides a semiconductor structure. Referring to fig. 14, a schematic structural diagram of an embodiment of a semiconductor structure of the present invention is shown.
The semiconductor structure includes: a substrate 100; a source doped layer 101 on the substrate 100; a semiconductor pillar 102 on the source doped layer 101; a drain doped layer 112 located on top of the semiconductor pillars 102; a gate structure 109 surrounding a portion of the sidewall of the semiconductor pillar 102 and exposing the drain doped layer 112, the gate structure 109 including a work function layer 1091 covering a portion of the sidewall of the semiconductor pillar 102 and a gate layer 1092 covering the work function layer 1091; dopant ions located in the work function layer 1091 near the drain doped layer 112, the dopant ions being capable of increasing the threshold voltage of the semiconductor structure.
The voltage of the drain doped layer 112 is higher than the voltage of the source doped layer 101, so that the electric field of the drain doped layer 112 is stronger, hot carriers in the corresponding drain doped layer 112 are liable to damage the gate structure 109, the magnitude of the electric field strength is positively correlated with the voltage strength, a longitudinal electric field exists at the drain doped layer 112, the longitudinal voltage at the drain doped layer 112 is equal to the longitudinal voltage loaded on the gate structure 109 minus the threshold voltage of the semiconductor structure, the voltage at the drain doped layer 112 is reduced by doping ions in the work function layer 1091, the longitudinal electric field at the corresponding drain doped layer 112 is reduced, the reliability of the drain doped layer 112 is improved, namely the reliability of the semiconductor structure is improved, and the starting voltage at the source doped layer 101 is lower only at the position close to the drain doped layer 112, so that the driving current of the semiconductor structure is higher, and the electrical performance of the semiconductor structure is optimized.
In this embodiment, when the semiconductor structure is used to form PMOS, the doping ions include: one or more of Al, ti and Ta.
The doping ions are located in the work function layer 1091 near the position of the drain doping layer 112, so that the fermi level of the work function layer 1091 tends to change towards the conduction band bottom, the fermi potential of the work function layer 1091 increases, the inversion layer of the semiconductor structure is more difficult to generate, the threshold voltage of the semiconductor structure is increased, the longitudinal voltage loaded on the drain doping layer 112 is reduced, correspondingly, the longitudinal electric field at the drain doping layer 112 is reduced, hot carriers in the drain doping layer 112 are not easy to damage the gate structure 109, and the electrical performance of the transistor is optimized.
The dopant ions are located in the work function layer 1091 near the drain doped layer 112, that is, the ion doping concentration at the drain doped layer 112 is higher than the ion doping concentration at the source doped layer 101, so that the turn-on voltage at the source doped layer 101 is lower, so that the driving current of the semiconductor structure is higher.
The concentration of the dopant ions should not be too high or too low. If the concentration of the doping ions is too high, an inversion layer of the semiconductor structure is more difficult to generate, and the threshold voltage of the semiconductor structure is too high, so that the semiconductor structure is more difficult to turn on. If the dopant concentration is too low, the threshold voltage of the semiconductor structure is not significantly increased, and the electric field at the drain doped layer 112 cannot be reduced, resulting in the gate structure 109 being easily damaged by hot carriers. In this example, the concentration of dopant ions is 1.0E21 atoms per cubic centimeter to 1.0E24 atoms per cubic centimeter.
In other embodiments, when the semiconductor structure is used to form an NMOS, the dopant ions include: F. n, H, C and O.
The doped ions are located in the work function layer at the position close to the leakage doped layer, so that the fermi level of the work function layer tends to change at the top of the valence band, the fermi potential of the work function layer is increased, the inversion layer of the semiconductor structure is more difficult to generate, the threshold voltage of the semiconductor structure is improved, the longitudinal voltage loaded on the leakage doped layer is reduced, correspondingly, the longitudinal electric field at the leakage doped layer is reduced, hot carriers in the leakage doped layer are not easy to damage the gate structure, and the electrical performance of the transistor is optimized.
The concentration of the dopant ions is 1.0e19 atoms per cubic centimeter to 9.0E21 atoms per cubic centimeter.
The substrate 100 provides a process platform for forming semiconductor structures.
In this embodiment, the substrate 100 is a silicon substrate. In other embodiments, the material of the substrate may also be germanium, silicon carbide, gallium arsenide, or indium gallium, and the substrate may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate.
The semiconductor pillars 102 are used to form channels during operation of the semiconductor structure. In this embodiment, the semiconductor pillar 102 is a single crystal material with high purity. The material of the semiconductor pillars 102 is silicon. In other embodiments, the material of the semiconductor pillars may also be germanium, silicon carbide, gallium arsenide, or indium gallium arsenide.
The semiconductor pillars 102 are not easily too short or too tall. If the semiconductor column 102 is too short, the channel region formed later is too short, short channel effect is easy to generate, and the electrical performance of the semiconductor structure cannot be improved; if the semiconductor pillars 102 are too high, the semiconductor pillars 102 are prone to collapse, and the process of forming the semiconductor pillars 102 is too difficult. In this embodiment, the height of the semiconductor pillars 102 is 150 nm to 800 nm.
The drain doped layer 112 and the source doped layer 101 provide stress to the channel during operation of the semiconductor structure, increasing the carrier mobility. The source doped layer 101 serves as the source of the semiconductor structure and the drain doped layer 112 serves as the drain of the semiconductor structure.
In this embodiment, the semiconductor structure is used to form the PMOS (Positive Channel Metal Oxide Semiconductor) transistor, i.e., the source doped layer 101 and the drain doped layer 112 are P-type ion doped silicon germanium. In this embodiment, by doping P-type ions in silicon germanium, the P-type ions replace the positions of silicon atoms in the crystal lattice, and the more P-type ions are doped, the higher the concentration of the polynomials is, and the stronger the conductivity is. Specifically, the P-type ions include B, ga or In.
In other embodiments, semiconductor structures are used to form NMOS (Negative channel Metal Oxide Semiconductor) transistors, i.e., the source and drain doped layers are respectively silicon carbide or silicon phosphide doped with N-type ions. By doping N-type ions in silicon carbide or silicon phosphide, the N-type ions replace the positions of silicon atoms in a crystal lattice, the more N-type ions are doped, the higher the concentration of the polyions is, and the higher the conductivity is. Specifically, the N-type ions include P, as or Sb.
The gate structure 109 is used to control the opening and closing of the channel in the semiconductor pillar 102.
In this embodiment, the semiconductor structure is used to form PMOS.
Specifically, the material of the work function layer 1091 includes one or more of titanium nitride, tantalum nitride, titanium carbide, tantalum silicon nitride, titanium silicon nitride, and tantalum carbide. In other embodiments, the semiconductor structure is used to form an NMOS. Specifically, the material of the work function layer includes one or more of titanium aluminide, tantalum carbide, aluminum, or titanium carbide.
In this embodiment, the material of the gate layer 1092 is magnesium-tungsten alloy. In other embodiments, the material of the gate layer may also be W, al, cu, ag, au, pt, ni or Ti.
It should be noted that the distance between the gate structure 109 and the bottom of the drain doped layer 112 should not be too large or too small. If the distance is too large, the gate structure 109 on the semiconductor pillar 102 is too short, which is easy to cause poor effect of controlling the short channel effect of the gate structure 109, and is unfavorable for improving the electrical performance of the semiconductor structure. If the distance is too short, bridging between the gate structure 109 and the drain doped layer 112 may occur, which is detrimental to optimizing the electrical performance of the semiconductor structure. In this embodiment, the gate structure 109 is located at a distance of 6 nm to 10 nm from the bottom of the drain doped layer 112.
The semiconductor structure further includes: an interlayer dielectric layer 110 covers the sidewalls of the gate structure 109 and exposes the top surface of the gate structure 109.
The interlayer dielectric layer 110 is used for realizing electrical isolation between adjacent devices, and the material of the interlayer dielectric layer 110 is an insulating material.
In this embodiment, the material of the interlayer dielectric layer 110 is silicon oxide, and in other embodiments, the material of the interlayer dielectric layer may be another insulating material such as silicon nitride or silicon oxynitride.
The semiconductor structure further includes: a dielectric layer 113 is disposed on the interlayer dielectric layer 110, and the dielectric layer 113 covers sidewalls of the bottom contact plug 114, the gate contact plug 115, and the top contact plug 116.
The dielectric layer 113 is used to achieve electrical isolation between adjacent devices, and the material of the dielectric layer 113 is an insulating material. In this embodiment, the material of the dielectric layer 113 is silicon oxide. In other embodiments, the material of the dielectric layer may be silicon nitride or silicon oxynitride, or other insulating materials.
The semiconductor structure further includes: an isolation layer 104 is located between the gate structure 109 and the source doped layer 101, and the isolation layer 104 covers a portion of the sidewalls of the semiconductor pillars 102.
Isolation layer 104 is used to electrically isolate gate structure 109 from source doped layer 101, optimizing the electrical performance of the semiconductor structure. In this embodiment, the material of the isolation layer 104 is an insulating material.
Specifically, the material of the isolation layer 104 includes one or more of silicon oxide, silicon nitride, silicon carbonitride oxide, silicon oxynitride, boron nitride, and boron carbonitride. In this embodiment, the material of the isolation layer 104 is silicon oxide. Silicon oxide is a dielectric material with common process and low cost, has high process compatibility, and is beneficial to reducing the process difficulty and the process cost for forming the isolation layer 104; in addition, the smaller dielectric constant of silicon oxide is also beneficial to improving the function of the subsequent isolation layer 104 for isolating adjacent devices.
It should be noted that the spacer layer 104 is not too thick or too thin. If the isolation layer 104 is too thick, the gate structure 109 surrounding a portion of the sidewall of the semiconductor pillar 102 is too short, which may result in poor control of short channel effects by the gate structure 109, which is detrimental to improving the electrical performance of the semiconductor structure. If the isolation layer 104 is too thin, the distance between the gate structure 109 surrounding a portion of the sidewall of the semiconductor pillar 102 and the source doped layer 101 is too short, which is likely to cause bridging between the gate structure 109 and the source doped layer 101, and is not beneficial to optimizing the electrical performance of the semiconductor structure. In this embodiment, the thickness of the isolation layer 104 is 5 nm to 15 nm.
The semiconductor structure further includes a gate dielectric layer 108 between the gate structure 109 and the semiconductor pillar 102 and between the gate structure 109 and the spacer 104.
The gate dielectric layer 108 is used to electrically isolate the gate structure 109 from the semiconductor pillars 102.
In this embodiment, the gate structure 109 is a metal gate structure, so the material of the gate dielectric layer 108 includes HfO 2 、ZrO 2 HfSiO, hfSiON, hfTaO, hfTiO, hfZrO and Al 2 O 3 One or more of them. In other embodiments, when the gate structure is a polysilicon gate structure, the gate dielectric layer may be made of one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride oxide, and amorphous carbon.
The semiconductor structure further includes a protective layer 106 between the isolation layer 104 and the semiconductor pillars 102 and between the isolation layer 104 and the source doped layer 101.
The material of the protection layer 106 is a dielectric material. And the materials of the isolation layer 104 and the protection layer 106 are different, and the isolation layer 104 and the protection layer 106 have etching selectivity. Specifically, the material of the protective layer 106 includes one or more of silicon oxide, silicon nitride, silicon carbonitride oxide, silicon oxynitride, boron nitride, and boron carbonitride. In this embodiment, the material of the protection layer 106 is silicon oxide.
It should be noted that the protective layer 106 should not be too thick or too thin. If the protective layer 106 is too thick, the process time for forming the protective layer 106 is too long, and the gate structure 109 is too short, which is detrimental to improving the electrical performance of the semiconductor structure, and the effect of controlling the short channel effect of the gate structure 109 is not good. If the protective layer 106 is too thin, the bottom surface of the semiconductor pillar 102 is easily oxidized during the process of forming the isolation layer 104, resulting in poor uniformity of the semiconductor pillar 102, which cannot well improve the electrical performance of the semiconductor structure. In this embodiment, the thickness of the protective layer 106 is 3 nm to 8 nm.
The semiconductor structure further includes: a bottom contact plug 114 penetrating the protective layer 106, the isolation layer 104, the gate dielectric layer 108, the interlayer dielectric layer 110, and the dielectric layer 113 and connected to the source doped layer 101; a gate contact plug 115 penetrating the interlayer dielectric layer 110 and the dielectric layer 113 and connected to the gate structure 109; a top contact plug 116 penetrates the dielectric layer 113 and is connected to the drain doped layer 112.
The bottom contact plug 114, the gate contact plug 115, and the top contact plug 116 are used to make electrical connection between the semiconductor structure and the semiconductor structure in addition to making electrical connection within the semiconductor structure. In this embodiment, the conductive material is W. In other embodiments, the material of the conductive material may also be Al, cu, ag, au, or the like.
The semiconductor structure may be formed by the forming method described in the foregoing embodiments, or may be formed by other forming methods. For a specific description of the semiconductor structure in this embodiment, reference may be made to the corresponding description in the foregoing embodiment, which is not repeated here.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.

Claims (21)

1. A method of forming a semiconductor structure, comprising:
providing a substrate;
forming a source doping layer on the substrate, wherein the source doping layer is used as a source electrode;
forming a semiconductor column on the source doped layer;
forming a drain doping layer at the top end of the semiconductor column, wherein the drain doping layer is used as a drain electrode;
forming a gate structure surrounding a portion of the sidewall of the semiconductor pillar and exposing the drain doped layer, the gate structure including a work function layer covering the semiconductor pillar portion sidewall and a gate layer covering the work function layer;
after forming the gate structure exposing the drain doped layer, doping ions capable of increasing the threshold voltage of the semiconductor structure are doped in the work function layer at a position close to the drain doped layer.
2. The method of forming a semiconductor structure of claim 1, wherein ions are doped in said work function layer by means of ion implantation after forming said gate structure.
3. The method of forming a semiconductor structure of claim 1 or 2, wherein when the semiconductor structure is used to form an NMOS, the process parameters of doping include: the dopant ions include one or more of F, N, H, C and O; the implantation dosage is 1.0E14 atoms per square centimeter to 9.0E16 atoms per square centimeter, the implantation energy is 0.5Kev to 10Kev, and the included angle between the direction of ion implantation and the normal line of the substrate is 7 degrees to 25 degrees;
alternatively, when the semiconductor structure is used to form PMOS, the process parameters of doping include: the doping ions comprise one or more of Al, ti and Ta; the implantation dose is 1.0E16 atoms per square centimeter to 1.0E19 atoms per square centimeter, the implantation energy is 0.8Kev to 12Kev, and the included angle between the direction of ion implantation and the normal line of the substrate is 7 degrees to 25 degrees.
4. The method of forming a semiconductor structure of claim 1, wherein ions are doped in the work function layer by way of annealing after forming the work function layer.
5. The method of forming a semiconductor structure of claim 4, wherein when the semiconductor structure is used to form an NMOS, the process parameters of doping include: the dopant ions include one or more of F and H; f (F) 2 The flow rate is 10sccm to 800sccm, or H 2 The flow rate is 10sccm to 800sccm; the process temperature is 850-1050 ℃; the chamber pressure is 0.5 times to 10 times standard atmospheric pressure.
6. The method of forming a semiconductor structure of claim 1, further comprising, after forming the semiconductor pillar: and forming an isolation layer on the source doping layer exposed by the semiconductor column, wherein the isolation layer covers part of the side wall of the semiconductor column.
7. The method of forming a semiconductor structure of claim 6, wherein the spacer layer has a thickness of 5 nm to 15 nm.
8. The method of forming a semiconductor structure of claim 6, wherein the step of forming an isolation layer comprises:
forming an isolation material layer covering the semiconductor column;
and etching back a part of the isolating material layer, and forming the isolating layer on the source doping layer exposed out of the semiconductor column.
9. The method of forming a semiconductor structure of claim 8, wherein a mask layer is formed on the semiconductor pillars;
The step of forming the drain doped layer comprises the following steps: after the isolation material layer is formed, before the isolation layer is formed, a planarization process is adopted to remove the isolation material layer higher than the mask layer; removing the mask layer exposed by the isolation material layer to form an isolation layer groove surrounded by the isolation material layer and the semiconductor column;
and forming the leakage doping layer in the isolation layer groove.
10. The method of forming a semiconductor structure of claim 8, wherein the step of forming the drain doped layer comprises: removing the isolation material layer higher than the semiconductor column by adopting a planarization process after the isolation material layer is formed and before the isolation layer is formed; and carrying out ion doping on the semiconductor column to form the leakage doped layer.
11. The method of forming a semiconductor structure of claim 1, wherein the step of forming a gate structure comprises:
conformally covering a gate material structure on the semiconductor column and the source doped layer exposed by the semiconductor column;
forming an interlayer dielectric layer covering part of the side wall of the semiconductor column after forming the gate material structure; and removing the gate material structure higher than the interlayer dielectric layer to form a gate structure covering the side wall of the semiconductor column part.
12. The method of forming a semiconductor structure of claim 11, wherein a mask layer is formed on the semiconductor pillar, the step of forming the interlayer dielectric layer comprising: forming an interlayer dielectric material layer covering the gate material structure;
the step of forming the drain doped layer comprises the following steps: removing the interlayer dielectric material layer and the grid electrode material structure which are higher than the mask layer by adopting planarization process; removing the mask layer exposed from the interlayer dielectric material layer to form a groove surrounded by the grid material structure and the semiconductor column; and forming a leakage doping layer in the groove.
13. The method of forming a semiconductor structure of claim 12, the step of forming the drain doped layer comprising: removing the interlayer dielectric material layer higher than the semiconductor column by adopting a planarization process; and carrying out ion doping on the semiconductor column to form a leakage doping layer.
14. The method of claim 1, wherein the gate structure is spaced from the bottom of the drain doped layer by a distance of 6 nm to 10 nm.
15. The method of forming a semiconductor structure of claim 8, further comprising, after forming the semiconductor pillars, prior to forming the isolation material layer: conformally covering a protective material layer on the semiconductor pillars and the source doped layer exposed by the semiconductor pillars;
The method for forming the semiconductor structure further comprises the following steps: and after the isolation layer is formed, removing the protection material layer exposed by the isolation layer before forming the source doping layer, and forming a protection layer between the semiconductor column and the isolation layer and between the source doping layer and the isolation layer.
16. A semiconductor structure, comprising:
a substrate;
the source doping layer is positioned on the substrate and is used as a source electrode;
a semiconductor pillar located on the source doped layer;
the drain doping layer is positioned at the top end of the semiconductor column and is used as a drain electrode;
a gate structure surrounding a portion of the sidewall of the semiconductor pillar and exposing the drain doped layer, the gate structure including a work function layer covering the semiconductor pillar portion sidewall and a gate layer covering the work function layer;
and the doping ions are positioned in the work function layer at a position close to the leakage doping layer, and can increase the threshold voltage of the semiconductor structure.
17. The semiconductor structure of claim 16, further comprising an isolation layer between the gate structure and the source doped layer, the isolation layer covering a portion of sidewalls of the semiconductor pillar.
18. The semiconductor structure of claim 17, wherein the spacer layer has a thickness of 5 nm to 15 nm.
19. The semiconductor structure of claim 17, further comprising a protective layer between the isolation layer and the semiconductor pillar and between the isolation layer and the source doped layer.
20. The semiconductor structure of claim 16, wherein the gate structure is a distance of 6 nm to 10 nm from a bottom of the drain doped layer.
21. The semiconductor structure of claim 16, wherein,
when the semiconductor structure is used to form an NMOS, the dopant ions include: F. n, H, C and O; the concentration of the doping ions is 1.0E19 atoms per cubic centimeter to 9.0E21 atoms per cubic centimeter;
alternatively, when the semiconductor structure is used to form PMOS, the dopant ions include: one or more of Al, ti and Ta; the concentration of the dopant ions is 1.0E21 atoms per cubic centimeter to 1.0E24 atoms per cubic centimeter.
CN201910153187.1A 2019-02-28 2019-02-28 Semiconductor structure and forming method thereof Active CN111627819B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201910153187.1A CN111627819B (en) 2019-02-28 2019-02-28 Semiconductor structure and forming method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201910153187.1A CN111627819B (en) 2019-02-28 2019-02-28 Semiconductor structure and forming method thereof

Publications (2)

Publication Number Publication Date
CN111627819A CN111627819A (en) 2020-09-04
CN111627819B true CN111627819B (en) 2023-10-17

Family

ID=72259644

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201910153187.1A Active CN111627819B (en) 2019-02-28 2019-02-28 Semiconductor structure and forming method thereof

Country Status (1)

Country Link
CN (1) CN111627819B (en)

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104009082A (en) * 2013-02-27 2014-08-27 爱思开海力士有限公司 Transistor, resistance variable memory device including the same, and manufacturing method thereof
CN105826265A (en) * 2015-01-09 2016-08-03 中芯国际集成电路制造(上海)有限公司 Method for forming semiconductor device
CN105870020A (en) * 2015-01-23 2016-08-17 中国科学院微电子研究所 Semiconductor device and forming method thereof
CN108206209A (en) * 2016-12-16 2018-06-26 爱思开海力士有限公司 Semiconductor devices and its manufacturing method with buried gate structure
US10170577B1 (en) * 2017-12-04 2019-01-01 International Business Machines Corporation Vertical transport FETs having a gradient threshold voltage
CN109148290A (en) * 2017-06-28 2019-01-04 中芯国际集成电路制造(上海)有限公司 The manufacturing method of semiconductor device

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9385195B1 (en) * 2015-03-31 2016-07-05 Stmicroelectronics, Inc. Vertical gate-all-around TFET
US9934977B1 (en) * 2017-01-27 2018-04-03 International Business Machines Corporation Salicide bottom contacts

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104009082A (en) * 2013-02-27 2014-08-27 爱思开海力士有限公司 Transistor, resistance variable memory device including the same, and manufacturing method thereof
CN105826265A (en) * 2015-01-09 2016-08-03 中芯国际集成电路制造(上海)有限公司 Method for forming semiconductor device
CN105870020A (en) * 2015-01-23 2016-08-17 中国科学院微电子研究所 Semiconductor device and forming method thereof
CN108206209A (en) * 2016-12-16 2018-06-26 爱思开海力士有限公司 Semiconductor devices and its manufacturing method with buried gate structure
CN109148290A (en) * 2017-06-28 2019-01-04 中芯国际集成电路制造(上海)有限公司 The manufacturing method of semiconductor device
US10170577B1 (en) * 2017-12-04 2019-01-01 International Business Machines Corporation Vertical transport FETs having a gradient threshold voltage

Also Published As

Publication number Publication date
CN111627819A (en) 2020-09-04

Similar Documents

Publication Publication Date Title
CN107863299B (en) FinFET and manufacturing method thereof
CN110265301B (en) Semiconductor structure and forming method thereof
TWI713771B (en) Forming of semiconductor device
CN108878521B (en) Vertical tunneling field effect transistor and forming method thereof
CN108573910B (en) Semiconductor structure and forming method thereof
CN112151377B (en) Semiconductor structure and forming method thereof
CN109920733B (en) Semiconductor structure and transistor forming method
CN111613581A (en) Semiconductor structure and forming method thereof
CN112713088B (en) Semiconductor structure and forming method thereof
CN111627819B (en) Semiconductor structure and forming method thereof
US11450743B2 (en) Method of forming a semiconductor device with implantation of impurities at high temperature
CN112151605B (en) Semiconductor structure and forming method thereof
CN112786451B (en) Semiconductor structure and forming method thereof
CN112309845B (en) Semiconductor structure and forming method thereof
CN112447593B (en) Semiconductor structure and forming method thereof
CN108807266B (en) Semiconductor structure and forming method thereof
CN113113307B (en) Semiconductor structure and forming method thereof
CN113838752B (en) Semiconductor structure and forming method thereof
CN112310198B (en) Semiconductor structure and forming method thereof
CN111627814A (en) Semiconductor structure and forming method thereof
CN111627854B (en) Semiconductor structure and forming method thereof
CN112151595B (en) Semiconductor structure and forming method thereof
CN112151606B (en) Semiconductor structure and forming method thereof
CN113451133B (en) Semiconductor structure and forming method thereof
CN112103249B (en) Semiconductor structure and forming method thereof

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant