CN112151595A - Semiconductor structure and forming method thereof - Google Patents

Semiconductor structure and forming method thereof Download PDF

Info

Publication number
CN112151595A
CN112151595A CN201910579439.7A CN201910579439A CN112151595A CN 112151595 A CN112151595 A CN 112151595A CN 201910579439 A CN201910579439 A CN 201910579439A CN 112151595 A CN112151595 A CN 112151595A
Authority
CN
China
Prior art keywords
semiconductor
layer
forming
semiconductor pillar
pillar
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201910579439.7A
Other languages
Chinese (zh)
Other versions
CN112151595B (en
Inventor
周飞
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
Original Assignee
Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Semiconductor Manufacturing International Shanghai Corp, Semiconductor Manufacturing International Beijing Corp filed Critical Semiconductor Manufacturing International Shanghai Corp
Priority to CN201910579439.7A priority Critical patent/CN112151595B/en
Publication of CN112151595A publication Critical patent/CN112151595A/en
Application granted granted Critical
Publication of CN112151595B publication Critical patent/CN112151595B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H01L29/0688—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions characterised by the particular shape of a junction between semiconductor regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

A semiconductor structure and a forming method thereof are provided, wherein the forming method comprises the following steps: forming a base, wherein the base comprises a substrate, a source doping layer located on the substrate and a semiconductor column protruding out of the source doping layer, the semiconductor column is of a T-shaped structure and comprises a first semiconductor column and a second semiconductor column located on the first semiconductor column, and the width of the second semiconductor column is larger than that of the first semiconductor column; forming a gate structure surrounding a portion of a sidewall of the first semiconductor pillar, the gate structure exposing the second semiconductor pillar; and forming a drain doping layer on the top of the second semiconductor pillar. The embodiment of the invention is beneficial to improving the performance of the semiconductor structure.

Description

Semiconductor structure and forming method thereof
Technical Field
Embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular, to a semiconductor structure and a method for forming the same.
Background
With the rapid development of semiconductor manufacturing technology, semiconductor devices are moving toward higher element density and higher integration, and the trend of semiconductor process nodes following moore's law is decreasing. Transistors are currently being widely used as the most basic semiconductor devices, and therefore, as the element density and integration of semiconductor devices increase, the channel length of transistors has to be shortened in order to accommodate the reduction of process nodes.
The shortening of the channel length of the transistor has the advantages of increasing the die density of the chip, increasing the switching speed, and the like. However, as the channel length is shortened, the distance between the source and the drain of the transistor is also shortened, and the controllability of the gate to the channel is deteriorated, so that a sub-threshold leakage (SCE) phenomenon, that is, a so-called short-channel effect (short-channel leakage) is more likely to occur, and the channel leakage of the transistor is increased.
Therefore, in order to better accommodate the scaling requirements of device dimensions, semiconductor processes are gradually starting to transition from planar transistors to more power efficient three-dimensional transistors, such as Gate-all-around (GAA) transistors. In the all-around gate transistor, the gate surrounds the region where the channel is located from the periphery, and compared with a planar transistor, the all-around gate transistor has stronger control capability on the channel, and can better inhibit a short-channel effect. The fully-wrapped Gate transistor includes a transverse Gate-all-around (LGAA) transistor and a Vertical Gate-all-around (VGAA) transistor, in which a channel of the VGAA extends in a direction perpendicular to a surface of the substrate, which is advantageous for improving an area utilization efficiency of the semiconductor structure, and thus is advantageous for further realizing a reduction in feature size.
Disclosure of Invention
Embodiments of the present invention provide a semiconductor structure and a method for forming the same, so as to improve the performance of the semiconductor structure.
To solve the above problems, an embodiment of the present invention provides a method for forming a semiconductor structure, including: forming a base, wherein the base comprises a substrate, a source doping layer located on the substrate and a semiconductor column protruding out of the source doping layer, the semiconductor column is of a T-shaped structure and comprises a first semiconductor column and a second semiconductor column located on the first semiconductor column, and the width of the second semiconductor column is larger than that of the first semiconductor column; forming a gate structure surrounding a portion of a sidewall of the first semiconductor pillar, the gate structure exposing the second semiconductor pillar; and forming a drain doping layer on the top of the second semiconductor pillar.
Correspondingly, an embodiment of the present invention further provides a semiconductor structure, including: a substrate; the source doping layer is positioned on the substrate; the semiconductor pillar protrudes out of the source doping layer, is of a T-shaped structure and comprises a first semiconductor pillar and a second semiconductor pillar located on the first semiconductor pillar, and the width of the second semiconductor pillar is larger than that of the first semiconductor pillar; a gate structure surrounding a portion of a sidewall of the first semiconductor pillar, the gate structure exposing the second semiconductor pillar; and the drain doping layer is positioned at the top of the second semiconductor pillar.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following advantages:
the semiconductor pillar formed in the embodiment of the invention is a T-shaped structure, the semiconductor pillar comprises a first semiconductor pillar and a second semiconductor pillar positioned on the first semiconductor pillar, the width of the second semiconductor pillar is larger than that of the first semiconductor pillar, therefore, the width of the second semiconductor pillar is larger along the direction vertical to the side wall of the semiconductor pillar, and the area of the drain doping layer is correspondingly increased after the drain doping layer is formed on the top of the second semiconductor pillar subsequently, in the subsequent process of forming the contact hole plug electrically connected with the drain doping layer, the contact performance of the contact hole plug and the drain doping layer is improved, in addition, the contact resistance of the contact hole plug and the drain doping layer can be reduced by increasing the contact area of the contact hole plug and the drain doping layer; in summary, the embodiment of the invention improves the performance of the semiconductor structure by forming the semiconductor pillar with the T-shaped structure.
Drawings
FIG. 1 is a schematic diagram of a semiconductor structure;
fig. 2 to 14 are schematic structural diagrams corresponding to steps in an embodiment of a method for forming a semiconductor structure of the present invention.
Detailed Description
The devices formed at present still have the problem of poor performance. The reason for poor device performance is analyzed in combination with a schematic structure diagram of a semiconductor structure.
Referring to fig. 1, a schematic diagram of a semiconductor structure is shown.
The semiconductor structure includes: a substrate 1; a source doping layer 2 located on the substrate 1; the semiconductor column 3 protrudes out of the source doping layer 2; a drain doping layer 4 positioned on the top of the semiconductor pillar 3; and a gate structure 5 surrounding a portion of the sidewall of the semiconductor pillar 3 and exposing the drain doping layer 4.
In the semiconductor structure, the drain doping layer 4 is positioned at the top of the semiconductor pillar 3. In the semiconductor field, the width dimension of the semiconductor pillar 3 is generally smaller, because the dimension of the drain doping layer 4 is limited by the width dimension of the semiconductor pillar 3, the width dimension of the drain doping layer 4 is generally smaller, when a contact hole plug electrically connected with the drain doping layer 4 is formed subsequently, the difficulty of the process for forming the contact hole plug is greater, the contact performance of the contact hole plug and the drain doping layer 4 is easily reduced, meanwhile, the contact area of the contact hole plug and the drain doping layer 4 is smaller, and the contact resistance of the contact hole plug and the drain doping layer 4 is also greater, so that the performance of the formed semiconductor structure is poor.
In order to solve the technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, including: forming a base, wherein the base comprises a substrate, a source doping layer located on the substrate and a semiconductor column protruding out of the source doping layer, the semiconductor column is of a T-shaped structure and comprises a first semiconductor column and a second semiconductor column located on the first semiconductor column, and the width of the second semiconductor column is larger than that of the first semiconductor column; forming a gate structure surrounding a portion of a sidewall of the first semiconductor pillar, the gate structure exposing the second semiconductor pillar; and forming a drain doping layer on the top of the second semiconductor pillar.
The semiconductor pillar formed in the embodiment of the invention is a T-shaped structure, the semiconductor pillar comprises a first semiconductor pillar and a second semiconductor pillar positioned on the first semiconductor pillar, the width of the second semiconductor pillar is larger than that of the first semiconductor pillar, therefore, the width of the second semiconductor pillar is larger along the direction vertical to the side wall of the semiconductor pillar, and the area of the drain doping layer is correspondingly increased after the drain doping layer is formed on the top of the second semiconductor pillar subsequently, in the subsequent process of forming the contact hole plug electrically connected with the drain doping layer, the contact performance of the contact hole plug and the drain doping layer is improved, in addition, the contact resistance of the contact hole plug and the drain doping layer can be reduced by increasing the contact area of the contact hole plug and the drain doping layer; in summary, the embodiment of the invention improves the performance of the semiconductor structure by forming the semiconductor pillar with the T-shaped structure.
In order to make the aforementioned objects, features and advantages of the embodiments of the present invention comprehensible, specific embodiments accompanied with figures are described in detail below.
Fig. 2 to 14 are schematic structural diagrams corresponding to steps in an embodiment of a method for forming a semiconductor structure of the present invention.
Referring to fig. 2 to 7, a base (not labeled) is formed, the base includes a substrate 100, a source doped layer 105 located on the substrate 100, and a semiconductor pillar 110 (as shown in fig. 7) protruding from the source doped layer 105, the semiconductor pillar 110 is a T-shaped structure, the semiconductor pillar 110 includes a first semiconductor pillar 10 (as shown in fig. 7) and a second semiconductor pillar 11 (as shown in fig. 7) located on the first semiconductor pillar 10, and a width of the second semiconductor pillar 11 is greater than a width of the first semiconductor pillar 10.
The substrate provides a process platform for subsequent process.
In this embodiment, the substrate 100 is a silicon substrate. In other embodiments, the substrate material can also be germanium, silicon carbide, gallium arsenide, or indium gallium, and the substrate can also be a silicon-on-insulator substrate or a germanium-on-insulator substrate.
When a pmos (positive Channel Metal Oxide semiconductor) transistor is formed, the material of the source doping layer 105 is silicon germanium doped with P-type ions. By doping the P-type ions in the silicon germanium, the P-type ions replace the positions of silicon atoms in the crystal lattice, and the more the P-type ions are doped, the higher the concentration of the majority ions is, and the stronger the conductivity is. Specifically, the P-type ions include B, Ga or In.
When an nmos (negative channel Metal Oxide semiconductor) transistor is formed, the material of the source doping layer 105 is silicon carbide or silicon phosphide doped with N-type ions. By doping N-type ions in silicon carbide or silicon phosphide, the N-type ions are used for replacing the positions of silicon atoms in crystal lattices, and the more N-type ions are doped, the higher the concentration of majority ions is, and the stronger the conductivity is. Specifically, the N-type ions include P, As or Sb.
In this embodiment, a first epitaxial layer (not shown) is formed by an epitaxial growth method, and ions are doped in situ during the formation of the first epitaxial layer to form the source doping layer 105. In other embodiments, after the in-situ self-doping is performed in the process of forming the first epitaxial layer, the ion doping may be performed on the first epitaxial layer continuously in an ion implantation manner to form the source doping layer. The doping ions can achieve the effect of improving the carrier mobility of the transistor. In other embodiments, the first epitaxial layer may be ion-doped only by ion implantation.
In this embodiment, the formed semiconductor pillar 110 has a T-shaped structure, the semiconductor pillar 110 includes a first semiconductor pillar 10 and a second semiconductor pillar 11 located on the first semiconductor pillar 10, and a width of the second semiconductor pillar 11 is greater than a width of the first semiconductor pillar 10.
The semiconductor pillar 110 is used to provide a process platform for forming a gate structure and a drain doping layer. The first semiconductor pillar 10 is used for subsequently providing a channel region of a MOS device during operation, and the second semiconductor pillar 11 is used for providing a process foundation for subsequently forming a drain doping layer.
In this embodiment, the material of the semiconductor pillar 110 is silicon. In other embodiments, the material of the semiconductor pillar may also be germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, according to actual requirements.
When forming a PMOS transistor, the semiconductor pillar 110 is doped with N-type ions, wherein the N-type ions may be P ions, As ions, or Sb ions; when forming an NMOS transistor, the semiconductor pillar 110 is doped with P-type ions, wherein the P-type ions may be B ions, Ga ions, or In ions.
Along the direction perpendicular to the side wall of the semiconductor pillar 110, the width of the second semiconductor pillar 11 is larger, the area of the drain doping layer is correspondingly increased after the drain doping layer is formed at the top of the second semiconductor pillar 11, and the contact performance of the contact hole plug and the drain doping layer is favorably improved in the subsequent process of forming the contact hole plug electrically connected with the drain doping layer; in summary, the performance of the semiconductor structure is improved by forming the semiconductor pillar with the T-shaped structure in the embodiment.
The ratio of the height of the second semiconductor pillar 11 to the total height of the semiconductor pillar 110 should not be too small or too large. If the ratio of the height of the second semiconductor pillar 11 to the total height of the semiconductor pillar 110 is too small, the volume of a drain doping layer formed at the top of the second semiconductor pillar 11 is too small, which may affect the carrier mobility of the device; if the ratio of the height of the second semiconductor pillar 11 to the total height of the semiconductor pillar 110 is too large, the height of the first semiconductor pillar 10 is too small while the total height of the semiconductor pillar 110 is not changed, which easily results in too little material of the first semiconductor pillar 10 for providing a channel region, and easily affects the effective channel length of the device. For this reason, in the present embodiment, the height of the second semiconductor pillar 11 is one fifth to one third of the total height of the semiconductor pillar 110.
Specifically, in this embodiment, the height of the second semiconductor pillar 11 is 3 nm to 8 nm, so that the contact performance of the subsequent drain doping layer and the contact hole plug can be significantly improved, and the performance of the semiconductor structure can be improved.
The width of the second semiconductor pillar 11 is not too small nor too large in a direction perpendicular to the sidewalls of the semiconductor pillar 110. If the width of the second semiconductor pillar 11 is too small, the width of the drain doping layer is too small after the drain doping layer is formed on the top of the second semiconductor pillar 11, so that the contact performance between the drain doping layer and the subsequent contact hole plug is difficult to improve; if the width of the second semiconductor pillars 11 is too large, the distance between adjacent second semiconductor pillars 11 is too close, and even a short circuit occurs between adjacent second semiconductor pillars 11, which may cause a leakage current. For this reason, in the present embodiment, the width of the second semiconductor pillar 11 is 1.5 times to 3 times the width of the first semiconductor pillar 10.
Specifically, in this embodiment, the width of the second semiconductor pillar 11 is 8 nm to 20 nm, so that the effect of the second semiconductor pillar 11 for improving the contact performance between the subsequent drain doping layer and the contact hole plug is more significant, and the reliability of the semiconductor structure is improved.
In this embodiment, the step of forming the semiconductor pillar 110 includes:
referring to fig. 2 to 6, a protection layer 102 is formed on the source doping layer 105 (as shown in fig. 6), a groove 300 is formed in the protection layer 102 (as shown in fig. 6), the cross section of the groove 300 is T-shaped, the groove 300 includes a bottom groove 210 (as shown in fig. 6) and a top groove 220 (as shown in fig. 6) located on the bottom groove 210, the opening width of the top groove 220 is greater than that of the bottom groove 210, and the top of the bottom groove 210 is communicated with the bottom of the top groove 220.
The protective layer 102 is used to provide a process platform for forming the recess 300.
In order to reduce the influence of the protective layer 102 on the semiconductor structure, the material of the protective layer 102 is silicon oxide, silicon nitride, silicon oxynitride, boron nitride, or silicon oxycarbonitride. The materials are all insulating materials, and have small influence on the performance of the semiconductor structure. In this embodiment, the material of the protection layer 102 is silicon oxide. Silicon oxide is a commonly used insulating material in a semiconductor process, and the process compatibility is high.
The recess 300 is used to provide a spatial location for the formation of a semiconductor pillar, and the recess 300 is also used to define the formation area and shape of the semiconductor pillar.
Specifically, the step of forming the groove 300 includes:
as shown in fig. 2, an initial protection layer 101 is formed on the source doping layer 105; as shown in fig. 3, an initial groove 200 exposing the source doping layer 105 is formed in the initial protective layer 101.
The initial recess 200 is used for the subsequent formation of the recess 300.
Specifically, a portion of the initial groove 200 on a side close to the source doping layer 105 serves as a bottom groove. Therefore, the width of the initial groove 200 is equal to the width of the bottom groove.
In this embodiment, the initial protection layer 101 is etched by a dry etching process to form the initial groove 200. The dry etching process has the characteristic of anisotropic etching, and the profile controllability is good, so that the profile of the groove 200 can meet the process requirements.
As shown in fig. 4, a filling layer 103 is formed in the initial recess 200, and the top of the filling layer 103 is lower than the top of the initial protection layer 101.
The top of the filling layer 103 is lower than the top of the initial protection layer 101, so as to provide a process base for the subsequent etching of the sidewall of the initial groove 200 exposed by the filling layer 103.
In order to reduce the difficulty of forming and removing the filling layer 103 and reduce the influence of the filling layer 103 on the semiconductor structure, the filling layer 103 is made of a material which is easy to form and remove.
For this purpose, the material of the filling layer 103 is a BARC (Bottom-antireflective Coating) material, an ODL (organic Dielectric layer) material, a SOC (spin-on carbon) material, a photoresist, a DARC (Dielectric-antireflective Coating) material, or a DUO (deep UV light absorbing oxide) material. In this embodiment, the material of the filling layer 103 is a BARC material.
In this embodiment, the step of forming the filling layer 103 includes: forming a filling material layer (not shown) filled in the initial groove 200, wherein the filling material layer also covers the top of the initial protection layer 101; and removing part of the thickness of the filling material layer on the top of the initial protection layer 101 and in the initial groove 200, and using the remaining filling material layer as the filling layer 103.
As shown in fig. 5, the sidewalls of the initial recess 200 exposed by the filling layer 103 are etched along a direction perpendicular to the sidewalls of the initial recess 200 to form the top recess 220, and the initial protection layer 101 is left as the protection layer 102.
In this embodiment, an isotropic etching process is used to etch the sidewall of the initial groove 200 exposed by the filling layer 103. By adopting the isotropic etching process, the sidewall of the initial groove 200 exposed by the filling layer 103 can be etched in a direction perpendicular to the sidewall of the initial groove 200, so that the opening width of the top groove 220 is greater than the opening width of the initial groove 200.
In the isotropic etching process, the initial protection layer 101 is also etched along a normal direction of the surface of the substrate 100. The thickness of the initial protection layer 101 is larger along the normal direction of the surface of the substrate 100, so that after the isotropic etching process is performed, the top of the filling layer 103 is still lower than the top of the initial protection layer 101, so that the top groove 220 can be formed.
In this embodiment, the sidewall of the initial groove 220 exposed by the filling layer 103 may be etched by using a SiCoNi process.
The SiCoNi process is used as a low-strength high-precision chemical etching method, and generally comprises the following steps: firstly, generating etching gas; etching the material layer to be etched by the etching gas to form a byproduct; carrying out an annealing process to sublimate and decompose the by-product into a gaseous product; and removing the gaseous product by air suction. In this embodiment, the etching gas of the SiCoNi process includes a fluorocarbon-based gas and a hydrogen-containing fluorocarbon-based gas.
The SiCoNi process is favorable for accurately controlling the etching amount of the side wall of the initial groove 220, so that the width of the subsequent second semiconductor column is accurately controlled.
In other embodiments, a hydrofluoric acid solution may also be used to etch the exposed sidewalls of the initial trench. The adoption of the hydrofluoric acid solution is easy to realize isotropic etching, and the hydrofluoric acid solution is a solution commonly used for etching silicon oxide materials in a semiconductor process, so that the process cost is low and the process compatibility is high.
As shown in fig. 6, the filling layer 103 is removed (as shown in fig. 5), and the remaining initial groove 200 penetrating the top groove 220 is used as the bottom groove 210.
In this embodiment, the material of the filling layer 103 is a BARC material, and the filling layer 103 can be removed by an ashing process.
Referring to fig. 7, the semiconductor pillar 110 is formed in the recess 300, wherein a portion of the semiconductor pillar 110 located in the bottom recess 210 serves as the first semiconductor pillar 10, a portion of the semiconductor pillar 110 located in the top recess 220 serves as the second semiconductor pillar 11, and a width of the second semiconductor pillar 11 is greater than a width of the first semiconductor pillar 10.
Specifically, the semiconductor pillars 110 are formed in the recesses 300 using an epitaxial process, thereby improving the formation quality of the semiconductor pillars 110.
Referring to fig. 8, a drain doping layer 125 is formed on the top of the second semiconductor pillars 11 (shown in fig. 7).
Along the direction perpendicular to the sidewall of the semiconductor pillar 110, the width of the second semiconductor pillar 11 is larger, and in this embodiment, after the drain doping layer 125 is formed at the top of the second semiconductor pillar 11, the area of the drain doping layer 125 is correspondingly increased, so that in the subsequent process of forming a contact hole plug electrically connected to the drain doping layer 125, the requirement for alignment shift (overlay shift) of the process of forming the contact hole plug is favorably reduced, the process difficulty of forming the contact hole plug is correspondingly reduced, the process window is increased, and meanwhile, the contact performance of the contact hole plug and the drain doping layer 125 is favorably improved, and in this embodiment, the contact resistance between the contact hole plug and the drain doping layer 125 can be reduced by increasing the contact area between the contact hole plug and the drain doping layer 125; in summary, the performance of the semiconductor structure is improved by forming the second semiconductor pillars 11 with a larger width.
The drain doping layer 125 and the source doping layer 105 are the same in doping ion type and material.
When a PMOS transistor is formed, the material of the drain doping layer 125 is silicon germanium doped with P-type ions. By doping the P-type ions in the silicon germanium, the P-type ions replace the positions of silicon atoms in the crystal lattice, and the more the P-type ions are doped, the higher the concentration of the majority ions is, and the stronger the conductivity is. Specifically, the P-type ions include B, Ga or In.
When forming an NMOS transistor, the material of the drain doping layer 125 is silicon carbide or silicon phosphide doped with N-type ions, respectively. By doping N-type ions in silicon carbide or silicon phosphide, the N-type ions are used for replacing the positions of silicon atoms in crystal lattices, and the more N-type ions are doped, the higher the concentration of majority ions is, and the stronger the conductivity is. Specifically, the N-type ions include P, As or Sb.
In this embodiment, the step of forming the drain doping layer 125 includes: the second semiconductor pillar 11 (shown in fig. 7) exposed by the protection layer 102 is subjected to ion doping treatment, and a portion of the second semiconductor pillar 11 doped with ions is used as the drain doping layer 125.
In this embodiment, the second semiconductor pillar 11 exposed by the protection layer 102 is subjected to ion doping treatment to form the drain doping layer 125, and an additional step of forming a mask layer is not required, which is beneficial to simplifying process steps and improving process integration; in addition, in the present embodiment, the drain doping layer 125 is formed before the gate structure is formed, so that in the subsequent step of forming the gate dielectric layer, the step of removing the gate dielectric layer surrounding the second semiconductor pillar 11 is not required, which is also beneficial to simplifying the process flow and reducing the process difficulty.
In other embodiments, an epitaxial layer may be formed on the top of the second semiconductor pillar exposed by the protection layer by using an epitaxial process, and the drain doping layer may be formed in situ from doping ions during the formation of the epitaxial layer.
The present embodiment takes the formation of the drain doping layer 125 before the formation of the gate structure as an example. In other embodiments, a drain doped layer may also be formed on top of the second semiconductor pillar after the gate structure is formed.
Referring to fig. 9 in combination, in this embodiment, after the semiconductor pillar 110 (shown in fig. 7) is formed, the method further includes: a portion of the thickness of the protective layer 102 is etched back, and the remaining protective layer 102 serves as an isolation layer 106.
Specifically, after the drain doping layer 125 is formed on the top of the second semiconductor pillar 11, the isolation layer 106 is formed.
A gate structure is subsequently formed on the isolation layer 106, and the isolation layer 106 is used for isolating the gate structure from the source doping layer 105.
The isolation layer 106 is formed by etching back the protection layer 102 with a certain thickness, which is beneficial to saving the process flow and having high process integration degree.
In this embodiment, a dry etching process is used to etch back the protective layer 102 with a certain thickness. The dry etching process has anisotropic etching characteristics and good profile controllability, and is beneficial to accurately controlling the etching amount of the protective layer 102 and improving the etching efficiency.
Referring to fig. 10 to 13, a gate structure 120 (as shown in fig. 13) is formed, wherein the gate structure 120 surrounds a portion of the sidewall of the first semiconductor pillar 10, and the gate structure 120 exposes the second semiconductor pillar 11.
The gate structure 120 is used to control the conduction channel of the MOS device to be turned on or off during operation.
In the present embodiment, the gate structure 120 is a metal gate structure. As shown in fig. 13, the gate structure 120 includes a work function layer 111 surrounding a portion of the sidewall of the first semiconductor pillar 10 and a gate electrode layer 112 surrounding the work function layer 111.
When the formed MOS device is an NMOS transistor, the material of the work function layer 111 includes one or more of titanium aluminide, tantalum carbide, aluminum, or titanium carbide; when the MOS device formed is a PMOS transistor, the material of the work function layer 111 includes one or more of titanium nitride, tantalum nitride, titanium carbide, tantalum silicon nitride, titanium silicon nitride, and tantalum carbide.
In this embodiment, the gate electrode layer 112 is made of magnesium-tungsten alloy. In other embodiments, the gate electrode layer may be made of W, Al, Cu, Ag, Au, Pt, Ni, Ti, or the like.
Therefore, in the step of forming the gate structure 120, the gate structure 120 surrounds a portion of the sidewall of the first semiconductor pillar 10 exposed by the isolation layer 106.
Accordingly, in this embodiment, the step of forming the gate structure 120 includes:
as shown in fig. 10, an initial work function layer 108 conformally covering the semiconductor pillar 110 exposed by the isolation layer 106 and an initial gate electrode layer 109 conformally covering the initial work function layer 108 are formed, wherein the initial work function layer 108 and the initial gate electrode layer 109 also extend to a portion of the source doped layer 105 on one side of the semiconductor pillar 110. Specifically, the initial work function layer 108 and the initial gate electrode layer 109 extend onto the isolation layer 106 above the source doped layer 105 on the side of the semiconductor pillar 110.
The initial work function layer 108 provides for the subsequent formation of a work function layer; the initial gate electrode layer 109 is prepared for subsequent formation of a gate electrode layer.
In this embodiment, the initial work function layer 108 and the gate electrode layer 109 are formed by a deposition process and an etching process which are sequentially performed, so that the initial work function layer 108 and the gate electrode layer 109 expose a portion of the source doping layer 105.
Specifically, the deposition process is an atomic layer deposition process.
As shown in fig. 11 and 12, a first dielectric layer 115 (as shown in fig. 12) is formed on the source doping layer 105, wherein the first dielectric layer 115 covers a portion of the sidewall of the semiconductor pillar 110, and the top of the first dielectric layer 115 is lower than the bottom of the drain doping layer 125.
The first dielectric layer 115 is used to achieve electrical isolation between adjacent devices.
Therefore, the material of the first dielectric layer 115 is a dielectric material. In this embodiment, the first dielectric layer 115 is made of silicon oxide. In other embodiments, the material of the first dielectric layer may also be other dielectric materials such as silicon nitride, silicon oxynitride, and the like.
Specifically, the step of forming the first dielectric layer 115 includes: forming an initial dielectric layer 126 (as shown in fig. 11), wherein the initial dielectric layer 126 covers the initial gate electrode layer 109 and the isolation layer 106; a portion of the thickness of the initial dielectric layer 126 is removed to form a first dielectric layer 115 covering a portion of the sidewalls of the initial gate electrode layer 109.
In this embodiment, a dry etching process is used to remove a portion of the thickness of the initial dielectric layer 126. The dry etching process has anisotropic etching characteristics, and the position of the top surface of the first dielectric layer 115 is easily controlled by selecting the dry etching process.
As shown in fig. 13, the initial gate electrode layer 109 (shown in fig. 12) and the initial work function layer 108 (shown in fig. 12) exposed by the first dielectric layer 115 are removed, the initial gate electrode layer 109 is used as a gate electrode layer 112, the initial work function layer 108 is used as a work function layer 111, and the gate electrode layer 112 and the work function layer 111 are used for forming a gate structure 120.
In this embodiment, the initial work function layer 108 and the initial gate electrode layer 109 are etched by a dry etching process. The dry etching process is beneficial to accurately controlling the etching amount of the first dielectric layer 115 and reducing the damage to other film layers.
Referring to fig. 10 in combination, the method for forming the semiconductor structure further includes: after the isolation layer 106 is formed, and before the initial work function layer 108 and the initial gate electrode layer 109 are formed, the method further includes: a gate dielectric layer 107 is formed conformally covering the semiconductor pillars 110 exposed by the isolation layer 106.
The gate dielectric layer 107 is used to electrically isolate the gate structure 120 from the semiconductor pillar 110.
The subsequently formed gate structure 120 is a metal gate structure, so that the gate dielectric layer 107 is made of a high-k dielectric material; wherein, the high-k dielectric material is a dielectric material with a relative dielectric constant larger than that of silicon oxide. Specifically, the material of the gate dielectric layer 107 is HfO2. In other embodiments, the material of the gate dielectric layer may also be selected from ZrO2HfSiO, HfSiON, HfTaO, HfTiO, HfZrO or Al2O3And the like.
In other embodiments, the gate dielectric layer may further include a gate oxide layer and a high-k dielectric layer on the gate oxide layer, and the gate oxide layer may be made of silicon oxide or silicon oxynitride.
In this embodiment, the gate dielectric layer 107 is formed by an atomic layer deposition process. In other embodiments, the gate dielectric layer may also be formed by a chemical vapor deposition process.
Therefore, with continued reference to fig. 13, after the gate structure 120 is formed, the gate structure 120 exposes the gate dielectric layer 107 on the surface of the drain doping layer 125.
In this embodiment, the gate dielectric layer 107 on the surface of the drain doping layer 125 is retained, so that the gate dielectric layer 107 protects the drain doping layer 125, thereby better achieving electrical isolation between the drain doping layer 125 and the gate structure 120.
After the gate structure 120 is formed, the following process further includes:
referring to fig. 14, a second dielectric layer 127 is formed to cover the first dielectric layer 115 and the drain doping layer 125, wherein the second dielectric layer 127 and the first dielectric layer 115 form an interlayer dielectric layer (not shown); a source contact hole plug 122 electrically connected with the source doping layer 105 is formed in the interlayer dielectric layer on one side of the gate structure 120, a drain contact hole plug 121 electrically connected with the drain doping layer 125 is formed in the second dielectric layer 127, a gate contact hole plug 123 is formed in the interlayer dielectric layer on the other side of the gate structure 120, and the gate contact hole plug 123 is electrically connected with the gate structure 120.
The area of the drain doping layer 125 is large, so that in the process of forming the drain contact hole plug 121, the requirement for alignment deviation of the process of forming the drain contact hole plug 121 is favorably reduced, the process difficulty of forming the drain contact hole plug 121 is correspondingly reduced, the process window is enlarged, and meanwhile, the contact performance of the drain contact hole plug 121 and the drain doping layer 125 is favorably improved.
The second dielectric layer 127 is also used to achieve isolation between adjacent devices. The second dielectric layer 127 is also used to provide a process platform for forming the drain contact hole plug 121, the source contact hole plug 122, and the gate contact hole plug 123, and the second dielectric layer 127 is also used to realize isolation between adjacent contact hole plugs.
In this embodiment, the second dielectric layer 127 and the first dielectric layer 115 are made of the same material. The second dielectric layer 127 is made of silicon oxide.
In this embodiment, the material of the drain contact hole plug 121 is tungsten.
In this embodiment, the material of the source contact hole plug 122 and the gate contact hole plug 123 is the same as the material of the drain contact hole plug 121, and the description thereof is omitted.
Correspondingly, the invention also provides a semiconductor structure. Referring to fig. 14, a schematic structural diagram of an embodiment of a semiconductor structure of the present invention is shown.
The semiconductor structure includes: a substrate 100; a source doped layer 105 on the substrate 100; a semiconductor pillar 110 (as shown in fig. 7) protruding from the source doped layer 105, wherein the semiconductor pillar 110 has a T-shaped structure, the semiconductor pillar 110 includes a first semiconductor pillar 10 and a second semiconductor pillar 11 (as shown in fig. 7) located on the first semiconductor pillar 10, and a width of the second semiconductor pillar 11 is greater than a width of the first semiconductor pillar 10; a gate structure 120, the gate structure 120 surrounding a portion of the sidewall of the first semiconductor pillar 10, the gate structure 120 exposing the second semiconductor pillar 11; and a drain doping layer 125 on the top of the second semiconductor pillar 11.
The width of the second semiconductor pillar 11 is greater than the width of the first semiconductor pillar 10, and the width of the second semiconductor pillar 11 is greater along a direction perpendicular to the sidewall of the semiconductor pillar 110, the drain doping layer 125 is located at the top of the second semiconductor pillar 11, and the area of the drain doping layer 125 is also greater, so that the contact performance between the contact plug and the drain doping layer 125 is improved in the process of forming the contact plug electrically connected to the drain doping layer 125, and in addition, the contact resistance between the contact plug and the drain doping layer 125 can be reduced by increasing the contact area between the contact plug and the drain doping layer 125; in summary, the performance of the semiconductor structure is improved by the T-shaped semiconductor pillar 110 in the embodiment.
The substrate 100 provides a process platform for the formation of semiconductor structures.
In this embodiment, the substrate 100 is a silicon substrate. In other embodiments, the substrate material can also be germanium, silicon carbide, gallium arsenide, or indium gallium, and the substrate can also be a silicon-on-insulator substrate or a germanium-on-insulator substrate.
When forming a PMOS transistor, the material of the source doping layer 105 is silicon germanium doped with P-type ions. By doping the P-type ions in the silicon germanium, the P-type ions replace the positions of silicon atoms in the crystal lattice, and the more the P-type ions are doped, the higher the concentration of the majority ions is, and the stronger the conductivity is. Specifically, the P-type ions include B, Ga or In.
When forming an NMOS transistor, the material of the source doping layer 105 is silicon carbide or silicon phosphide doped with N-type ions, respectively. By doping N-type ions in silicon carbide or silicon phosphide, the N-type ions are used for replacing the positions of silicon atoms in crystal lattices, and the more N-type ions are doped, the higher the concentration of majority ions is, and the stronger the conductivity is. Specifically, the N-type ions include P, As or Sb.
The semiconductor pillar 110 provides a process platform for forming the gate structure 120 and the drain doping layer 125. The first semiconductor pillar 10 is used to provide a channel region for a MOS device during operation, and the second semiconductor pillar 11 is used to provide a process base for forming the drain doping layer 125.
In this embodiment, the material of the semiconductor pillar 110 is silicon. In other embodiments, the material of the semiconductor pillar may also be germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, according to actual requirements.
When forming a PMOS transistor, the semiconductor pillar 110 is doped with N-type ions, wherein the N-type ions may be P ions, As ions, or Sb ions; when forming an NMOS transistor, the semiconductor pillar 110 is doped with P-type ions, wherein the P-type ions may be B ions, Ga ions, or In ions.
The ratio of the height of the second semiconductor pillar 11 to the total height of the semiconductor pillar 110 should not be too small or too large. If the ratio of the height of the second semiconductor pillar 11 to the total height of the semiconductor pillar 110 is too small, the volume of the drain doping layer 125 at the top of the second semiconductor pillar 11 is too small, which may affect the carrier mobility of the device; if the ratio of the height of the second semiconductor pillar 11 to the total height of the semiconductor pillar 110 is too large, the ratio of the height of the first semiconductor pillar 10 is too small, and if the total height of the semiconductor pillar 110 is not changed, the height of the first semiconductor pillar 10 is too small, which may easily cause the material of the first semiconductor pillar 10 to be too small for being used as a channel region, which may easily affect the effective channel length of a device. For this reason, in the present embodiment, the height of the second semiconductor pillar 11 is one fifth to one third of the total height of the semiconductor pillar 110.
Specifically, in the present embodiment, the height of the second semiconductor pillar 11 is 3 nm to 8 nm.
The width of the second semiconductor pillar 11 is not too small nor too large in a direction perpendicular to the sidewalls of the semiconductor pillar 110. If the width of the second semiconductor pillar 11 is too small, the width of the drain doping layer 125 at the top of the second semiconductor pillar 11 is also too small, and it is difficult to improve the contact performance between the drain doping layer 125 and the contact hole plug; if the width of the second semiconductor pillars 11 is too large, the distance between adjacent second semiconductor pillars 11 is too close, and even a short circuit occurs between adjacent second semiconductor pillars 11, which may cause a leakage current. For this reason, in the present embodiment, the width of the second semiconductor pillar 11 is 1.5 times to 3 times the width of the first semiconductor pillar 10.
Specifically, in this embodiment, the width of the second semiconductor pillar 11 is 8 nm to 20 nm, so that the second semiconductor pillar 11 has a significant effect of improving the contact performance between the drain doping layer 125 and the contact hole plug, and the reliability of the semiconductor structure is improved.
The semiconductor structure further includes: and an isolation layer 106 on the source doping layer 105 and surrounding a portion of the sidewall of the first semiconductor pillar 10 exposed by the gate structure 120.
The isolation layer 106 is used for isolating the gate structure 120 from the source doped layer 105.
In this embodiment, the material of the isolation layer 106 is silicon oxide. Silicon oxide is a commonly used insulating material in a semiconductor process, and the process compatibility is high. In other embodiments, the material of the isolation layer may also be silicon nitride, silicon oxynitride, boron nitride, or silicon oxycarbonitride.
The gate structure 120 is used to control the conduction channel of the MOS device to be turned on or off during operation.
In the present embodiment, the gate structure 120 is a metal gate structure. The gate structure 120 includes a work function layer 111 surrounding a sidewall of the exposed portion of the first semiconductor pillar 10 of the doped layer 104 and a gate electrode layer 112 surrounding the work function layer 111.
Specifically, the gate structure 120 surrounds the sidewall of the first semiconductor pillar 10 exposed by the isolation layer 106. The gate electrode layer 112 and the work function layer 111 also extend to the source doped layer 105 on one side of the semiconductor pillar 110. Specifically, the gate electrode layer 112 and the work function layer 111 also extend onto the isolation layer 106 above the source doped layer 105 on the side of the semiconductor pillar 110.
When the semiconductor structure is an NMOS transistor, the material of the work function layer 111 includes one or more of titanium aluminide, tantalum carbide, aluminum, or titanium carbide; when the semiconductor structure is a PMOS transistor, the material of the work function layer 111 includes one or more of titanium nitride, tantalum nitride, titanium carbide, tantalum silicon nitride, titanium silicon nitride, and tantalum carbide.
In this embodiment, the gate electrode layer 112 is made of magnesium-tungsten alloy. In other embodiments, the gate electrode layer may be made of W, Al, Cu, Ag, Au, Pt, Ni, Ti, or the like.
In this embodiment, the semiconductor structure further includes: and a gate dielectric layer 107 conformally covering the semiconductor pillars 110 exposed by the isolation layer 106.
The gate dielectric layer 107 is used to electrically isolate the gate structure 120 from the semiconductor pillar 110.
The gate structure 120 is a metal gate structure, and therefore, the gate dielectric layer 107 is made of a high-k dielectric material; wherein, the high-k dielectric material is a dielectric material with a relative dielectric constant larger than that of silicon oxide. Specifically, the material of the gate dielectric layer 107 is HfO2. In other embodiments, the material of the gate dielectric layer may also be selected from ZrO2HfSiO, HfSiON, HfTaO, HfTiO, HfZrO or Al2O3And the like.
In other embodiments, the gate dielectric layer may further include a gate oxide layer and a high-k dielectric layer on the gate oxide layer, and the gate oxide layer may be made of silicon oxide or silicon oxynitride.
In this embodiment, the gate dielectric layer 107 on the surface of the drain doping layer 125 is retained, so that the gate dielectric layer 107 protects the drain doping layer 125, thereby better isolating the drain doping layer 125 from the gate structure 120.
The drain doping layer 125 and the source doping layer 105 are the same in doping ion type and material.
When a PMOS transistor is formed, the material of the drain doping layer 125 is silicon germanium doped with P-type ions. By doping the P-type ions in the silicon germanium, the P-type ions replace the positions of silicon atoms in the crystal lattice, and the more the P-type ions are doped, the higher the concentration of the majority ions is, and the stronger the conductivity is. Specifically, the P-type ions include B, Ga or In.
When forming an NMOS transistor, the material of the drain doping layer 125 is silicon carbide or silicon phosphide doped with N-type ions, respectively. By doping N-type ions in silicon carbide or silicon phosphide, the N-type ions are used for replacing the positions of silicon atoms in crystal lattices, and the more N-type ions are doped, the higher the concentration of majority ions is, and the stronger the conductivity is. Specifically, the N-type ions include P, As or Sb.
In this embodiment, the second semiconductor pillar 11 is doped with ions, and a portion of the second semiconductor pillar 11 doped with ions is used as the drain doping layer 125. In other embodiments, the drain doping layer may also be an epitaxial layer doped with ions, the epitaxial layer being located on top of the second semiconductor pillar.
In this embodiment, the semiconductor structure further includes: a first dielectric layer 115, located on the substrate 100 where the gate structure 120 is exposed, where the first dielectric layer 115 exposes the second semiconductor pillar 11; a second dielectric layer 127 covering the first dielectric layer 115 and the drain doping layer 125, wherein the second dielectric layer 127 and the first dielectric layer 115 form an interlayer dielectric layer (not labeled); a source contact hole plug 122 located in the interlayer dielectric layer at one side of the gate structure 120 and electrically connected to the source doping layer 105; a drain contact hole plug 121 located in the second dielectric layer 127 and electrically connected to the drain doping layer 125; and a gate contact hole plug 123 located in the interlayer dielectric layer at the other side of the gate structure 120 and electrically connected to the gate structure 120.
The first dielectric layer 115 is used to achieve electrical isolation between adjacent devices.
Therefore, the material of the first dielectric layer 115 is a dielectric material. In this embodiment, the first dielectric layer 115 is made of silicon oxide. In other embodiments, the dielectric layer may also be made of other dielectric materials such as silicon nitride and silicon oxynitride.
The second dielectric layer 127 is also used to achieve isolation between adjacent devices. The second dielectric layer 127 is also used to provide a process platform for forming the drain contact hole plug 121, the source contact hole plug 122, and the gate contact hole plug 123, and the second dielectric layer 127 is also used to realize isolation between adjacent contact hole plugs. In this embodiment, the second dielectric layer 127 and the first dielectric layer 115 are made of the same material. The second dielectric layer 127 is made of silicon oxide.
The drain contact hole plug 121 is used for electrically connecting the drain doping layer 125 with an external circuit or other interconnection structure; the source contact hole plug 122 is used to electrically connect the source doping layer 115 with an external circuit or other interconnect structure; the gate contact hole plug 123 is used to electrically connect the gate structure 120 with an external circuit or other interconnect structure.
In this embodiment, the material of the drain contact hole plug 121 is tungsten.
In this embodiment, the material of the source contact hole plug 122 and the gate contact hole plug 123 is the same as the material of the drain contact hole plug 121, and the description thereof is omitted.
The semiconductor structure may be formed by the formation method described in the foregoing embodiment, or may be formed by another formation method. For a detailed description of the semiconductor structure in this embodiment, reference may be made to the corresponding description in the foregoing embodiments, and details of this embodiment are not repeated herein.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims (20)

1. A method of forming a semiconductor structure, comprising:
forming a base, wherein the base comprises a substrate, a source doping layer located on the substrate and a semiconductor column protruding out of the source doping layer, the semiconductor column is of a T-shaped structure and comprises a first semiconductor column and a second semiconductor column located on the first semiconductor column, and the width of the second semiconductor column is larger than that of the first semiconductor column;
forming a gate structure surrounding a portion of a sidewall of the first semiconductor pillar, the gate structure exposing the second semiconductor pillar;
and forming a drain doping layer on the top of the second semiconductor pillar.
2. The method of forming a semiconductor structure of claim 1, wherein the step of forming the semiconductor pillar comprises: forming a protective layer on the source doping layer, wherein a groove is formed in the protective layer, the section of the groove is in a T shape, the groove comprises a bottom groove and a top groove positioned on the bottom groove, the opening width of the top groove is greater than that of the bottom groove, and the top of the bottom groove is communicated with the bottom of the top groove;
and forming the semiconductor column in the groove, wherein the part of the semiconductor column in the bottom groove is used as the first semiconductor column, and the part of the semiconductor column in the top groove is used as the second semiconductor column.
3. The method of forming a semiconductor structure of claim 2, wherein the step of forming the recess comprises: forming an initial protection layer on the source doping layer;
forming an initial groove exposing the source doping layer in the initial protection layer; forming a filling layer in the initial groove, wherein the top of the filling layer is lower than that of the initial protective layer;
etching the exposed side wall of the initial groove of the filling layer along the direction vertical to the side wall of the initial groove to form the top groove, and taking the residual initial protective layer as the protective layer;
and removing the filling layer, wherein the residual initial groove communicated with the top groove is used as the bottom groove.
4. The method of forming a semiconductor structure of claim 2, wherein the semiconductor pillars are formed in the recesses using an epitaxial process.
5. The method of forming a semiconductor structure of claim 2, wherein after forming the semiconductor pillar and before forming the gate structure, further comprising: etching back the protective layer with partial thickness, and taking the residual protective layer as an isolation layer;
in the step of forming the gate structure, the gate structure surrounds a portion of the sidewall of the first semiconductor pillar exposed by the isolation layer.
6. The method of forming a semiconductor structure of claim 3, wherein the exposed initial trench sidewalls of the fill layer are etched using an isotropic etch process.
7. The method of claim 6, wherein the exposed initial trench sidewalls of the fill layer are etched using a SiCoNi process or a hydrofluoric acid solution.
8. The method for forming a semiconductor structure of claim 3, wherein the initial recess is formed by etching the initial protection layer using a dry etching process.
9. The method of claim 2, wherein the protective layer is formed of silicon oxide, silicon nitride, silicon oxynitride, boron nitride, or silicon oxycarbonitride.
10. The method of forming a semiconductor structure of claim 5, wherein a dry etch process is used to etch back a portion of the thickness of the protective layer.
11. The method of claim 3, wherein the material of the fill layer is a BARC material, an ODL material, an SOC material, a photoresist, a DARC material, or a DUO material.
12. The method of forming a semiconductor structure of claim 1, wherein a height of the second semiconductor pillar is one fifth to one third of a total height of the semiconductor pillars.
13. The method of forming a semiconductor structure of claim 1, wherein a width of the second semiconductor pillar is 1.5 times to 3 times a width of the first semiconductor pillar.
14. The method of forming a semiconductor structure of claim 1, wherein the second semiconductor pillar has a width of 8 nm to 20 nm.
15. The method of forming a semiconductor structure of claim 2, wherein the step of forming the drain doping layer comprises: and carrying out ion doping treatment on the second semiconductor columns exposed out of the protective layer, wherein the second semiconductor columns doped with ions are used as the drain doping layer.
16. A semiconductor structure, comprising:
a substrate;
the source doping layer is positioned on the substrate;
the semiconductor pillar protrudes out of the source doping layer, is of a T-shaped structure and comprises a first semiconductor pillar and a second semiconductor pillar located on the first semiconductor pillar, and the width of the second semiconductor pillar is larger than that of the first semiconductor pillar;
a gate structure surrounding a portion of a sidewall of the first semiconductor pillar, the gate structure exposing the second semiconductor pillar;
and the drain doping layer is positioned at the top of the second semiconductor pillar.
17. The semiconductor structure of claim 16, wherein a height of the second semiconductor pillar is one fifth to one third of a total height of the semiconductor pillars.
18. The semiconductor structure of claim 16, wherein a width of the second semiconductor pillar is 1.5 to 3 times a width of the first semiconductor pillar.
19. The semiconductor structure of claim 16, wherein the width of the second semiconductor pillar is 8 nm to 20 nm.
20. The semiconductor structure of claim 16, wherein the second semiconductor pillar is doped with ions, and a portion of the second semiconductor pillar doped with ions serves as the drain doping layer.
CN201910579439.7A 2019-06-28 2019-06-28 Semiconductor structure and forming method thereof Active CN112151595B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201910579439.7A CN112151595B (en) 2019-06-28 2019-06-28 Semiconductor structure and forming method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201910579439.7A CN112151595B (en) 2019-06-28 2019-06-28 Semiconductor structure and forming method thereof

Publications (2)

Publication Number Publication Date
CN112151595A true CN112151595A (en) 2020-12-29
CN112151595B CN112151595B (en) 2024-01-26

Family

ID=73891542

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201910579439.7A Active CN112151595B (en) 2019-06-28 2019-06-28 Semiconductor structure and forming method thereof

Country Status (1)

Country Link
CN (1) CN112151595B (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090001352A1 (en) * 2007-03-27 2009-01-01 Samsung Electronics Co., Ltd. Non-Volatile Memory Device, Method of Manufacturing the Same, and Semiconductor Package
CN101877317A (en) * 2009-04-29 2010-11-03 台湾积体电路制造股份有限公司 Non-planar transistors and methods of fabrication thereof
JP2014022386A (en) * 2012-07-12 2014-02-03 Ps4 Luxco S A R L Semiconductor device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090001352A1 (en) * 2007-03-27 2009-01-01 Samsung Electronics Co., Ltd. Non-Volatile Memory Device, Method of Manufacturing the Same, and Semiconductor Package
CN101877317A (en) * 2009-04-29 2010-11-03 台湾积体电路制造股份有限公司 Non-planar transistors and methods of fabrication thereof
JP2014022386A (en) * 2012-07-12 2014-02-03 Ps4 Luxco S A R L Semiconductor device

Also Published As

Publication number Publication date
CN112151595B (en) 2024-01-26

Similar Documents

Publication Publication Date Title
CN112309860A (en) Semiconductor structure and forming method thereof
KR20220022085A (en) Gate structures in transistors and method of forming same
CN110718465B (en) Semiconductor structure and forming method thereof
CN108878521B (en) Vertical tunneling field effect transistor and forming method thereof
CN111106009A (en) Semiconductor structure and forming method thereof
CN108122760B (en) Semiconductor structure and forming method thereof
CN109920733B (en) Semiconductor structure and transistor forming method
KR102647993B1 (en) Semicondutor device and method of manufacture
CN111863933A (en) Semiconductor structure and forming method thereof
CN112713088B (en) Semiconductor structure and forming method thereof
CN112151605B (en) Semiconductor structure and forming method thereof
CN113809011B (en) Semiconductor structure and forming method thereof
CN111490092B (en) Semiconductor structure and forming method thereof
CN112151595B (en) Semiconductor structure and forming method thereof
CN108807266B (en) Semiconductor structure and forming method thereof
CN109285876B (en) Semiconductor structure and forming method thereof
CN112786451A (en) Semiconductor structure and forming method thereof
CN113838802A (en) Semiconductor structure and forming method thereof
CN112151381A (en) Semiconductor structure and forming method thereof
CN112310198B (en) Semiconductor structure and forming method thereof
CN111627819B (en) Semiconductor structure and forming method thereof
CN113327856B (en) Semiconductor structure and forming method thereof
CN112103249B (en) Semiconductor structure and forming method thereof
CN113838806B (en) Semiconductor structure and forming method thereof
CN112289746B (en) Semiconductor structure and forming method thereof

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant