CN112151606A - Semiconductor structure and forming method thereof - Google Patents

Semiconductor structure and forming method thereof Download PDF

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Publication number
CN112151606A
CN112151606A CN201910577060.2A CN201910577060A CN112151606A CN 112151606 A CN112151606 A CN 112151606A CN 201910577060 A CN201910577060 A CN 201910577060A CN 112151606 A CN112151606 A CN 112151606A
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semiconductor
forming
drain
doping layer
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CN112151606B (en
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周飞
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET

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Abstract

A semiconductor structure and a method of forming the same, the method comprising: providing a substrate; forming a source doping layer on a substrate; forming a semiconductor pillar on the source doping layer; forming a drain doping layer covering the top of the semiconductor column and surrounding partial side wall of the semiconductor column on one side of the top of the semiconductor column; forming a gate structure which surrounds partial side wall of the semiconductor column and exposes the drain doping layer; and after the gate structure is formed, a drain plug is formed at the top of the drain doping layer and is electrically connected with the drain doping layer. According to the invention, the drain doping layer which covers the top of the semiconductor column and surrounds partial side wall of the semiconductor column is formed, so that the width of the drain doping layer is increased, the surface area of the top of the drain doping layer is correspondingly increased, the process window for forming the drain plug is increased, the drain plug is easy to form on the top of the drain doping layer, the electric connection effect of the drain plug and the drain doping layer is improved, and the performance of the VGAA transistor is improved.

Description

Semiconductor structure and forming method thereof
Technical Field
Embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular, to a semiconductor structure and a method for forming the same.
Background
With the rapid development of semiconductor manufacturing technology, semiconductor devices are moving toward higher element density and higher integration, and the trend of semiconductor process nodes following moore's law is decreasing. As the channel length decreases, the controllability of the gate structure to the channel becomes weaker, thereby causing a sub-threshold leakage (SCE) phenomenon, so-called short channel effect.
In order to better accommodate the scaling requirements of device dimensions, semiconductor processes are gradually starting to transition from planar transistors to more power efficient three-dimensional transistors, such as gate-all-around (GAA) transistors. In the all-around gate transistor, the gate structure surrounds the channel region, and compared with a planar transistor, the all-around gate transistor has stronger control capability on a channel and can better inhibit a short-channel effect.
The fully-wrapped-gate transistor includes a lateral-all-around-gate (LGAA) transistor and a vertical-all-around-gate (VGAA) transistor. Wherein the channel of the VGAA transistor extends in a direction perpendicular to the substrate surface, which improves the area utilization efficiency of the semiconductor structure, thereby achieving a further feature size reduction.
Disclosure of Invention
Embodiments of the present invention provide a semiconductor structure and a method for forming the same, which improve the performance of a VGAA transistor.
To solve the above problems, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate; forming a source doping layer on the substrate; forming a semiconductor pillar on the source doping layer; forming a drain doping layer covering the top of the semiconductor column and surrounding partial side wall of the semiconductor column on one side of the top of the semiconductor column; forming a gate structure which surrounds partial side walls of the semiconductor columns and exposes the drain doping layer; and forming a drain plug at the top of the drain doping layer after the gate structure is formed, wherein the drain plug is electrically connected with the drain doping layer.
Optionally, in the step of forming the drain doping layer, the height of the semiconductor pillar surrounded by the drain doping layer is 2nm to 6 nm.
Optionally, in the step of forming the drain doping layer, the thickness of the drain doping layer is 2nm to 5 nm.
Optionally, the drain doping layer is formed by a selective epitaxy process.
Optionally, after forming the semiconductor pillar and before forming the drain doping layer, the method further includes: forming a protective layer on the source doping layer exposed out of the semiconductor pillar, wherein the protective layer covers part of the side wall of the semiconductor pillar; and in the step of forming the drain doping layer, the drain doping layer covers the semiconductor columns exposed out of the protective layer.
Optionally, the step of forming the protective layer includes: forming a protective material layer on the source doping layer exposed from the semiconductor pillar; and etching back the protective material layer with partial thickness to expose partial side walls of the semiconductor columns, and taking the residual protective material layer as the protective layer.
Optionally, the material of the protective layer is a dielectric material; after the drain doping layer is formed and before the gate structure is formed, the method further includes: and etching back the protective layer with partial thickness to expose partial side walls of the semiconductor columns, and taking the residual protective layer as an isolation layer.
Optionally, after the gate structure is formed, the top of the gate structure is lower than the bottom of the drain doping layer.
Optionally, the distance from the top of the gate structure to the bottom of the drain doping layer is 3nm to 5 nm.
Optionally, the step of forming the gate structure includes: forming a gate material layer conformally covering the semiconductor pillar, wherein the gate material layer also extends to a part of the source doping layer on one side of the semiconductor pillar; forming an interlayer dielectric layer on the source doping layer, wherein the interlayer dielectric layer covers part of the side wall of the semiconductor column, and the top of the interlayer dielectric layer is lower than the bottom of the drain doping layer; and removing the gate material layer exposed from the interlayer dielectric layer to form the gate structure.
Optionally, before forming the gate structure, the method further includes: and forming a gate dielectric layer which conformally covers the semiconductor column and the drain doping layer.
Correspondingly, an embodiment of the present invention further provides a semiconductor structure, including: a substrate; the source doping layer is positioned on the substrate; a semiconductor pillar located on the source doping layer; the drain doping layer is positioned on one side of the top of the semiconductor column, covers the top of the semiconductor column and surrounds part of the side wall of the semiconductor column; the grid structure surrounds partial side walls of the semiconductor columns and exposes the drain doping layer; and the drain electrode plug is positioned at the top of the drain doping layer and is electrically connected with the drain doping layer.
Optionally, the height of the semiconductor pillar surrounded by the drain doping layer is 2nm to 6 nm.
Optionally, the thickness of the drain doping layer is 2nm to 5 nm.
Optionally, the drain doping layer includes an epitaxial layer doped with conductive ions.
Optionally, the semiconductor structure further includes: and the isolation layer is positioned between the gate structure and the source doping layer and covers part of the side wall of the semiconductor column.
Optionally, the top of the gate structure is lower than the bottom of the drain doping layer.
Optionally, the distance from the top of the gate structure to the bottom of the drain doping layer is 3nm to 5 nm.
Optionally, the semiconductor structure further includes: and the gate dielectric layer is positioned between the semiconductor column and the gate structure and conformally covers the top and the side wall of the drain doping layer exposed by the gate structure.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following advantages:
in the embodiment of the invention, the drain doping layer which covers the top of the semiconductor column and surrounds partial side wall of the semiconductor column is formed on one side of the top of the semiconductor column, so that the width of the drain doping layer is increased, the surface area of the top of the drain doping layer is correspondingly increased, the process window for forming the drain plug is increased, the drain plug is easy to form on the top of the drain doping layer, the electric connection effect of the drain plug and the drain doping layer is improved, and the performance of the VGAA transistor is improved, for example: the contact resistance between the drain doping layer and the drain plug is reduced.
Drawings
FIG. 1 is a schematic diagram of a semiconductor structure;
fig. 2 to 11 are schematic structural diagrams corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention.
Detailed Description
The performance of VGAA transistors is currently still in need of improvement. There are still reasons for improvement in the performance of VGAA transistors that are analyzed in conjunction with a semiconductor structure.
Referring to fig. 1 in combination, fig. 1 is a schematic diagram of a semiconductor structure.
The semiconductor structure includes: a substrate 10; a source doping layer 11 on the substrate 10; a semiconductor pillar 12 on the source doping layer 11; a drain doping layer 14 on top of the semiconductor pillar 13; an isolation layer 13 located on the source doping layer 11 exposed from the semiconductor pillar 12, wherein the isolation layer 13 covers a portion of a sidewall of the semiconductor pillar 12; a gate structure 15 surrounding a portion of the sidewall of the semiconductor pillar 12 exposed by the isolation layer 13, wherein the gate structure 15 exposes the drain doping layer 14; and a drain plug 18 located on the drain doping layer 14 and electrically connected to the drain doping layer 14.
The drain doped layer 14 is located at the top of the semiconductor pillar 12, but as the device feature size is continuously reduced, the width of the semiconductor pillar 12 is smaller, resulting in a smaller width of the drain doped layer 14. Accordingly, in the process of forming the drain plug 18, difficulty in controlling overlay (overlay) precision may be increased, so as to increase difficulty in the process of forming the drain plug 18, reduce the electrical connection effect between the drain plug 18 and the drain doping layer 14, and adversely affect the performance of the transistor, for example: resulting in an increase in contact resistance between the drain doping layer 14 and the drain plug 18.
In order to solve the technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate; forming a source doping layer on the substrate; forming a semiconductor pillar on the source doping layer; forming a drain doping layer covering the top of the semiconductor column and surrounding partial side wall of the semiconductor column on one side of the top of the semiconductor column; forming a gate structure which surrounds partial side walls of the semiconductor columns and exposes the drain doping layer; and forming a drain plug at the top of the drain doping layer after the gate structure is formed, wherein the drain plug is electrically connected with the drain doping layer.
In the embodiment of the present invention, the drain doping layer covering the top of the semiconductor pillar and surrounding a partial sidewall of the semiconductor pillar is formed on one side of the top of the semiconductor pillar, and compared with the drain doping layer formed only on the top of the semiconductor pillar, the width of the drain doping layer is increased in the embodiment of the present invention, which correspondingly increases the top surface area of the drain doping layer, thereby increasing the process window for forming the drain plug, easily forming the drain plug on the top of the drain doping layer, and improving the electrical connection effect between the drain plug and the drain doping layer, thereby improving the performance of the VGAA transistor, for example: the contact resistance between the drain doping layer and the drain plug is reduced.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 2 to 11 are schematic structural diagrams corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention.
Referring to fig. 2, a substrate 100 is provided.
The substrate 100 is used to provide a process platform for the subsequent formation of VGAA transistors.
In this embodiment, the substrate 100 is a silicon substrate. In other embodiments, the material of the substrate may also be other materials such as germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, and the substrate may also be another type of substrate such as a silicon-on-insulator substrate or a germanium-on-insulator substrate.
With continued reference to fig. 2, a source doped layer 110 is formed on the substrate 100.
The source doped layer 110 serves as the source of the VGAA transistor.
In this embodiment, a selective epitaxial growth process is used to form the first epitaxial layer, and the source doping layer 110 is formed by in-situ self-doping ions during the process of forming the first epitaxial layer.
In this embodiment, taking the formed semiconductor structure as a pmos (positive channel metal oxide semiconductor) transistor as an example, the material of the source doping layer 110 is silicon germanium doped with P-type ions, that is, the material of the first epitaxial layer is silicon germanium. The first epitaxial layer is used for providing a pressure stress effect for a channel region of the PMOS transistor, so that the carrier mobility of the PMOS transistor is improved. Wherein the P-type ions include B, Ga or In.
In other embodiments, the semiconductor structure may also be an nmos (negative channel metal oxide semiconductor) transistor, and the material of the source doping layer is silicon carbide or silicon phosphide doped with N-type ions, that is, the material of the first epitaxial layer is silicon carbide or silicon phosphide. The first epitaxial layer is used for providing a tensile stress effect for a channel region of the NMOS transistor, so that the carrier mobility of the NMOS transistor is improved. Wherein the N-type ions comprise P, As or Sb.
With continued reference to fig. 2, semiconductor pillars 120 are formed on the source doped layer 110.
The semiconductor pillar 120 is used to provide a channel of a transistor.
In this embodiment, the material of the semiconductor pillar 120 is silicon. In other embodiments, the material of the semiconductor pillar may also be germanium, silicon carbide, gallium arsenide, or indium gallium arsenide.
Specifically, the step of forming the semiconductor pillars 120 includes: after forming the source doping layer 110, forming a semiconductor material layer (not shown in the figure) on the source doping layer 110; forming a mask layer 130 on the semiconductor material layer; and etching the semiconductor material layer by using the mask layer 130 as a mask to form the semiconductor pillar 120.
In this embodiment, a semiconductor material layer is formed on the source doping layer 110 by a selective epitaxial growth method.
In this embodiment, the mask layer 130 is a hard mask layer, and the mask layer 130 is made of silicon nitride.
It should be noted that the height (not labeled) of the semiconductor pillars 120 should not be too small, and should not be too large. In the subsequent step of forming the drain doping layer, the drain doping layer surrounds a part of the sidewall of the semiconductor pillar near the top, and if the height of the semiconductor pillar 120 is too small, in order to enable the height of the semiconductor pillar surrounded by the drain doping layer to meet the process requirement, the gate structure on the sidewall of the subsequent semiconductor pillar 120 is too short, so that the control capability of the gate structure on the channel is easily reduced, and the subsequently formed channel region is also too short, so that a short channel effect is easily generated; if the height of the semiconductor pillars 120 is too large, the semiconductor pillars 120 are susceptible to collapse, and also the process difficulty in forming the semiconductor pillars 120 is increased. For this reason, in the present embodiment, the height (not labeled) of the semiconductor pillar 120 is 30nm to 200 nm.
Referring to fig. 3 to 4, a protection layer 140 (as shown in fig. 4) is formed on the source doping layer 110 exposed by the semiconductor pillar 120, and the protection layer 140 covers a portion of the sidewall of the semiconductor pillar 120.
The protection layer 140 exposes the top and a portion of the sidewall of the semiconductor pillar 120, and the protection layer 140 is used to define a formation position of a subsequent drain doping layer on the semiconductor pillar 120.
Specifically, the step of forming the protective layer 140 includes: forming a protective material layer 145 (shown in fig. 3) on the exposed source doped layer 110 of the semiconductor pillar 120; the protective material layer 145 is etched back to a partial thickness to expose a portion of the sidewall of the semiconductor pillar 120, and the remaining protective material layer 145 serves as the protective layer 140.
In this embodiment, in order to improve the surface flatness of the protection layer 140, after forming the protection material layer 145, before etching back the protection material layer 145 with a certain thickness, the method further includes: the top of the mask layer 130 is used as a stop position to planarize the protection material layer 145.
In this embodiment, the protection layer 140 is a dielectric material, and the formation of the protection layer 140 is also used to prepare for the subsequent formation of an isolation layer.
By selecting a dielectric material, the step of forming a film layer for protecting a portion of the sidewall of the semiconductor pillar 120 is eliminated, the existing process is less modified, the process compatibility is high, and the process cost and the process time are saved.
Accordingly, the material of the protective layer 140 includes one or more of silicon oxide, silicon nitride, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride, and boron carbonitride. In this embodiment, the material of the protection layer 140 is silicon oxide.
In this embodiment, the protective material layer 145 is formed by a Flowable Chemical Vapor Deposition (FCVD) process. The flowable chemical vapor deposition process has good filling capability, is beneficial to reducing the probability of defects such as cavities and the like formed in the protective material layer 145, and is correspondingly beneficial to improving the film forming quality of the protective material layer 145, thereby improving the quality of the protective layer 140.
In this embodiment, the material of the protection layer 140 is silicon oxide. The silicon oxide is a dielectric material with common process and low cost, and has high process compatibility; in addition, the silicon oxide has a small dielectric constant, and is favorable for improving the electrical isolation effect of a subsequent isolation layer.
In this embodiment, after forming the protection layer 140, the method further includes: the mask layer 130 is removed.
The mask layer 130 is removed to expose the top of the semiconductor pillar 120 for preparation of a subsequent formation of a drain doping layer.
Moreover, the mask layer 130 is removed after the protective layer 140 is formed, so that the mask layer 130 protects the top of the semiconductor pillar 120 during the formation of the protective layer 140.
Referring to fig. 5, on a side of the top of the semiconductor pillar 120, a drain doping layer 150 covering the top of the semiconductor pillar 120 and surrounding a portion of the sidewall of the semiconductor pillar 120 is formed.
The drain doped layer 150 serves as the drain of the VGAA transistor.
In this embodiment, the drain doping layer 150 covers the top of the semiconductor pillar 120 and surrounds the drain doping layer 150 on a partial sidewall of the semiconductor pillar 120, and compared with the drain doping layer formed only on the top of the semiconductor pillar, the width of the drain doping layer 150 is increased in this embodiment, which correspondingly increases the top surface area of the drain doping layer 150, thereby increasing the process window for forming the drain plug subsequently, easily forming the drain plug on the top of the drain doping layer 150, and improving the electrical connection effect between the drain plug and the drain doping layer 150, and further improving the performance of the VGAA transistor, for example: the contact resistance between the drain doping layer 150 and the drain plug is reduced.
In this embodiment, in the step of forming the drain doping layer 150, the drain doping layer 150 covers the semiconductor pillars 120 exposed by the protection layer 140.
Specifically, the second epitaxial layer is formed through a selective epitaxial growth process, and the drain doping layer 150 is formed by self-doping ions in situ in the process of forming the second epitaxial layer.
By selecting the selective epitaxial growth process, the drain doping layer 150 is only formed on the surface of the semiconductor pillar 120 exposed by the protection layer 140, so that the process complexity of forming the drain doping layer 150 is reduced, and the formation quality of the drain doping layer 150 is improved.
In this embodiment, taking the formed semiconductor structure as a PMOS transistor as an example, the second epitaxial layer is doped with P-type ions, and the material of the second epitaxial layer is silicon germanium. In other embodiments, when the semiconductor structure is an NMOS transistor, the second epitaxial layer is doped with N-type ions, and the material of the second epitaxial layer is silicon carbide or silicon phosphide.
For a detailed description of the drain doping layer 150, reference may be made to the foregoing description of the source doping layer 110, which is not repeated herein.
The thickness T1 of the drain doped layer 150 should not be too small or too large. If the thickness T1 of the drain doping layer 150 is too small, and the increase of the width of the drain doping layer 150 is too small, it is not beneficial to increase the process window for forming the drain plug, and it is not beneficial to improve the electrical connection effect between the drain plug and the drain doping layer 150; if the thickness T1 of the drain doped layer 150 is too large, bridging between adjacent drain doped layers 150 is easily caused. For this reason, in the present embodiment, the thickness T1 of the drain doping layer 150 is 2nm to 5 nm.
The height H of the semiconductor pillar 120 surrounded by the drain doping layer 150 should not be too small or too large. If the height H is too small, the difficulty in controlling the height H is easily increased, which correspondingly increases the difficulty in the process of etching back the partial thickness protection material layer 145; if the height H is too large, the gate structure on the sidewall of the subsequent semiconductor pillar 120 is too short under the condition that the height of the semiconductor pillar 120 is constant, which easily causes the control capability of the gate structure on the channel to be reduced, and also causes the channel region to be formed subsequently to be too short, which easily causes the short channel effect. For this reason, in the present embodiment, the height H of the semiconductor pillar 120 surrounded by the drain doping layer 150 is 2nm to 6 nm.
Referring to fig. 6, after the drain doping layer 150 is formed, the forming method further includes: a portion of the thickness of the protection layer 140 is etched back (as shown in fig. 5), exposing a portion of the sidewalls of the semiconductor pillars 120, and the protection layer 140 is left to serve as an isolation layer 160.
The isolation layer 160 exposes a portion of the sidewall of the semiconductor pillar 120 in preparation for the formation of a subsequent gate structure, and the isolation layer 160 serves to electrically isolate the subsequently formed gate structure from the source doping layer 160.
In this embodiment, the isolation layer 160 is formed by etching back the protection layer 140. By performing the etching back process twice on the protection material layer 145 (as shown in fig. 3), the required protection layer 140 and the required isolation layer 160 are obtained, so that the protection layer 140 and the isolation layer 160 respectively play their own roles in different steps, which simplifies the process complexity of forming the semiconductor structure and reduces the process cost.
In this embodiment, a dry etching process is adopted to etch back the protection layer 140 with a partial thickness. The dry etching process has anisotropic etching characteristics, and by selecting the dry etching process, the surface flatness of the isolation layer 160 is easily improved, and the etching amount of the protection layer 140 is easily controlled.
It should be noted that the thickness T2 of the isolation layer 160 is not too small nor too large. If the thickness T2 of the isolation layer 160 is too small, the electrical isolation effect of the isolation layer 160 on the gate structure and the source doped layer 160 is easily reduced; if the thickness T2 of the isolation layer 160 is too large, the heights of the semiconductor pillars 120 exposed by the drain doping layer 150 and the isolation layer 160 are too small, and if the height H (as shown in fig. 5) of the semiconductor pillar 120 surrounded by the drain doping layer 150 is ensured to meet the process requirements, the gate structures on the sidewalls of the subsequent semiconductor pillars 120 are too short, which may easily cause the control capability of the gate structures on the channels to be reduced, and may also cause the subsequently formed channel regions to be too short, which may easily cause short channel effects. For this reason, in the present embodiment, the thickness T2 of the isolation layer 160 is 2nm to 10 nm.
Referring to fig. 7 to 10 in combination, a gate structure 300 (shown in fig. 10) is formed to surround a portion of the sidewall of the semiconductor pillar 120 and expose the drain doping layer 150.
The gate structure 300 is used to control the turning on and off of the channel region of the transistor.
In this embodiment, the gate structure 300 is a metal gate structure, and the gate structure 300 includes a work function layer 310 (shown in fig. 10) surrounding a portion of the sidewall of the semiconductor pillar 120 and a gate layer 320 (shown in fig. 10) covering the work function layer 310.
In this embodiment, for example, the formed semiconductor structure is a PMOS transistor, the material of the work function layer 310 is a P-type work function material, and the material of the work function layer 310 includes one or more of TiN, TaN, TaSiN, TaAlN, and TiAlN.
In other embodiments, when the formed semiconductor structure is an NMOS transistor, the material of the work function layer is an N-type work function material, and the material of the work function layer includes one or more of TiAl, Mo, MoN, AlN, and TiAlC.
In this embodiment, the material of the gate layer 320 is Al. In other embodiments, the material of the gate layer may also be W, Cu, Ag, Au, Pt, Ni, Ti, or the like.
In this embodiment, after the gate structure 300 is formed, the top of the gate structure 300 is lower than the bottom of the drain doping layer 150, so that the gate structure 300 is isolated from the drain doping layer 150, thereby reducing the probability of bridging between the gate structure 300 and the drain doping layer 150.
It should be noted that the distance (not labeled) from the top of the gate structure 300 to the bottom of the drain doping layer 150 should not be too small, and should not be too large. If the distance is too small, the probability of bridging between the gate structure 300 and the drain doping layer 150 is correspondingly increased; if the distance is too large, the gate structure 300 is too short, which may result in a decrease in the channel control capability of the gate structure 300, and a short channel effect may be caused due to too short a subsequently formed channel region. For this reason, in the present embodiment, the distance from the top of the gate structure 300 to the bottom of the drain doping layer 150 is 3nm to 5 nm.
The steps for forming the gate structure 300 are described in detail below with reference to the accompanying drawings.
Referring to fig. 7, a gate material layer 305 is formed conformally covering the semiconductor pillar 120, the gate material layer 305 also extending onto a portion of the source doped layer 160 on one side of the semiconductor pillar 120.
In this embodiment, the gate material layer 305 includes a work function material layer 315 and a gate material layer 325 on the work function material layer 315.
The work-function material layer 315 provides for subsequent formation of a work-function layer and the gate material layer 325 provides for subsequent formation of a gate layer.
In this embodiment, the gate material layer 305 is formed by a deposition process and an etching process performed successively, so that the gate material layer 305 exposes a portion of the source doped layer 160.
Specifically, the deposition process is an atomic layer deposition process.
Referring to fig. 8 to 9, an interlayer dielectric layer 170 (as shown in fig. 9) is formed on the source doped layer 110, wherein the interlayer dielectric layer 170 covers a portion of the sidewall of the semiconductor pillar 120, and the top of the interlayer dielectric layer 170 is lower than the bottom of the drain doped layer 150.
The interlayer dielectric layer 170 provides for the subsequent removal of the gate material layer 305 exposed from the interlayer dielectric layer 170.
In addition, the interlayer dielectric layer 170 is used to achieve electrical isolation between adjacent devices.
Therefore, the material of the interlayer dielectric layer 170 is an insulating material. In this embodiment, the interlayer dielectric layer 170 is made of silicon oxide. In other embodiments, the interlayer dielectric layer may also be made of other insulating materials such as silicon nitride or silicon oxynitride.
Specifically, the step of forming the interlayer dielectric layer 170 includes: forming an interlayer dielectric material layer 175 overlying the gate material layer 305 (as shown in fig. 8); and etching back a part of the thickness of the interlayer dielectric material layer 175 to form an interlayer dielectric layer 170 covering a part of the sidewall of the gate material layer 30.
In this embodiment, a dry etching process is used to etch back the interlayer dielectric material layer 175 with a certain thickness. The dry etching process has anisotropic etching characteristics, and the top surface position of the interlayer dielectric layer 170 is easily controlled by selecting the dry etching process.
In this embodiment, the top of the interlayer dielectric layer 170 is lower than the bottom of the drain doping layer 150, so that the gate structure formed subsequently is isolated from the drain doping layer 150.
Specifically, the distance from the top of the interlayer dielectric layer 170 to the bottom of the drain doping layer 150 is 3nm to 5 nm.
Referring to fig. 10, the gate material layer 305 exposed by the interlayer dielectric layer 170 is removed (as shown in fig. 9), and a gate structure 300 is formed.
In this embodiment, a dry etching process is used to remove the gate material layer 305 exposed from the interlayer dielectric layer 170. The dry etching process facilitates precise control of the amount of gate material layer 305 removed and reduces damage to other layers.
With continuing reference to fig. 7, it should be noted that the method for forming a semiconductor structure further includes: after the isolation layer 160 is formed, a gate dielectric layer 200 is formed to conformally cover the semiconductor pillar 120 and the drain doping layer 150 before the gate material layer 305 is formed.
The gate dielectric layer 200 is used to electrically isolate the subsequent gate structure from the semiconductor pillar 120.
The subsequently formed gate structure is a metal gate structure, and thus the material of the gate dielectric layer 200 includes HfO2、ZrO2HfSiO, HfSiON, HfTaO, HfTiO, HfZrO and Al2O3One or more of them. In this embodiment, the gate dielectric layer 200 is made of HfO2。
In other embodiments, when the gate structure is a polysilicon gate structure, the material of the gate dielectric layer correspondingly includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, and amorphous carbon.
In this embodiment, the gate dielectric layer 200 is formed by an atomic layer deposition process. In other embodiments, the gate dielectric layer may also be formed by a chemical vapor deposition process.
Therefore, with continued reference to fig. 10, after the gate structure 300 is formed, the gate structure 300 exposes the gate dielectric layer 200 on the surface of the drain doping layer 150.
In this embodiment, the gate dielectric layer 200 on the surface of the drain doping layer 150 is retained, so that the gate dielectric layer 200 protects the drain doping layer 150, thereby better isolating the drain doping layer 150 from the gate structure 300.
Referring to fig. 11, after the gate structure 300 is formed, the method for forming the semiconductor structure further includes: a top dielectric layer 180 is formed overlying the interlevel dielectric layer 170 and the drain doped layer 150.
The top dielectric layer 180 is used to provide a process platform for the subsequent formation of conductive plugs. In addition, the top dielectric layer 180 also serves to achieve electrical isolation between adjacent transistors.
For this reason, in this embodiment, the material of the top dielectric layer 180 is silicon oxide. In other embodiments, the material of the top dielectric layer may also be other insulating materials such as silicon nitride or silicon oxynitride.
Specifically, the top dielectric layer 180 covers the interlayer dielectric layer 170 and the gate dielectric layer 200.
With continued reference to fig. 11, a drain plug 191 is formed on top of the drain doped layer 150, the drain plug 191 electrically connecting the drain doped layer 150.
The drain plug 191 serves to electrically connect the drain doping layer 150 to an external circuit.
Specifically, the step of forming the drain plug 191 includes: etching the top dielectric layer 180 and the gate dielectric layer 200, and forming through holes exposing the drain doping layer 150 in the top dielectric layer 180 and the gate dielectric layer 200; and filling a conductive material into the through hole, wherein the conductive material in the through hole is used as a drain plug 191.
The drain doping layer 150 covers the top of the semiconductor pillar 120 and surrounds a portion of the sidewall of the semiconductor pillar 120, which increases a process window for forming the through hole, and facilitates exposing the through hole to the drain doping layer 150.
In this embodiment, the material of the drain plug 191 is W. In other embodiments, the material of the drain plug may also be Al, Cu, Ag, Au, or the like.
In this embodiment, the forming method further includes: a gate plug 192 connected to the gate structure 300 and a source plug 193 electrically connected to the source doping layer 110 are formed.
The gate plug 192 is used to electrically connect the gate structure 300 to an external circuit, and the source plug 193 is used to electrically connect the source doped layer 110 to an external circuit.
Specifically, the source plug 193 is formed in the top dielectric layer 180 and the interlayer dielectric layer 170 on one side of the semiconductor pillar 120, and is connected to the source doping layer 110 on the isolation layer 160; the gate plug 192 is formed in the top dielectric layer 180, the interlayer dielectric layer 170 and the isolation layer 160 at the other side of the semiconductor pillar 120.
The gate plug 192 and the source plug 193 may be formed in the same step, and the forming method of the gate plug 192 and the source plug 193 is similar to the forming method of the drain plug 191, and thus, the description thereof is omitted.
Correspondingly, the invention also provides a semiconductor structure. Referring to fig. 11, a schematic structural diagram of an embodiment of a semiconductor structure of the present invention is shown.
The semiconductor structure includes: a substrate 100; a source doped layer 110 on the substrate 100; a semiconductor pillar 120 on the source doping layer 110; a drain doping layer 150 located at one side of the top of the semiconductor pillar 120, wherein the drain doping layer 150 covers the top of the semiconductor pillar 120 and surrounds a portion of the sidewall of the semiconductor pillar 120; a gate structure 300 surrounding a portion of the sidewall of the semiconductor pillar 120 and exposing the drain doping layer 150; and a drain plug 191 positioned on top of the drain doping layer 150 and electrically connected to the drain doping layer 150.
The substrate 100 is used to provide a process platform for forming VGAA transistors.
In this embodiment, the substrate 100 is a silicon substrate. In other embodiments, the material of the substrate may also be other materials such as germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, and the substrate may also be another type of substrate such as a silicon-on-insulator substrate or a germanium-on-insulator substrate.
The semiconductor pillar 120 is used to provide a channel of a transistor.
In this embodiment, the material of the semiconductor pillar 120 is silicon. In other embodiments, the material of the semiconductor pillar may also be germanium, silicon carbide, gallium arsenide, or indium gallium arsenide.
It should be noted that the height (not labeled) of the semiconductor pillars 120 should not be too small, and should not be too large. The drain doping layer 150 surrounds a portion of the sidewall of the semiconductor pillar 120 near the top, and if the height of the semiconductor pillar 120 is too small, in order to enable the height H (as shown in fig. 5) of the semiconductor pillar 120 surrounded by the drain doping layer 150 to meet the process requirement, the gate structure 300 on the sidewall of the semiconductor pillar 120 is too short, which easily causes the control capability of the gate structure 300 on the channel to be reduced, and also causes the subsequently formed channel region to be too short, which easily causes a short channel effect; if the height of the semiconductor pillars 120 is too large, the semiconductor pillars 120 are susceptible to collapse, and also the process difficulty in forming the semiconductor pillars 120 is increased. For this reason, in the present embodiment, the height (not labeled) of the semiconductor pillar 120 is 30nm to 200 nm.
The source doped layer 110 serves as a source of the VGAA transistor, and the drain doped layer 150 serves as a drain of the VGAA transistor.
The source doped layer 110 and the drain doped layer 150 are used for providing stress to a channel when the semiconductor structure operates, thereby improving carrier mobility of the transistor.
In this embodiment, the source doping layer 110 includes a first epitaxial layer doped with conductive ions, and the drain doping layer 150 includes a second epitaxial layer doped with conductive ions.
In this embodiment, taking the semiconductor structure as a PMOS transistor as an example, the conductive ions are P-type ions, the materials of the first epitaxial layer and the second epitaxial layer are silicon germanium, and the first epitaxial layer and the second epitaxial layer are used for providing a compressive stress effect for a channel region of the PMOS transistor. Wherein the P-type ions include B, Ga or In.
In other embodiments, when the semiconductor structure is an NMOS transistor, the conductive ions are N-type ions, the first epitaxial layer is made of silicon carbide or silicon phosphide, the second epitaxial layer is made of silicon carbide or silicon phosphide, and the first epitaxial layer and the second epitaxial layer are used for providing a tensile stress effect to a channel region of the NMOS transistor. Wherein the N-type ions comprise P, As or Sb.
In this embodiment, the drain doping layer 150 covers the top of the semiconductor pillar 120 and surrounds the drain doping layer 150 on a partial sidewall of the semiconductor pillar 120, and compared with the drain doping layer formed only on the top of the semiconductor pillar, the width of the drain doping layer 150 is increased in this embodiment, which correspondingly increases the top surface area of the drain doping layer 150, thereby increasing the process window for forming the drain plug 191, easily forming the drain plug 191 on the top of the drain doping layer 150, and improving the electrical connection effect between the drain plug 191 and the drain doping layer 150, thereby improving the performance of the VGAA transistor, for example: the contact resistance between the drain doping layer 150 and the drain plug 191 is reduced.
The thickness T1 (shown in fig. 5) of the drain doped layer 150 should not be too small or too large. If the thickness T1 of the drain doping layer 150 is too small, and the increase of the width of the drain doping layer 150 is too small, it is not beneficial to increase the process window for forming the drain plug, and it is not beneficial to improve the electrical connection effect between the drain plug 191 and the drain doping layer 150; if the thickness T1 of the drain doped layer 150 is too large, bridging between adjacent drain doped layers 150 is easily caused. For this reason, in the present embodiment, the thickness T1 of the drain doping layer 150 is 2nm to 5 nm.
The height H (as shown in fig. 5) of the semiconductor pillar 120 surrounded by the drain doped layer 150 is not too small and not too large. If the height H is too small, the difficulty in controlling the height H is easily increased; if the height H is too large, the gate structure 300 on the sidewall of the semiconductor pillar 120 is too short when the height of the semiconductor pillar 120 is constant, which may result in a decrease in the channel control capability of the gate structure 300, and may also result in a too short channel region of the transistor, which may result in a short channel effect. For this reason, in the present embodiment, the height H of the semiconductor pillar 120 surrounded by the drain doping layer 150 is 2nm to 6 nm.
The gate structure 300 is used to control the turning on and off of the channel region of the transistor.
In this embodiment, the gate structure 300 is a metal gate structure, and the gate structure 300 includes a work function layer 310 surrounding a portion of the sidewall of the semiconductor pillar 120 and a gate layer 320 covering the work function layer 310.
It should be noted that the gate layer 320 further extends to a portion of the source doping layer 160 on one side of the semiconductor pillar 120, so as to provide a process base for forming a gate plug electrically connected to the gate layer 320.
In this embodiment, taking the semiconductor structure as a PMOS transistor as an example, the material of the work function layer 310 is a P-type work function material, and the material of the work function layer 310 includes one or more of TiN, TaN, TaSiN, TaAlN, and TiAlN.
In other embodiments, when the semiconductor structure is an NMOS transistor, the material of the work function layer is an N-type work function material, and the material of the work function layer includes one or more of TiAl, Mo, MoN, AlN, and TiAlC.
In this embodiment, the material of the gate layer 320 is Al. In other embodiments, the material of the gate layer may also be W, Cu, Ag, Au, Pt, Ni, Ti, or the like.
In this embodiment, the top of the gate structure 300 is lower than the bottom of the drain doping layer 150, so that the gate structure 300 is isolated from the drain doping layer 150, thereby reducing the probability of bridging between the gate structure 300 and the drain doping layer 150.
It should be noted that the distance (not labeled) from the top of the gate structure 300 to the bottom of the drain doping layer 150 should not be too small, and should not be too large. If the distance is too small, the probability of bridging between the gate structure 300 and the drain doping layer 150 is correspondingly increased; if the distance is too large, the gate structure 300 is too short, which may result in a decrease in the channel control capability of the gate structure 300, and a short channel effect may be caused due to too short a subsequently formed channel region. For this reason, in the present embodiment, the distance from the top of the gate structure 300 to the bottom of the drain doping layer 150 is 3nm to 5 nm.
In this embodiment, the semiconductor structure further includes: and the gate dielectric layer 200 is positioned between the semiconductor pillar 120 and the gate structure 300 and conformally covers the top and the side wall of the drain doping layer 150 exposed by the gate structure 300.
The gate dielectric layer 200 is used to realize electrical isolation between the gate structure 300 and the semiconductor pillar 120.
The gate structure 300 is a metal gate structure, and thus the material of the gate dielectric layer 200 includes HfO2、ZrO2HfSiO, HfSiON, HfTaO, HfTiO, HfZrO and Al2O3One or more of them. In this embodiment, the gate dielectric layer 200 is made of HfO2。
In other embodiments, when the gate structure is a polysilicon gate structure, the material of the gate dielectric layer correspondingly includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, and amorphous carbon.
In this embodiment, the gate dielectric layer 200 conformally covers the top and the sidewall of the drain doping layer 150 exposed by the gate structure 300, and the gate dielectric layer 200 protects the drain doping layer 150, thereby achieving the isolation between the drain doping layer 150 and the gate structure 300.
In this embodiment, the semiconductor structure further includes: an isolation layer 160 located between the gate structure 300 and the source doped layer 110, wherein the isolation layer 160 covers a portion of the sidewall of the semiconductor pillar 120.
The isolation layer 160 is used to electrically isolate the gate structure 300 from the source doped layer 160.
Therefore, the material of the isolation layer 160 is an insulating material. Specifically, the material of the isolation layer 160 includes one or more of silicon oxide, silicon nitride, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride, and boron carbonitride. In this embodiment, the material of the isolation layer 160 is silicon oxide.
In this embodiment, the isolation layer 160 also covers the exposed source doping layer 110 of the semiconductor pillar 120.
Note that the thickness T2 (shown in fig. 6) of the isolation layer 160 should not be too small, nor too large. If the thickness T2 of the isolation layer 160 is too small, the electrical isolation effect of the isolation layer 160 on the gate structure 300 and the source doped layer 160 is easily reduced, and the probability of bridging between the gate structure 300 and the source doped layer 160 is high; if the thickness T2 of the isolation layer 160 is too large, the heights of the semiconductor pillars 120 exposed by the drain doping layer 150 and the isolation layer 160 are too small, and if it is ensured that the height H of the semiconductor pillar 120 surrounded by the drain doping layer 150 can meet the process requirements, the gate structures 300 on the sidewalls of the semiconductor pillars 120 are too short, which may cause the control capability of the gate structures 300 on the channel to be reduced, and may also cause the subsequently formed channel regions to be too short, which may cause the short channel effect. For this reason, in the present embodiment, the thickness T2 of the isolation layer 160 is 2nm to 10 nm.
In this embodiment, the semiconductor structure further includes: and an interlayer dielectric layer 170 covering the sidewall of the gate structure 300 and exposing the top of the gate structure 300.
The interlayer dielectric layer 170 is used to achieve electrical isolation between adjacent devices.
Therefore, the material of the interlayer dielectric layer 170 is an insulating material. In this embodiment, the interlayer dielectric layer 170 is made of silicon oxide. In other embodiments, the interlayer dielectric layer may also be made of other insulating materials such as silicon nitride or silicon oxynitride.
In this embodiment, the semiconductor structure further includes: and a top dielectric layer 180 covering the interlayer dielectric layer 170 and the drain doping layer 150.
The top dielectric layer 180 is used to provide a process platform for the formation of the conductive plug. In addition, the top dielectric layer 180 also serves to achieve electrical isolation between adjacent transistors.
For this reason, in this embodiment, the material of the top dielectric layer 180 is silicon oxide. In other embodiments, the material of the top dielectric layer may also be other insulating materials such as silicon nitride or silicon oxynitride.
Specifically, the top dielectric layer 180 covers the interlayer dielectric layer 170 and the gate dielectric layer 200.
The drain plug 191 serves to electrically connect the drain doping layer 150 to an external circuit.
In this embodiment, the drain plug 191 penetrates through the top dielectric layer 180 and the gate dielectric layer 200 on the top of the drain doping layer 150.
The process of forming the drain plug 191 generally includes a step of forming a via hole and a step of filling the via hole, and the drain doping layer 150 covers the top of the semiconductor pillar 120 and surrounds the drain doping layer 150 on a portion of the sidewall of the semiconductor pillar 120, which increases a process window for forming the via hole and facilitates exposing the via hole to the drain doping layer 150.
In this embodiment, the material of the drain plug 191 is W. In other embodiments, the material of the drain plug may also be Al, Cu, Ag, Au, or the like.
In this embodiment, the semiconductor structure further includes: a gate plug 192 connected to the gate structure 300, and a source plug 193 electrically connected to the source doped layer 110.
The gate plug 192 is used to electrically connect the gate structure 300 to an external circuit, and the source plug 193 is used to electrically connect the source doped layer 110 to an external circuit.
Specifically, the source plug 193 is located in the top dielectric layer 180 and the interlayer dielectric layer 170 on one side of the semiconductor pillar 120, and is connected to the source doping layer 110 located on the isolation layer 160; the gate plug 192 is located in the top dielectric layer 180, the interlayer dielectric layer 170 and the isolation layer 160 at the other side of the semiconductor pillar 120.
In this embodiment, for the specific description of the gate plug 192 and the source plug 193, reference may be made to the corresponding description of the drain plug 191, which is not repeated herein.
The semiconductor structure may be formed by the formation method described in the foregoing embodiment, or may be formed by another formation method. For a detailed description of the semiconductor structure in this embodiment, reference may be made to the corresponding description in the foregoing embodiments, and details of this embodiment are not repeated herein.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims (19)

1. A method of forming a semiconductor structure, comprising:
providing a substrate;
forming a source doping layer on the substrate;
forming a semiconductor pillar on the source doping layer;
forming a drain doping layer covering the top of the semiconductor column and surrounding partial side wall of the semiconductor column on one side of the top of the semiconductor column;
forming a gate structure which surrounds partial side walls of the semiconductor columns and exposes the drain doping layer;
and forming a drain plug at the top of the drain doping layer after the gate structure is formed, wherein the drain plug is electrically connected with the drain doping layer.
2. The method for forming a semiconductor structure according to claim 1, wherein in the step of forming the drain doping layer, a height of the semiconductor pillar surrounded by the drain doping layer is 2nm to 6 nm.
3. The method of forming a semiconductor structure according to claim 1, wherein in the step of forming the drain doping layer, the thickness of the drain doping layer is 2nm to 5 nm.
4. The method of forming a semiconductor structure of claim 1, wherein the drain doped layer is formed by a selective epitaxy process.
5. The method of forming a semiconductor structure according to claim 1, wherein after forming the semiconductor pillar and before forming the drain doping layer, the method further comprises: forming a protective layer on the source doping layer exposed out of the semiconductor pillar, wherein the protective layer covers part of the side wall of the semiconductor pillar;
and in the step of forming the drain doping layer, the drain doping layer covers the semiconductor columns exposed out of the protective layer.
6. The method of forming a semiconductor structure of claim 5, wherein forming the protective layer comprises:
forming a protective material layer on the source doping layer exposed from the semiconductor pillar;
and etching back the protective material layer with partial thickness to expose partial side walls of the semiconductor columns, and taking the residual protective material layer as the protective layer.
7. The method of forming a semiconductor structure of claim 5, wherein the material of the protective layer is a dielectric material;
after the drain doping layer is formed and before the gate structure is formed, the method further includes: and etching back the protective layer with partial thickness to expose partial side walls of the semiconductor columns, and taking the residual protective layer as an isolation layer.
8. The method of claim 1, wherein after forming the gate structure, a top of the gate structure is lower than a bottom of the drain dopant layer.
9. The method of claim 8, wherein a distance from a top of the gate structure to a bottom of the drain doped layer is 3nm to 5 nm.
10. The method of forming a semiconductor structure of claim 1, wherein forming the gate structure comprises:
forming a gate material layer conformally covering the semiconductor pillar, wherein the gate material layer also extends to a part of the source doping layer on one side of the semiconductor pillar;
forming an interlayer dielectric layer on the source doping layer, wherein the interlayer dielectric layer covers part of the side wall of the semiconductor column, and the top of the interlayer dielectric layer is lower than the bottom of the drain doping layer;
and removing the gate material layer exposed from the interlayer dielectric layer to form the gate structure.
11. The method of forming a semiconductor structure of claim 1, further comprising, prior to forming the gate structure: and forming a gate dielectric layer which conformally covers the semiconductor column and the drain doping layer.
12. A semiconductor structure, comprising:
a substrate;
the source doping layer is positioned on the substrate;
a semiconductor pillar located on the source doping layer;
the drain doping layer is positioned on one side of the top of the semiconductor column, covers the top of the semiconductor column and surrounds part of the side wall of the semiconductor column;
the grid structure surrounds partial side walls of the semiconductor columns and exposes the drain doping layer;
and the drain electrode plug is positioned at the top of the drain doping layer and is electrically connected with the drain doping layer.
13. The semiconductor structure of claim 12, wherein the semiconductor pillar surrounded by the drain doped layer has a height of 2nm to 6 nm.
14. The semiconductor structure of claim 12, wherein the thickness of the drain doped layer is 2nm to 5 nm.
15. The semiconductor structure of claim 12, wherein the drain doped layer comprises an epitaxial layer doped with conductive ions.
16. The semiconductor structure of claim 12, wherein the semiconductor structure further comprises: and the isolation layer is positioned between the gate structure and the source doping layer and covers part of the side wall of the semiconductor column.
17. The semiconductor structure of claim 12, wherein a top of the gate structure is lower than a bottom of the drain doping layer.
18. The semiconductor structure of claim 17, wherein a distance from a top of the gate structure to a bottom of the drain doped layer is 3nm to 5 nm.
19. The semiconductor structure of claim 12, wherein the semiconductor structure further comprises: and the gate dielectric layer is positioned between the semiconductor column and the gate structure and conformally covers the top and the side wall of the drain doping layer exposed by the gate structure.
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