CN114068394B - Method for forming semiconductor structure - Google Patents

Method for forming semiconductor structure Download PDF

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Publication number
CN114068394B
CN114068394B CN202010760778.8A CN202010760778A CN114068394B CN 114068394 B CN114068394 B CN 114068394B CN 202010760778 A CN202010760778 A CN 202010760778A CN 114068394 B CN114068394 B CN 114068394B
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layer
source
drain
cap layer
gate
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CN114068394A (en
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王楠
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76805—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics the opening being a via or contact hole penetrating the underlying conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H01L23/5283—Cross-sectional geometry

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Semiconductor Memories (AREA)

Abstract

A method of forming a semiconductor structure, comprising: providing a substrate, wherein the substrate comprises a shared contact area, a gate structure is arranged on the substrate, a gate cap layer is arranged at the top of the gate structure, source and drain doping areas are arranged at two sides of the gate structure, and a stacked source and drain interconnection layer and a stacked source and drain cap layer are arranged at the top of the source and drain doping areas; etching the source and drain cap layer or the gate cap layer of the shared contact region to form a first groove penetrating through the source and drain cap layer or the gate cap layer; forming a sacrificial layer in the first groove, wherein the etching resistance of the sacrificial layer is smaller than that of the source-drain cap layer; forming a top dielectric layer covering the sacrificial layer, the grid cap layer and the source drain cap layer; etching the top dielectric layer, the gate cap layer and the sacrificial layer at the top of the gate structure or the top dielectric layer, the sacrificial layer and the source drain cap layer in the shared contact region to form a second groove communicated with the first groove; a shared contact plug is formed in the first trench and the second trench. The invention improves the performance of the semiconductor structure.

Description

Method for forming semiconductor structure
Technical Field
The embodiment of the invention relates to the field of semiconductor manufacturing, in particular to a method for forming a semiconductor structure.
Background
With the continued development of integrated circuit fabrication technology, the demands on the degree of integration and performance of integrated circuits are becoming ever higher. In order to improve the integration level and reduce the cost, the critical dimensions of the components are continuously reduced, and the circuit density inside the integrated circuit is increasingly high, so that the wafer surface cannot provide enough area to manufacture the required interconnection line.
In order to meet the requirements of the interconnect lines with reduced critical dimensions, the different metal layers or the conduction between the metal layers and the substrate is realized through the interconnect structure. The interconnect structure includes an interconnect line and a contact hole plug formed within the contact opening. The contact hole plugs are connected with the semiconductor device, and the interconnection lines realize the connection between the contact hole plugs, so that a circuit is formed.
The contact hole plugs in the transistor structure comprise gate contact hole plugs on the surface of the gate structure, used for realizing connection between the gate structure and an external circuit, source and drain contact hole plugs on the surface of the source and drain doped regions, used for realizing connection between the source and drain doped regions and the external circuit, and shared contact plugs (share contact) used for electrically connecting the gate and the source and drain doped regions.
Currently, to achieve further reduction of transistor area, active gate contact plug (Contact Over Active Gate, COAG) processes are introduced. Compared with the traditional gate contact plug above the gate structure of the isolation region, the COAG process can enable the gate contact plug to be above the gate structure of an Active Area (AA), thereby further saving the Area of the chip.
Disclosure of Invention
The embodiment of the invention solves the problem of providing a method for forming a semiconductor structure, which improves the performance of the semiconductor structure.
In order to solve the above problems, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate, wherein a gate structure extending along a first direction is formed on the substrate, a gate cap layer is formed on the top of the gate structure, source and drain doping regions positioned in the substrate are formed on two sides of the gate structure, an active drain interconnection layer is formed on the top of the source and drain doping regions, and an active drain cap layer is formed on the top of the source and drain interconnection layer, wherein a region, which is used for forming a shared contact plug and electrically connected with the gate structure and the source and drain doping regions, on the substrate is used as a shared contact region; etching the source-drain cap layer or the gate cap layer in the shared contact region to form a first groove penetrating through the source-drain cap layer or the gate cap layer; forming a sacrificial layer in the first groove, wherein the etching resistance of the sacrificial layer is smaller than that of the source-drain cap layer; forming a top dielectric layer covering the sacrificial layer, the grid cap layer and the source drain cap layer; etching the top dielectric layer, the gate cap layer and the sacrificial layer on the top of the gate structure in the shared contact region, or etching the top dielectric layer, the sacrificial layer and the source drain cap layer on the top of the gate structure, and forming a second groove communicated with the first groove in the top dielectric layer and the gate cap layer; and forming a shared contact plug in the first groove and the second groove, wherein the shared contact plug is electrically connected with the grid structure and the source-drain doped region.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following advantages:
in the forming method provided by the embodiment of the invention, in a shared contact area, a source-drain cap layer or a gate cap layer is etched to form a first groove penetrating through the source-drain cap layer or the gate cap layer, and a sacrificial layer is formed in the first groove and is used for occupying the space of the first groove, the etching resistance of the sacrificial layer is smaller than that of the source-drain cap layer, then in the shared contact area, a top dielectric layer, the gate cap layer and the sacrificial layer at the top of the gate structure are etched, or alternatively, a top dielectric layer, the sacrificial layer and the source-drain cap layer at the top of the gate structure are etched, a second groove communicated with the first groove is formed in the top dielectric layer, the gate cap layer and the source-drain cap layer are usually made of materials with etching selectivity, so that by pre-etching the source-drain cap layer or the gate cap layer in the shared contact area, in order to form the first trench, correspondingly, when the second trench is formed subsequently, only the gate cap layer or the source drain cap layer which is not etched in the shared contact region is needed to be etched, namely, before the top dielectric layer is formed, one of the gate cap layer and the source drain cap layer is etched, so that the gate cap layer and the source drain cap layer are respectively etched in different processes, the etching resistance of the sacrificial layer is smaller than that of the source drain cap layer, and the sacrificial layer is easy to etch in the subsequent process of forming the second trench, therefore, the influence of transverse etching on the top dielectric layer is reduced in the process of forming the second trench, the cross section shape and the opening size of the second trench are ensured, the probability that the second trench exposes adjacent gate structures or source drain interconnection layers in other areas outside the shared contact region is correspondingly reduced, therefore, the probability of short circuit between the shared contact plug and other adjacent grid structures or source-drain interconnection layers is reduced, and the performance of the semiconductor structure is improved.
Drawings
FIGS. 1-4 are schematic views illustrating steps corresponding to one embodiment of a method for forming a semiconductor structure;
fig. 5 to 19 are schematic structural views corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention.
Detailed Description
After the active gate contact plug (Contact Over Active Gate, COAG) process is introduced at present, the formation difficulty of the shared contact plug is high, and the process risk is high. The reasons that the formation difficulty of the shared contact plug is high and the process risk is high are combined with a semiconductor structure to analyze.
Fig. 1 to 4 are schematic structural views corresponding to steps in an embodiment of a method for forming a semiconductor structure.
Referring to fig. 1, a substrate 10 is provided, a gate structure 20 is formed on the substrate 10, a gate cap layer 21 is formed on top of the gate structure 20, source-drain doped regions 30 are formed in the substrate 10 on both sides of the gate structure 20, a bottom dielectric layer (not shown) is formed on the substrate 10 on the side of the gate structure 20, the bottom dielectric layer covers the sidewalls of the gate structure 20 and the gate cap layer 21, and an active-drain interconnection layer 31 and an active-drain cap layer 32 on top of the active-drain interconnection layer 31 are formed in the bottom dielectric layer on top of the active-drain doped regions 30.
A region of the substrate 10, which is used to form a shared contact plug (share contact) electrically connecting the gate structure 20 and the source/drain doped region 30, is used as a shared contact region (not labeled).
With continued reference to fig. 1, a top dielectric layer 40 is formed overlying the gate cap layer 21 and the source drain cap layer 32.
A gate plug is then formed on top of the gate structure 20 through the top dielectric layer 40 and the gate cap layer 21, and the gate plug is formed on the active region, the gate plug being an active gate contact plug (Contact Over Active Gate, COAG). Further, source-drain plugs penetrating the top dielectric layer 30 and the source-drain cap layer 32 are subsequently formed on top of the source-drain interconnect layer 31.
In the COAG process, in order to reduce the bridging probability between the source and drain plugs and the gate structure 20 and between the gate plug and the source and drain interconnection layer 31, a higher etching selection ratio is provided between the gate cap layer 21 and the source and drain cap layer 32, so that the source and drain cap layer 32 can protect the source and drain interconnection layer 31 in the process of forming the gate plug, and the gate cap layer 21 can protect the gate structure 20 in the process of forming the source and drain plug.
Referring to fig. 2 to 4 in combination, in the shared contact region, a shared contact plug 60 (shown in fig. 4) penetrating the top dielectric layer 40, the gate cap layer 21 and the source drain cap layer 32 is formed, the shared contact plug 60 being in contact with the gate structure 20 and the source drain interconnection layer 31.
Specifically, the step of forming the shared contact plug 50 includes: as shown in fig. 2, the top dielectric layer 40 of the shared contact region is etched to form openings 41 exposing the gate cap layer 21 and the source drain cap layer 32; as shown in fig. 3, the gate cap layer 21 and the source-drain cap layer 32 at the bottom of the opening 41 are etched to form a shared contact hole 50 penetrating the top dielectric layer 40, the gate cap layer 21 and the source-drain cap layer 32, and the shared contact hole 50 exposes the gate structure 20 and the source-drain interconnection layer 31; as shown in fig. 4, a shared contact plug 60 is formed in the shared contact hole 50.
Because the gate cap layer 21 and the source drain cap layer 32 have a higher etching selectivity, after the top dielectric layer 40 is etched, the gate cap layer 21 and the source drain cap layer 32 need to be etched respectively by using different etching processes, and in the process of etching the gate cap layer 21 and the source drain cap layer 32, the opening 41 in the top dielectric layer 40 is easily affected by transverse etching, so that adverse effects are caused on the profile morphology of the opening 41, even the problem that the size of the opening 41 becomes larger occurs, and further misetching is easily caused on adjacent other gate cap layers 21 or source drain cap layers 32, and the probability of shorting the shared contact plug 60 with adjacent other gate structures 20 or source drain interconnection layers 31 is correspondingly increased.
Therefore, the formation of the shared contact plug 60 is difficult at present, and the performance of the semiconductor structure is easily degraded.
In order to solve the technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate, wherein a gate structure extending along a first direction is formed on the substrate, a gate cap layer is formed on the top of the gate structure, source and drain doping regions positioned in the substrate are formed on two sides of the gate structure, an active drain interconnection layer is formed on the top of the source and drain doping regions, and an active drain cap layer is formed on the top of the source and drain interconnection layer, wherein a region, which is used for forming a shared contact plug and electrically connected with the gate structure and the source and drain doping regions, on the substrate is used as a shared contact region; etching the source-drain cap layer or the gate cap layer in the shared contact region to form a first groove penetrating through the source-drain cap layer or the gate cap layer; forming a sacrificial layer in the first groove, wherein the etching resistance of the sacrificial layer is smaller than that of the source-drain cap layer; forming a top dielectric layer covering the sacrificial layer, the grid cap layer and the source drain cap layer; etching the top dielectric layer, the gate cap layer and the sacrificial layer on the top of the gate structure in the shared contact region, or etching the top dielectric layer, the sacrificial layer and the source drain cap layer on the top of the gate structure, and forming a second groove communicated with the first groove in the top dielectric layer and the gate cap layer; and forming a shared contact plug in the first groove and the second groove, wherein the shared contact plug is electrically connected with the grid structure and the source-drain doped region.
In the forming method provided by the embodiment of the invention, in a shared contact area, a source-drain cap layer or a gate cap layer is etched to form a first groove penetrating through the source-drain cap layer or the gate cap layer, and a sacrificial layer is formed in the first groove and is used for occupying the space of the first groove, the etching resistance of the sacrificial layer is smaller than that of the source-drain cap layer, then in the shared contact area, a top dielectric layer, the gate cap layer and the sacrificial layer at the top of the gate structure are etched, or alternatively, a top dielectric layer, the sacrificial layer and the source-drain cap layer at the top of the gate structure are etched, a second groove communicated with the first groove is formed in the top dielectric layer, the gate cap layer and the source-drain cap layer are usually made of materials with etching selectivity, so that by pre-etching the source-drain cap layer or the gate cap layer in the shared contact area, in order to form the first trench, correspondingly, when the second trench is formed subsequently, only the gate cap layer or the source drain cap layer which is not etched in the shared contact region is needed to be etched, namely, before the top dielectric layer is formed, one of the gate cap layer and the source drain cap layer is etched, so that the gate cap layer and the source drain cap layer are respectively etched in different processes, the etching resistance of the sacrificial layer is smaller than that of the source drain cap layer, and the sacrificial layer is easy to etch in the subsequent process of forming the second trench, therefore, the influence of transverse etching on the top dielectric layer is reduced in the process of forming the second trench, the cross section shape and the opening size of the second trench are ensured, the probability that the second trench exposes adjacent gate structures or source drain interconnection layers in other areas outside the shared contact region is correspondingly reduced, therefore, the probability of short circuit between the shared contact plug and other adjacent grid structures or source-drain interconnection layers is reduced, and the performance of the semiconductor structure is improved.
In order that the above objects, features and advantages of embodiments of the invention may be readily understood, a more particular description of the invention will be rendered by reference to specific embodiments thereof which are illustrated in the appended drawings.
Fig. 5 to 19 are schematic structural views corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention.
Referring to fig. 5 to 7 in combination, fig. 5 is a top view, fig. 6 is a cross-sectional view of fig. 5 along A1A2 cut line, fig. 7 is a cross-sectional view of fig. 5 along A1B 2 cut line, a substrate (not shown) is provided, a gate structure 200 extending in a first direction (as shown in a Y direction in fig. 5) is formed on the substrate, a gate cap layer 240 is formed on top of the gate structure 200, source and drain doped regions 210 are formed on both sides of the gate structure 200 within the substrate, a source and drain interconnection layer 220 is formed on top of the source and drain doped regions 210, and a source and drain cap layer 230 is formed on top of the source and drain interconnection layer 220, wherein a region of the substrate, which is used to form a shared contact plug for electrically connecting the gate structure 200 and the source and drain doped regions 210, serves as a shared contact region 100S.
For ease of illustration, fig. 5 illustrates only the fin 110, the gate cap 240, and the source drain cap 230.
The substrate is used for providing a process platform for a subsequent process.
In this embodiment, the base is used to form a fin field effect transistor (FinFET), and thus the base includes a substrate 100 and a fin 110 protruding from the substrate 100. In other embodiments, when the base is used to form a planar field effect transistor, the base is correspondingly a planar substrate.
In this embodiment, the substrate 100 is a silicon substrate.
In other embodiments, the substrate may also be a substrate of other material types. For example, the material of the substrate may be germanium, silicon carbide, gallium arsenide, indium gallium arsenide, or other materials, and the substrate may also be a silicon-on-insulator substrate or another type of substrate such as a germanium-on-insulator substrate.
In this embodiment, the material of the fin 110 is the same as the material of the substrate 100.
In this embodiment, a region on the substrate for forming a shared contact plug electrically connecting the gate structure 200 and the source/drain doped region 210 is used as the shared contact region 100S.
Specifically, the direction that is parallel to the substrate surface and perpendicular to the first direction is a second direction (as shown in the X direction in fig. 5), and the shared contact region 100S extends along the second direction.
As an example, the substrate is used to form an SRAM (Static Random Access Memory ) device. Depending on the design requirements of the SRAM device, portions of the gate structure 200 and the source drain doped region 210 need to be electrically connected by a shared contact plug.
In this embodiment, the method for forming a semiconductor structure further includes: after the fin 110 is formed, an isolation layer 101 is formed on the substrate 100 exposed by the fin 110, and the isolation layer 101 covers a portion of the sidewall of the fin 110.
The isolation layer 101 is used to isolate adjacent devices. The material of the isolation layer 101 may be silicon oxide, silicon nitride or silicon oxynitride. In this embodiment, the material of the isolation layer 101 is silicon nitride.
The gate structure 200 is used to control the turn-on or turn-off of the conduction channel during operation of the device.
In this embodiment, the gate structure 200 is located on the isolation layer 101, and the gate structure 200 spans across the fin 110 and covers a portion of the top surface and a portion of the sidewall of the fin 110.
In this embodiment, the gate structure 110 is a metal gate structure, and the gate structure 200 includes a high-k gate dielectric layer (not shown), a work function layer (not shown) on the high-k gate dielectric layer, and a gate electrode layer (not shown) on the work function layer.
The high-k gate dielectric layer is made of a high-k dielectric material, wherein the high-k dielectric material is a dielectric material with a relative dielectric constant larger than that of silicon oxide. Specifically, the material of the high-k gate dielectric layer can be selected from HfO 2 、ZrO 2 HfSiO, hfSiON, hfTaO, hfTiO, hfZrO or Al 2 O 3 Etc.
The work function layer is used to adjust the threshold voltage of the formed transistor. When the PMOS transistor is formed, the work function layer is a P-type work function layer, and the material of the P-type work function layer comprises one or more of TiN, taN, taSiN, taAlN and TiAlN; when the NMOS transistor is formed, the work function layer is an N-type work function layer, and the material of the N-type work function layer comprises one or more of TiAl, mo, moN, alN and TiAlC.
The gate electrode layer is used for electrically leading out the gate structure 200. In this embodiment, the material of the gate electrode layer is Al, cu, ag, au, pt, ni, ti or W.
In this embodiment, the source-drain doped regions 210 are located in the fin 110 at two sides of the gate structure 200.
Specifically, adjacent gate structures 200 share a source-drain doped region 210.
In this embodiment, the source-drain doped region 210 is formed in the substrate of the shared contact region 100S.
When forming an NMOS transistor, the source-drain doped region 210 includes a stress layer doped with N-type ions, where the stress layer is made of Si or SiC, and the stress layer provides a tensile stress for a channel region of the NMOS transistor, so As to facilitate improving carrier mobility of the NMOS transistor, and the N-type ions are P ions, as ions, or Sb ions; when forming a PMOS transistor, the source-drain doped region 210 includes a stress layer doped with P-type ions, where the stress layer is made of Si or SiGe, and the stress layer provides compressive stress to the channel region of the PMOS transistor, so as to facilitate improving carrier mobility of the PMOS transistor, and the P-type ions are B ions, ga ions, or In ions.
In this embodiment, a sidewall 205 is further formed on the sidewall of the gate structure 200.
The sidewall 205 is used to define a formation region of the source/drain doped region 210, and the sidewall 205 is also used to protect the sidewall of the gate structure 200. The side wall 205 may have a single-layer structure or a stacked-layer structure, and the material of the side wall 205 includes one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride oxide, silicon oxynitride, boron nitride, and boron carbonitride. As an example, the side wall 205 is a single-layer structure, and the material of the side wall 205 is silicon nitride.
It should be further noted that a bottom dielectric layer (not shown) is further formed on the substrate at the side of the gate structure 200, and the top of the bottom dielectric layer is flush with the top of the gate cap layer 240 and the source/drain cap layer 230.
The bottom dielectric layer is used to isolate adjacent devices and also to electrically isolate between the source and drain interconnect layers 220. In this embodiment, the bottom dielectric layer is an interlayer dielectric layer (Inter Layer Dielectric, ILD).
The bottom dielectric layer is made of an insulating material, and the material of the bottom dielectric layer comprises one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride and silicon oxycarbonitride. In this embodiment, the material of the bottom dielectric layer is silicon nitride.
The source-drain interconnection layer 220 is in contact with the source-drain doped region 210, so as to electrically connect the source-drain doped region 210 with an external circuit or other interconnection structure.
In this embodiment, a source-drain plug and a shared contact plug that are in contact with the source-drain interconnect layer 220 are subsequently formed on the source-drain interconnect layer 220, and the source-drain plug and the shared contact plug are electrically connected to the source-drain doped region 210 through the source-drain interconnect layer 220.
In this embodiment, the material of the source-drain interconnection layer 220 is copper. The lower resistivity of copper is beneficial to improving the signal delay of the back-end RC, improving the processing speed of the chip, reducing the resistance of the source-drain interconnection layer 220 and correspondingly reducing the power consumption. In other embodiments, the material of the source-drain interconnection layer may be a conductive material such as tungsten or cobalt.
After a top dielectric layer is formed on the bottom dielectric layer, a gate plug contacting the gate structure 200 is formed on top of the gate structure 200 in an Active Area (AA), and a source-drain cap layer 230 is located on the top surface of the source-drain interconnection layer 220, so as to protect the source-drain interconnection layer 220 during the formation of the gate plug, thereby being beneficial to reducing the damage of the source-drain interconnection layer 220 and the probability of shorting the gate plug and the source-drain interconnection layer 220.
The source-drain cap layer 230 is made of a material with higher etching selectivity to the gate cap layer 240, the side wall 205, the bottom dielectric layer and the subsequently formed top dielectric layer, so that the source-drain cap layer 230 can protect the source-drain interconnection layer 220.
In this embodiment, the material of the source-drain cap layer 230 includes one or more of silicon nitride, silicon carbide, silicon carbonitride, silicon oxynitride, silicon nitride oxide, boron nitride and boron carbonitride.
Specifically, the source-drain cap 230 and the sidewall 205 are made of different materials.
As an example, the source-drain cap layer 230 is made of silicon carbide.
After a top dielectric layer is formed on the bottom dielectric layer, a source-drain plug contacting the source-drain interconnection layer 220 is formed on top of the source-drain interconnection layer 220, and a gate cap layer 240 is located on the top surface of the gate structure 200, for protecting the gate structure 200, so as to reduce the damage of the gate structure 200 and the probability of shorting the source-drain plug with the gate structure 200.
The gate cap layer 240 is made of a material having etching selectivity to the source/drain cap layer 230, the bottom dielectric layer, and the subsequently formed top dielectric layer, so as to facilitate ensuring that the source/drain cap layer 230 can protect the gate structure 200.
In this embodiment, the material of the gate cap layer 240 includes one or more of silicon nitride, silicon carbide, silicon carbonitride, silicon oxynitride, silicon nitride oxide, boron nitride and boron carbonitride.
Specifically, the gate cap layer 240 and the source drain cap layer 230 are of different materials.
As an example, the material of the gate cap layer 240 is silicon nitride.
The materials of the gate cap layer 240 and the side wall 205 are the same, so that when the shared contact hole is formed later, the side wall 205 can be etched while the gate cap layer 240 is etched, thereby reducing the complexity of the etching process. Moreover, the formation process of the semiconductor structure adopts less film materials, which is also beneficial to reducing the complexity of the process.
In other embodiments, different materials may be used for the gate cap layer and the sidewall.
As an example, the gate structure 200 is formed by a process of forming a gate electrode layer (high k last metal gate last) after forming a high-k gate dielectric layer, and thus, the sidewall 205 covers the sidewalls of the gate structure 200 and the gate cap 240.
Specifically, after forming the gate structure 200 in the bottom dielectric layer, etching back a portion of the gate structure 200; after etching back a portion of the thickness of the gate structure 200, a gate cap layer 240 is formed in the region enclosed by the bottom dielectric layer and the remaining gate structure 200.
The step of forming the gate cap layer 240 includes a step of depositing a gate cap material layer and a step of planarizing the gate cap material layer (e.g., a chemical mechanical polishing process) sequentially.
In this embodiment, after the gate cap layer 240 is formed, the source-drain interconnection layer 220 and the source-drain cap layer 230 are formed.
Specifically, the step of forming the source-drain interconnection layer 220 includes: etching the bottom dielectric layer above the source-drain doped region 210 to form an opening exposing the source-drain doped region 210; forming an initial source-drain interconnect layer (not shown) in the opening, the top surface of the initial source-drain interconnect layer being flush with the top surface of the gate cap layer 240; and etching back a part of the original source-drain interconnection layer to form a source-drain interconnection layer 220.
Correspondingly, a source-drain cap material layer is filled in the area surrounded by the source-drain interconnection layer 220 and the side wall 205, the top surface of the gate cap layer 240 is used as a stop position, the source-drain cap material layer is subjected to planarization, and the remaining source-drain cap material layer after the planarization is used as the source-drain cap layer 230.
Referring to fig. 8 to 10 in combination, fig. 8 is a top view, fig. 9 is a cross-sectional view taken along line A1A2 in fig. 8, and fig. 10 is a cross-sectional view taken along line B1B2 in fig. 8, in the shared contact region 100S, the source and drain cap layer 230 or the gate cap layer 240 is etched to form a first trench 310 penetrating the source and drain cap layer 230 or the gate cap layer 240.
The first trench 310 is used to provide a spatial location for the subsequent formation of a sacrificial layer.
After the top dielectric layer is formed on the bottom dielectric layer, a shared contact plug is formed in the shared contact region 100S, and the shared contact plug electrically connects the gate structure 200 and the source/drain doped region 210, so, in order to form the shared contact plug, after etching the top dielectric layer, not only the source/drain cap layer 230 of the shared contact region 100S, but also the gate cap layer 240 of the shared contact region 100S needs to be etched, so as to form a shared contact trench penetrating through the source/drain cap layer 230 and the gate cap layer 240 of the shared contact region 100S, wherein a high etching selection ratio is provided between the source/drain cap layer 230 and the gate cap layer 240, which results in a high difficulty in an etching process when forming the shared contact trench.
Therefore, in this embodiment, before the top dielectric layer is formed, the source-drain cap layer 230 or the gate cap layer 240 is etched first, so that the drain cap layer 230 and the gate cap layer 240 are etched respectively in different processes, and accordingly, only one of the drain cap layer 230 and the gate cap layer 240 needs to be etched after the top dielectric layer is etched later, so that the influence of lateral etching on the subsequent top dielectric layer is reduced.
In this embodiment, the etching of the source-drain cap layer 230 to form the first trench 310 is taken as an example.
Specifically, the step of forming the first trench 310 includes: in the shared contact region 100S, the source-drain cap layer 230 and the source-drain interconnection layer 220 are sequentially etched, so as to form a first trench 310 penetrating the source-drain cap layer 230 and the source-drain interconnection layer 220.
Wherein the step of forming the first trench 310 further comprises: before etching, a first mask layer is formed on the gate cap layer 240, the side wall 205, the source/drain cap layer 230 and the bottom dielectric layer, where the first mask layer has a first mask opening exposing the source/drain cap layer 230 of the shared contact region 100S.
Correspondingly, etching is performed along the first mask opening by taking the first mask layer as a mask, so as to form a first groove 310; after forming the first trench 310, the method further includes: and removing the first mask layer.
As an example, the material of the first mask layer is photoresist.
It should be noted that, the source-drain cap layer 230 is made of a material having etching selectivity to the gate cap layer 240, the sidewall 205 and the bottom dielectric layer, so that the probability of damage to the gate cap layer 240, the sidewall 205 and the bottom dielectric layer is low during the process of forming the first trench 310, which correspondingly increases the process window for forming the first mask opening.
For example, along the second direction, the first mask opening may further expose the sidewalls 205 at both sides of the source/drain cap 230 or the gate cap 240 of the shared contact region 100S.
In the process of forming the semiconductor structure, according to design requirements, the step of cutting the source-drain interconnection layer 220 along the first direction is included, so that the first trench 310 is formed by etching the source-drain cap layer 230 and the source-drain interconnection layer 220, so that the first trench 310 can be formed and the cutting process of the source-drain interconnection layer 220 by using the same mask can be performed, thereby being beneficial to reducing the process cost.
Specifically, the source-drain doped region 210 is formed in the substrate of the shared contact region 100S, and thus, the first trench 310 exposes the source-drain doped region 210.
In other embodiments, only the source-drain cap layer may be etched to form the first trench exposing the source-drain interconnection layer according to the process requirements.
In this embodiment, an anisotropic dry etching process is used to etch the first trench 310.
The dry etching process has higher process controllability and is easy to adjust the etching selection ratio between different film layers. In addition, during the dry etching process, the source-drain cap layer 230 and the source-drain interconnection layer 220 can be etched in sequence in the same etching equipment by adjusting etching gas and etching parameters, so that the process is simple and a conversion machine is not required. In addition, the anisotropic dry etching process has the characteristic of anisotropic etching, that is, the longitudinal etching rate of the etching process is greater than the transverse etching rate of the etching process, so that the opening size of the first trench 310 along the first direction is beneficial to precisely controlling, the shape quality of the side wall of the first trench 310 is improved, and the damage probability of the side wall 205 can be reduced.
The opening size of the first groove 310 is not too small nor too large in the first direction. If the opening size of the first trench 310 is too small, not only is the difficulty of the etching process for forming the first trench 310 increased, but also the aspect ratio of the first trench 310 is easily caused to be too large, thereby increasing the difficulty of forming a sacrificial layer in the first trench 310 later. For this reason, in the present embodiment, the opening size of the first trench 310 is 16 nm to 30 nm along the first direction. For example, the opening size of the first trench 310 is 20 nm or 25 nm along the first direction.
As an example, in the shared contact region 100S, two source-drain doped regions 210 are formed on one side of the gate structure 200, and the first trench 310 exposes the top and the sidewall of one of the source-drain doped regions 210 and exposes the sidewall of the other of the source-drain doped regions 210. In other embodiments, when the opening size of the first trench along the first direction is larger, the first trench exposes the tops of the two source-drain doped regions.
Referring to fig. 11 to 13 in combination, fig. 11 is a top view, fig. 12 is a cross-sectional view taken along line A1A2 in fig. 11, and fig. 13 is a cross-sectional view taken along line B1B2 in fig. 11, a sacrificial layer 320 is formed in the first trench 310, and the etching resistance of the sacrificial layer 320 is less than that of the source drain cap layer 230.
The sacrificial layer 320 occupies the space of the first trench 310, thereby providing a process basis for a subsequent process.
Specifically, a top dielectric layer covering the sacrificial layer 320, the gate cap layer 240 and the source drain cap layer 230 is subsequently formed, and in the shared contact region 100S, the top dielectric layer on top of the gate structure 200, the gate cap layer 240 and the sacrificial layer 320 are etched, or the top dielectric layer on top of the gate structure 200, the sacrificial layer 320 and the source drain cap layer 230 are etched, and a second trench communicating with the first trench 310 is formed in the top dielectric layer. In this embodiment, before the top dielectric layer is formed, one of the gate cap layer 240 and the source/drain cap layer 230 is etched first, so that the gate cap layer 240 and the source/drain cap layer 230 are etched respectively in different processes, and the etching resistance of the sacrificial layer 320 is smaller than that of the source/drain cap layer 230, and in the subsequent process of forming the second trench, the sacrificial layer 320 is easy to be etched, so that in the process of forming the second trench, the top dielectric layer is advantageously reduced from being affected by lateral etching, the cross-sectional shape and the opening size of the second trench are ensured, and the probability that the second trench exposes the adjacent gate structure 200 or the source/drain interconnection layer 220 in other areas outside the shared contact area 100S is correspondingly reduced, so that the probability that the shared contact plug is shorted with the adjacent other gate structure 200 or the source/drain interconnection layer 220 is reduced, and the performance of the semiconductor structure is further improved.
Accordingly, the sacrificial layer 320 is made of a material having a higher etching selectivity than the gate cap layer 240 and the source/drain cap layer 230, so that damage to the gate cap layer 240 or the source/drain cap layer 230 in other regions is reduced when the sacrificial layer 320 is etched later.
In addition, in this embodiment, the material of the sacrificial layer 320 is selected as follows: and when the top dielectric layer is etched later, the etching selectivity ratio between the top dielectric layer and the sacrificial layer 320 is less than 3:1. The etch rates of the top dielectric layer and the sacrificial layer 320 are close to each other, further facilitating the sacrificial layer 320 to be etched. For example, during etching of the top dielectric layer, sacrificial layer 320 is etched.
Specifically, the materials of the sacrificial layer 320, the gate cap layer 240, and the source drain cap layer 230 are different.
In this embodiment, the material of the sacrificial layer 320 is a dielectric material. By selecting a dielectric material, it is convenient to be able to preserve a part of the width of the sacrificial layer 320 according to the process requirements when forming the second trench later, which is correspondingly advantageous for improving the process window when forming the second trench.
Specifically, the dielectric material includes one or more of silicon oxide, aluminum oxide, and titanium oxide. As one example, the dielectric material is silicon oxide. The cost of silicon oxide is lower and the process compatibility is higher.
Specifically, the step of forming the sacrificial layer 320 includes: filling a sacrificial material layer (not shown) in the first trench 310; and taking the top of the gate cap layer 240 or the source drain cap layer 230 as a stop position, performing planarization treatment on the sacrificial material layer, and reserving the remaining sacrificial material layer in the first trench 310 as a sacrificial layer 320.
In this embodiment, a chemical vapor deposition process may be used to fill the first trench 310 with a sacrificial material layer, and a chemical mechanical polishing process may be used to planarize the sacrificial material layer.
The hardness and the density of the gate cap layer 240 and the source drain cap layer 230 are higher, so that the gate cap layer 240 and the source drain cap layer 230 can both better function to define the stop position of the planarization process.
Referring to fig. 14 and 15 in combination, fig. 14 is a cross-sectional view based on fig. 12, and fig. 15 is a cross-sectional view based on fig. 13, forming a top dielectric layer 103 covering the sacrificial layer 320, the gate cap layer 240, and the source drain cap layer 230.
The top dielectric layer 103 is used to jointly realize electrical isolation among the subsequent gate plug, the source-drain plug and the shared contact plug with the bottom dielectric layer.
The material of the top dielectric layer 103 is a dielectric material, and the material of the top dielectric layer 103 includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride and silicon oxycarbonitride.
In this embodiment, a deposition process (e.g., a chemical vapor deposition process) is used to form the material of the top dielectric layer 103.
The first trench 310 is filled with the sacrificial layer 320, so that the top surface of the top dielectric layer 103 has a higher flatness.
Referring to fig. 16 and 17 in combination, fig. 16 is a cross-sectional view based on fig. 14, and fig. 17 is a cross-sectional view based on fig. 15, in the shared contact region 100S, a top dielectric layer 103, a gate cap layer 240, and a sacrificial layer 320 on top of the gate structure 200 are etched, and a second trench 330 in communication with the first trench 310 is formed in the top dielectric layer 103 and the gate cap layer 240.
The second trenches 330 and the first trenches 310 constitute shared contact trenches (not shown) to provide spatial locations for subsequent formation of shared contact plugs.
Specifically, the step of forming the second trench 330 further includes: a second mask layer is formed on the top dielectric layer 103 before etching, the second mask layer having a second mask opening (not shown) exposing the top dielectric layer 103 of the shared contact region 100S.
Correspondingly, etching is performed along the second mask opening by taking the second mask layer as a mask, so as to form a second trench 330; after forming the second trench 330, the method further includes: and removing the second mask layer.
During the process of forming the second trench 330, the sidewall 205 in the shared contact region 100S is also etched. The remaining sidewall 205 in the shared contact region 100S is made flush with the top of the gate structure 200 by etching the sidewall 205, so that the material of the shared contact plug is easily filled into the second trench 330 and the first trench 310.
As an example, the material of the second mask layer is photoresist.
It should be noted that, the gate cap layer 240 is made of a material having etching selectivity to the source/drain cap layer 230, the bottom dielectric layer, and the top dielectric layer 103, so that the probability of damage to the source/drain cap layer 230, the bottom dielectric layer, and the top dielectric layer 103 during the formation of the second trench 330 is low, which correspondingly increases the process window for forming the second mask opening.
For example, along the second direction, the second trench 330 may also expose a portion of the top of the source-drain cap 230 adjacent to the shared contact region 100S.
In this embodiment, the etching resistance of the sacrificial layer 320 is smaller than that of the source-drain cap layer 230, and compared with the scheme that after etching the top dielectric layer, the gate cap layer and the source-drain cap layer are etched respectively to form a shared contact trench penetrating through the top dielectric layer, the gate cap layer and the source-drain cap layer, in the process of forming the second trench 330, the sacrificial layer 320 is easy to etch, which is beneficial to reducing the influence of lateral etching on the top dielectric layer 103, so that the cross-sectional shape and the opening size of the second trench 330 are ensured, and the probability that the second trench 330 exposes the adjacent gate structure 200 or the source-drain interconnection layer 220 in other areas outside the shared contact area 100S is correspondingly reduced, thereby reducing the probability that the subsequent shared contact plug is shorted with the adjacent other gate structure 200 or the source-drain interconnection layer 220, and further improving the performance of the semiconductor structure.
In this embodiment, since the top dielectric layer 103 is less affected by the lateral etching during the process of forming the second trench 330, a mask (mask) can be used to define the shape and position of the second trench 330, so as to avoid an increase in the number of masks.
In this embodiment, the second trench 330 is formed by etching using an anisotropic dry etching process.
The dry etching process has higher process controllability and is easy to adjust the etching selection ratio between different film layers. In addition, during the dry etching process, the top dielectric layer 103, the gate cap layer 240 and the sacrificial layer 320 can be etched in the same etching apparatus by adjusting etching gas and etching parameters, so that the process is simple and a conversion machine is not required. In addition, the anisotropic dry etching process has the characteristic of anisotropic etching, namely, the longitudinal etching rate of the etching process is larger than the transverse etching rate of the etching process, so that the opening sizes of the second groove 330 along the first direction and the second direction are controlled accurately, and the shape and quality of the side wall of the second groove 330 are improved.
In this embodiment, in the step of forming the second trench 330, the etching selectivity of the sacrificial layer 320 and the gate cap layer 240 is greater than 5:1, and the etching selectivity of the sacrificial layer 320 and the source drain cap layer 230 is greater than 5:1, so as to reduce etching damage to the gate cap layer 240 or the source drain cap layer 230 in other regions except the shared contact region 100S.
In this embodiment, the opening size of the second trench 330 is larger than the opening size of the first trench 310 along the first direction.
The first trench 310 and the second trench 330 are formed in different processes, and the opening size of the second trench 330 is larger than the opening size of the first trench 310, so that in the process of forming the second trench 330, the requirement on overlay accuracy can be reduced, and the bottom of the second trench 330 and the top of the first trench 310 can be easily communicated.
In this embodiment, after the second trench 320 is formed, a part of the width of the sacrificial layer 320 remains on the sidewall of the second trench 320 facing the boundary of the shared contact region 100S (as shown in fig. 8) in the second direction.
By reserving a part of the sacrificial layer 320, the risk of the process of forming the second trench 320, that is, the probability of damaging the gate cap layer 240 or the sidewall 205 adjacent to the shared contact region 100S in the second direction, is reduced, so that the probability of shorting the shared contact plug formed in the second trench 320 with the adjacent gate structure 200 is reduced.
It should be noted that the width of the residual sacrificial layer 320 is not too small or too large. If the width of the remaining sacrificial layer 320 is too small, it is easy to increase the probability of damage of the gate cap layer 240 or the sidewall 205 adjacent to the shared contact region 100S in the second direction, thereby increasing the probability of shorting of the subsequent shared contact plug to the adjacent gate structure 200; if the width of the remaining sacrificial layer 320 is too large, the remaining space of the first trench 310 is smaller, so as to reduce the contact area between the subsequent shared contact plug and the source/drain doped region 210, which correspondingly leads to an increase in contact resistance. For this reason, in the present embodiment, the width of the residual sacrificial layer 320 is 2 nm to 10 nm. For example, the width of the residual sacrificial layer 320 is 3 nm, 5 nm, 7 nm, or 9 nm.
In this embodiment, the first trench 310 is formed by etching the source-drain cap layer 230.
In other embodiments, the first trench may also be formed by etching the gate cap layer of the shared contact region.
Specifically, in this embodiment, the step of forming the first trench includes: and in the shared contact region, sequentially etching the gate cap layer, the side wall and the gate structure to form a first groove penetrating through the gate cap layer and the gate structure.
In the process of forming the semiconductor structure, according to design requirements, the method comprises the step of cutting off the gate structure along the first direction, so that the first groove is formed by etching the gate cap layer and the gate structure, and the same photomask (mask) can be used for cutting off the gate structure and forming the first groove, thereby being beneficial to reducing the process cost.
Correspondingly, a second groove is formed by etching the top dielectric layer, the sacrificial layer and the source drain cap layer at the top of the gate structure.
Referring to fig. 18 and 19 in combination, fig. 18 is a cross-sectional view based on fig. 16, and fig. 19 is a cross-sectional view based on fig. 17, a shared contact plug 340 is formed in the first trench 310 and the second trench 330, the shared contact plug 340 electrically connecting the gate structure 200 and the source drain doped region 210.
The shared contact plug 340 is electrically connected to the gate structure 200 and the source-drain doped region 210, so that the gate structure 200 and the source-drain doped region 210 can be connected to a common potential, thereby meeting the requirement of device operation.
Specifically, the step of forming the shared contact plug 340 includes: filling the first trenches 310 and the second trenches 330 with a conductive material, wherein the conductive material also covers the top dielectric layer 103; and flattening the conductive material by taking the top surface of the top dielectric layer 103 as a stop position, and taking the rest conductive material as a shared contact plug 340.
In this embodiment, the process of filling the first trench 310 and the second trench 330 with the conductive material includes one or more of an electrochemical plating process, a physical vapor deposition process and a chemical vapor deposition process.
In this embodiment, a chemical mechanical polishing process is used to planarize the conductive material.
In this embodiment, the material of the shared contact plug 340 is copper. The lower resistivity of copper is beneficial to improving the signal delay of the back RC, improving the processing speed of the chip, reducing the resistance of the shared contact plug 340 and correspondingly reducing the power consumption. In other embodiments, the material of the shared contact plug may also be tungsten or cobalt.
The forming method further includes: forming a gate plug (not shown) penetrating the top dielectric layer 103 and the gate cap layer 240 on top of the gate structure 200 in other regions than the shared contact region 100S, the gate plug being in contact with the gate structure 200; in other regions than the shared contact region 100S, source-drain plugs (not shown) penetrating the source-drain cap layer 230 over the source-drain interconnect layer 220 are formed, the source-drain plugs being in contact with the source-drain interconnect layer 220.
The gate plug is used to make electrical connection between the gate structure 200 and an external circuit or other interconnect structure, and the source drain plug is used to make electrical connection between the source drain doped region 210 and an external circuit or other interconnect structure.
In this embodiment, the gate plug is formed above the gate structure 200 in the active region, that is, the gate plug is an active gate contact plug (Contact Over Active Gate, COAG), and compared with the scheme that the gate plug contacts the gate structure in the isolation region, the embodiment omits the portion of the gate structure 200 in the isolation region, which is beneficial to saving the area of the chip and realizing further reduction of the chip size.
Specifically, the step of forming the gate plug includes: etching the top dielectric layer 103 and the gate cap layer 240 in the non-shared contact region (i.e., in other regions than the shared contact region 100S) to form a gate contact hole (not shown) exposing the top of the gate structure 200; and forming a gate plug in the gate contact hole.
The gate cap layer 240 and the source/drain cap layer 230 have a higher etching selectivity, so that the source/drain cap layer 230 protects the source/drain interconnection layer 220 during the process of forming the gate contact hole, thereby reducing the probability of shorting the gate plug and the source/drain interconnection layer 220.
Specifically, the step of forming the source drain plug includes: etching the top dielectric layer 103 and the source-drain cap layer 230 in the non-shared contact region (i.e., in the other region except the shared contact region 100S) to form a source-drain contact hole (not shown) exposing the top of the source-drain interconnection layer 220; and forming a source-drain plug in the source-drain contact hole.
Similarly, the gate cap layer 240 and the source/drain cap layer 230 have a higher etching selectivity, so that the gate cap layer 240 protects the gate structure 200 during the process of forming the source/drain contact hole, thereby reducing the probability of shorting the source/drain plug with the gate structure 200.
The specific descriptions of the gate plug and the source drain plug are not repeated here.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.

Claims (16)

1. A method of forming a semiconductor structure, comprising:
providing a substrate, wherein a gate structure extending along a first direction is formed on the substrate, a gate cap layer is formed on the top of the gate structure, source and drain doping regions positioned in the substrate are formed on two sides of the gate structure, an active drain interconnection layer is formed on the top of the source and drain doping regions, and an active drain cap layer is formed on the top of the source and drain interconnection layer, wherein a region, which is used for forming a shared contact plug and electrically connected with the gate structure and the source and drain doping regions, on the substrate is used as a shared contact region;
etching the source-drain cap layer or the gate cap layer in the shared contact region to form a first groove penetrating through the source-drain cap layer or the gate cap layer;
forming a sacrificial layer in the first groove, wherein the etching resistance of the sacrificial layer is smaller than that of the source-drain cap layer;
forming a top dielectric layer covering the sacrificial layer, the grid cap layer and the source drain cap layer;
etching the top dielectric layer, the gate cap layer and the sacrificial layer on the top of the gate structure in the shared contact region, or etching the top dielectric layer, the sacrificial layer and the source drain cap layer on the top of the gate structure, and forming a second groove communicated with the first groove in the top dielectric layer and the gate cap layer;
And forming a shared contact plug in the first groove and the second groove, wherein the shared contact plug is electrically connected with the grid structure and the source-drain doped region.
2. The method of forming a semiconductor structure of claim 1, wherein the first trench is formed by etching the source drain cap layer;
the step of forming the first trench includes: and etching the source-drain cap layer and the source-drain interconnection layer in sequence in the shared contact region to form a first groove penetrating through the source-drain cap layer and the source-drain interconnection layer.
3. The method of forming a semiconductor structure of claim 2, wherein in the step of providing a substrate, the source-drain doped region is formed in the substrate of the shared contact region;
in the step of forming the first trench, the first trench exposes the source-drain doped region.
4. The method of forming a semiconductor structure of claim 1, wherein the first trench is formed by etching the gate cap layer;
the step of forming the first trench includes: and etching the gate cap layer and the gate structure in the shared contact region in sequence to form a first groove penetrating through the gate cap layer and the gate structure.
5. The method of claim 1, wherein in etching the sacrificial layer, an etch selectivity of the sacrificial layer to the gate cap layer is greater than 5:1, and an etch selectivity of the sacrificial layer to the source drain cap layer is greater than 5:1.
6. The method of forming a semiconductor structure of claim 1, wherein materials of the sacrificial layer, the gate cap layer, and the source drain cap layer are different.
7. The method of forming a semiconductor structure of claim 1, wherein in the step of etching the top dielectric layer, an etch selectivity between the top dielectric layer and the sacrificial layer is less than 3:1.
8. The method of claim 1, wherein the sacrificial layer is a dielectric material.
9. The method of forming a semiconductor structure of claim 8, wherein the dielectric material comprises one or more of silicon oxide, aluminum oxide, and titanium dioxide.
10. The method of forming a semiconductor structure of claim 8, wherein a direction parallel to the substrate surface and perpendicular to the first direction is a second direction;
In the step of forming the second trench, a sacrificial layer with a partial width remains on the sidewall of the second trench facing the boundary of the shared contact region in the second direction.
11. The method of claim 10, wherein the sacrificial layer has a width of 2 nm to 10 nm.
12. The method of forming a semiconductor structure of claim 1, wherein an opening size of the second trench is greater than an opening size of the first trench along the first direction.
13. The method of forming a semiconductor structure of claim 1, wherein an opening dimension of the first trench is 16 nm to 30 nm along the first direction.
14. The method of forming a semiconductor structure of claim 1, wherein the first trench is formed by etching using an anisotropic dry etching process.
15. The method of forming a semiconductor structure of claim 1, wherein the second trench is formed by etching using an anisotropic dry etching process.
16. The method of forming a semiconductor structure of claim 1, wherein forming a shared contact plug in the first trench and the second trench comprises: filling the first trench and the second trench with a conductive material, wherein the conductive material also covers the top dielectric layer;
And taking the top surface of the top dielectric layer as a stop position, carrying out planarization treatment on the conductive material, and taking the rest conductive material as a shared contact plug.
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Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103681291A (en) * 2012-09-12 2014-03-26 中芯国际集成电路制造(上海)有限公司 Metal silicide forming method
US9929157B1 (en) * 2016-12-22 2018-03-27 Globalfoundries Inc. Tall single-fin fin-type field effect transistor structures and methods
US10026824B1 (en) * 2017-01-18 2018-07-17 Globalfoundries Inc. Air-gap gate sidewall spacer and method
CN108321089A (en) * 2017-01-17 2018-07-24 中芯国际集成电路制造(上海)有限公司 Semiconductor structure and forming method thereof
CN108933173A (en) * 2017-05-19 2018-12-04 中芯国际集成电路制造(上海)有限公司 Semiconductor device and its manufacturing method
CN110571187A (en) * 2018-06-05 2019-12-13 中芯国际集成电路制造(上海)有限公司 Method for manufacturing semiconductor device

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10832963B2 (en) * 2018-08-27 2020-11-10 International Business Machines Corporation Forming gate contact over active free of metal recess

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103681291A (en) * 2012-09-12 2014-03-26 中芯国际集成电路制造(上海)有限公司 Metal silicide forming method
US9929157B1 (en) * 2016-12-22 2018-03-27 Globalfoundries Inc. Tall single-fin fin-type field effect transistor structures and methods
CN108321089A (en) * 2017-01-17 2018-07-24 中芯国际集成电路制造(上海)有限公司 Semiconductor structure and forming method thereof
US10026824B1 (en) * 2017-01-18 2018-07-17 Globalfoundries Inc. Air-gap gate sidewall spacer and method
CN108933173A (en) * 2017-05-19 2018-12-04 中芯国际集成电路制造(上海)有限公司 Semiconductor device and its manufacturing method
CN110571187A (en) * 2018-06-05 2019-12-13 中芯国际集成电路制造(上海)有限公司 Method for manufacturing semiconductor device

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