CN114068395B - Semiconductor structure and forming method thereof - Google Patents

Semiconductor structure and forming method thereof Download PDF

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Publication number
CN114068395B
CN114068395B CN202010762860.4A CN202010762860A CN114068395B CN 114068395 B CN114068395 B CN 114068395B CN 202010762860 A CN202010762860 A CN 202010762860A CN 114068395 B CN114068395 B CN 114068395B
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layer
source
dielectric layer
forming
drain
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CN114068395A (en
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王楠
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76805—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics the opening being a via or contact hole penetrating the underlying conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76832—Multiple layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate

Abstract

A semiconductor structure and a method of forming the same, the method comprising: providing a substrate, wherein a grid structure is arranged on the substrate, active drain doping layers are arranged in the substrate at two sides of the grid structure, a first dielectric layer is arranged on the substrate exposed out of the grid structure, and the substrate comprises a plurality of adjacent device unit areas along the extending direction of the grid structure; forming a barrier layer on the top of the first dielectric layer at the junction of the device unit area; etching a first dielectric layer with partial thickness by taking the barrier layer as a mask, and forming openings exposing the tops of the source-drain doping layers in the first dielectric layers on two sides of the gate structure; forming a bottom source drain plug at the top of the source drain doping layer exposed by the opening; forming a second dielectric layer on the top of the bottom source drain plug, wherein the second dielectric layer covers the side wall of the barrier layer; and forming a top source drain plug electrically connected with the bottom source drain plug in the second dielectric layer, wherein the top source drain plugs in the adjacent device unit areas are isolated by a barrier layer. The invention improves the alignment precision of the top source drain plug and the corresponding bottom source drain plug through the barrier layer.

Description

Semiconductor structure and forming method thereof
Technical Field
Embodiments of the present disclosure relate to semiconductor manufacturing, and more particularly, to a semiconductor structure and a method for forming the same.
Background
With the continued development of integrated circuit fabrication technology, the demands on the degree of integration and performance of integrated circuits are becoming ever higher. In order to improve the integration level and reduce the cost, the critical dimensions of the components are continuously reduced, and the circuit density inside the integrated circuit is increasingly high, so that the wafer surface cannot provide enough area to manufacture the required interconnection line.
In order to meet the requirements of the interconnect lines with reduced critical dimensions, the different metal layers or the conduction between the metal layers and the substrate is realized through the interconnect structure. The interconnect structure includes an interconnect line and a contact hole plug formed within the contact opening. The contact hole plugs are connected with the semiconductor device, and the interconnection lines realize the connection between the contact hole plugs, so that a circuit is formed. The contact hole plug in the transistor structure comprises a gate contact hole plug positioned on the surface of the gate structure and used for realizing the connection between the gate structure and an external circuit, and also comprises a source and drain contact hole plug positioned on the surface of the source and drain doped layer and used for realizing the connection between the source and drain doped layer and the external circuit.
Currently, to achieve further reduction of transistor area, active gate contact plug (Contact Over Active Gate, COAG) processes are introduced. Compared with the traditional gate contact plug above the gate structure of the isolation region, the COAG process can enable the gate contact plug to be above the gate structure of an Active Area (AA), thereby further saving the Area of the chip.
Disclosure of Invention
The embodiment of the invention solves the problem of providing a semiconductor structure and a forming method thereof, and improves the electrical performance of the semiconductor structure.
In order to solve the above problems, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate, wherein a grid structure is formed on the substrate, source-drain doping layers are formed in the substrates at two sides of the grid structure, a first dielectric layer is formed on the substrate exposed by the grid structure, the first dielectric layer covers the source-drain doping layers, and the substrate comprises a plurality of adjacent device unit areas along the extending direction of the grid structure; forming a barrier layer on the top of the first dielectric layer at the junction of the device unit area; etching part of the first dielectric layer with the thickness by taking the barrier layer as a mask, and forming openings exposing the source-drain doping layers in the first dielectric layer at two sides of the gate structure; forming a bottom source drain plug at the top of the source drain doping layer exposed by the opening; forming a second dielectric layer on the top of the bottom source drain plug, wherein the second dielectric layer covers the side wall of the barrier layer; and forming a top source drain plug electrically connected with the bottom source drain plug in the second dielectric layer, wherein the top source drain plugs in adjacent device unit areas are isolated by the barrier layer.
Correspondingly, the embodiment of the invention also provides a semiconductor structure, which comprises: a substrate comprising a plurality of adjacent device cell regions; the grid structure is positioned on the substrate, and the extending direction of the grid structure is the same as the arrangement direction of the device unit area; the source-drain doping layers are positioned in the substrates at two sides of the grid structure; the first dielectric layer is positioned on the substrate exposed by the grid structure, covers the side wall of the grid structure, and in the device unit area, the first dielectric layers on two sides of the grid structure are exposed out of the top of the source-drain doping layer; the barrier layer is positioned on the top of the first dielectric layer at the junction of the device unit area; the bottom source drain plug is positioned at the top of the source drain doping layer exposed out of the first dielectric layer; the second dielectric layer is positioned at the top of the bottom source drain plug and covers the side wall of the barrier layer; and a top source drain plug penetrating through the second dielectric layer above the bottom source drain plug and electrically connected with the bottom source drain plug, wherein the top source drain plugs in adjacent device unit areas are isolated by the barrier layer.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following advantages:
in the scheme disclosed by the embodiment of the invention, a blocking layer is formed on the top of a first dielectric layer at the junction of a device unit area, the blocking layer is used as a mask to etch the first dielectric layer with partial thickness, an opening exposing the top of a source-drain doping layer is formed in the first dielectric layer of the device unit area, after a bottom source-drain plug is formed on the top of the source-drain doping layer exposed by the opening, a second dielectric layer covering the side wall of the blocking layer is formed on the top of the bottom source-drain plug, then a top source-drain plug electrically connected with the bottom source-drain plug is formed in the second dielectric layer, and the top source-drain plugs in adjacent device unit areas are isolated by the blocking layer; the method and the device have the advantages that compared with the scheme that after the blocking layer is removed, the top source drain plug is formed in the second medium layer, the alignment precision of the top source drain plug and the corresponding bottom source drain plug is improved, and the bridging probability of the top source drain plug in the adjacent device unit area is correspondingly reduced, so that the electrical performance of the semiconductor structure is improved.
Drawings
Fig. 1 to 6 are schematic structural views corresponding to steps in a method for forming a semiconductor structure;
fig. 7 to 16 are schematic structural views corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention.
Detailed Description
Currently, the electrical performance of semiconductor structures is still to be improved. The method for forming the semiconductor structure is combined, and the reason that the performance of the semiconductor structure needs to be improved is analyzed. Fig. 1 to 6 are schematic structural diagrams corresponding to steps in a method for forming a semiconductor structure.
Referring to fig. 1, a substrate is provided, which includes a substrate 10 and a plurality of discrete fins 12 located on the substrate, an isolation layer 11 is formed on the substrate 10 where the fins 12 are exposed, the isolation layer 11 covers a portion of a sidewall of the fins 12, a gate structure (not shown) crossing the fins 12 is formed on the isolation layer 11, source and drain doped layers 19 are formed in the fins 12 on two sides of the gate structure, a first dielectric layer 18 is formed on the isolation layer 11 where the gate structure is exposed, the first dielectric layer 18 covers the source and drain doped layers 19, and the substrate includes a plurality of adjacent device unit areas i along an extension direction of the gate structure (i.e., a direction perpendicular to an extension direction of the fins 12).
Referring to fig. 2, a barrier layer 20 is formed on top of the first dielectric layer 18 at the junction of the device cell regions i.
Referring to fig. 3, with the barrier layer 20 as a mask, a portion of the first dielectric layer 18 is etched to form an opening 31 exposing the top of the source/drain doped layer 19 in the first dielectric layer 18 of the device unit region i.
Referring to fig. 4, bottom source drain plugs 21 are formed on top of the source drain doped layer 19 exposed by the openings 31 (shown in fig. 3).
After forming the bottom source drain plug 21, the method further includes: the barrier layer 20 is removed.
Referring to fig. 5, the barrier layer 20 is removed, and a second dielectric layer 22 is formed on top of the bottom source drain plugs 21 and the first dielectric layer 18.
Referring to fig. 6, a top source drain plug 23 penetrating the second dielectric layer 22 and electrically connected to the bottom source drain plug 21 is formed.
Specifically, the step of forming the top source drain plug 23 includes: etching the second dielectric layer 22 to form a contact hole exposing the bottom source-drain plug 21; a top source drain plug 23 is formed in the contact hole.
It has been found that, as the feature size of the device is reduced, the pitch between the adjacent fin portions 12 is smaller and smaller, so that the pitch between the source-drain doped layers 19 in the adjacent device unit regions i is reduced correspondingly, and accordingly, during the process of etching the second dielectric layer 22 to form a contact hole, the overlay deviation (overlay shift) has a great influence on the position accuracy of the contact hole, which easily causes a problem that the top source-drain plug 23 and the corresponding bottom source-drain plug 21 cannot be aligned completely (as shown by a dotted circle in fig. 6), which increases the bridging probability of the top source-drain plug 23 in the adjacent device unit regions i correspondingly, and both the above two aspects easily cause the electrical performance of the semiconductor structure to be degraded.
In order to solve the technical problem, an embodiment of the present invention provides a method for manufacturing a semiconductor structure, including: providing a substrate, wherein a grid structure is formed on the substrate, source-drain doping layers are formed in the substrates at two sides of the grid structure, a first dielectric layer is formed on the substrate exposed by the grid structure, the first dielectric layer covers the source-drain doping layers, and the substrate comprises a plurality of adjacent device unit areas along the extending direction of the grid structure; forming a barrier layer on the top of the first dielectric layer at the junction of the device unit area; etching part of the first dielectric layer with the thickness by taking the barrier layer as a mask, and forming openings exposing the source-drain doping layers in the first dielectric layer at two sides of the gate structure; forming a bottom source drain plug at the top of the source drain doping layer exposed by the opening; forming a second dielectric layer on the top of the bottom source drain plug, wherein the second dielectric layer covers the side wall of the barrier layer; and forming a top source drain plug electrically connected with the bottom source drain plug in the second dielectric layer, wherein the top source drain plugs in adjacent device unit areas are isolated by the barrier layer.
In the scheme disclosed by the embodiment of the invention, a blocking layer is formed on the top of a first dielectric layer at the junction of a device unit area, the blocking layer is used as a mask to etch the first dielectric layer with partial thickness, an opening exposing the top of a source-drain doping layer is formed in the first dielectric layer of the device unit area, after a bottom source-drain plug is formed on the top of the source-drain doping layer exposed by the opening, a second dielectric layer covering the side wall of the blocking layer is formed on the top of the bottom source-drain plug, then a top source-drain plug electrically connected with the bottom source-drain plug is formed in the second dielectric layer, and the top source-drain plugs in adjacent device unit areas are isolated by the blocking layer; the method and the device have the advantages that compared with the scheme that after the blocking layer is removed, the top source drain plug is formed in the second medium layer, the alignment precision of the top source drain plug and the corresponding bottom source drain plug is improved, and the bridging probability of the top source drain plug in the adjacent device unit area is correspondingly reduced, so that the electrical performance of the semiconductor structure is improved.
In order that the above objects, features and advantages of embodiments of the invention may be readily understood, a more particular description of the invention will be rendered by reference to specific embodiments thereof which are illustrated in the appended drawings.
Fig. 7 to 16 are schematic structural views corresponding to each step in an embodiment of a method for forming a semiconductor structure according to the present invention.
Referring to fig. 7, fig. 7 (a) is a cross-sectional view along an extension direction of the gate structure 107 and at a top position of the source/drain doped region, fig. 7 (b) is a cross-sectional view along a top position of the gate structure 107 in a direction perpendicular to the extension direction of the gate structure 107, a substrate (not shown) is provided, where the gate structure 107 is formed on the substrate 100, source/drain doped layers 109 are formed in the substrate on both sides of the gate structure 107, a first dielectric layer 108 is formed on the substrate exposed by the gate structure 107, the first dielectric layer 108 covers the source/drain doped layers 109, and the substrate includes a plurality of adjacent device unit regions i along the extension direction of the gate structure 107.
The substrate is used for providing a process platform for a subsequent process.
In this embodiment, the substrate is used to form a fin field effect transistor (FinFET). The base includes a substrate 100 and a fin 102 protruding from the substrate 100. In other embodiments, when the base is used to form a planar field effect transistor, the base is correspondingly a planar substrate.
In this embodiment, the fin 102 is made of silicon, which is the same material as the substrate 100. In other embodiments, the substrate material may also be germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, and the substrate may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate.
In this embodiment, the method for forming a semiconductor structure further includes: after the fin 102 is formed, an isolation layer 101 is formed on the substrate 100 exposed by the fin 102, and the isolation layer 101 covers a part of the sidewall of the fin 102.
The isolation layer 101 is used to isolate adjacent devices. The material of the isolation layer 101 may be silicon oxide, silicon nitride or silicon oxynitride. In this embodiment, the material of the isolation layer 101 is silicon nitride.
The gate structure 107 is used to control the turning on or off of the conduction channel during operation of the device.
In this embodiment, the gate structure 107 is located on the substrate 100, and the gate structure 107 spans across the fin 102 and covers a portion of the top surface and a portion of the sidewall of the fin 102.
In this embodiment, the gate structure 107 is a metal gate structure, and the gate structure 107 includes a high-k gate dielectric layer 106, a work function layer 104 on the high-k gate dielectric layer 106, and a gate electrode layer 105 on the work function layer 104.
The material of the high-k gate dielectric layer 106 is a high-k dielectric material, where the high-k dielectric material refers to a dielectric material having a relative dielectric constant greater than that of silicon oxide. Specifically, the material of the high-k gate dielectric layer 106 may be selected from the group consisting of HfO 2 、ZrO 2 HfSiO, hfSiON, hfTaO, hfTiO, hfZrO or Al 2 O 3 Etc.
The work function layer 104 is used to adjust the threshold voltage of the transistor formed. When the PMOS transistor is formed, the work function layer 104 is a P-type work function layer, and the material of the P-type work function layer includes one or more of TiN, taN, taSiN, taAlN and TiAlN; when forming an NMOS transistor, the work function layer 104 is an N-type work function layer, and the material of the N-type work function layer includes one or more of TiAl, mo, moN, alN and TiAlC.
The gate electrode layer 105 is used to electrically draw out the gate structure 107. In this embodiment, the material of the gate electrode layer 105 is Al, cu, ag, au, pt, ni, ti or W.
In this embodiment, the source-drain doped layer 109 is located in the fin 102 at two sides of the gate structure 107.
Specifically, adjacent gate structures 107 share one source-drain doped layer 109.
When forming an NMOS transistor, the source-drain doped layer 109 includes a stress layer doped with N-type ions, where the stress layer is made of Si or SiC, and the stress layer provides a tensile stress for a channel region of the NMOS transistor, so As to facilitate improvement of carrier mobility of the NMOS transistor, and the N-type ions are P ions, as ions, or Sb ions; when forming the PMOS transistor, the source-drain doped layer 109 includes a stress layer doped with P-type ions, where the material of the stress layer is Si or SiGe, and the stress layer provides compressive stress to the channel region of the PMOS transistor, so as to facilitate improving carrier mobility of the PMOS transistor, and the P-type ions are B ions, ga ions, or In ions.
In this embodiment, as shown in fig. 7, a sidewall 103 is further formed on the sidewall of the gate structure 107.
The sidewall 103 is used to define a formation region of the source-drain doped layer 109, and the sidewall 103 is also used to protect a sidewall of the gate structure 107. The side wall 103 may have a single-layer structure or a stacked-layer structure, and the material of the side wall 103 includes one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride oxide, silicon oxynitride, boron nitride, and boron carbonitride. In this embodiment, the side wall 103 has a single-layer structure, and the material of the side wall 103 is silicon nitride.
The first dielectric layer 108 is used to isolate adjacent devices.
Subsequently, a bottom source-drain plug contacting the source-drain doped layer 109 is also formed in the first dielectric layer 108 above the source-drain doped layer 109, and the first dielectric layer 108 is correspondingly further used for realizing electrical isolation between the bottom source-drain plugs.
In this embodiment, the first dielectric layer 108 is an interlayer dielectric layer (Inter Layer Dielectric, ILD).
The material of the first dielectric layer 108 is an insulating material, and the material of the first dielectric layer 108 includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon oxycarbonitride. In this embodiment, the material of the first dielectric layer 108 is silicon nitride.
With continued reference to fig. 7, in this embodiment, the forming method further includes: a gate cap layer 132 is formed on top of the gate structure 107.
To save Area of the chip, the forming method introduces an Active gate contact plug (Contact Over Active Gate, COAG) process, so that the gate plug is subsequently formed over the Active Area (AA) gate structure 107.
The top source/drain plug is formed in the second dielectric layer above the source/drain doped layer 109, and the gate cap layer 132 is used for protecting the top of the gate structure 107, so that the probability of damaging the gate structure 107 and shorting the top source/drain plug with the gate structure 107 is reduced in the process of forming the top source/drain plug.
The gate cap layer 132 is made of a material having etching selectivity with the side wall 103, the first dielectric layer 108 and the second dielectric layer formed later, so that the gate cap layer 132 can protect the gate structure 107.
The material of the gate cap layer 132 includes one or more of SiC, siCO, siN and SiCN. In this embodiment, the material of the gate cap layer 132 is SiN.
As an example, the gate structure 107 is formed using a process that forms a gate electrode layer (high k last metal gate last) after forming a high-k gate dielectric layer, and thus the first dielectric layer 108 covers the sidewalls of the gate structure 107 and gate cap 132.
Specifically, after forming the gate structure 107 in the first dielectric layer 108, etching back a portion of the gate structure 107; after etching back the gate structure 107 with a partial thickness, a gate cap layer 132 is formed in the area enclosed by the first dielectric layer 108 and the remaining gate structure 107.
The step of forming the gate cap layer 132 includes a step of depositing a gate cap material layer and a step of planarizing the gate cap material layer (e.g., a chemical mechanical polishing process) sequentially.
Accordingly, the sidewall 103 covers the sidewalls of the gate structure 107 and the gate cap 132.
Referring to fig. 8, fig. 8 (a) is a cross-sectional view along the extension direction of the gate structure 107 and at the top position of the source/drain doped region, fig. 8 (b) is a cross-sectional view of the gate structure 107 at the top position along the extension direction of the gate structure 107, and a barrier layer 110 is formed on top of the first dielectric layer 108 at the junction of the device unit region i.
Openings exposing the tops of the source-drain doped layers 109 are formed in the first dielectric layers 108 on two sides of the gate structure 107, and the barrier layer 110 is used as an etching mask for forming the openings.
In addition, after forming the opening, the subsequent process further includes: forming a bottom source-drain plug on the top of the source-drain doped layer 109 exposed by the opening; forming a second dielectric layer on the top of the bottom source drain plug, wherein the second dielectric layer covers the side wall of the barrier layer; and forming a top source drain plug electrically connected with the bottom source drain plug in the second dielectric layer. The process of forming the top source drain plug generally includes a step of etching the second dielectric layer, and in the process of etching the second dielectric layer, the barrier layer 110 can define a lateral etching stop position, so that the alignment accuracy of the top source drain plug and the corresponding bottom source drain plug is improved, the bridging probability of the top source drain plug in the adjacent device unit area i is correspondingly reduced, and the electrical performance of the semiconductor structure is further improved. Wherein the lateral direction refers to an extension direction of the gate structure 107.
Specifically, the step of forming the barrier layer 110 includes: forming a barrier material layer overlying the first dielectric layer 108 and the gate cap layer 132; forming a graph layer on the barrier material layer at the juncture of the device unit area I; the barrier material layer is etched using the pattern layer as a mask, and the remaining barrier material layer serves as the barrier layer 110.
In this embodiment, the barrier material layer is formed by chemical vapor deposition.
In this embodiment, an anisotropic dry etching process is used to etch the barrier material layer. The anisotropic dry etch process has anisotropic etching characteristics, thereby facilitating precise control of the dimensions and sidewall topography of the barrier layer 110.
The barrier layer 110 is made of a material having etching selectivity to the gate cap layer 132, the sidewall 103, the first dielectric layer 108 and the subsequent second dielectric layer, and the etching rate of the barrier layer 110 by the etching process when the source-drain contact hole or the gate contact hole is subsequently formed is low.
And, a source-drain cap layer is formed on top of the bottom source-drain plug after the bottom source-drain plug is formed, and then, a material having etching selectivity with the source-drain cap layer is further selected for the barrier layer 110, so that damage to the barrier layer 110 is reduced in the process of subsequently etching the source-drain cap layer to form the source-drain contact hole.
In this embodiment, the material of the barrier layer 110 includes SiO 2 SiN, siON, siOC, siOCH, siC, siCN, alN and Al 2 O 3 One or more of the following.
It should be noted that the gate cap layer 132 is already formed on top of the gate structure 107, so that the formation of the barrier layer 110 is avoided from affecting the process of forming the gate cap layer 132.
Accordingly, as an example, to increase the process window for forming the barrier layer 110, the barrier layer 110 also extends to cover a portion of the top of the gate structure 107 in a direction perpendicular to the extending direction of the gate structure 107.
In other embodiments, the barrier layer may also be located only between adjacent gate structures.
Referring to fig. 9, fig. 9 (a) is a cross-sectional view along the extending direction of the gate structure 107 and at the top position of the source/drain doped region, fig. 9 (b) is a cross-sectional view along the extending direction of the gate structure perpendicular to the extending direction of the gate structure at the top position of the gate structure 107, and the first dielectric layer 108 with a partial thickness is etched with the barrier layer 110 as a mask, so that openings 111 exposing the top of the source/drain doped layer 109 are formed in the first dielectric layer 108 on both sides of the gate structure 107.
The openings 111 provide space locations for subsequent bottom source drain plug formation.
In this embodiment, a dry etching process (for example, an anisotropic dry etching process) is used to etch the first dielectric layer 108 above the source/drain doped layer 109. The dry etching process has the characteristic of anisotropic etching, which is beneficial to improving the profile control of the opening 111.
Specifically, in the process of etching the first dielectric layer 108, the top of the source-drain doped layer 109 is used as an etching stop position.
The barrier layer 110 is located on top of the first dielectric layer 108 at the junction of the device unit areas i, so that the openings 111 of the adjacent device unit areas i are isolated by the first dielectric layer 108.
Referring to fig. 10, fig. 10 (a) is a cross-sectional view along the extending direction of the gate structure 107 and at the top position of the source/drain doped region, fig. 10 (b) is a cross-sectional view along the extending direction of the gate structure 107 and at the top position of the gate structure 107, and bottom source/drain plugs 112 are formed on the top of the source/drain doped layer 109 exposed by the openings 111.
The bottom source drain plug 112 is used for electrically connecting with a top source drain plug formed later.
In this embodiment, the top of the bottom source drain plug 112 is lower than the top of the first dielectric layer 108.
Wherein the top of the bottom source drain plug 112 is lower than the top of the first dielectric layer 108, to provide a space for a subsequent formation of a source drain cap on top of the bottom source drain plug 112.
Specifically, the step of forming the bottom source drain plug 112 includes: forming an initial plug in the opening 111 by sequentially performing a deposition process and a planarization process, the top surface of the initial plug being flush with the top surface of the gate cap layer 132; the partial thickness of the initial plug is etched back to form the bottom source drain plug 112.
In this embodiment, a dry etching process is used to etch back the initial plug of a portion of thickness.
Referring to fig. 11 in combination, fig. 11 (a) is a cross-sectional view along an extension direction of the gate structure 107 and at a top position of the source/drain doped region, fig. 11 (b) is a cross-sectional view along a top position of the gate structure 107 in a direction perpendicular to the extension direction of the gate structure 107, and after forming the bottom source/drain plug 112, the forming method further includes: a source-drain cap 116 is formed on top of the bottom source-drain plug 112, the top of the source-drain cap 116 being lower than the top of the barrier layer 110.
A gate plug is subsequently formed over the top of the Active Area (AA) gate structure 107, and a source-drain cap 116 is located on the top surface of the bottom source-drain plug 112, so as to protect the bottom source-drain plug 112 during the formation of the gate plug, thereby facilitating the reduction of the probability of damaging the bottom source-drain plug 112 and shorting the gate plug to the bottom source-drain plug 112.
The source-drain cap layer 116 is made of a material having etching selectivity with the gate cap layer 132, the side wall 103, the first dielectric layer 108 and a second dielectric layer formed later, so that the source-drain cap layer 116 can protect the bottom source-drain plug 112.
In addition, in the subsequent process of forming the top source drain plug, not only the second dielectric layer but also the source drain cap layer 116 needs to be etched, so the material of the source drain cap layer 116 is a material that can be etched.
In this embodiment, the source/drain cap layer 116 material includes SiO 2 One or more of SiC and SiCN.
Specifically, the step of forming the source-drain cap 116 includes: forming a source-drain capping material layer (not shown) on the bottom source-drain plugs 112; the source drain cap material layer is etched back until the gate cap layer 132 is exposed, with the remaining source drain cap material layer acting as the source drain cap layer 116.
In this embodiment, after the gate cap layer 132 is formed, the source-drain cap layer 116 is formed, so that the gate cap layer 132 can be used to define a stop position of the etching back process during the formation of the source-drain cap layer 116.
Moreover, the barrier layer 110 is formed on top of the first dielectric layer 108 at the junction of the device unit region i, so that the complexity of the process for forming the gate cap layer 132 is advantageously reduced by forming the gate cap layer 132 first.
In this embodiment, a deposition process (e.g., a chemical vapor deposition process) is used to form the source-drain capping material layer.
In this embodiment, an etching process combining wet etching and dry etching is used to etch back the source drain cap material layer.
In this embodiment, after the gate cap layer 132 and the source/drain cap layer 116 are formed, the top surfaces of the gate cap layer 132 and the source/drain cap layer 116 are flush.
It should be noted that the thickness of the source-drain cap 116 should not be too large or too small. If the thickness of the source-drain cap layer 116 is too large, the space position for forming the second dielectric layer later is easily occupied too much, and accordingly, the effect is caused on the formation of the top source-drain plug in the second dielectric layer later, so that the performance of the semiconductor is affected; if the thickness of the source-drain cap 116 is too small, it is easy to cause the gate plug to contact the bottom source-drain plug 112, thereby shorting the gate structure to the source-drain doped layer, and affecting the performance of the semiconductor. For this reason, in the present embodiment, the thickness of the source-drain cap 116 is 8 nm to 25 nm.
Referring to fig. 12 to 13 in combination, a second dielectric layer 114 is formed on top of the bottom source drain plug 112 (as shown in fig. 13), and the second dielectric layer 114 covers the sidewalls of the barrier layer 110.
In fig. 12, (a) is a cross-sectional view along the extending direction of the gate structure 107 and at the top position of the source/drain doped region, fig. 12 (b) is a cross-sectional view along the extending direction of the gate structure 107 and at the top position of the gate structure 107, fig. 13 (a) is a cross-sectional view along the extending direction of the gate structure 107 and at the top position of the source/drain doped region, and fig. 13 (b) is a cross-sectional view along the extending direction of the gate structure 107 and at the top position of the gate structure 107.
The second dielectric layer 114 is used to electrically isolate the subsequent gate plug from the top source drain plug.
Thus, the material of the second dielectric layer 114 is a dielectric material.
It should be noted that, the subsequent process of forming the top source drain plug electrically connected to the bottom source drain plug 112 in the second dielectric layer 114 generally includes a step of etching the second dielectric layer 114, and in the process of etching the second dielectric layer 114, the sidewall of the barrier layer 110 is used as a lateral etching stop position, so that the etching selectivity between the second dielectric layer 114 and the barrier layer 110 is not too small.
In this embodiment, the etching selectivity between the second dielectric layer 114 and the barrier layer 110 is greater than 10:1.
In this embodiment, the material of the second dielectric layer 114 includes SiO 2 SiN, siON, siOC, siOCH, siC, siCN, alN and Al 2 O 3 One or more of the following.
Specifically, the step of forming the second dielectric layer 114 includes: as shown in fig. 12, a dielectric material layer 115 is formed on top of the bottom source drain plugs 112, and the dielectric material layer 115 covers the top of the barrier layer 110; as shown in fig. 13, the dielectric material layer 115 is planarized with the top of the barrier layer 110 as a stop position, and the remaining dielectric material layer 115 is used as the second dielectric layer 114.
In this embodiment, the dielectric material layer 115 is formed by a deposition process (e.g., a chemical vapor deposition process).
In this embodiment, a chemical mechanical polishing process is used to planarize the dielectric material layer 115.
Referring to fig. 14 to 16 in combination, a top source drain plug 119 (as shown in fig. 16) electrically connected to the bottom source drain plug 112 is formed in the second dielectric layer 114, and the top source drain plug 119 in the adjacent device cell region i is isolated by the barrier layer 110.
In fig. 14, (a) is a cross-sectional view along an extending direction of the gate structure 107 and at a top position of the source/drain doped region, fig. 14, (b) is a cross-sectional view along the extending direction of the gate structure 107 and at a top position of the source/drain doped region, fig. 15, (a) is a cross-sectional view along the extending direction of the gate structure 107 and at a top position of the source/drain doped region, fig. 15, (b) is a cross-sectional view along the extending direction of the gate structure 107 and at a top position of the source/drain doped region, fig. 16, (a) is a cross-sectional view along the extending direction of the gate structure 107 and at a top position of the gate structure 107, and fig. 16, (b) is a cross-sectional view along the extending direction of the gate structure 107 and at a top position of the source/drain doped region.
The top source drain plug 119 and the bottom source drain plug 112 constitute a source drain plug, thereby achieving electrical connection of the bottom source drain plug 112 with other interconnect structures or external circuitry.
Specifically, the step of forming the top source drain plug 119 with the extension direction of the gate structure 107 as a lateral direction includes: as shown in fig. 14, the second dielectric layer 114 on both sides of the barrier layer 110 is etched with the sidewall of the barrier layer 110 as a lateral etching stop position, so as to form a source-drain contact hole 117 exposing the bottom source-drain plug 112; as shown in fig. 15, a conductive material layer 118 is filled in the source-drain contact hole 117, and the conductive material layer 118 also covers the top of the second dielectric layer 114; as shown in fig. 16, the conductive material layer 118 is planarized with the top of the barrier layer 110 as a stop position, and the remaining conductive material in the source-drain contact hole 117 is used as a top source-drain plug 119.
Specifically, the source-drain contact hole 117 provides a spatial location for forming a top source-drain plug 119.
The barrier layer 110 is used as a mask for etching the first dielectric layer 108 to form an opening, and after the opening is formed, the barrier layer 110 is remained, so that the barrier layer 110 can define a lateral etching stop position in the process of forming the source-drain contact hole 117, thereby improving the alignment accuracy of the top source-drain plug 119 and the corresponding bottom source-drain plug 112, reducing the bridging probability between adjacent top source-drain plugs 119, and further improving the electrical performance of the semiconductor structure.
In this embodiment, the second dielectric layer 114 on both sides of the barrier layer 110 is etched using a dry etching process.
Specifically, the dry etching treatment process is an anisotropic dry etching process.
The anisotropic dry etching process has a longitudinal etching rate far greater than a transverse etching rate, and can obtain quite accurate pattern conversion, and the damage to the side wall of the second dielectric layer 114 is relatively small.
In this embodiment, in the step of etching the second dielectric layer 114 on both sides of the barrier layer 110, the etching selectivity between the second dielectric layer 114 and the barrier layer 110 is greater than 10:1.
Specifically, the etching selectivity refers to the relative etching rate between the second dielectric layer 114 and the barrier layer 110 under the dry etching process conditions. In this embodiment, in the dry etching process of the second dielectric layer 114, only the second dielectric layer 114 needs to be etched, and the barrier layer 110 needs to be retained. For this reason, in this embodiment, the etching selectivity between the second dielectric layer 114 and the barrier layer 110 is greater than 10:1.
In this embodiment, the planarization process is performed by using a chemical mechanical polishing process, which is beneficial to improving the flatness of the top surface of the top source drain plug 119.
In this embodiment, the top source drain plug 119 is made of copper. The lower resistivity of copper is beneficial to improving the signal delay of the back RC, improving the processing speed of the chip, reducing the resistance of the top source drain plug 119 and correspondingly reducing the power consumption. In other embodiments, the material of the top source drain plug may also be tungsten or cobalt.
The forming method further includes: a gate plug (not shown) is formed through the second dielectric layer and gate cap layer 132 over the top of the gate structure 107, which contacts the gate structure 107.
The gate plugs are used to make electrical connection between the gate structure 107 and an external circuit or other interconnect structure.
In this embodiment, the gate plug is formed above the gate structure 107 in the active region, that is, the gate plug is an active gate contact plug (Contact Over Active Gate, COAG), and compared with the scheme that the gate plug contacts the gate structure in the isolation region, the embodiment omits the portion of the gate structure 107 in the isolation region, which is beneficial to saving the area of the chip and realizing further reduction of the chip size.
Specifically, the step of forming the gate plug includes: etching the second mass layer and the gate cap layer 132 over the gate structure 107 to form a gate contact hole (not shown) exposing the gate structure 107; forming a gate plug filled in the gate contact hole.
The specific description of the gate plug is not repeated here.
Correspondingly, the invention further provides a semiconductor structure. Referring to fig. 16, a schematic structural diagram of an embodiment of a semiconductor structure of the present invention is shown. In fig. 16, (a) is a cross-sectional view along the extending direction of the gate structure 107 at the top position of the source/drain doped region, and (b) in fig. 16 is a cross-sectional view along the top position of the gate structure 107 in a direction perpendicular to the extending direction of the gate structure 107.
The semiconductor structure includes: a substrate (not shown) comprising a plurality of adjacent device cell regions i; a gate structure 107 located on the substrate, wherein an extending direction of the gate structure 107 is the same as an arrangement direction of the device unit region i; the source-drain doped layer 109 is located in the substrate at two sides of the gate structure 107; the first dielectric layer 108 is located on the exposed substrate of the gate structure 107, the first dielectric layer 108 covers the sidewall of the gate structure 107, and in the device unit area i, the first dielectric layer 108 on two sides of the gate structure 107 exposes the top of the source-drain doped layer 109; a barrier layer 110 located on top of the first dielectric layer 108 at the junction of the device cell region i; a bottom source drain plug 112 located on top of the source drain doped layer 109 exposed by the first dielectric layer 108; a second dielectric layer 114 located on top of the bottom source drain plug 112, where the second dielectric layer 114 covers the sidewall of the barrier layer 110; a top source drain plug 119 penetrates the second dielectric layer 114 above the bottom source drain plug 112 and is electrically connected to the bottom source drain plug 112, and adjacent top source drain plugs 119 in the device cell region i are isolated by the barrier layer 110.
In this embodiment, the substrate is used to form a fin field effect transistor (FinFET). The base includes a substrate 100 and a fin 102 protruding from the substrate 100. In other embodiments, when the base is used to form a planar field effect transistor, the base is correspondingly a planar substrate.
In this embodiment, the fin 102 is made of silicon, which is the same material as the substrate 100. In other embodiments, the substrate material may also be germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, and the substrate may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate.
In this embodiment, the semiconductor structure further includes: and the isolation layer 101 is positioned on the substrate 100 exposed by the fin 102, and the isolation layer 101 covers the side wall of the fin 102. The isolation layer 101 is used to isolate adjacent devices. The material of the isolation layer 101 may be silicon oxide, silicon nitride or silicon oxynitride. In this embodiment, the material of the isolation layer 101 is silicon nitride.
In this embodiment, the gate structure 107 is located on the substrate 100, and the gate structure 107 spans across the fin 102 and covers a portion of the top surface and a portion of the sidewall of the fin 102. In this embodiment, the gate structure 107 is a metal gate structure, and the gate structure 107 includes a high-k gate dielectric layer 106, a work function layer 104 on the high-k gate dielectric layer 106, and a gate electrode layer 105 on the work function layer 104.
In this embodiment, the source-drain doped layer 109 is located in the fin 102 at two sides of the gate structure 107. Specifically, adjacent gate structures 107 share one source-drain doped layer 109.
When forming an NMOS transistor, the source-drain doped layer 109 includes a stress layer doped with N-type ions, where the stress layer is made of Si or SiC, and the stress layer provides a tensile stress for a channel region of the NMOS transistor, so As to facilitate improvement of carrier mobility of the NMOS transistor, and the N-type ions are P ions, as ions, or Sb ions; when forming the PMOS transistor, the source-drain doped layer 109 includes a stress layer doped with P-type ions, where the material of the stress layer is Si or SiGe, and the stress layer provides compressive stress to the channel region of the PMOS transistor, so as to facilitate improving carrier mobility of the PMOS transistor, and the P-type ions are B ions, ga ions, or In ions.
The semiconductor structure further includes: the sidewall 103 is located on the sidewall of the gate structure 107. The sidewall 103 also serves to protect the sidewalls of the gate structure 107. The side wall 103 may have a single-layer structure or a stacked-layer structure, and the material of the side wall 103 includes one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride oxide, silicon oxynitride, boron nitride, and boron carbonitride. In this embodiment, the side wall 103 has a single-layer structure, and the material of the side wall 103 is silicon nitride.
In this embodiment, the semiconductor structure further includes: a source drain cap 116 is located between the bottom source drain plug 112 and the second dielectric layer 114. The top of the source drain cap 116 is lower than the top of the barrier 110. The source-drain cap layer 116 is made of a material having etching selectivity to the gate cap layer 132, the side wall 103, the first dielectric layer 108 and the second dielectric layer 114, so that the source-drain cap layer 116 can protect the bottom source-drain plug 112. The source-drain cap layer 116 material comprises SiO 2 One or more of SiC and SiCN.
It should be noted that the thickness of the source-drain cap 116 should not be too large or too small. If the thickness of the source-drain cap layer 116 is too large, the space position where the second dielectric layer 114 is formed is easily occupied too much, and accordingly, the formation of the top source-drain plug 119 in the second dielectric layer 114 is affected, thereby affecting the performance of the semiconductor; if the thickness of the source-drain cap 116 is too small, it is easy to cause the gate plug to contact the bottom source-drain plug, which causes a problem of shorting the gate to the bottom source-drain, thereby affecting the performance of the semiconductor. For this reason, in the present embodiment, the thickness of the source-drain cap 116 is 8 nm to 25 nm.
The first dielectric layer 108 is used to isolate adjacent devices. In this embodiment, the first dielectric layer 108 is an interlayer dielectric layer (Inter Layer Dielectric, ILD). The material of the first dielectric layer 108 is an insulating material, and the material of the first dielectric layer 108 includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon oxycarbonitride. In this embodiment, the material of the first dielectric layer 108 is silicon nitride.
The barrier layer 110 is located on top of the first dielectric layer 108 at the junction of the device cell region i.
In the device unit area i, the first dielectric layers 108 on two sides of the gate structure 107 expose the top of the source-drain doped layer 109, and the barrier layer 110 is located on top of the first dielectric layers 108 at the junction of the device unit area i; in the process of forming the semiconductor structure, the first dielectric layer 108 on two sides of the gate structure 107 is etched with the barrier layer 110 as a mask, so as to expose the top of the source/drain doped layer 109.
In addition, the process of forming the top source drain plug 119 generally includes a step of etching the second dielectric layer 114, where during the process of etching the second dielectric layer 114, the barrier layer 110 can define a lateral etching stop position, so as to improve the alignment accuracy of the top source drain plug 119 and the corresponding bottom source drain plug 112, and correspondingly reduce the bridging probability of the top source drain plug 119 in the adjacent device unit area i, thereby improving the electrical performance of the semiconductor structure. Wherein the lateral direction refers to an extension direction of the gate structure 107.
The barrier layer 110 is made of a material having etching selectivity to the gate cap layer 132, the sidewall 103, the first dielectric layer 108 and the second dielectric layer 114, and the etching rate of the barrier layer 110 is low by the etching process when forming the source-drain contact hole or the gate contact hole. The material of the barrier layer 110 comprises SiO 2 SiN, siON, siOC, siOCH, siC, siCN, alN and Al 2 O 3 One or more of the following. The source and drain contact holes are used for providing space positions for forming top source and drain plugs, and the gate contact holes are used for providing space positions for forming gate plugs.
The bottom source drain plug 112 is electrically connected to the top source drain plug 119.
In this embodiment, the top of the bottom source drain plug 112 is lower than the top of the first dielectric layer 108. Wherein the top of the bottom source drain plug 112 is lower than the top of the first dielectric layer 108, to provide a spatial location for forming a source drain cap on top of the bottom source drain plug 112.
The second dielectric layer 114 is used to electrically isolate the gate plug from the top source drain plug. Thus, the material of the second dielectric layer 114 is a dielectric material. The second dielectric layer 114 is primarily used to provide a location for conductive plugs (e.g., top source drain plugs 119 or gate plugs) while also being used to isolate adjacent devices. In this embodiment, the second dielectric layer 114 includes one or more of SiO2, siN, siON, siOC, siOCH, siC, siCN, alN, and Al2O 3.
It should be noted that, during the formation of the semiconductor structure, the top source drain plug 119 electrically connected to the bottom source drain plug 112 is formed in the second dielectric layer 114, and the process of forming the top source drain plug 119 generally includes a step of etching the second dielectric layer 114, and during the etching of the second dielectric layer 114, the sidewall of the barrier layer 110 is used as a lateral etching stop position, so that the etching selectivity between the second dielectric layer 114 and the barrier layer 110 is not too small. For this reason, in this embodiment, the material of the second dielectric layer 114 satisfies: the etch selectivity between the second dielectric layer 114 and the barrier layer 110 is greater than 10:1.
The top source drain plug 119 and the bottom source drain plug 112 constitute a source drain plug, thereby making electrical connection of the source drain doped layer 109 with other interconnect structures or external circuitry.
In this embodiment, the semiconductor structure further includes: a gate plug (not shown) is located over the top of the gate structure 107. The gate plug is in contact with the gate structure 107. The gate plugs are used to make electrical connection between the gate structure 107 and an external circuit or other interconnect structure. The specific description of the gate plug is not repeated here.
The semiconductor structure may be formed by the forming method described in the foregoing embodiments, or may be formed by other forming methods. For a specific description of the semiconductor structure in this embodiment, reference may be made to the corresponding description in the foregoing embodiment, which is not repeated here.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.

Claims (16)

1. A method of forming a semiconductor structure, comprising:
providing a substrate, wherein a grid structure is formed on the substrate, source-drain doping layers are formed in the substrates at two sides of the grid structure, a first dielectric layer is formed on the substrate exposed by the grid structure, the first dielectric layer covers the source-drain doping layers, and the substrate comprises a plurality of adjacent device unit areas along the extending direction of the grid structure;
forming a barrier layer on the top of the first dielectric layer at the junction of the device unit area;
etching part of the first dielectric layer with the thickness by taking the barrier layer as a mask, and forming openings exposing the tops of the source-drain doping layers in the first dielectric layer at two sides of the gate structure;
Forming a bottom source drain plug at the top of the source drain doping layer exposed by the opening;
forming a second dielectric layer on the top of the bottom source drain plug, wherein the second dielectric layer covers the side wall of the barrier layer;
and forming a top source drain plug electrically connected with the bottom source drain plug in the second dielectric layer, wherein the top source drain plugs in adjacent device unit areas are isolated by the barrier layer.
2. The method of forming a semiconductor structure of claim 1, further comprising: forming a gate cap layer on top of the gate structure;
after forming the bottom source-drain plug on top of the source-drain doped layer and before forming the second dielectric layer on top of the bottom source-drain plug, the method further comprises: and forming a source-drain cap layer on the top of the bottom source-drain plug, wherein the top of the source-drain cap layer is lower than the top of the barrier layer.
3. The method of forming a semiconductor structure of claim 2, wherein in the step of providing a substrate, the gate cap layer is formed on top of the gate structure, and the first dielectric layer covers sidewalls of the gate structure and gate cap layer;
In the step of forming the bottom source drain plug, the top of the bottom source drain plug is lower than the top of the first dielectric layer;
the step of forming the source-drain cap layer comprises the following steps: forming a source drain cap material layer on the bottom source drain plug; and etching the source drain cap material layer until the grid cap layer is exposed, wherein the remaining source drain cap material layer is used as the source drain cap layer.
4. The method of forming a semiconductor structure of claim 1, wherein the forming the top source drain plug with the extension direction of the gate structure as a lateral direction comprises: etching the second dielectric layers on two sides of the barrier layer by taking the side wall of the barrier layer as a transverse etching stop position to form a source-drain contact hole exposing the bottom source-drain plug;
filling a conductive material layer in the source-drain contact hole;
and taking the top of the barrier layer as a stop position, carrying out planarization treatment on the conductive material layer, and taking the rest conductive material in the contact hole as a top source drain plug.
5. The method of forming a semiconductor structure of claim 4, wherein the second dielectric layer is etched on both sides of the barrier layer using a dry etching process.
6. The method of forming a semiconductor structure of claim 1, wherein forming a second dielectric layer on top of said bottom source drain plug comprises: forming a dielectric material layer on the top of the bottom source drain plug, wherein the dielectric material layer covers the top of the barrier layer;
and taking the top of the barrier layer as a stop position, carrying out planarization treatment on the dielectric material layer, and taking the rest dielectric material layer as a second dielectric layer.
7. The method of claim 2, wherein the source drain cap layer has a thickness of 8 nm to 25 nm.
8. The method of forming a semiconductor structure of claim 2, wherein said source drain cap material comprises SiO 2 One or more of SiC and SiCN.
9. The method of claim 4, wherein in etching the second dielectric layer on both sides of the barrier layer, an etching selectivity between the second dielectric layer and the barrier layer is greater than 10:1.
10. The method of forming a semiconductor structure of claim 1, wherein the material of the barrier layer comprises SiO 2 SiN, siON, siOC, siOCH, siC, siCN, alN and Al 2 O 3 One or more of the following;
the second dielectric layer material comprises SiO 2 SiN, siON, siOC, siOCH, siC, siCN, alN and Al 2 O 3 One or more of the following.
11. A semiconductor structure, comprising:
a substrate comprising a plurality of adjacent device cell regions;
the grid structure is positioned on the substrate, and the extending direction of the grid structure is the same as the arrangement direction of the device unit area;
the source-drain doping layers are positioned in the substrates at two sides of the grid structure;
the first dielectric layer is positioned on the substrate exposed by the grid structure, covers the side wall of the grid structure, and in the device unit area, the first dielectric layers on two sides of the grid structure are exposed out of the top of the source-drain doping layer;
the barrier layer is positioned on the top of the first dielectric layer at the junction of the device unit area;
the bottom source drain plug is positioned at the top of the source drain doping layer exposed out of the first dielectric layer;
the second dielectric layer is positioned at the top of the bottom source drain plug and covers the side wall of the barrier layer;
and a top source drain plug penetrating through the second dielectric layer above the bottom source drain plug and electrically connected with the bottom source drain plug, wherein the top source drain plugs in adjacent device unit areas are isolated by the barrier layer.
12. The semiconductor structure of claim 11, wherein the semiconductor structure further comprises: the grid cap layer is positioned on the top of the grid structure;
and the source-drain cap layer is positioned between the bottom source-drain plug and the second dielectric layer.
13. The semiconductor structure of claim 12, wherein the source drain cap layer has a thickness of 8 nm to 25 nm.
14. The semiconductor structure of claim 12, wherein the source drain cap material comprises SiO 2 One or more of SiC and SiCN.
15. The semiconductor structure of claim 11, wherein an etch selectivity between materials of the second dielectric layer and the barrier layer is greater than 10:1.
16. The semiconductor structure of claim 11, wherein the barrier layer material comprises SiO 2 SiN, siON, siOC, siOCH, siC, siCN, alN and Al 2 O 3 One or more of the following;
the second dielectric layer material comprises SiO 2 、SiN、SiON、SiOC、SiOCH、SiC, siCN, alN and Al 2 O 3 One or more of the following.
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