CN111200017B - Semiconductor structure and forming method thereof - Google Patents

Semiconductor structure and forming method thereof Download PDF

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Publication number
CN111200017B
CN111200017B CN201811372225.4A CN201811372225A CN111200017B CN 111200017 B CN111200017 B CN 111200017B CN 201811372225 A CN201811372225 A CN 201811372225A CN 111200017 B CN111200017 B CN 111200017B
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layer
contact hole
conductive layer
forming
sidewall
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CN111200017A (en
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周飞
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76804—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics by forming tapered via holes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76805—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics the opening being a via or contact hole penetrating the underlying conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H01L23/5283—Cross-sectional geometry
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L2029/7858—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET having contacts specially adapted to the FinFET geometry, e.g. wrap-around contacts

Abstract

A semiconductor structure and a method for forming the same, the method for forming the same includes: providing a substrate, wherein a grid structure is formed on the substrate, active drain doping layers are formed in the substrates at two sides of the grid structure, a dielectric layer is formed on the substrate exposed by the grid structure, and the dielectric layer covers the top of the grid structure; forming first contact holes exposing the tops of the source-drain doping layers in the dielectric layers on two sides of the gate structure; forming a first conductive layer in the first contact hole, wherein the first conductive layer is electrically connected with the source-drain doped layer, and the top of the first conductive layer is lower than the top of the grid structure; forming a side wall layer on the side wall of the first contact hole exposed by the first conductive layer after forming the first conductive layer; after forming the sidewall layer, a second conductive layer is formed in the first contact hole, and the second conductive layer and the first conductive layer are used for forming a first contact hole plug. The embodiment of the invention is beneficial to reducing the contact resistance of the first contact hole plug and the source-drain doped layer and improving the breakdown voltage between the first contact hole plug and the grid structure, thereby improving the electrical property of the semiconductor structure.

Description

Semiconductor structure and forming method thereof
Technical Field
The present disclosure relates to semiconductor manufacturing, and more particularly, to a semiconductor structure and a method for forming the same.
Background
With the continued development of integrated circuit fabrication technology, the demands on the degree of integration and performance of integrated circuits are becoming ever higher. In order to improve the integration level and reduce the cost, the critical dimensions of the components are continuously reduced, and the circuit density inside the integrated circuit is increasingly high, so that the wafer surface cannot provide enough area to manufacture the required interconnection line.
In order to meet the requirements of the interconnect lines with reduced critical dimensions, the different metal layers or the conduction between the metal layers and the substrate is realized through the interconnect structure. The interconnect structure includes an interconnect line and a contact hole plug formed within the contact opening. The contact hole plugs are connected with the semiconductor device, and the interconnection lines realize the connection between the contact hole plugs, so that a circuit is formed.
The contact hole plug in the transistor structure comprises a contact hole plug positioned on the surface of the gate structure and used for realizing connection between the gate structure and an external circuit, and also comprises a contact hole plug positioned on the surface of the source-drain doped layer and used for realizing connection between the source-drain doped layer and the external circuit.
Because the critical dimension of the device is continuously reduced, the distance between the source and drain doped layers and the gate structure is continuously reduced, and the distance between the contact hole plug electrically connected with the source and drain doped layers and the gate structure is correspondingly reduced, the breakdown voltage between the contact hole plug and the gate structure is easily reduced, and the electrical performance of the semiconductor structure is adversely affected. Therefore, a sidewall layer is generally formed on the sidewall of the contact hole to increase the breakdown voltage between the contact hole plug and the gate structure on the surface of the source/drain doped layer.
Disclosure of Invention
The embodiment of the invention solves the problem of providing a semiconductor structure and a forming method thereof, and improves the electrical performance of the semiconductor structure.
In order to solve the above problems, the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate, wherein a grid structure is formed on the substrate, source drain doping layers are formed in the substrates at two sides of the grid structure, a dielectric layer is formed on the substrate exposed by the grid structure, and the dielectric layer covers the top of the grid structure; forming first contact holes in the dielectric layers at two sides of the gate structure, wherein the first contact holes expose the tops of the source-drain doped layers; forming a first conductive layer in the first contact hole, wherein the first conductive layer is electrically connected with the source-drain doped layer, and the top of the first conductive layer is lower than the top of the grid structure; forming a first conductive layer in the first contact hole, and forming a side wall layer on the side wall of the first contact hole exposed by the first conductive layer; and after the side wall layer is formed, forming a second conductive layer in the first contact hole, wherein the second conductive layer and the first conductive layer are used for forming a first contact hole plug.
Correspondingly, the embodiment of the invention also provides a semiconductor structure, which comprises: a substrate; a gate structure on the substrate; the source-drain doping layers are positioned in the substrates at two sides of the grid structure; the dielectric layer is positioned on the substrate exposed by the grid electrode structure and covers the top of the grid electrode structure; the first contact hole plug is positioned in the dielectric layer at two sides of the grid structure and is electrically connected with the source-drain doping layer, the first contact hole plug comprises a first conductive layer and a second conductive layer positioned on the first conductive layer, the top of the first conductive layer is lower than the top of the grid structure, and the second conductive layer covers part of the top of the first conductive layer; and the side wall layer is positioned between the second conductive layer and the dielectric layer.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following advantages:
in the embodiment of the invention, a first conductive layer electrically connected with the source-drain doped layer is formed in the first contact hole, and the top of the first conductive layer is lower than the top of the grid structure; forming a side wall layer on the side wall of the contact hole exposed by the first conductive layer after forming the first conductive layer in the first contact hole; after the side wall layer is formed, a second conductive layer is formed in the first contact hole, the second conductive layer and the first conductive layer are used for forming a first contact hole plug, compared with the scheme that the side wall layer is formed on the whole side wall of the first contact hole, the side wall layer only covers the side wall of the first contact hole exposed by the first conductive layer, the contact area of the first conductive layer and the source-drain doping layer is large, so that the contact resistance of the first contact hole plug and the source-drain doping layer is reduced, and the side wall layer is formed between the second conductive layer and the grid structure, so that the breakdown voltage between the first contact hole plug and the grid structure is improved, and the electrical performance of the semiconductor structure is improved.
Drawings
Fig. 1 to 4 are schematic structural views corresponding to steps in a method for forming a semiconductor structure;
fig. 5 to 13 are schematic structural views corresponding to each step in an embodiment of a method for forming a semiconductor structure according to the present invention.
Detailed Description
The devices formed at present still have the problem of poor performance. The reason for the poor performance of the device is analyzed by combining a forming method of a semiconductor structure.
Referring to fig. 1 to 4, schematic structural diagrams corresponding to steps in a method for forming a semiconductor structure are shown.
Referring to fig. 1, a substrate 500 is provided, a gate structure 520 is formed on the substrate 500, source-drain doped layers 550 are formed in the substrate 500 at two sides of the gate structure 520, a dielectric layer 560 is formed on the substrate 500 where the gate structure 520 is exposed, and the dielectric layer 560 covers the top of the gate structure 520.
Referring to fig. 2, a contact hole 600 is formed in the dielectric layer 560 at two sides of the gate structure 520, and the contact hole 600 exposes the top of the source-drain doped layer 550.
Referring to fig. 3, a sidewall layer 570 is formed on the sidewalls of the contact hole 600.
Referring to fig. 4, after the sidewall layer 570 is formed, a contact hole plug 580 is formed in the contact hole 600.
After the sidewall layer 570 is formed on the sidewall of the contact hole 600, the breakdown voltages of the contact hole plug 580 and the gate structure 520 are advantageously increased, but the sidewall layer 570 occupies a part of the space of the contact hole 600, and the opening size at the bottom of the contact hole 600 is smaller, so that the formation of the sidewall layer 570 reduces the contact area between the contact hole plug 580 and the source/drain doped layer 550, thereby resulting in a larger contact resistance between the contact hole plug 580 and the source/drain doped layer 550 and further reducing the electrical performance of the semiconductor structure.
In order to solve the technical problem, the invention provides a method for forming a semiconductor structure, which comprises the following steps: providing a substrate, wherein a grid structure is formed on the substrate, source drain doping layers are formed in the substrates at two sides of the grid structure, a dielectric layer is formed on the substrate exposed by the grid structure, and the dielectric layer covers the top of the grid structure; forming first contact holes in the dielectric layers at two sides of the gate structure, wherein the first contact holes expose the tops of the source-drain doped layers; forming a first conductive layer in the first contact hole, wherein the first conductive layer is electrically connected with the source-drain doped layer, and the top of the first conductive layer is lower than the top of the grid structure; forming a first conductive layer in the first contact hole, and forming a side wall layer on the side wall of the first contact hole exposed by the first conductive layer; and after the side wall layer is formed, forming a second conductive layer in the first contact hole, wherein the second conductive layer and the first conductive layer are used for forming a first contact hole plug.
In the embodiment of the invention, a first conductive layer electrically connected with the source-drain doped layer is formed in the first contact hole, and the top of the first conductive layer is lower than the top of the grid structure; forming a side wall layer on the side wall of the contact hole exposed by the first conductive layer after forming the first conductive layer in the first contact hole; after the side wall layer is formed, a second conductive layer is formed in the first contact hole, the second conductive layer and the first conductive layer are used for forming a first contact hole plug, compared with the scheme that the side wall layer is formed on the whole side wall of the first contact hole, the side wall layer only covers the side wall of the first contact hole exposed by the first conductive layer, the contact area of the first conductive layer and the source-drain doping layer is large, so that the contact resistance of the first contact hole plug and the source-drain doping layer is reduced, and the side wall layer is formed between the second conductive layer and the grid structure, so that the breakdown voltage between the first contact hole plug and the grid structure is improved, and the electrical performance of the semiconductor structure is improved.
In order that the above objects, features and advantages of embodiments of the invention may be readily understood, a more particular description of the invention will be rendered by reference to specific embodiments thereof which are illustrated in the appended drawings.
Fig. 5 to 13 are schematic structural views corresponding to each step in an embodiment of a method for forming a semiconductor structure according to the present invention.
Referring to fig. 5 to 6, a substrate 115 is provided, a gate structure 112 is formed on the substrate 115, source-drain doped layers 150 are formed in the substrate 115 at two sides of the gate structure 112, a dielectric layer 165 (as shown in fig. 6) is formed on the substrate 115 exposed by the gate structure 112, and the dielectric layer 165 covers the top of the gate structure 112.
The substrate 115 provides a process platform for subsequent formation of semiconductor structures.
In this embodiment, the substrate 115 is used to form a finfet. Accordingly, the base 115 includes the substrate 100 and the fin portion 110 protruding from the substrate 100, and correspondingly, the source-drain doped layer 150 is located in the fin portion 110 at two sides of the gate structure 112.
In this embodiment, the substrate 100 is a silicon substrate. In other embodiments, the substrate may also be made of other materials such as germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, and the substrate may also be made of other types of substrates such as silicon on insulator substrates or germanium on insulator substrates. The material of the substrate may be a material suitable for process requirements or easy integration.
In this embodiment, the fin 110 and the substrate 100 are integrally formed. Therefore, in this embodiment, the material of the fin portion 110 is the same as the material of the substrate 100, and the material of the fin portion 110 is silicon. In other embodiments, the material of the fin portion may be a semiconductor material suitable for forming the fin portion, such as germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, and the material of the fin portion may be different from the material of the substrate.
In this embodiment, an isolation layer 111 is further formed on the substrate 100 exposed by the fin portion 110, and the isolation layer 111 covers a portion of the sidewall of the fin portion 110.
The isolation layer 111 is used to isolate adjacent devices. Specifically, the isolation layer 111 is a shallow trench isolation structure (shallow trench isolation, STI).
In this embodiment, the material of the isolation layer 111 is silicon oxide. In other embodiments, the material of the isolation layer may be silicon nitride or other insulating materials such as silicon oxynitride.
In this embodiment, the gate structure 112 spans a portion of the top and a portion of the sidewalls of the fin 110. Specifically, the gate structure 112 is a metal gate structure, and the gate structure 112 includes a high-k gate dielectric layer (not shown) and a gate electrode (not shown) disposed on the high-k gate dielectric layer. In this embodiment, in order to improve the performance of the device, a gate last (gate last) is used to form the gate structure 112. In other embodiments, the process of forming the gate structure may also be a gate first process (gate first) or other processes.
In this embodiment, an etch stop layer 120 is also formed on top of the gate structure 112.
The etch stop layer 120 is used to protect the top of the gate structure 112 during formation of the dielectric layer 165. Furthermore, the subsequent process further comprises: a second contact hole is formed in the dielectric layer 165 on top of the gate structure 112, where the second contact hole exposes the top of the gate structure 112, so that the etching stop layer 120 is used to define a position where etching is stopped during the process of forming the second contact hole, thereby being beneficial to reducing the probability of damage to the gate structure 112.
In this embodiment, the material of the etching stop layer 120 is silicon nitride, and the hardness and the density of the silicon nitride are higher, so that the etching stop layer 120 can better play a role in defining the etching stop in the subsequent process of forming the second contact hole.
In this embodiment, a sidewall 130 is further formed on the sidewall of the gate structure 112.
The sidewall 130 is used for protecting the sidewall of the gate structure 112, and the sidewall 130 is further used for defining a formation region of the source-drain doped layer 150, so as to prevent the source-drain doped layer 150 from being too close to the channel region. Specifically, the sidewall 130 also covers the sidewall of the etching stop layer 120.
The material of the side wall 130 may be one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride oxide, silicon oxycarbide, boron nitride and boron carbonitride, and the side wall 130 may have a single-layer structure or a stacked-layer structure. In this embodiment, the side wall 130 is a single-layer structure, and the material of the side wall 130 is silicon nitride.
In this embodiment, the fin field effect transistor is an NMOS transistor, the source-drain doped layer 150 includes a stress layer doped with N-type ions, and the material of the stress layer may be Si or SiC, and the stress layer provides a tensile stress effect for a channel region of the NMOS transistor, so As to be beneficial to improving carrier mobility of the NMOS transistor, where the N-type ions are P ions, as ions, or Sb ions. In other embodiments, when the fin field effect transistor is a PMOS transistor, the source-drain doped layer includes a stress layer doped with P-type ions, where the stress layer may be Si or SiGe, and the stress layer provides compressive stress to a channel region of the PMOS transistor, so as to facilitate improving carrier mobility of the PMOS transistor, where the P-type ions are B ions, ga ions, or In ions.
The dielectric layer 165 is used to isolate adjacent devices, and the dielectric layer 165 is further used to provide a process platform for subsequently forming a first contact plug electrically connected to the source/drain doped layer 150 and a second contact plug electrically connected to the gate structure 112.
In this embodiment, the dielectric layer 165 includes a bottom dielectric layer 140 and a top dielectric layer 160 on the bottom dielectric layer 140, and the top of the bottom dielectric layer 140 is flush with the top of the etching stop layer 120.
In this embodiment, the bottom dielectric layer 140 is an interlayer dielectric layer (Inter Layer Dielectrics, ILD), and the bottom dielectric layer 140 is used to define the size and location of the gate structure 112 in the post-gate process.
The material of the bottom dielectric layer 140 is an insulating material. In this embodiment, the material of the bottom dielectric layer 140 is silicon oxide. In other embodiments, the material of the bottom dielectric layer may be another insulating material such as silicon nitride or silicon oxynitride.
In this embodiment, the top dielectric layer 160 is an Inter-metal dielectric (IMD), and the top dielectric layer 160 is used to provide a process platform for the subsequent formation of a second contact plug electrically connected to the gate structure 112.
The material of the top dielectric layer 160 is an insulating material. In this embodiment, in order to improve process compatibility, the materials of the top dielectric layer 160 and the bottom dielectric layer 140 are the same, the material of the bottom dielectric layer 140 is silicon oxide, and the material of the top dielectric layer 160 is correspondingly silicon oxide. In other embodiments, the material of the top dielectric layer may be silicon nitride or other insulating materials such as silicon oxynitride.
Specifically, referring to fig. 5 and 6 in combination, the step of forming the gate structure 112, the source-drain doped layer 150, and the dielectric layer 165 includes: forming a dummy gate structure (not shown) across the fin 110, the dummy gate structure covering a portion of the top and a portion of the sidewalls of the fin 110; forming source-drain doped layers 150 in the fin portions 110 at two sides of the pseudo gate structure; after forming the source-drain doped layer 150, forming a bottom dielectric film (not shown) covering the top of the dummy gate structure on the substrate 115 exposed by the dummy gate structure; planarizing the bottom dielectric film to expose the top of the dummy gate structure, leaving the remaining bottom dielectric film for use as the bottom dielectric layer 140; removing the dummy gate structure, forming a gate opening (not shown) in the bottom dielectric layer 140, forming an initial gate structure (not shown) in the gate opening, and etching back the initial gate structure to form the gate structure 112, wherein the top of the gate structure 112 is lower than the top of the bottom dielectric layer 140; forming the etching stop layer 120 on top of the gate structure 112, wherein the top of the etching stop layer 120 is flush with the bottom dielectric layer 140; a top dielectric film (not shown) is formed on the surface of the bottom dielectric layer 140, the top dielectric film is planarized, and the remaining top dielectric film remains to be used as the top dielectric layer 160, and the top dielectric layer 160 and the bottom dielectric layer 140 are used to form the dielectric layer 165.
Referring to fig. 7, a first contact hole 200 is formed in the dielectric layer 165 at two sides of the gate structure 112, and the first contact hole 200 exposes the top of the source-drain doped layer 150.
The first contact hole 200 provides a spatial location for the subsequent formation of a first contact hole plug.
In this embodiment, the step of forming the first contact hole 200 in the dielectric layer 165 on both sides of the gate structure 112 includes: and sequentially etching the top dielectric layer 160 and the bottom dielectric layer 140 on both sides of the gate structure 112 by adopting a dry etching process until the top of the source-drain doped layer 150 is exposed.
The dry etching process is an anisotropic etching process, has good etching profile control, and is beneficial to enabling the morphology of the first contact hole 200 to meet the process requirements.
In this embodiment, the shape of the first contact hole 200 is an inverted trapezoid, and the bottom opening size of the first contact hole 200 is smaller than the top opening size. In other embodiments, the sidewall of the first contact hole may be perpendicular to the surface of the substrate according to actual process requirements.
In other embodiments, the process of etching the dielectric layers on two sides of the gate structure may be a wet etching process or a process combining a dry process and a wet process according to the morphology of the first contact hole.
Referring to fig. 8 to 9, a first conductive layer 170 (shown in fig. 9) electrically connected to the source and drain doped layer 150 is formed in the first contact hole 200 (shown in fig. 7), and the top of the first conductive layer 170 is lower than the top of the gate structure 112.
The first conductive layer 170 is used to provide a process basis for the subsequent formation of a first contact plug electrically connected to the source/drain doped layer 150.
In this embodiment, the top of the first conductive layer 170 is lower than the top of the gate structure 112, and after a sidewall layer is formed on the sidewall of the first contact hole 200, the sidewall layer only covers the sidewall of the first contact hole 200 exposed by the first conductive layer 170, and the sidewall layer is not formed between the first conductive layer 170 and the dielectric layer 165, so that the contact area between the first conductive layer 170 and the source-drain doped layer 150 is larger, which is beneficial to reducing the contact resistance between the first contact hole plug and the source-drain doped layer 150; moreover, by making the top of the first conductive layer 170 lower than the top of the gate structure 112, the sidewall layer is formed between the second conductive layer in the bottom dielectric layer 140 and the gate structure 112, so that it is beneficial to improve the breakdown voltage between the first contact plug and the gate structure 112, and further to improve the electrical performance of the semiconductor structure.
In this embodiment, since the shape of the first contact hole 200 is inverted trapezoid, the sidewall of the first contact hole 200 is an inclined sidewall correspondingly, so that the closer to the top of the bottom dielectric layer 140, the closer to the gate structure 112 the sidewall of the first contact hole 200 located in the bottom dielectric layer 140 is, the sidewall layer is formed on the sidewall of the first contact hole 200 close to the gate structure 112 by making the top of the first conductive layer 170 lower than the top of the gate structure 112, so that the sidewall layer has more remarkable function of isolating the first contact hole plug and the gate structure 112, thereby further improving the breakdown voltage between the first contact hole plug and the gate structure 112 and further improving the electrical performance of the semiconductor structure.
It should be noted that, in the normal direction of the surface of the substrate 115, the height difference d between the top of the first conductive layer 170 and the top of the gate structure 112 should not be too small or too large. If the difference d between the top of the first conductive layer 170 and the top of the gate structure 112 is too small, then after forming a sidewall layer on the sidewall of the first contact hole 200 exposed by the first conductive layer 170, the bottom of the sidewall layer is correspondingly close to the top of the gate structure 112, and the portion of the sidewall layer close to the gate structure 112 is correspondingly smaller, so that the effect of the sidewall layer for isolating the first contact hole plug and the gate structure 112 is easily reduced, and the effect of the sidewall layer for improving the breakdown voltage between the first contact hole plug and the gate structure 112 is easily reduced; if the difference d between the top of the first conductive layer 170 and the top of the gate structure 112 is too large, the height of the first conductive layer 170 is too small, which easily results in too high contact resistance between the first contact plug and the source/drain doped layer 150, thereby reducing the electrical performance of the semiconductor structure. For this reason, in the present embodiment, the difference in height between the top of the first conductive layer 170 and the top of the gate structure 112 is 15nm to 30nm.
The material of the first conductive layer 170 is tungsten or cobalt. In this embodiment, the material of the first conductive layer 170 is cobalt. The resistivity of cobalt is lower and the conductivity is better, so that the contact resistance between the first conductive layer 170 and the source-drain doped layer 150 is further reduced.
Specifically, the step of forming the first conductive layer 170 in the first contact hole 200 includes: filling the first contact hole 200 with a first conductive material layer 166 (as shown in fig. 8); a portion of the thickness of the first conductive material layer 166 is removed, leaving the remaining first conductive material layer 166 within the first contact hole 200 as the first conductive layer 170 (as shown in fig. 9).
In this embodiment, the process of filling the first conductive material layer 166 in the first contact hole 200 is a chemical vapor deposition process. The chemical vapor deposition process is a deposition process commonly used in the semiconductor field, and is beneficial to improving process compatibility and reducing process difficulty.
Thus, in the step of filling the first contact hole 200 with the first conductive material layer 166, the first conductive material layer 166 also covers the top of the dielectric layer 165; correspondingly, after the first conductive material layer 166 is filled in the first contact hole 200, before removing a part of the thickness of the first conductive material layer 166, the method further includes: and flattening the first conductive material layer 166, and removing the first conductive material layer 166 on the top of the dielectric layer 165, so that the top of the remaining first conductive material layer 166 is flush with the top of the dielectric layer 165. By the planarization process, the flatness of the top surface of the first conductive layer 170 is advantageously improved.
In this embodiment, the process of removing a portion of the thickness of the first conductive material layer 166 is a dry etching process.
The dry etching process is an anisotropic etching process, which is favorable for reducing the influence on the dielectric layer 165 in the process of removing the first conductive material layer 166 with partial thickness, improving the appearance quality of the first conductive layer 170, and reducing the probability of forming conductive material residues on the sidewalls of the first contact holes 200 exposed by the first conductive layer 170.
Referring to fig. 10 to 12, after the first conductive layer 170 is formed in the first contact hole 200, a sidewall layer 185 (shown in fig. 12) is formed on the sidewall of the first contact hole 200 where the first conductive layer 170 is exposed.
Compared with the scheme of forming the sidewall layer on the whole sidewall of the first contact hole, by forming the sidewall layer 185 on the sidewall of the first contact hole 200 exposed by the first conductive layer 170, the sidewall layer 185 only covers the sidewall of the first contact hole 200 exposed by the first conductive layer 170, which is beneficial to reducing the contact resistance between the subsequent first contact hole plug and the source drain doped layer 150; further, after the second conductive layer is formed in the first contact hole 200, a sidewall layer 185 is formed between the second conductive layer and the gate structure 112, which is beneficial to improving the breakdown voltage between the first contact hole plug and the gate structure 112.
The thickness of the sidewall layer 185 is not too small or too large in the direction perpendicular to the sidewall of the first contact hole 200. If the thickness of the sidewall layer 185 is too small, the effect of the sidewall layer 185 to isolate the second conductive layer from the gate structure 112 is easily reduced, thereby easily reducing the effect of the sidewall layer 185 to increase the breakdown voltage between the first contact plug and the gate structure 112; if the thickness of the sidewall layer 185 is too large, the contact area between the second conductive layer and the first conductive layer 170 is too small, so that the contact resistance between the first contact plug and the source drain doped layer 150 is easily increased. For this reason, in the present embodiment, the thickness of the sidewall layer 185 is 3nm to 8nm in the direction perpendicular to the sidewall of the first contact hole 200.
The material of the sidewall layer 185 is a dielectric material in order to isolate the subsequent second conductive layer from the gate structure 112.
In this embodiment, the material of the sidewall layer 185 is silicon nitride, and the density of the silicon nitride is high, so that the sidewall layer has a good isolation effect, which is beneficial to further improving the breakdown voltage between the first contact plug and the gate structure 112. In other embodiments, the material of the sidewall layer may be silicon oxynitride, silicon oxide, or other insulating materials.
Specifically, the step of forming the sidewall layer 185 on the sidewall of the first contact hole 200 where the first conductive layer 170 is exposed includes: forming a sidewall film 180 conformally covering the exposed sidewalls of the first contact hole 200 of the first conductive layer 170 and the top of the first conductive layer 170 (as shown in fig. 10), wherein the sidewall film 180 also covers the top of the dielectric layer 165; the sidewall film 180 on top of the first conductive layer 170 and on top of the dielectric layer 165 is removed, and the sidewall film 180 located on the sidewall of the first contact hole 200 is left as the sidewall layer 185.
In this embodiment, the process of forming the sidewall film 180 is an atomic layer deposition (Atomic layer deposition, ALD) process.
The atomic layer deposition process has a better conformal coverage capability, which is beneficial to ensuring that the sidewall film 180 can conformally cover the sidewall of the first contact hole 200 and the top of the first conductive layer 170 exposed by the first conductive layer 170 in the step of forming the sidewall film 180, and is beneficial to improving the thickness uniformity of the sidewall layer 185.
In this embodiment, the process of removing the sidewall film 180 on top of the first conductive layer 170 and on top of the dielectric layer 165 is a dry etching process.
The dry etching process is an anisotropic etching process, which is advantageous in reducing the probability of damage to the sidewall film 180 on the sidewall of the first contact hole 200 in the step of removing the sidewall film 180 on the top of the first conductive layer 170 and on the top of the dielectric layer 165, so that the sidewall film 180 on the sidewall of the first contact hole 200 is preserved after removing the sidewall film 180 on the top of the first conductive layer 170 and on the top of the dielectric layer 165, and in improving the film quality of the sidewall layer 185.
Referring to fig. 11 in combination, in this embodiment, after forming the sidewall film 180, before removing the sidewall film 180 on top of the first conductive layer 170 and on top of the dielectric layer 165, the method further includes: an initial second contact hole 300 is formed in the dielectric layer 165 on top of the gate structure 112, the initial second contact hole 300 exposing the top of the etch stop layer 120.
The initial second contact hole 300 is used to provide a process basis for the subsequent formation of a second contact hole through the top dielectric layer 160 and the etch stop layer 120.
In this embodiment, before removing the sidewall films 180 on the top of the first conductive layer 170 and on the top of the dielectric layer 165, the initial second contact hole 300 exposing the top of the etching stop layer 120 is formed, and since the material of the etching stop layer 120 and the material of the sidewall film 180 are the same, the sidewall films 180 on the top of the first conductive layer 170 and on the top of the dielectric layer 165 and the etching stop layer 120 exposed by the initial second contact hole 300 can be removed in the same step, which is beneficial to simplifying the process steps and improving the process manufacturing efficiency; in addition, compared with the scheme that the initial second contact hole 300 exposes the top of the gate structure 112, the etching stop layer exposed by the initial second contact hole 300 can be etched first in the step of removing the sidewall film 180 on the top of the first conductive layer 170 and the top of the dielectric layer 165, thereby being beneficial to reducing the probability of damaging the top of the gate structure 112.
Referring to fig. 12 in combination, correspondingly, in this embodiment, the forming method further includes: and removing the etching stop layer 120 exposed by the initial second contact hole 300, exposing the top of the gate structure 112, and forming a second contact hole 400 penetrating the dielectric layer 165 and the etching stop layer 120.
The second contact hole 400 provides a space for a subsequent formation of a second contact hole plug.
In this embodiment, the materials of the etching stop layer 120 and the sidewall film 180 are the same, so that in the step of removing the sidewall film 180 on top of the first conductive layer 170 and on top of the dielectric layer 165, the etching stop layer 120 exposed by the initial second contact hole 300 is removed.
By removing the sidewall films on top of the first conductive layer 170 and on top of the dielectric layer 165 and the etching stop layer 120 exposed by the initial second contact hole 300 in the same process step, the process steps are simplified, and the process manufacturing efficiency is improved. In other embodiments, the step of removing the sidewall films on top of the first conductive layer and on top of the dielectric layer and the step of removing the etching stop layer exposed by the initial second contact hole may also be performed in different process steps.
Referring to fig. 13, after the sidewall layer 185 is formed, a second conductive layer 190 is formed in the first contact hole 200 (as shown in fig. 12), and the second conductive layer 190 and the first conductive layer 170 are used to form a first contact hole plug 191.
A sidewall layer 185 is formed between the second conductive layer 190 and the gate structure 112, which is beneficial to improving the breakdown voltage between the first contact plug 191 and the gate structure 112, thereby improving the electrical performance of the semiconductor structure.
In this embodiment, the material of the second conductive layer 190 is tungsten. Tungsten is a common metal material used in contact plug fabrication, which is beneficial to improving process compatibility.
Specifically, the step of forming the second conductive layer 190 in the first contact hole 200 includes: filling a second conductive material layer (not shown) in the first contact hole 200, wherein the second conductive material layer also covers the top of the dielectric layer 165; and flattening the second conductive material layer, removing the second conductive material layer higher than the top of the dielectric layer 165, and keeping the remaining second conductive material layer as the second conductive layer 190, wherein the top of the second conductive layer 190 is flush with the top of the dielectric layer 165.
In this embodiment, the step of forming the second conductive layer 190 in the first contact hole 200 further includes: a second contact plug 195 electrically connected to the gate structure 112 is formed within the second contact hole 300 (shown in fig. 12), the top of the second contact plug 195 being flush with the top of the dielectric layer 165.
In this embodiment, in order to simplify the process steps and improve the process compatibility, the second contact hole plug 195 and the second conductive layer 190 are formed in the same step, and accordingly, the material of the second contact hole plug 195 is the same as that of the second conductive layer 190, and the material of the second contact hole plug 195 is tungsten. In other embodiments, the second contact plug and the second conductive layer may also be formed in different process steps, and accordingly, the material of the second contact plug may also be different from the second conductive layer.
Correspondingly, the embodiment of the invention also provides a semiconductor structure. Referring to fig. 13, a schematic structure diagram of an embodiment of the semiconductor structure of the present invention is shown.
The semiconductor structure includes: a substrate 115; a gate structure 112 on the substrate 115; the source-drain doped layer 150 is located in the substrate 115 at two sides of the gate structure 112; a dielectric layer 165 on the exposed substrate 115 of the gate structure 112, where the dielectric layer 165 covers the top of the gate structure 112; a first contact plug 191 located in the dielectric layer 165 at two sides of the gate structure 112 and electrically connected to the source-drain doped layer 150, where the first contact plug 191 includes a first conductive layer 170 and a second conductive layer 190 located on the first conductive layer 170, the top of the first conductive layer 170 is lower than the top of the gate structure 112, and the second conductive layer 190 covers a part of the top of the first conductive layer 170; a sidewall layer 185 between the second conductive layer 190 and the dielectric layer 165.
The substrate 115 provides a process platform for the formation of semiconductor structures.
In this embodiment, the semiconductor structure is a fin field effect transistor. Accordingly, the base 115 includes the substrate 100 and the fin portion 110 protruding from the substrate 100, and correspondingly, the source-drain doped layer 150 is located in the fin portion 110 at two sides of the gate structure 112.
In this embodiment, the substrate 100 is a silicon substrate. In other embodiments, the substrate may also be made of other materials such as germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, and the substrate may also be made of other types of substrates such as silicon on insulator substrates or germanium on insulator substrates. The material of the substrate may be a material suitable for process requirements or easy integration.
In this embodiment, the fin 110 and the substrate 100 are integrally formed. Therefore, in this embodiment, the material of the fin portion 110 is the same as the material of the substrate 100, and the material of the fin portion 110 is silicon. In other embodiments, the material of the fin portion may be a semiconductor material suitable for forming the fin portion, such as germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, and the material of the fin portion may be different from the material of the substrate.
In this embodiment, the semiconductor structure further includes: and the isolation layer 111 is positioned on the substrate 100 exposed by the fin portion 110.
The isolation layer 111 is used to isolate adjacent devices. Specifically, the isolation layer 111 is a shallow trench isolation structure.
In this embodiment, the material of the isolation layer 111 is silicon oxide. In other embodiments, the material of the isolation layer may be silicon nitride or other insulating materials such as silicon oxynitride.
In this embodiment, the gate structure 112 is a metal gate structure, and the gate structure 112 spans the fin 110 and covers a portion of the top and a portion of the sidewall of the fin 110, and the gate structure 112 includes a high-k gate dielectric layer (not shown) and a gate electrode (not shown) on the high-k gate dielectric layer.
The dielectric layer 165 is used to isolate adjacent devices, and the dielectric layer 165 is further used to provide a process platform for forming a first contact plug 191 electrically connected to the source/drain doped layer 150 and a second contact plug 195 electrically connected to the gate structure 112.
In this embodiment, the dielectric layer 165 includes a bottom dielectric layer 140 and a top dielectric layer 160 on the bottom dielectric layer 140, and the top of the bottom dielectric layer 140 is flush with the top of the etching stop layer 120.
In this embodiment, the bottom dielectric layer 140 is an interlayer dielectric layer, and the bottom dielectric layer 140 is used to define the size and the position of the gate structure 112.
The material of the bottom dielectric layer 140 is an insulating material. In this embodiment, the material of the bottom dielectric layer 140 is silicon oxide. In other embodiments, the material of the bottom dielectric layer may be another insulating material such as silicon nitride or silicon oxynitride.
In this embodiment, the top dielectric layer 160 is a metal dielectric layer, and the top dielectric layer 160 is further used to form a second contact plug 195 electrically connected to the gate structure 112 to provide a process platform.
The material of the top dielectric layer 160 is an insulating material. In this embodiment, in order to improve process compatibility, the materials of the top dielectric layer 160 and the bottom dielectric layer 140 are the same, the material of the bottom dielectric layer 140 is silicon oxide, and the material of the top dielectric layer 160 is correspondingly silicon oxide. In other embodiments, the material of the top dielectric layer may be silicon nitride or other insulating materials such as silicon oxynitride.
The first contact plug 191 is used to make electrical connection with the source drain doped layer 150.
In this embodiment, the top of the first conductive layer 170 is lower than the top of the gate structure 112, the sidewall layer 185 is only located between the second conductive layer 190 and the dielectric layer 165, and the sidewall layer 185 is not formed between the first conductive layer 170 and the dielectric layer 165, so that the contact area between the first conductive layer 170 and the source-drain doped layer 150 is larger, which is beneficial to reducing the contact resistance between the first contact plug 191 and the source-drain doped layer 150; moreover, by making the top of the first conductive layer 170 lower than the top of the gate structure 112, a sidewall layer 185 is formed between the second conductive layer 190 located in the bottom dielectric layer 140 and the gate structure 112, so that it is advantageous to increase the breakdown voltage between the first contact plug 191 and the gate structure 112, and thus to increase the electrical performance of the semiconductor structure.
In this embodiment, the sidewall of the first contact hole plug 191 is an inclined sidewall, so the closer to the top of the bottom dielectric layer 140, the closer to the gate structure 112 the sidewall of the first contact hole plug 191 located in the bottom dielectric layer 140, and by making the top of the first conductive layer 170 lower than the top of the gate structure 112, the sidewall layer 185 is formed on the sidewall of the first contact hole plug 191 close to the gate structure 112, so the effect of the sidewall layer 185 for isolating the first contact hole plug 191 and the gate structure 112 is more remarkable, thereby further improving the breakdown voltage between the first contact hole plug 191 and the gate structure 112 and further improving the electrical performance of the semiconductor structure.
It should be noted that, in the normal direction of the surface of the substrate 115, the height difference d between the top of the first conductive layer 170 and the top of the gate structure 112 should not be too small or too large. If the difference d in height between the top of the first conductive layer 170 and the top of the gate structure 112 is too small, the bottom of the sidewall layer 185 is correspondingly close to the top of the gate structure 112, and the portion of the sidewall layer 185 close to the gate structure 112 is correspondingly smaller, so that the effect of the sidewall layer 185 for isolating the first contact hole plug 191 and the gate structure 112 is easily reduced, and thus the effect of the sidewall layer 185 for increasing the breakdown voltage between the first contact hole plug 191 and the gate structure 112 is easily reduced; if the difference d between the top of the first conductive layer 170 and the top of the gate structure 112 is too large, the height of the first conductive layer 170 is too small, which easily results in too high contact resistance between the first contact plug 191 and the source/drain doped layer 150, thereby degrading the electrical performance of the semiconductor structure. For this reason, in the present embodiment, the difference in height between the top of the first conductive layer 170 and the top of the gate structure 112 is 15nm to 30nm.
The material of the first conductive layer 170 is tungsten or cobalt. In this embodiment, the material of the first conductive layer 170 is cobalt. The resistivity of cobalt is lower and the conductivity is better, so that the contact resistance between the first conductive layer 170 and the source-drain doped layer 150 is further reduced.
In this embodiment, the material of the second conductive layer 190 is tungsten. Tungsten is a common metal material used in contact plug fabrication, which is beneficial to improving process compatibility.
Compared with the scheme that the side wall layer 185 is positioned between the first contact hole plug 191 and the dielectric layer 165, the side wall layer 185 is positioned only between the second conductive layer 190 and the dielectric layer 165, and the contact area between the first contact hole plug 191 and the source-drain doped layer 150 is larger, so that the contact resistance between the first contact hole plug 191 and the source-drain doped layer 150 is reduced; moreover, a sidewall layer 185 is formed between the second conductive layer 190 and the gate structure 112, and the sidewall layer 185 can isolate the first contact plug 191 from the gate structure 112, so that it is beneficial to improve the breakdown voltage between the first contact plug 191 and the gate structure 112, thereby improving the electrical performance of the semiconductor structure.
The thickness of the sidewall layer 185 is not too small or too large in the direction perpendicular to the sidewall of the second conductive layer 190. If the thickness of the sidewall layer 185 is too small, the effect of the sidewall layer 185 for isolating the second conductive layer 190 and the gate structure 112 is easily reduced, thereby easily reducing the effect of the sidewall layer 185 for improving the breakdown voltage between the first contact hole plug 191 and the gate structure 112; if the thickness of the sidewall layer 185 is too large, the contact area of the second conductive layer 190 with the first conductive layer 170 is too small, so that the contact resistance of the first contact hole plugs 191 and the source-drain doped layer 150 is easily increased. For this reason, in the present embodiment, the thickness of the sidewall layer 185 is 3nm to 8nm in the direction perpendicular to the sidewall of the first contact hole 200.
To enable the sidewall layer 185 to isolate the second conductive layer 190 from the gate structure 112, the sidewall layer 185 is formed of a dielectric material.
In this embodiment, the material of the sidewall layer 185 is silicon nitride, and the density of the silicon nitride is high, so that the sidewall layer has a good isolation effect, which is beneficial to further improving the breakdown voltage between the first contact hole plug 191 and the gate structure 112. In other embodiments, the material of the sidewall layer may be silicon oxynitride, silicon oxide, or other insulating materials.
In this embodiment, the semiconductor structure further includes: a second contact plug 195 is located in the dielectric layer 165 on top of the gate structure 112, the second contact plug 195 being electrically connected to the gate structure 112. Specifically, the top of the second contact plug 195 is flush with the top of the dielectric layer 165.
In this embodiment, in order to simplify the process steps and improve the process compatibility, the second contact hole plug 195 and the second conductive layer 190 are formed in the same step, and accordingly, the material of the second contact hole plug 195 is the same as that of the second conductive layer 190, and the material of the second contact hole plug 195 is tungsten. In other embodiments, the second contact plug and the second conductive layer may also be formed in different process steps, and accordingly, the material of the second contact plug may also be different from the second conductive layer.
In this embodiment, an etch stop layer 120 is also formed on top of the gate structure 112.
The etch stop layer 120 is used to protect the top of the gate structure 112 during formation of the dielectric layer 165. In addition, in the semiconductor process, after a contact hole exposing the top of the gate structure 112 is formed in the dielectric layer 165 on the top of the gate structure 112, a second contact hole plug 195 electrically connected to the gate structure 112 is formed in the contact hole, and the etching stop layer 120 can serve to define an etching stop position during the process of forming the contact hole, so that the probability of damage to the gate structure 112 is reduced.
In this embodiment, the material of the etching stop layer 120 is silicon nitride, and the hardness and the density of the silicon nitride are higher, so that the etching stop layer 120 can better play a role in defining the etching stop in the subsequent process of forming the second contact hole.
In this embodiment, the semiconductor structure further includes: and a sidewall 130 on the sidewall of the gate structure 112.
The side wall 130 is used for protecting the side wall of the gate structure 112 during the formation of the semiconductor structure, and the side wall 130 is also used for defining the formation region of the source/drain doped layer 150 to prevent the source/drain doped layer 150 from being too close to the channel region. Specifically, the sidewall 130 also covers the sidewall of the etching stop layer 120.
The material of the side wall 130 may be one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride oxide, silicon oxycarbide, boron nitride and boron carbonitride, and the side wall 130 may have a single-layer structure or a stacked-layer structure. In this embodiment, the side wall 130 is a single-layer structure, and the material of the side wall 130 is silicon nitride.
In this embodiment, when the fin field effect transistor is an NMOS transistor, the source-drain doped layer 150 includes a stress layer doped with N-type ions, where the material of the stress layer may be Si or SiC, and the stress layer provides a tensile stress effect for a channel region of the NMOS transistor, so As to be beneficial to improving carrier mobility of the NMOS transistor, where the N-type ions are P-ions, as ions, or Sb ions. In other embodiments, when the fin field effect transistor is a PMOS transistor, the source-drain doped layer includes a stress layer doped with P-type ions, where the material of the stress layer may be Si or SiGe, and the stress layer provides a compressive stress to a channel region of the PMOS transistor, so as to facilitate improving carrier mobility of the PMOS transistor, where the P-type ions are B ions, ga ions, or In ions.
The semiconductor structure may be formed by the forming method described in the foregoing embodiments, or may be formed by other forming methods. For a specific description of the semiconductor structure in this embodiment, reference may be made to the corresponding description in the foregoing embodiment, which is not repeated here.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.

Claims (11)

1. A method of forming a semiconductor structure, comprising:
providing a substrate, wherein a grid structure is formed on the substrate, source drain doping layers are formed in the substrates at two sides of the grid structure, a dielectric layer is formed on the substrate exposed by the grid structure, and the dielectric layer covers the top of the grid structure;
forming first contact holes in the dielectric layers at two sides of the gate structure, wherein the first contact holes expose the tops of the source-drain doped layers;
forming a first conductive layer in the first contact hole, wherein the first conductive layer is electrically connected with the source-drain doped layer, and the top of the first conductive layer is lower than the top of the grid structure; the height difference between the top of the first conductive layer and the top of the gate structure is 15nm to 30nm along the normal direction of the substrate surface; the step of forming the first conductive layer includes: filling a first conductive material layer in the first contact hole; removing part of the first conductive material layer, and reserving the rest first conductive material layer in the first contact hole as the first conductive layer;
Forming a first conductive layer in the first contact hole, and forming a side wall layer on the side wall of the first contact hole exposed by the first conductive layer; the step of forming the sidewall layer includes: forming a side wall film which conformally covers the side wall of the first contact hole exposed by the first conductive layer and the top of the first conductive layer, wherein the side wall film also covers the top of the dielectric layer; removing the side wall films at the top of the first conductive layer and the top of the dielectric layer, and reserving the side wall film positioned at the side wall of the first contact hole as the side wall layer;
and after the side wall layer is formed, forming a second conductive layer in the first contact hole, wherein the second conductive layer and the first conductive layer are used for forming a first contact hole plug.
2. The method of forming a semiconductor structure of claim 1, wherein forming a first conductive layer within the first contact hole comprises: filling a first conductive material layer in the first contact hole;
and removing part of the first conductive material layer, and reserving the rest first conductive material layer in the first contact hole as the first conductive layer.
3. The method of forming a semiconductor structure of claim 2, wherein the process of removing a portion of the thickness of the first conductive material layer is a dry etching process.
4. The method of forming a semiconductor structure of claim 1, wherein forming a sidewall layer on the exposed first contact hole sidewall of the first conductive layer comprises an atomic layer deposition process.
5. The method of claim 1, wherein the removing the sidewall film on top of the first conductive layer and on top of the dielectric layer is a dry etching process.
6. The method of forming a semiconductor structure of claim 1, wherein in the step of providing the substrate, an etch stop layer is further formed on top of the gate structure;
after the sidewall film is formed, before removing the sidewall film on top of the first conductive layer and on top of the dielectric layer, the method further comprises: forming an initial second contact hole in the dielectric layer at the top of the gate structure, wherein the initial second contact hole exposes the top of the etching stop layer;
the step of removing the top of the first conductive layer and the sidewall film at the top of the dielectric layer further comprises: removing the etching stop layer exposed by the initial second contact hole, exposing the top of the grid structure, and forming a second contact hole penetrating through the dielectric layer and the etching stop layer;
The step of forming the second conductive layer in the first contact hole further includes: and forming a second contact hole plug electrically connected with the grid structure in the second contact hole.
7. The method of claim 1, wherein the sidewall layer is a dielectric material.
8. The method of claim 1, wherein the sidewall layer is made of silicon nitride, silicon oxynitride or silicon oxide.
9. The method of forming a semiconductor structure of claim 1, wherein a thickness of the sidewall layer is 3nm to 8nm in a direction perpendicular to a sidewall surface of the first contact hole.
10. The method of claim 1, wherein the material of the first conductive layer is tungsten or cobalt and the material of the second conductive layer is tungsten.
11. The method of forming a semiconductor structure of claim 1, wherein the gate structure is a metal gate structure.
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