CN112309858B - Semiconductor structure and forming method thereof - Google Patents
Semiconductor structure and forming method thereof Download PDFInfo
- Publication number
- CN112309858B CN112309858B CN201910696119.XA CN201910696119A CN112309858B CN 112309858 B CN112309858 B CN 112309858B CN 201910696119 A CN201910696119 A CN 201910696119A CN 112309858 B CN112309858 B CN 112309858B
- Authority
- CN
- China
- Prior art keywords
- source
- layer
- forming
- drain
- drain doped
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000000034 method Methods 0.000 title claims abstract description 85
- 239000004065 semiconductor Substances 0.000 title claims abstract description 58
- 239000010410 layer Substances 0.000 claims abstract description 577
- 239000011241 protective layer Substances 0.000 claims abstract description 88
- 239000000758 substrate Substances 0.000 claims abstract description 75
- 239000011229 interlayer Substances 0.000 claims abstract description 50
- 230000008569 process Effects 0.000 claims description 55
- 239000000463 material Substances 0.000 claims description 54
- 150000002500 ions Chemical class 0.000 claims description 47
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 39
- 229910052710 silicon Inorganic materials 0.000 claims description 39
- 239000010703 silicon Substances 0.000 claims description 39
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 20
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 20
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 15
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 15
- 239000003989 dielectric material Substances 0.000 claims description 14
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims description 14
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 14
- 229910021332 silicide Inorganic materials 0.000 claims description 13
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 13
- 238000005530 etching Methods 0.000 claims description 6
- 229910003460 diamond Inorganic materials 0.000 claims description 4
- 239000010432 diamond Substances 0.000 claims description 4
- 238000011065 in-situ storage Methods 0.000 claims description 4
- 230000009286 beneficial effect Effects 0.000 abstract description 14
- 238000002955 isolation Methods 0.000 description 13
- 229910052751 metal Inorganic materials 0.000 description 11
- 239000002184 metal Substances 0.000 description 11
- 230000015572 biosynthetic process Effects 0.000 description 9
- 230000000694 effects Effects 0.000 description 7
- 230000005669 field effect Effects 0.000 description 6
- 239000002356 single layer Substances 0.000 description 5
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 4
- 229910008484 TiSi Inorganic materials 0.000 description 4
- 238000005229 chemical vapour deposition Methods 0.000 description 4
- 238000001312 dry etching Methods 0.000 description 3
- 230000009969 flowable effect Effects 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- 229910052721 tungsten Inorganic materials 0.000 description 3
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 2
- 229910052582 BN Inorganic materials 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- PZNSFCLAULLKQX-UHFFFAOYSA-N Boron nitride Chemical compound N#B PZNSFCLAULLKQX-UHFFFAOYSA-N 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 2
- 229910001080 W alloy Inorganic materials 0.000 description 2
- NTCVORQAIAUAJB-UHFFFAOYSA-N [Mg].[W] Chemical compound [Mg].[W] NTCVORQAIAUAJB-UHFFFAOYSA-N 0.000 description 2
- 229910003481 amorphous carbon Inorganic materials 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 229910017052 cobalt Inorganic materials 0.000 description 2
- 239000010941 cobalt Substances 0.000 description 2
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- 230000006872 improvement Effects 0.000 description 2
- 239000011810 insulating material Substances 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- 238000007517 polishing process Methods 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- 235000001674 Agaricus brunnescens Nutrition 0.000 description 1
- 229910018072 Al 2 O 3 Inorganic materials 0.000 description 1
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 1
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 description 1
- 229910004129 HfSiO Inorganic materials 0.000 description 1
- KXNLCSXBJCPWGL-UHFFFAOYSA-N [Ga].[As].[In] Chemical compound [Ga].[As].[In] KXNLCSXBJCPWGL-UHFFFAOYSA-N 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
- 239000011800 void material Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41791—Source or drain electrodes for field effect devices for transistors with a horizontal current flow in a vertical sidewall, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
- H01L29/66803—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with a step of doping the vertical sidewall, e.g. using tilted or multi-angled implants
Abstract
A semiconductor structure and a method for forming the same, the method for forming the same includes: providing a substrate, wherein the substrate comprises a substrate and a fin part protruding out of the substrate, a grid structure is formed on the substrate, and the grid structure spans across the fin part and covers part of the top and part of the side wall of the fin part; forming first source-drain doping layers in fin parts on two sides of the grid structure; forming at least one second source-drain doped layer on the first source-drain doped layer, wherein the step of forming the second source-drain doped layer comprises the following steps: forming a protective layer which is positioned on the substrate and exposes the first source-drain doping layer or the lower Fang Dier source-drain doping layer; forming a second source-drain doping layer on the first source-drain doping layer exposed from the protective layer or the lower Fang Dier source-drain doping layer; forming an interlayer dielectric layer covering the second source-drain doped layer on the protective layer; and forming contact hole plugs surrounding the first source-drain doping layer and the second source-drain doping layer in the interlayer dielectric layer and the protective layer. The embodiment of the invention is beneficial to reducing the contact resistance between the source-drain doped layer and the contact hole plug.
Description
Technical Field
Embodiments of the present disclosure relate to semiconductor manufacturing, and more particularly, to a semiconductor structure and a method for forming the same.
Background
With the gradual development of semiconductor process technology, the development trend of the semiconductor process node following moore's law is continuously reduced. To accommodate the reduction in process nodes, the channel length of MOSFET field effect transistors is also correspondingly reduced. However, as the channel length of the device is shortened, the distance between the source and the drain of the device is shortened, so that the control capability of the gate to the channel is deteriorated, and the difficulty of pinching off (pin off) the channel by the gate voltage is also increased, so that the phenomenon of subthreshold leakage (subthreshold leakage), namely the so-called short-channel effect (SCE), is more likely to occur.
Accordingly, to better accommodate the demands of device scaling, semiconductor processes are increasingly beginning to transition from planar MOSFETs to three-dimensional transistors with higher efficiency, such as fin field effect transistors (finfets). In the FinFET, the gate can control the ultrathin body (fin part) from at least two sides, and compared with a planar MOSFET, the gate has stronger control capability on a channel, and can well inhibit short channel effect; and finfets have better compatibility with existing integrated circuit fabrication than other devices.
Disclosure of Invention
The embodiment of the invention solves the problem of providing a semiconductor structure and a forming method thereof, and reduces the contact resistance between a source-drain doping layer and a contact hole plug.
In order to solve the above problems, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate, wherein the substrate comprises a substrate and a fin part protruding out of the substrate, a grid structure is formed on the substrate, and the grid structure spans across the fin part and covers part of the top and part of the side wall of the fin part; forming first source-drain doping layers in fin parts on two sides of the grid structure; forming at least one second source-drain doping layer on the first source-drain doping layer, wherein the step of forming the second source-drain doping layer comprises the following steps: forming a protective layer which is positioned on the substrate and exposes the first source-drain doping layer or the lower Fang Dier source-drain doping layer; forming a second source-drain doping layer on the first source-drain doping layer exposed from the protective layer or the lower Fang Dier source-drain doping layer; forming an interlayer dielectric layer on the protective layer, wherein the interlayer dielectric layer covers the second source-drain doping layer; and forming contact hole plugs surrounding the first source-drain doping layer and the second source-drain doping layer in the interlayer dielectric layer and the protective layer.
Optionally, the step of forming the first source-drain doped layer includes: etching fin parts on two sides of the gate structure, and forming grooves in the fin parts on two sides of the gate structure; and forming the first source-drain doped layer in the groove, wherein the top of the first source-drain doped layer is higher than the top of the fin part.
Optionally, the number of the second source-drain doped layers is one, and the step of forming the second source-drain doped layers includes: forming a protective layer exposing the top of the first source-drain doping layer on the substrate exposed by the gate structure, wherein the top of the protective layer is higher than the top of the fin part and lower than the top of the first source-drain doping layer; and forming an epitaxial layer on the first source-drain doped layer exposed by the protective layer by adopting an epitaxial process, and forming the second source-drain doped layer by in-situ self-doping ions in the process of forming the epitaxial layer.
Optionally, the material of the protective layer is a dielectric material.
Optionally, the material of the protective layer is the same as that of the interlayer dielectric layer.
Optionally, the step of forming the contact hole plug includes: etching the interlayer dielectric layer and the protective layer to form contact holes exposing the first source-drain doping layer and the second source-drain doping layer; and forming a contact hole plug for filling the contact hole.
Optionally, the groove is sigma-shaped.
Optionally, the first source-drain doped layer or the second source-drain doped layer has a diamond structure along the extending direction perpendicular to the fin portion.
Optionally, after forming the contact hole, before forming the contact hole plug, the method further includes: and forming silicide layers on the surfaces of the first source drain doping layer and the second source drain doping layer exposed from the contact holes.
Correspondingly, the embodiment of the invention also provides a semiconductor structure, which comprises: a substrate; a fin protruding from the substrate; a gate structure crossing the fin and covering a portion of the top and a portion of the sidewall of the fin; the first source-drain doping layers are positioned in fin parts at two sides of the grid structure; the protective layer is positioned on the substrate, is in the same layer with the first source-drain doping layer and exposes the top of the first source-drain doping layer; at least one second source-drain doping layer positioned on the first source-drain doping layer exposed by the protective layer; the interlayer dielectric layer is positioned on the protective layer and covers the second source-drain doping layer; and the contact hole plug is positioned in the interlayer dielectric layer and the protective layer and surrounds the first source-drain doping layer and the second source-drain doping layer.
Optionally, the top of the first source-drain doped layer is higher than the top of the fin portion; the number of the second source-drain doping layers is one; the top of the protective layer is higher than the top of the fin part and lower than the top of the first source-drain doping layer; the second source-drain doping layer comprises an epitaxial layer which is positioned on the first source-drain doping layer exposed by the protective layer and doped with ions.
Optionally, the material of the protective layer is a dielectric material.
Optionally, the material of the protective layer is the same as that of the interlayer dielectric layer.
Optionally, the material of the protective layer includes silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, or silicon carbonitride oxide.
Optionally, the semiconductor structure further includes: and the silicide layer is positioned between the first source-drain doping layer and the contact hole plug and between the second source-drain doping layer and the contact hole plug.
Optionally, a distance between the top of the protective layer and the top of the first source-drain doped layer is 1 nm to 3 nm along a normal direction of the substrate surface.
Optionally, the top of the second source-drain doped layer is lower than the top of the gate structure along the normal direction of the substrate surface, and the distance between the top of the second source-drain doped layer and the top of the gate structure is 100 to 500 a.
Optionally, the first source-drain doped layer or the second source-drain doped layer has a diamond structure along the extending direction perpendicular to the fin portion.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following advantages:
according to the embodiment of the invention, after the first source-drain doping layer, at least one second source-drain doping layer is formed on the first source-drain doping layer, that is, the source-drain doping layer formed by the embodiment of the invention is of a laminated structure, compared with the scheme that the source-drain doping layer is not of the laminated structure, the embodiment of the invention is easy to enable the surface area of the source-drain doping layer to be larger by adjusting the size and the profile morphology of the first source-drain doping layer and the second source-drain doping layer, so that when a contact hole plug surrounding the first source-drain doping layer and the second source-drain doping layer is formed subsequently, the contact area of the contact hole plug and the first source-drain doping layer and the second source-drain doping layer is increased, and the contact resistance of the source-drain doping layer and the contact hole plug is reduced.
In addition, the contact surface of the source-drain doped layer is increased along the direction (longitudinal direction) perpendicular to the substrate, and compared with the scheme of increasing the surface of the source-drain doped layer along the direction (transverse direction) perpendicular to the fin part, the embodiment of the invention is beneficial to preventing the problem that short circuit (merge) is easy to occur between adjacent source-drain doped layers due to the fact that the transverse dimension of the source-drain doped layer is too large.
Drawings
FIG. 1 is a schematic diagram of a semiconductor structure;
fig. 2 to 13 are schematic structural views corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention;
fig. 14 and 15 are schematic structural views of an embodiment of the semiconductor structure of the present invention.
Detailed Description
The devices formed at present still have the problem of poor performance. The reason for the poor performance of the device is analyzed by combining a semiconductor structure.
Referring to fig. 1, a schematic structural diagram of a semiconductor structure is shown.
The semiconductor structure includes: a substrate 1; a fin 2 protruding from the substrate 1; a gate structure (not shown) that spans across the fin 2 and covers a portion of the top and a portion of the sidewalls of the fin 2; the source-drain doped layers 3 are positioned in the fin parts 2 at two sides of the grid structure; the interlayer dielectric layer 4 is positioned on the substrate 1 and covers the source-drain doped layer 3; and the contact hole plug 5 is positioned in the interlayer dielectric layer 4 and surrounds the source-drain doped layer 3.
In the semiconductor structure, the contact hole plug 5 surrounds the source-drain doped layer 3, which is beneficial to increasing the contact area between the contact hole plug 5 and the source-drain doped layer 3.
However, as the critical dimensions of the device are further reduced, the dimensions of the source-drain doped layer 3 are also continuously reduced, and the surface area of the source-drain doped layer 3 is also reduced, which results in a smaller contact area between the contact plug 5 and the source-drain doped layer 3, and the contact resistance between the contact plug 5 and the source-drain doped layer 3 is difficult to meet the process requirements.
One current method is to increase the size of the source-drain doped layer 3, thereby increasing the surface area of the source-drain doped layer 3, and further increasing the contact area between the contact plug 5 and the source-drain doped layer 3 to reduce the contact resistance.
However, increasing the size of the source-drain doped layer 3 increases the size of the source-drain doped layer 3 in the extending direction (lateral direction) of the vertical fin 2. Along with the reduction of the critical dimension of the device, the distance between the adjacent fin portions 2 is also reduced continuously, and the lateral dimension of the source-drain doped layer 3 is larger, so that the problem that the distance between the adjacent source-drain doped layers 3 is too close and short circuit is easy to occur is easily caused.
In order to solve the technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate, wherein the substrate comprises a substrate and a fin part protruding out of the substrate, a grid structure is formed on the substrate, and the grid structure spans across the fin part and covers part of the top and part of the side wall of the fin part; forming first source-drain doping layers in fin parts on two sides of the grid structure; forming at least one second source-drain doping layer on the first source-drain doping layer, wherein the step of forming the second source-drain doping layer comprises the following steps: forming a protective layer which is positioned on the substrate and exposes the first source-drain doping layer or the lower Fang Dier source-drain doping layer; forming a second source-drain doping layer on the first source-drain doping layer exposed from the protective layer or the lower Fang Dier source-drain doping layer; forming an interlayer dielectric layer on the protective layer, wherein the interlayer dielectric layer covers the second source-drain doping layer; and forming contact hole plugs surrounding the first source-drain doping layer and the second source-drain doping layer in the interlayer dielectric layer and the protective layer.
According to the embodiment of the invention, after the first source-drain doping layer, at least one second source-drain doping layer is formed on the first source-drain doping layer, that is, the source-drain doping layer formed by the embodiment of the invention is of a laminated structure, compared with the scheme that the source-drain doping layer is not of the laminated structure, the embodiment of the invention is easy to enable the surface area of the source-drain doping layer to be larger by adjusting the size and the profile morphology of the first source-drain doping layer and the second source-drain doping layer, so that when a contact hole plug surrounding the first source-drain doping layer and the second source-drain doping layer is formed subsequently, the contact area of the contact hole plug and the first source-drain doping layer and the second source-drain doping layer is increased, and the contact resistance of the source-drain doping layer and the contact hole plug is reduced.
In addition, the contact surface of the source-drain doped layer is increased along the direction (longitudinal direction) perpendicular to the substrate, and compared with the scheme of increasing the surface of the source-drain doped layer along the direction (transverse direction) perpendicular to the fin part, the embodiment of the invention is beneficial to preventing the problem that short circuit is easy to occur between adjacent source-drain doped layers due to the fact that the transverse dimension of the source-drain doped layer is too large.
In order that the above objects, features and advantages of embodiments of the invention may be readily understood, a more particular description of the invention will be rendered by reference to specific embodiments thereof which are illustrated in the appended drawings.
Fig. 2 to 13 are schematic structural views corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention.
Referring to fig. 2 and 3, fig. 2 is a cross-sectional view along the direction of extension of an vertical fin, and fig. 3 is a cross-sectional view along the direction of extension of a fin, providing a base (not labeled) comprising a substrate 100 and a fin 110 protruding from the substrate 100, on which a gate structure 135 is formed, the gate structure 135 crossing the fin 110 and covering a portion of the top and a portion of the sidewall of the fin 110.
The substrate 100 provides a process platform for the subsequent formation of semiconductor structures.
In this embodiment, the substrate 100 is a silicon substrate. In other embodiments, the substrate material may also be germanium, silicon carbide, gallium arsenide, or indium gallium, and the substrate may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate.
The fin 110 is used to provide a conductive channel for the field effect transistor during operation.
The fin 110 is of the same material as the substrate 100. In this embodiment, the fin 110 is made of silicon. In other embodiments, the fin material may also be germanium, silicon carbide, gallium arsenide, or indium gallium arsenide.
In this embodiment, after forming the substrate 100 and the fin 110, the method further includes: an isolation layer 120 is formed on the substrate 100 where the fin portion 110 is exposed, and the isolation layer 120 covers a portion of the sidewall of the fin portion 110.
The isolation layer 120 is used as an isolation structure of the semiconductor structure to isolate adjacent devices. In this embodiment, the material of the isolation layer 120 is silicon oxide. In other embodiments, the material of the isolation layer may be silicon nitride or other insulating materials such as silicon oxynitride.
In this embodiment, the gate structure 135 is a dummy gate structure (dummy gate), and the gate structure 135 occupies a space for a subsequently formed metal gate structure.
In this embodiment, the gate structure 135 is a single-layer structure, and the gate structure 135 includes a gate layer. The material of the gate layer may be polysilicon, silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, or amorphous carbon. In this embodiment, the gate layer is made of polysilicon.
In other embodiments, the gate structure may also be a stacked structure, where the gate structure includes a gate oxide layer and a gate layer disposed on the gate oxide layer. In this embodiment, the material of the gate oxide layer may be silicon oxide or silicon oxynitride.
In this embodiment, the step of forming the gate structure 135 includes: forming a gate material layer (not shown) across the fin 110 and covering the top and sidewalls of the fin 110; forming a patterned gate mask layer 121 on the gate material layer; the gate material layer is patterned using the gate mask layer 121 as a mask to form the gate structure 135.
In this embodiment, after the gate structure 135 is formed, the gate mask layer 121 is remained, and the gate mask layer 121 can protect the top of the gate structure 135 in a subsequent process. In this embodiment, the material of the gate mask layer 121 is silicon nitride.
In this embodiment, after the gate structure 135 is formed, the forming method further includes: a sidewall 122 is formed on the sidewall of the gate structure 135.
The sidewall 122 is used to protect the sidewall of the gate structure 135, and the sidewall 122 is also used to define a formation region of the subsequent first source-drain doped layer.
The material of the side wall 122 may be one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride oxide, silicon oxycarbide, boron nitride and boron carbonitride, and the side wall 122 may have a single-layer structure or a stacked-layer structure. In this embodiment, the side wall 122 has a single-layer structure, and the material of the side wall 122 is silicon nitride.
It should be noted that, in this embodiment, for convenience of illustration and description, only the gate structure 135, the gate mask layer 121, and the sidewall 122 are illustrated in the cross-sectional view along the extending direction of the fin 110.
Referring to fig. 4 to 7, fig. 4 and 6 are cross-sectional views along the direction of extension of the vertical fin, and fig. 5 and 7 are cross-sectional views along the direction of extension of the fin, and a first source-drain doped layer 130 (shown in fig. 6) is formed in the fin 110 on both sides of the gate structure 135.
The first source-drain doped layer 130 is used for providing a process basis for forming a second source-drain doped layer, and the first source-drain doped layer 130 and the second source-drain doped layer form a source-drain doped layer of the semiconductor structure.
When the NMOS transistor is formed, the first source-drain doped layer 130 includes a stress layer doped with N-type ions, where the stress layer is made of Si or SiC, and the stress layer provides a tensile stress effect for a channel region of the NMOS transistor, so As to facilitate improvement of carrier mobility of the NMOS transistor, and the N-type ions are P ions, as ions, or Sb ions; when forming the PMOS transistor, the first source-drain doped layer 130 includes a stress layer doped with P-type ions, where the material of the stress layer is Si or SiGe, and the stress layer provides compressive stress to the channel region of the PMOS transistor, so as to facilitate improving carrier mobility of the PMOS transistor, and the P-type ions are B ions, ga ions, or In ions.
In this embodiment, the step of forming the first source-drain doped layer 130 includes: as shown in fig. 4 and 5, fin 110 on both sides of gate structure 135 is etched, and recess 145 is formed in fin 110 on both sides of gate structure 135; as shown in fig. 6 and 7, the first source-drain doped layer 130 is formed in the recess 145, and the top of the first source-drain doped layer 130 is higher than the top of the fin 110.
In this embodiment, the recess 145 has a sigma shape. In other embodiments, the recess may also be bowl-shaped or rectangular.
In this embodiment, the top of the first source-drain doped layer 130 is higher than the top of the fin portion 110, which provides a process foundation for forming a protective layer that exposes the top of the first source-drain doped layer 130 and covers the fin portion 110, and further can form a second source-drain doped layer on the first source-drain doped layer 130 exposed by the protective layer.
In this embodiment, an epitaxial process is used to form an epitaxial layer in the recess 145, and ions are self-doped in situ during the process of forming the epitaxial layer, so as to form the first source-drain doped layer 130. Wherein the epitaxial layer is used as the stress layer.
In this embodiment, the first source-drain doped layer 130 has a sigma-shaped structure, that is, the first source-drain doped layer 130 has a diamond-shaped structure along the extending direction perpendicular to the fin 110. In other embodiments, the shape of the first source-drain doped layer may be mushroom-shaped, inverted bowl-shaped, or other shapes.
Referring to fig. 8 to 10, forming at least one second source-drain doped layer 160 (as shown in fig. 10) on the first source-drain doped layer 130, the step of forming the second source-drain doped layer 160 includes: forming a protective layer 150 on the substrate 100 and exposing the first source-drain doped layer 130 or the lower Fang Dier source-drain doped layer 160; a second source-drain doped layer 160 is formed on the first source-drain doped layer 130 or the underlying Fang Dier source-drain doped layer 160 exposed by the protective layer 150.
In this embodiment, after the first source-drain doped layer 130 is formed, at least one second source-drain doped layer 160 is further formed on the first source-drain doped layer 130, that is, the source-drain doped layer formed in this embodiment is in a stacked structure, and compared with the solution that the source-drain doped layer is not in a stacked structure, the size and the profile morphology of the first source-drain doped layer 130 and the second source-drain doped layer 160 are easily adjusted, so that the surface area of the source-drain doped layer is larger, and when contact hole plugs surrounding the first source-drain doped layer 130 and the second source-drain doped layer 160 are subsequently formed, the contact area between the contact hole plugs and the first source-drain doped layer 130 and the second source-drain doped layer 160 is advantageously increased, and the contact resistance between the source-drain doped layer and the contact hole plugs is advantageously reduced.
In addition, the contact surface of the source-drain doped layer is increased in the direction perpendicular to the substrate 100 (longitudinal direction), which is advantageous in preventing the problem that the lateral dimension of the source-drain doped layer is too large to cause shorting (merge) between adjacent source-drain doped layers, compared with the scheme in which the surface of the source-drain doped layer is increased in the direction perpendicular to the fin portion (lateral direction).
In this embodiment, the second source-drain doped layer 160 is made of the same material as the first source-drain doped layer 130.
When forming an NMOS transistor, the second source-drain doped layer 160 includes a stress layer doped with N-type ions, where the stress layer is made of Si or SiC, and the stress layer provides a tensile stress for a channel region of the NMOS transistor, so As to facilitate improving carrier mobility of the NMOS transistor, and the N-type ions are P ions, as ions, or Sb ions; when forming the PMOS transistor, the second source-drain doped layer 160 includes a stress layer doped with P-type ions, where the stress layer is made of Si or SiGe, and the stress layer provides compressive stress to the channel region of the PMOS transistor, so as to facilitate improving carrier mobility of the PMOS transistor, and the P-type ions are B ions, ga ions, or In ions.
In this embodiment, the number of the second source-drain doped layers 160 is one. In other embodiments, the number of second source-drain doped layers is not limited to only one.
It should be noted that, in this embodiment, the top of the second source-drain doped layer 160 is lower than the top of the gate structure 135, which provides a process basis for forming an interlayer dielectric layer on the substrate 100 exposed by the gate structure 135 and forming a contact plug surrounding the first source-drain doped layer 130 and the second source-drain doped layer 160.
The distance between the top of the second source-drain doped layer 160 and the top of the gate structure 135 along the normal direction of the surface of the substrate 100 is preferably not too small or too large. If the distance is too small, the height of the top of the second source-drain doped layer 160 is correspondingly larger, and the relative area between the second source-drain doped layer 160 and the gate structure 135 is correspondingly larger, which tends to increase the parasitic capacitance between the source-drain doped layer and the gate structure 135, and also tends to increase the difficulty of forming an interlayer dielectric layer on the substrate 100 exposed by the gate structure 135 and forming a contact plug surrounding the first source-drain doped layer 130 and the second source-drain doped layer 160; if the distance is too large, the height of the top of the second source-drain doped layer 160 is correspondingly small, which tends to result in an insignificant effect of increasing the contact surface of the source-drain doped layer. For this reason, in the present embodiment, the distance between the top of the second source-drain doped layer 160 and the top of the gate structure 135 along the normal direction of the surface of the substrate 100 is 100 to 500 a.
Specifically, in this embodiment, the step of forming the second source-drain doped layer 160 includes:
as shown in fig. 8 and 9, a protection layer 150 (shown in fig. 9) exposing the top of the first source-drain doped layer 130 is formed on the substrate 100 where the gate structure 135 (shown in fig. 7) is exposed, wherein the top of the protection layer 150 is higher than the top of the fin 110 and lower than the top of the first source-drain doped layer 130. Specifically, the protective layer 150 is formed on the isolation layer 120.
The second source/drain doped layer is formed by an epitaxial process, and the protective layer 150 is used to act as a mask in the subsequent step of forming the second source/drain doped layer, thereby protecting part of the sidewall of the first source/drain doped layer 130 from epitaxial growth over the entire surface of the first source/drain doped layer 130.
Furthermore, the top of the protection layer 150 is higher than the top of the fin 110, so as to prevent epitaxial growth based on the fin 110 when the second source-drain doped layer 160 is formed later.
In this embodiment, the material of the protection layer 150 is a dielectric material. By selecting the dielectric material, the influence of the protective layer 150 on the performance of the semiconductor structure is reduced, and the protective layer 150 is not required to be removed later, thereby being beneficial to simplifying the process steps and improving the process compatibility.
The material of the protective layer 150 includes silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, or silicon carbonitride oxide. In this embodiment, the material of the protection layer 150 is silicon oxide. Silicon oxide is a dielectric material commonly used in the process and having low cost, and has high process compatibility, which is beneficial to reducing the process difficulty and process cost of forming the protection layer 150.
It should be noted that, in the normal direction of the surface of the substrate 100, the distance between the top of the protection layer 150 and the top of the first source-drain doped layer 130 should not be too small or too large. If the distance is too small, the height of the first source-drain doped layer 130 exposed by the protective layer 150 is too small, and then when a second source-drain doped layer is formed on the first source-drain doped layer 130 exposed by the protective layer 150, the volume of the second source-drain doped layer is too small, which easily results in an insignificant effect of increasing the surface area of the source-drain doped layer, and the second source-drain doped layer is usually formed by an epitaxial process, and the process difficulty of the epitaxial process is easily increased due to too small height of the first source-drain doped layer 130 exposed by the protective layer 150; if the distance is too large, the risk that the fin portion 110 is exposed by the protection layer 150 is easily increased, and the second source-drain doped layer is easily formed on the sidewall of the first source-drain doped layer 130, so that the lateral dimension of the source-drain doped layer is too large, and the risk that a shorting problem occurs between adjacent source-drain doped layers is easily increased. For this reason, in this embodiment, the distance between the top of the protection layer 150 and the top of the first source/drain doped layer 130 is 1 nm to 3 nm along the normal direction of the surface of the substrate 100.
In this embodiment, the step of forming the protective layer 150 includes: as shown in fig. 8, an initial protective layer 140 is formed on the substrate to cover the first source-drain doped layer 130; as shown in fig. 9, a part of the initial protective layer 140 is removed, and the initial protective layer 140 remains as the protective layer 150.
In this embodiment, the initial protection layer 140 is formed by a flowable chemical vapor deposition (flowable chemical vapor deposition, FCVD) process. By selecting the flowable chemical vapor deposition process, the filling capability of the material of the initial protection layer 140 is improved, so that the probability of generating defects such as voids (void) in the initial protection layer 140 is reduced, and the formation quality of the protection layer 150 is correspondingly improved.
In this embodiment, in the step of forming the initial protection layer 140, the initial protection layer 140 further covers the top of the gate structure 135. Therefore, in this embodiment, before removing a part of the initial protection layer 140, the method further includes: an initial protective layer 140 is removed above the top of the gate mask layer 122 using a planarization process.
By the planarization process, the top surface flatness of the initial protection layer 140 is improved, and the top surface flatness of the protection layer 150 is correspondingly improved. Specifically, in the present embodiment, the planarization process is performed using a Chemical-mechanical polishing process (Chemical-Mechanical Polishing, CMP).
In this embodiment, a dry etching process is used to remove a portion of the initial protection layer 140.
The dry etching process is easy to realize anisotropic etching, has good process controllability, and is favorable for accurately etching the initial protection layer 140, so that the height of the protection layer 150 meets the process requirement.
In this embodiment, taking the number of the second source-drain doped layers 160 as one as an example, only one protection layer 150 is formed correspondingly. In other embodiments, when the number of the second source-drain doped layers is greater than or equal to two, a plurality of the protective layers may be formed correspondingly.
As shown in fig. 10, an epitaxial process is used to form the epitaxial layer on the first source-drain doped layer 130 exposed by the protective layer 150, and the second source-drain doped layer 160 is formed by in-situ self-doping ions during the process of forming the epitaxial layer.
Specifically, the epitaxial layer serves as the stress layer to provide compressive or tensile stress to the channel region.
By adopting the epitaxial process, the material of the second source-drain doped layer 160 with higher purity is obtained, and the formation quality of the second source-drain doped layer 160 is improved.
In this embodiment, after the second source-drain doped layer 160 is formed by using an epitaxial process, the second source-drain doped layer 160 is also in a diamond structure along the extending direction perpendicular to the fin 110. In other embodiments, the shape of the second source-drain doped layer may be mushroom-shaped, inverted bowl-shaped, or other shapes.
In this embodiment, the second source-drain doped layer 160 and the first source-drain doped layer 130 are both diamond-shaped along the extending direction perpendicular to the fin 110, which is beneficial to further increasing the surface area of the formed source-drain doped layer.
Referring to fig. 11, an interlayer dielectric layer 170 is formed on the protective layer 150, and the interlayer dielectric layer 170 covers the second source drain doped layer 160.
After forming the interlayer dielectric layer 170, the interlayer dielectric layer 170 and the protective layer 150 form a dielectric layer for isolating adjacent devices, and the interlayer dielectric layer 170 and the protective layer 150 also provide a process platform for forming contact plugs surrounding the second source-drain doped layer 160 and the first source-drain doped layer 130.
Thus, the material of the interlayer dielectric layer 170 is a dielectric material, such as one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon oxycarbonitride.
In this embodiment, the material of the interlayer dielectric layer 170 is the same as the material of the protection layer 150, and the material of the interlayer dielectric layer 170 is silicon oxide, which is beneficial to improving process compatibility.
Referring to fig. 12 to 13, contact hole plugs 190 (shown in fig. 13) surrounding the first and second source and drain doped layers 130 and 160 are formed in the interlayer dielectric layer 170 and the protective layer 150.
Contact plugs 190 are used to electrically connect the source drain doped layers to other interconnect structures or external circuitry.
In this embodiment, the surface area of the source-drain doped layer formed by the first source-drain doped layer 130 and the second source-drain doped layer 160 is larger, so that when the contact hole plug 190 surrounding the first source-drain doped layer 130 and the second source-drain doped layer 160 is formed, the contact area between the contact hole plug 190 and the first source-drain doped layer 130 and the second source-drain doped layer 160 is advantageously increased, and the contact resistance between the source-drain doped layer and the contact hole plug 190 is further advantageously reduced.
In this embodiment, the contact plug 190 is made of tungsten. In other embodiments, the material of the contact plug may be cobalt or other conductive materials.
In this embodiment, the step of forming the contact hole plug 190 includes:
as shown in fig. 12, the interlayer dielectric layer 170 and the protective layer 150 are etched to form contact holes 200 exposing the first source/drain doped layer 130 and the second source/drain doped layer 160.
The contact holes 200 provide a spatial location for subsequent formation of contact hole plugs. The contact hole 200 exposes the first and second source-drain doped layers 130 and 160, thereby providing for a subsequent contact hole plug to surround the first and second source-drain doped layers 130 and 160.
In this embodiment, a dry etching process is used to etch the interlayer dielectric layer 170 and the protection layer 150.
As shown in fig. 13, a contact hole plug 190 filling the contact hole 200 is formed.
Specifically, a conductive layer (not shown) is formed to fill the contact hole 200 and cover the top of the interlayer dielectric layer 170; and removing the conductive layer higher than the top of the interlayer dielectric layer 170, and taking the rest of the conductive layer as the contact hole plug 190.
In this embodiment, the conductive layer is formed by a chemical vapor deposition process.
In this embodiment, a chemical mechanical polishing process is used to remove the conductive layer higher than the top of the interlayer dielectric layer 170, so as to improve the flatness of the top surface of the contact plug 190.
In this embodiment, referring to fig. 12, after forming the contact hole 200, before forming the contact hole plug 190, the method further includes: silicide layer 180 is formed on the surfaces of the first source/drain doped layer 130 and the second source/drain doped layer 160 exposed by the contact hole 200.
After forming the contact hole plugs filling the contact holes 200, the silicide layer 180 is located between the first source-drain doped layer 130 and the contact hole plugs, and between the second source-drain doped layer 160 and the contact hole plugs, and the silicide layer 180 is used for reducing contact resistance between the contact hole plugs and the first source-drain doped layer 130 and the second source-drain doped layer 160, and improving adhesion between the contact hole plugs and the first source-drain doped layer 130 and the second source-drain doped layer 160, so as to improve contact performance between the contact hole plugs and the source-drain doped layers.
The silicide layer 180 may be TiSi, niSi, coSi, or the like. In this embodiment, the silicide layer 180 is made of TiSi.
Note that, in this embodiment, the gate structure 135 is a dummy gate structure, so after the interlayer dielectric layer 170 is formed, before the contact hole 200 is formed, the forming method further includes: removing the gate mask layer 121 and the gate structure 135, and forming a gate opening (not shown) in the interlayer dielectric layer 170; a metal gate structure (not shown) is formed in the gate opening.
The gate openings provide spatial locations for forming metal gate structures.
The metal gate structure is used for controlling the on and off of the conducting channel when the field effect transistor works.
A metal gate structure spans the fin 110 and covers a portion of the top and a portion of the sidewalls of the fin 110. The metal gate structure includes a gate dielectric layer (not shown) and a gate electrode layer (not shown) on the gate dielectric layer.
The gate dielectric layer is used to electrically isolate the metal gate structure from the fin 110. In this embodiment, the gate dielectric layer is made of a high-k dielectric material. Specifically, the gate dielectric layer is made of HfO 2 . In other embodiments, the material of the gate dielectric layer may also be selected from ZrO 2 HfSiO, hfSiON, hfTaO, hfTiO, hfZrO or Al 2 O 3 Etc.
The gate electrode layer is used for realizing the electrical connection between the metal gate structure and other interconnection structures or external circuits. In this embodiment, the gate electrode layer is made of magnesium-tungsten alloy. In other embodiments, the material of the gate electrode layer may also be W, al, cu, ag, au, pt, ni or Ti.
The detailed description of the related steps for forming the metal gate structure is omitted here.
Correspondingly, the invention further provides a semiconductor structure. Referring to fig. 14 through 15, fig. 14 is a cross-sectional view along the direction of extension of the vertical fin, and fig. 15 is a cross-sectional view along the direction of extension of the fin, illustrating a schematic structural view of an embodiment of a semiconductor structure according to the present invention.
The semiconductor structure includes: a substrate 300; a fin 310 protruding from the substrate 300; a gate structure 400 that spans across the fin 310 and covers a portion of the top and a portion of the sidewalls of the fin 310; the first source-drain doped layer 330 is located in the fin portion 310 at two sides of the gate structure 400; a protective layer 350 on the substrate 300 and in the same layer as the first source/drain doped layer 330, and exposing the top of the first source/drain doped layer 330; at least one second source-drain doped layer 360 located on the first source-drain doped layer 330 exposed by the protective layer 350; an interlayer dielectric layer 370 on the protection layer 350 and covering the second source-drain doped layer 360; contact plugs 390 are located in the interlayer dielectric layer 370 and the protective layer 350 and surround the first source drain doped layer 330 and the second source drain doped layer 360.
In this embodiment, the semiconductor structure includes at least one second source-drain doped layer 360 located on the first source-drain doped layer 330 exposed by the protective layer 350, that is, the source-drain doped layer of the semiconductor structure provided in this embodiment is a stacked structure, and compared with the solution that the source-drain doped layer is not a stacked structure, the size and the profile morphology of the first source-drain doped layer 330 and the second source-drain doped layer 360 are easily adjusted, so that the surface area of the source-drain doped layer is larger, thereby being beneficial to increasing the contact area between the contact hole plug 390 and the first source-drain doped layer 330 and the second source-drain doped layer 360, and further being beneficial to reducing the contact resistance between the source-drain doped layer and the contact hole plug 390.
In addition, the contact surface of the source-drain doped layer is increased in the direction (longitudinal direction) perpendicular to the substrate 300, which is advantageous in preventing the problem that the lateral dimension of the source-drain doped layer is too large to cause short circuit between adjacent source-drain doped layers, compared with the scheme in which the surface of the source-drain doped layer is increased in the direction (transverse direction) perpendicular to the fin portion.
The substrate 300 provides a process platform for the formation of semiconductor structures. In this embodiment, the substrate 300 is a silicon substrate.
In this embodiment, the semiconductor structure further includes: and the isolation layer 320 is positioned on the substrate 300 exposed by the fin portion 310, and the isolation layer 320 covers part of the side wall of the fin portion 310.
The isolation layer 320 is used as an isolation structure of the semiconductor structure to isolate adjacent devices. In this embodiment, the material of the isolation layer 320 is silicon oxide. In other embodiments, the material of the isolation layer may be silicon nitride or other insulating materials such as silicon oxynitride.
The gate structure 400 is used to control the on and off of the conduction channel when the field effect transistor is in operation.
In this embodiment, the gate structure 400 is a metal gate structure. The gate structure 400 includes a gate dielectric layer (not shown) and a gate electrode layer (not shown) on the gate dielectric layer.
The gate dielectric layer is used to electrically isolate gate structure 400 from fin 310. In this embodiment, the gate dielectric layer is made of a high-k dielectric material. Specifically, the gate dielectric layer is made of HfO 2 。
The gate electrode layer is used to make electrical connection of the gate structure 400 to other interconnect structures or external circuitry. In this embodiment, the gate electrode layer is made of magnesium-tungsten alloy.
In other embodiments, the gate structure may not be a metal gate structure, and the gate structure may include a gate oxide layer and a gate layer on the gate oxide layer. In this embodiment, the material of the gate oxide layer may be silicon oxide or silicon oxynitride, and the material of the gate layer may be polysilicon, silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride oxide, or amorphous carbon.
In this embodiment, the semiconductor structure further includes: and a sidewall 322 on the sidewall of the gate structure 400. The sidewall 322 is used to protect the sidewall of the gate structure 400, and the sidewall 322 is also used to define a formation region of the first source-drain doped layer 330.
The material of the side wall 322 may be one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride oxide, silicon oxycarbide, boron nitride and boron carbonitride, and the side wall 322 may have a single-layer structure or a stacked-layer structure. In this embodiment, the side wall 322 has a single-layer structure, and the material of the side wall 322 is silicon nitride.
It should be noted that, in this embodiment, only the gate structure 400 and the sidewall 322 are illustrated in fig. 15 for convenience of illustration and description.
The first source-drain doped layer 330 is used for providing a process basis for forming the second source-drain doped layer 360, and the first source-drain doped layer 330 and the second source-drain doped layer 360 also form a source-drain doped layer of the semiconductor structure.
When the NMOS transistor is formed, the first source-drain doped layer 330 includes a stress layer doped with N-type ions, where the stress layer is made of Si or SiC, and the stress layer provides a tensile stress for a channel region of the NMOS transistor, so As to facilitate improving carrier mobility of the NMOS transistor, and the N-type ions are P ions, as ions, or Sb ions; when forming the PMOS transistor, the first source-drain doped layer 330 includes a stress layer doped with P-type ions, where the material of the stress layer is Si or SiGe, and the stress layer provides compressive stress to the channel region of the PMOS transistor, so as to facilitate improving carrier mobility of the PMOS transistor, and the P-type ions are B ions, ga ions, or In ions.
In this embodiment, the first source-drain doped layer 330 has a sigma-shaped structure, that is, the first source-drain doped layer 330 has a diamond-shaped structure along the extending direction perpendicular to the fin 310. In other embodiments, the shape of the first source-drain doped layer may be mushroom-shaped, inverted bowl-shaped, or other shapes.
In this embodiment, the top of the first source-drain doped layer 330 is higher than the top of the fin 310, so as to provide a process foundation for forming the protection layer 350, and further enable the second source-drain doped layer 360 to be located on the first source-drain doped layer 330 exposed by the protection layer 350.
In this embodiment, the top of the protection layer 350 is higher than the top of the fin 310 and lower than the top of the first source-drain doped layer 330.
The step of forming the second source/drain doped layer 360 generally includes an epitaxial process, and the protective layer 350 is used to act as a mask in the step of forming the second source/drain doped layer 360, thereby protecting a portion of the sidewall of the first source/drain doped layer 330 from epitaxial growth over the entire surface of the first source/drain doped layer 330.
In this embodiment, the top of the protection layer 350 is higher than the top of the fin 310, so as to prevent epitaxial growth based on the fin 310 in the step of forming the second source-drain doped layer 360.
In this embodiment, the material of the protection layer 350 is a dielectric material. By selecting a dielectric material, the influence of the protective layer 350 on the performance of the semiconductor structure is reduced, and the protective layer 350 can be reserved in the semiconductor structure, thereby facilitating the simplification of process steps and the improvement of process compatibility.
The material of the protective layer 350 includes silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, or silicon carbonitride oxide. In this embodiment, the material of the protection layer 350 is the same as that of the interlayer dielectric layer 370, which is beneficial to improving process compatibility.
Specifically, the material of the protection layer 350 is silicon oxide. Silicon oxide is a dielectric material commonly used in the process and having low cost, and has high process compatibility, which is beneficial to reducing the process difficulty and the process cost for forming the protective layer 350.
It should be noted that, in the normal direction of the surface of the substrate 300, the distance between the top of the protection layer 350 and the top of the first source-drain doped layer 330 should not be too small or too large. If the distance is too small, the height of the first source-drain doped layer 330 exposed by the protective layer 350 is correspondingly too small, and the volume of the second source-drain doped layer 360 is too small, so that the effect of increasing the surface area of the source-drain doped layer is not obvious easily, and the difficulty of forming the second source-drain doped layer 360 is increased easily; if the distance is too large, the risk of exposing the fin 310 by the protection layer 350 is increased, and the formation of the second source-drain doped layer 360 on the sidewall of the first source-drain doped layer 330 is easily caused, which in turn easily causes the lateral dimension of the source-drain doped layer to be too large. For this reason, in this embodiment, the distance between the top of the protection layer 350 and the top of the first source/drain doped layer 330 is 1 nm to 3 nm along the normal direction of the surface of the substrate 300.
In this embodiment, taking the number of the second source-drain doped layers 360 as one as an example, the number of the protective layers 350 is only one. In other embodiments, when the number of the second source-drain doped layers is greater than or equal to two, the semiconductor structure may include a plurality of the protective layers, respectively.
The second source-drain doped layer 360 is made of the same material as the first source-drain doped layer 330.
The second source/drain doped layer 360 includes an epitaxial layer doped with ions on the first source/drain doped layer 330 exposed by the protective layer 350.
When forming an NMOS transistor, the second source-drain doped layer 360 includes a stress layer doped with N-type ions, where the stress layer is made of Si or SiC, and the stress layer provides a tensile stress to a channel region of the NMOS transistor, so As to facilitate improving carrier mobility of the NMOS transistor, and the N-type ions are P ions, as ions, or Sb ions; when forming the PMOS transistor, the second source-drain doped layer 360 includes a stress layer doped with P-type ions, where the stress layer is made of Si or SiGe, and the stress layer provides compressive stress to the channel region of the PMOS transistor, so as to facilitate improving carrier mobility of the PMOS transistor, and the P-type ions are B ions, ga ions, or In ions.
Wherein the epitaxial layer is used as the stress layer.
In this embodiment, the number of the second source-drain doped layers 360 is one. In other embodiments, the number of second source-drain doped layers is not limited to only one.
It should be noted that, in this embodiment, the top of the second source-drain doped layer 360 is lower than the top of the gate structure 400, so as to provide a process basis for forming the interlayer dielectric layer 370 and the contact hole plug 390.
It should be further noted that, in the normal direction of the surface of the substrate 300, the distance between the top of the second source-drain doped layer 360 and the top of the gate structure 400 is not too small or too large. If the distance is too small, the height of the top of the second source-drain doped layer 360 is relatively large, and the relative area between the second source-drain doped layer 360 and the gate structure 400 is relatively large, which tends to increase the parasitic capacitance between the source-drain doped layer and the gate structure 400, and also tends to increase the difficulty of forming the contact plug 390; if the distance is too large, the height of the top of the second source-drain doped layer 360 is correspondingly small, which tends to result in an insignificant effect of increasing the contact surface of the source-drain doped layer. For this reason, in the present embodiment, the distance between the top of the second source/drain doped layer 360 and the top of the gate structure 400 along the normal direction of the surface of the substrate 300 is 100 to 500 a.
In this embodiment, the second source-drain doped layer 360 is also diamond-shaped along the direction perpendicular to the extension direction of the fin 310. In other embodiments, the second source-drain doped layer may also have other shapes such as mushroom shape, inverted bowl shape, etc.
In this embodiment, the second source-drain doped layer 360 and the first source-drain doped layer 330 are both diamond-shaped along the extending direction perpendicular to the fin 310, which is beneficial to further increasing the surface area of the source-drain doped layer.
Thus, the material of the interlayer dielectric layer 370 is a dielectric material, such as one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon oxycarbonitride.
In this embodiment, the material of the interlayer dielectric layer 370 is the same as the material of the protection layer 350, and the material of the interlayer dielectric layer 370 is silicon oxide, which is beneficial to improving process compatibility.
Contact plugs 390 are used to make electrical connection of the source drain doped layers to other interconnect structures or external circuitry. In this embodiment, the contact plug 390 is made of tungsten. In other embodiments, the material of the contact plug may be cobalt or other conductive materials.
In this embodiment, the semiconductor structure further includes: silicide layer 380 is located between the first source drain doped layer 330 and the contact plug 390, and between the second source drain doped layer 360 and the contact plug 390.
The silicide layer 380 is used to reduce the contact resistance between the contact plug 390 and the first and second source-drain doped layers 330 and 360, and to improve the adhesion between the contact plug 390 and the first and second source-drain doped layers 330 and 360, thereby improving the contact performance between the contact plug 390 and the source-drain doped layers.
The silicide layer 380 may be TiSi, niSi, coSi, or the like. In this embodiment, the silicide layer 380 is made of TiSi.
The semiconductor structure may be formed by the forming method described in the foregoing embodiments, or may be formed by other forming methods. For a specific description of the semiconductor structure in this embodiment, reference may be made to the corresponding description in the foregoing embodiment, which is not repeated here.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.
Claims (18)
1. A method of forming a semiconductor structure, comprising:
providing a substrate, wherein the substrate comprises a substrate and a fin part protruding out of the substrate, a grid structure is formed on the substrate, and the grid structure spans across the fin part and covers part of the top and part of the side wall of the fin part;
forming first source-drain doping layers in fin parts on two sides of the grid structure;
forming at least one second source-drain doping layer on the first source-drain doping layer, wherein the step of forming the second source-drain doping layer comprises the following steps: forming a protective layer which is positioned on the substrate and exposes the first source-drain doping layer or the lower Fang Dier source-drain doping layer; forming a second source-drain doping layer on the first source-drain doping layer exposed from the protective layer or the lower Fang Dier source-drain doping layer;
forming an interlayer dielectric layer on the protective layer, wherein the interlayer dielectric layer covers the second source-drain doping layer;
and forming contact hole plugs surrounding the first source-drain doping layer and the second source-drain doping layer in the interlayer dielectric layer and the protective layer.
2. The method of forming a semiconductor structure of claim 1, wherein forming the first source drain doped layer comprises: etching fin parts on two sides of the gate structure, and forming grooves in the fin parts on two sides of the gate structure; and forming the first source-drain doped layer in the groove, wherein the top of the first source-drain doped layer is higher than the top of the fin part.
3. The method of forming a semiconductor structure of claim 2, wherein the number of second source-drain doped layers is one, the step of forming the second source-drain doped layers comprising: forming a protective layer exposing the top of the first source-drain doping layer on the substrate exposed by the gate structure, wherein the top of the protective layer is higher than the top of the fin part and lower than the top of the first source-drain doping layer;
and forming an epitaxial layer on the first source-drain doped layer exposed by the protective layer by adopting an epitaxial process, and forming the second source-drain doped layer by in-situ self-doping ions in the process of forming the epitaxial layer.
4. The method of claim 1, wherein the material of the protective layer is a dielectric material.
5. The method of forming a semiconductor structure of claim 1, wherein the protective layer is the same material as the interlayer dielectric layer.
6. The method of forming a semiconductor structure of claim 1, wherein forming the contact hole plug comprises: etching the interlayer dielectric layer and the protective layer to form contact holes exposing the first source-drain doping layer and the second source-drain doping layer; and forming a contact hole plug for filling the contact hole.
7. The method of forming a semiconductor structure of claim 2, wherein said recess is sigma-shaped.
8. The method of claim 1, wherein the first source drain doped layer or the second source drain doped layer has a diamond structure along a direction perpendicular to an extension of the fin.
9. The method of forming a semiconductor structure of claim 6, wherein after forming said contact hole, prior to forming said contact hole plug, further comprising: and forming silicide layers on the surfaces of the first source drain doping layer and the second source drain doping layer exposed from the contact holes.
10. A semiconductor structure, comprising:
a substrate;
a fin protruding from the substrate;
a gate structure crossing the fin and covering a portion of the top and a portion of the sidewall of the fin;
the first source-drain doping layers are positioned in fin parts at two sides of the grid structure;
the protective layer is positioned on the substrate, is in the same layer with the first source-drain doping layer and exposes the top of the first source-drain doping layer;
at least one second source-drain doping layer positioned on the first source-drain doping layer exposed by the protective layer;
the interlayer dielectric layer is positioned on the protective layer and covers the second source-drain doping layer;
And the contact hole plug is positioned in the interlayer dielectric layer and the protective layer and surrounds the first source-drain doping layer and the second source-drain doping layer.
11. The semiconductor structure of claim 10, wherein a top of the first source drain doped layer is higher than a top of the fin;
the number of the second source-drain doping layers is one;
the top of the protective layer is higher than the top of the fin part and lower than the top of the first source-drain doping layer;
the second source-drain doping layer comprises an epitaxial layer which is positioned on the first source-drain doping layer exposed by the protective layer and doped with ions.
12. The semiconductor structure of claim 10, wherein the material of the protective layer is a dielectric material.
13. The semiconductor structure of claim 10, wherein the protective layer is the same material as the interlayer dielectric layer.
14. The semiconductor structure of claim 10, wherein the material of the protective layer comprises silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, or silicon oxycarbonitride.
15. The semiconductor structure of claim 10, wherein the semiconductor structure further comprises: and the silicide layer is positioned between the first source-drain doping layer and the contact hole plug and between the second source-drain doping layer and the contact hole plug.
16. The semiconductor structure of claim 11, wherein a distance between a top of the protective layer and a top of the first source drain doped layer along a normal direction of the substrate surface is 1 nm to 3 nm.
17. The semiconductor structure of claim 10, wherein a top of the second source-drain doped layer is lower than a top of the gate structure along a normal direction of the substrate surface, and a distance between the top of the second source-drain doped layer and the top of the gate structure is 100 to 500 a.
18. The semiconductor structure of claim 10, wherein the first source drain doped layer or the second source drain doped layer is diamond-shaped in a direction perpendicular to an extension of the fin.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910696119.XA CN112309858B (en) | 2019-07-30 | 2019-07-30 | Semiconductor structure and forming method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910696119.XA CN112309858B (en) | 2019-07-30 | 2019-07-30 | Semiconductor structure and forming method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN112309858A CN112309858A (en) | 2021-02-02 |
| CN112309858B true CN112309858B (en) | 2023-06-13 |
Family
ID=74485699
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201910696119.XA Active CN112309858B (en) | 2019-07-30 | 2019-07-30 | Semiconductor structure and forming method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN112309858B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112447593B (en) * | 2019-08-30 | 2024-03-01 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103996711A (en) * | 2013-01-24 | 2014-08-20 | 三星电子株式会社 | Semiconductor device and fabricating method thereof |
| CN104078355A (en) * | 2013-03-28 | 2014-10-01 | 中芯国际集成电路制造(上海)有限公司 | Forming method of fin field effect transistor |
| JP2014216409A (en) * | 2013-04-24 | 2014-11-17 | ピーエスフォー ルクスコ エスエイアールエルＰＳ４ Ｌｕｘｃｏ Ｓ．ａ．ｒ．ｌ． | Semiconductor device manufacturing method |
| CN104347425A (en) * | 2013-08-01 | 2015-02-11 | 三星电子株式会社 | Semiconductor device and method for fabricating the same |
| CN109037213A (en) * | 2017-06-09 | 2018-12-18 | 中芯国际集成电路制造(上海)有限公司 | A kind of semiconductor devices and preparation method thereof and electronic device |
| CN109148581A (en) * | 2017-06-28 | 2019-01-04 | 中芯国际集成电路制造(上海)有限公司 | A kind of manufacturing method of semiconductor devices |
| CN109817525A (en) * | 2017-11-22 | 2019-05-28 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
Family Cites Families (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2013065672A (en) * | 2011-09-16 | 2013-04-11 | Toshiba Corp | Semiconductor device and method of manufacturing semiconductor device |
| KR102038486B1 (en) * | 2013-04-09 | 2019-10-30 | 삼성전자 주식회사 | Semiconductor device and method for fabricating the same |
| US9406804B2 (en) * | 2014-04-11 | 2016-08-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | FinFETs with contact-all-around |
| US9793400B2 (en) * | 2015-10-12 | 2017-10-17 | International Business Machines Corporation | Semiconductor device including dual-layer source/drain region |
| KR102480447B1 (en) * | 2015-11-20 | 2022-12-22 | 삼성전자주식회사 | Semiconductor devices and methods of manufacturing the same |
| US10276662B2 (en) * | 2016-05-31 | 2019-04-30 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method of forming contact trench |
| US9905663B2 (en) * | 2016-06-24 | 2018-02-27 | International Business Machines Corporation | Fabrication of a vertical fin field effect transistor with a reduced contact resistance |
| US20190067474A1 (en) * | 2017-08-25 | 2019-02-28 | Globalfoundries Inc. | Vertical finfet with improved top source/drain contact |
| US10468311B2 (en) * | 2017-10-06 | 2019-11-05 | International Business Machines Corporation | Nanosheet substrate isolated source/drain epitaxy by nitrogen implantation |
-
2019
- 2019-07-30 CN CN201910696119.XA patent/CN112309858B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103996711A (en) * | 2013-01-24 | 2014-08-20 | 三星电子株式会社 | Semiconductor device and fabricating method thereof |
| CN104078355A (en) * | 2013-03-28 | 2014-10-01 | 中芯国际集成电路制造(上海)有限公司 | Forming method of fin field effect transistor |
| JP2014216409A (en) * | 2013-04-24 | 2014-11-17 | ピーエスフォー ルクスコ エスエイアールエルＰＳ４ Ｌｕｘｃｏ Ｓ．ａ．ｒ．ｌ． | Semiconductor device manufacturing method |
| CN104347425A (en) * | 2013-08-01 | 2015-02-11 | 三星电子株式会社 | Semiconductor device and method for fabricating the same |
| CN109037213A (en) * | 2017-06-09 | 2018-12-18 | 中芯国际集成电路制造(上海)有限公司 | A kind of semiconductor devices and preparation method thereof and electronic device |
| CN109148581A (en) * | 2017-06-28 | 2019-01-04 | 中芯国际集成电路制造(上海)有限公司 | A kind of manufacturing method of semiconductor devices |
| CN109817525A (en) * | 2017-11-22 | 2019-05-28 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN112309858A (en) | 2021-02-02 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN110277316B (en) | Semiconductor structure and forming method thereof | |
| CN112309860B (en) | Semiconductor structure and forming method thereof | |
| US11676869B2 (en) | Semiconductor device and manufacturing method thereof | |
| US10832967B2 (en) | Tapered fin-type field-effect transistors | |
| CN111863711B (en) | Semiconductor structure and forming method thereof | |
| TW201729347A (en) | Semiconductor device | |
| CN111106009B (en) | Semiconductor structure and forming method thereof | |
| CN110718465B (en) | Semiconductor structure and forming method thereof | |
| CN112151376B (en) | Semiconductor structure and forming method thereof | |
| CN111554578B (en) | Semiconductor structure and forming method thereof | |
| CN112309858B (en) | Semiconductor structure and forming method thereof | |
| CN111200017B (en) | Semiconductor structure and forming method thereof | |
| US11955535B2 (en) | Methods for forming air spacers in semiconductor devices | |
| CN111463275B (en) | Semiconductor structure and forming method thereof | |
| CN111435645B (en) | Semiconductor structure and forming method thereof | |
| CN110808286B (en) | Semiconductor structure and forming method thereof | |
| CN110767607A (en) | Semiconductor structure and forming method thereof | |
| CN114068394B (en) | Method for forming semiconductor structure | |
| CN112289746B (en) | Semiconductor structure and forming method thereof | |
| CN111863710B (en) | Semiconductor structure and forming method thereof | |
| CN111627854B (en) | Semiconductor structure and forming method thereof | |
| CN112103249B (en) | Semiconductor structure and forming method thereof | |
| CN117637745A (en) | Semiconductor structure and forming method thereof | |
| CN116072675A (en) | Semiconductor structure and forming method thereof | |
| CN116072676A (en) | Semiconductor structure and forming method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |