CN117637745A

CN117637745A - Semiconductor structure and forming method thereof

Info

Publication number: CN117637745A
Application number: CN202210990561.5A
Authority: CN
Inventors: 谭程
Original assignee: Semiconductor Manufacturing International Shanghai Corp
Current assignee: Semiconductor Manufacturing International Shanghai Corp
Priority date: 2022-08-18
Filing date: 2022-08-18
Publication date: 2024-03-01

Abstract

A semiconductor structure and a method of forming the same, the method comprising: providing a substrate, wherein a channel bulge is formed at the top of the substrate, a grid structure crossing the channel bulge is formed on the substrate, active drain doping layers are formed in the channel bulge at two sides of the grid structure, an interlayer dielectric layer is formed on the substrate exposed by the grid structure, and the substrate comprises a first region and a second region along the direction perpendicular to the extending direction of the channel bulge; forming an opening penetrating through the interlayer dielectric layer at the junction position of the source-drain doping layer of the first region and the source-drain doping layer of the second region; forming a dielectric layer in the opening; removing the interlayer dielectric layer covering the source-drain doped layer in the first region and the second region, and forming grooves exposing the top surfaces and the side walls of the source-drain doped layer at the top of the substrate of the first region and the second region; and forming a source-drain plug in the groove, wherein the source-drain plug covers the top surface and the side wall of the source-drain doped layer. The contact area between the source-drain plug and the source-drain doped layer is increased, and the contact resistance between the source-drain plug and the source-drain doped layer is reduced.

Description

Semiconductor structure and forming method thereof

Technical Field

Embodiments of the present disclosure relate to semiconductor manufacturing, and more particularly, to a semiconductor structure and a method for forming the same.

Background

With the rapid development of semiconductor manufacturing technology, semiconductor devices are being developed toward higher element density, and higher integration. The device is used as the most basic semiconductor device, is widely applied at present, the control capability of the traditional planar device on channel current is weakened, short channel effect is generated to cause leakage current, and the electrical property of the semiconductor device is finally affected.

In order to overcome the short channel effect of the device and suppress leakage current, fin field effect transistors (Fin FETs), which are an emerging multi-gate device, are proposed in the prior art, which generally include a Fin protruding from the surface of a semiconductor substrate, a gate structure covering a portion of the top surface and sidewalls of the Fin, and source-drain doped layers in the Fin on both sides of the gate structure.

In the manufacturing process of the semiconductor device, the plug electrically connected with the source-drain doped layer in the fin part is formed, so that the active area is electrically connected with an external circuit.

However, the performance of semiconductor structures remains to be improved.

Disclosure of Invention

The embodiment of the invention solves the problem of providing a semiconductor structure and a forming method thereof, and optimizes the performance of a semiconductor device.

To solve the above problems, an embodiment of the present invention provides a semiconductor structure, including: a substrate comprising a first region and a second region; a channel boss on top of the substrate; a gate structure on the substrate and crossing the channel projection; the grid side wall layer is positioned on the side wall of the grid structure; the source-drain doped layers are positioned in channel convex parts at two sides of the grid structure; the source-drain plug is positioned on the substrate exposed by the grid structure and covers the top surface and the side wall of the source-drain doped layer and the side wall of the channel protruding part, and the source-drain plug is electrically connected with the source-drain doped layer; an etching stop layer positioned on a part of side walls of the source-drain doping layer closest to the boundary position of the first region and a part of side walls of the source-drain doping layer closest to the boundary position of the second region; the dielectric layer is positioned at the junction position of the source-drain doping layer of the first region and the source-drain doping layer of the second region, and covers the etching stop layer, the side wall of the gate structure and the side wall of the source-drain plug, and the top of the dielectric layer is flush with the top of the source-drain plug.

Correspondingly, the embodiment of the invention also provides a method for forming the semiconductor structure, which comprises the following steps: providing a substrate, wherein a channel protruding part is formed on the top of the substrate, a grid structure crossing the channel protruding part is formed on the substrate, the grid structure covers part of the top and part of the side wall of the channel protruding part, an active drain doping layer is formed in the channel protruding part on two sides of the grid structure, an interlayer dielectric layer is formed on the substrate exposed by the grid structure, the interlayer dielectric layer covers the active drain doping layer and the side wall of the grid structure and is flush with the top of the grid structure, and the substrate comprises a first region and a second region along the direction perpendicular to the extending direction of the channel protruding part; forming an opening penetrating through the interlayer dielectric layer at the junction position of the source-drain doping layer of the first region and the source-drain doping layer of the second region; forming a dielectric layer in the opening; removing the interlayer dielectric layer covering the source-drain doped layer in the first region and the second region after the dielectric layer is formed, and forming grooves exposing the top surfaces and the side walls of the source-drain doped layer on the top of the substrate in the first region and the second region; and forming a source-drain plug in the groove, wherein the source-drain plug covers the top surface and the side wall of the source-drain doped layer, and the source-drain plug is electrically connected with the source-drain doped layer.

Compared with the prior art, the technical scheme of the embodiment of the invention has the following advantages:

in the method for forming the semiconductor structure provided by the embodiment of the invention, the opening penetrating through the interlayer dielectric layer is formed at the junction position of the source-drain doped layer of the first region and the source-drain doped layer of the second region, the dielectric layer is formed in the opening, and in the process of subsequently removing the interlayer dielectric layer covering the source-drain doped layer in the first region and the second region, the interlayer dielectric layer covering the source-drain doped layer in the first region and the second region can be removed cleanly by utilizing the etching selection ratio between the dielectric layer and the interlayer dielectric layer, so that the top surface and the side wall of the source-drain doped layer are exposed, and correspondingly, in the process of subsequently forming the source-drain plug, the contact area between the source-drain plug and the source-drain doped layer is increased, so that the contact resistance between the source-drain plug and the source-drain doped layer is reduced, and the performance of the semiconductor structure is improved.

Drawings

Fig. 1 to 5 are schematic structural views corresponding to steps in a method for forming a semiconductor structure;

FIG. 6 is a schematic diagram of a semiconductor structure according to an embodiment of the present invention;

Fig. 7 to 17 are schematic structural views corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention.

Detailed Description

As known from the background art, the performance of the semiconductor device is still to be improved. The reason why the performance of a semiconductor device is still to be improved is now analyzed in conjunction with a method of forming a semiconductor structure.

Fig. 1 to 5 are schematic structural views corresponding to steps in a method for forming a semiconductor structure.

Referring to fig. 1 to 3, in which fig. 1 is a top view, fig. 2 is a cross-sectional view along the bb direction of fig. 1, fig. 3 is a cross-sectional view along the aa direction of fig. 1, a substrate 10 is provided, a fin 11 is raised on top of the substrate 10, a gate structure 12 is formed on the substrate 10 to span the fin 11, the gate structure 12 covers part of the top and part of the sidewall of the fin 11, source/drain doped layers 14 are formed in the fin 11 on both sides of the gate structure 12, an interlayer dielectric layer 13 is formed on the substrate 10 where the gate structure 12 is exposed, and the interlayer dielectric layer 13 covers the source/drain doped layers 14 and the sidewall of the gate structure 12 and is flush with the top of the gate structure 12.

Referring to fig. 4, the interlayer dielectric layer 13 on top of the source drain doped layer 14 is removed to form an opening 16 exposing the top surface of the source drain doped layer 14.

Referring to fig. 5, a source-drain plug 18 is formed in the opening 16, the source-drain plug 18 covers the top surface of the source-drain doped layer 14, and the source-drain plug 18 is electrically connected to the source-drain doped layer 14.

According to the research, as the process size of the semiconductor structure is smaller and smaller, the distance between the adjacent fin portions 11 is smaller and smaller, and accordingly, the distance between the adjacent source and drain doped layers 14 is smaller and smaller, in the process of removing the interlayer dielectric layer 13 positioned on the top of the source and drain doped layers 14 and forming the opening 16 exposing the top surface of the source and drain doped layers 14, the process window for removing the interlayer dielectric layer 13 between the adjacent source and drain doped layers 14 is smaller and smaller due to the smaller and smaller distance between the adjacent source and drain doped layers 14, the process difficulty of removing the interlayer dielectric layer 13 on the side wall of the source and drain doped layers 14 is increased, the opening 16 can only expose the top surface of the source and drain doped layers 14, after the source and drain plug 18 is formed later, the source and drain plug 18 is only in contact with the top surface of the source and drain doped layers 14, the contact area between the source and drain plug 18 and the source and drain doped layers 14 is excessively small, and the contact resistance between the source and drain plug 18 and the source and the drain doped layers 14 is increased, so that the performance of the semiconductor structure is affected.

In order to solve the technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate, wherein a channel protruding part is formed on the top of the substrate, a grid structure crossing the channel protruding part is formed on the substrate, the grid structure covers part of the top and part of the side wall of the channel protruding part, a source drain doping layer is formed in the channel protruding part on two sides of the grid structure, an interlayer dielectric layer is formed on the substrate exposed by the grid structure, the interlayer dielectric layer covers the source drain doping layer and the side wall of the grid structure and is flush with the top of the grid structure, and the substrate comprises a first area and a second area along the direction perpendicular to the extending direction of the channel protruding part; forming an opening penetrating through the interlayer dielectric layer at the junction position of the source-drain doping layer of the first region and the source-drain doping layer of the second region; forming a dielectric layer in the opening; removing the interlayer dielectric layer covering the source-drain doped layer in the first region and the second region after forming the dielectric layer, and forming grooves exposing the top surfaces and the side walls of the source-drain doped layer on the top of the substrate in the first region and the second region; and forming a source-drain plug in the groove, wherein the source-drain plug covers the top surface and the side wall of the source-drain doped layer, and the source-drain plug is electrically connected with the source-drain doped layer.

In the method for forming the semiconductor structure provided by the embodiment of the invention, the opening penetrating through the interlayer dielectric layer is formed at the junction position of the source-drain doped layer of the first region and the source-drain doped layer of the second region, the dielectric layer is formed in the opening, and in the process of subsequently removing the interlayer dielectric layer covering the source-drain doped layer in the first region and the second region, the interlayer dielectric layer covering the source-drain doped layer in the first region and the second region can be removed by utilizing the etching selection ratio between the dielectric layer and the interlayer dielectric layer, so that the top surface and the side wall of the source-drain doped layer are exposed, and correspondingly, the contact area between the source-drain plug and the source-drain doped layer is increased in the process of subsequently forming the source-drain plug, so that the contact resistance between the source-drain plug and the source-drain doped layer is reduced, and the performance of the semiconductor structure is improved.

In order that the above objects, features and advantages of embodiments of the invention may be readily understood, a more particular description of the invention will be rendered by reference to specific embodiments thereof which are illustrated in the appended drawings.

Fig. 6 is a schematic structural diagram of an embodiment of a semiconductor structure according to the present invention.

The semiconductor structure includes: a substrate (not labeled) comprising a first region 200A and a second region 200B; a channel boss 201 on top of the substrate; a gate structure 202 on the substrate and crossing the channel protrusion 201; a gate sidewall layer (not shown) located on the sidewall of the gate structure 202; the source-drain doped layer 204 is positioned in the channel convex part 201 at two sides of the gate structure 202; a source-drain plug 216, which is located on the exposed substrate of the gate structure 202 and covers the top surface and the sidewall of the source-drain doped layer 204 and the sidewall of the channel protruding portion 201, wherein the source-drain plug 216 is electrically connected with the source-drain doped layer 204; an etch stop layer 206 located on a portion of the sidewall of the source/drain doped layer 204 nearest to the boundary of the first region 200A and on a portion of the sidewall of the source/drain doped layer 204 nearest to the boundary of the second region 200B; the dielectric layer 210 is located at the boundary between the source-drain doped layer 204 of the first region 200A and the source-drain doped layer 204 of the second region 200B, and the dielectric layer 210 covers the etching stop layer 206, the sidewalls of the gate structure 202, and the sidewalls of the source-drain plug 216, and the top of the dielectric layer 210 is level with the top of the source-drain plug 216.

It should be noted that, by disposing the dielectric layer 210 at the boundary position between the source-drain doped layer 204 of the first region 200A and the source-drain doped layer 204 of the second region 200B, in the process of forming the source-drain plug 216, the etching selectivity between the dielectric layer 210 and the film layer (e.g., the interlayer dielectric layer) covering the source-drain doped layer 204 in the first region 200A and the second region 200B can be utilized to remove the interlayer dielectric layer covering the source-drain doped layer 204, so that the top surface and the side wall of the source-drain doped layer 204 are exposed, and accordingly, the contact area between the source-drain plug 216 and the source-drain doped layer 204 is increased, and the contact resistance between the source-drain plug 216 and the source-drain doped layer 204 is reduced, thereby improving the performance of the semiconductor structure.

The substrate is used for providing a process platform for the subsequent process.

In this embodiment, the substrate is used to form a fin field effect transistor (FinFET).

For this reason, in this embodiment, the fin 201 is raised on top of the substrate, and the fin 201 with a partial height near the top of the fin 201 is used as the channel raised portion 201.

The channel boss 201 provides a conductive channel for the transistor.

The base is a silicon substrate 200, and the silicon substrate 200 and the fin 201 are of an integrated structure.

The fin 201 is made of silicon, which is the same material as the substrate 200. In other embodiments, the material of the substrate may also be germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, and the substrate may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate.

In other embodiments, the channel protrusions are a stacked structure including one or more channel layers spaced apart along a normal direction of the substrate surface.

In this embodiment, the substrate includes a first region 200A and a second region 200B, the first region 200A and the second region 200B being device regions of the transistor

The gate structure 202 is used to control the turning on or off of the conductive channel during operation of the device.

In this embodiment, the gate structure 202 is located on the substrate 200, and the gate structure 202 spans the channel protruding portion 201 and covers part of the top and part of the side walls of the channel protruding portion 201.

In this embodiment, the gate structure 202 includes a gate dielectric layer (not shown), and a gate electrode layer (not shown) covering the gate dielectric layer.

The gate dielectric layer is used for isolating the gate electrode layer and the conductive channel. The gate dielectric layer material comprises HfO ₂ 、ZrO ₂ 、HfSiO、HfSiON、HfTaO、HfTiO、HfZrO、Al ₂ O ₃ 、SiO ₂ And La (La) ₂ O ₃ One or more of the following.

The gate electrode layer is used for subsequent electrical connection with the external interconnect structure. The material of the gate electrode layer includes one or more of TiN, taN, ta, ti, tiAl, W, al, tiSiN and TiAlC.

As one example, the gate electrode layer may include a work function layer, and an electrode layer on the work function layer, wherein the work function layer is used to adjust a threshold voltage of the transistor. In other embodiments, the gate electrode layer may also include only the work function layer.

In this embodiment, the semiconductor structure further includes: the gate cap layer 205 is located on top of the gate structure 202, and the top of the gate cap layer 205 is flush with the top of the source drain plug 216.

Specifically, in the process of forming the semiconductor structure, the gate cap layer 205 protects the top of the gate structure 202, and in the process of forming the source drain plug 216, the top of the gate cap layer 205 serves as a stop position, so that the top of the source drain plug 216 is flush with the top of the gate cap layer 205, and the top surface flatness of the source drain plug 216 is improved.

In this embodiment, the material of the gate cap layer 205 includes one or more of silicon oxide, silicon nitride, and silicon oxynitride. As an example, the material of the gate cap layer 205 is silicon oxynitride.

The gate sidewall layer is used to protect the sidewalls of the gate structure 202.

The grid side wall layer can be of a single-layer structure or a laminated structure, and the material of the grid side wall layer can be one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride oxide, silicon oxynitride, boron nitride and boron carbonitride. In this embodiment, the gate sidewall layer is of a single-layer structure, and the gate sidewall layer is made of silicon nitride.

The source drain doped layer 204 is used as a source region and a drain region of the transistor.

When the NMOS transistor is formed, the source-drain doped layer 204 includes a stress layer doped with N-type ions, where the stress layer is made of Si or SiC, and the stress layer provides a tensile stress for a channel region of the NMOS transistor, so that carrier mobility of the NMOS transistor is improved, and the N-type ions are P ions, as ions, or Sb ions; when forming the PMOS transistor, the source-drain doped layer 204 includes a stress layer doped with P-type ions, where the stress layer is made of Si or SiGe, and the stress layer provides compressive stress to the channel region of the PMOS transistor, so as to facilitate improving carrier mobility of the PMOS transistor, and the P-type ions are B ions, ga ions, or In ions.

In this embodiment, the etching stop layer 206 is located on a portion of the sidewall of the source-drain doped layer 204 closest to the boundary position of the first region 200A and a portion of the sidewall of the source-drain doped layer 204 closest to the boundary position of the second region 200B.

It should be noted that, in the formation process of the source drain plug 216 and the dielectric layer 210, the etching stop layer 206 protects the top surface and the sidewall of the source drain doped layer 204, so as to reduce the probability of damaging the source drain doped layer 204, thereby improving the performance of the semiconductor structure.

It should be further noted that, according to the process requirement of the top dimension of the source drain plug 216, during the formation process of the source drain plug 216, the etching stop layer 206 closest to the sidewall of the portion of the source drain doped layer 204 at the boundary position of the first region 200A and the etching stop layer 206 closest to the sidewall of the portion of the source drain doped layer 204 at the boundary position of the second region 200B may be left.

In this embodiment, the material of the etch stop layer 206 includes one or both of silicon nitride and silicon oxynitride.

The hardness of the silicon nitride and silicon oxynitride materials is relatively high, and the etching stop layer 206 is not easily etched in the process of forming the source/drain plug 216 and the dielectric layer 210, so that the etching stop layer 206 has a relatively good protection effect on the top surface and the side wall of the source/drain doped layer 204.

It should be noted that, by disposing the dielectric layer 210 at the boundary position between the source-drain doped layer 204 of the first region 200A and the source-drain doped layer 204 of the second region 200B, in the process of forming the source-drain plug 216, the etching selectivity between the dielectric layer 210 and the film layer (for example, the interlayer dielectric layer) covering the source-drain doped layer 204 in the first region 200A and the second region 200B can be utilized to remove the interlayer dielectric layer covering the source-drain doped layer 204, so that the top surface and the side wall of the source-drain doped layer 204 are all exposed, and accordingly, the contact area between the source-drain plug 216 and the source-drain doped layer 204 is increased, and the contact resistance between the source-drain plug 216 and the source-drain doped layer 204 is reduced, thereby improving the performance of the semiconductor structure.

It should also be noted that the dielectric layer 210 serves as an electrical isolation between adjacent source and drain plugs 216.

In this embodiment, the material of the dielectric layer 210 includes one or both of silicon oxide containing carbon and silicon oxynitride.

The carbon-containing silicon oxide and silicon oxynitride are both dielectric materials, and the dielectric layer 210 plays an electrical isolation role on the adjacent source-drain plugs 216, meanwhile, in the process of forming the source-drain plugs 216, the carbon-containing silicon oxide and silicon oxynitride have a higher etching selectivity ratio with the materials selected for the film layer (such as an interlayer dielectric layer) covering the source-drain doped layer 204, and in the process of removing the interlayer dielectric layer covering the source-drain doped layer 204 in the first region 200A and the second region 200B, the effect of removing the interlayer dielectric layer covering the source-drain doped layer 204 in the first region 200A and the second region 200B is achieved by using the etching selectivity ratio between the dielectric layer 210 and the interlayer dielectric layer, so that the top surface and the side wall of the source-drain doped layer 204 are fully exposed, the contact area between the source-drain plugs 216 and the source-drain doped layer 204 is increased, and the contact resistance between the source-drain plugs 216 and the source-doped layer 204 is further reduced.

In this embodiment, the semiconductor structure further includes: silicide layer 210 is located between source drain doped layer 204 and source drain plug 216, and between source drain plug 216 and channel boss 201.

Specifically, the silicide layer 210 is used to further reduce the contact resistance between the source-drain doped layer 204 and the source-drain doped layer 204, thereby improving the performance of the semiconductor structure.

In this embodiment, the material of the silicide layer 210 includes one or more of TiSi, tiSiN, and TiSiON.

Specifically, tiSi, tiSiN, and TiSiON are all metal silicides, which have a conductive function, so that the source-drain doped layer 204 and the source-drain plug 216 can be electrically connected to each other, and meanwhile, the metal silicide has an effect of reducing a contact resistance between the source-drain doped layer 204 and the source-drain doped layer 204, thereby improving performance of the semiconductor structure.

The source drain plug 216 is electrically connected to the source drain doped layer 204 for making electrical connection between the source drain doped layer 204 and an external circuit or other interconnect structure.

In this embodiment, the source/drain plug 216 is made of tungsten. The lower resistivity of tungsten is beneficial to improving the signal delay of the back-end RC, improving the processing speed of the chip, reducing the resistance of the source drain plug 216 and correspondingly reducing the power consumption. In other embodiments, the source-drain plug 216 may also be made of a conductive material such as molybdenum or ruthenium.

Referring to fig. 7 to 9, in which fig. 7 is a top view, fig. 8 is a cross-sectional view along the AA direction of fig. 7, fig. 9 is a cross-sectional view along the BB direction of fig. 7, a substrate is provided, a channel protrusion 101 is formed on the top of the substrate, a gate structure 102 crossing the channel protrusion 101 is formed on the substrate, the gate structure 102 covers a portion of the top and a portion of the sidewall of the channel protrusion 101, an active drain doping layer 104 is formed in the channel protrusion 101 on both sides of the gate structure 102, an interlayer dielectric layer 103 is formed on the substrate exposed by the gate structure 102, the interlayer dielectric layer 103 covers the active drain doping layer 104 and the sidewall of the gate structure 102 and is flush with the top of the gate structure 102, and the substrate includes a first region 100A and a second region 100B along a direction perpendicular to the extending direction of the channel protrusion 101.

For this reason, in this embodiment, the fin 101 is raised on the top of the substrate, and the fin 101 with a partial height near the top of the fin 101 is used as the channel raised portion 101.

The channel boss 101 provides a conductive channel for the transistor.

The base is a silicon substrate 100, and the silicon substrate 100 and the fin 101 are in an integrated structure.

The material of the fin 101 is the same as the material of the substrate 100, both being silicon. In other embodiments, the material of the substrate may also be germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, and the substrate may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate.

In this embodiment, the substrate includes a first region 100A and a second region 100B, and the first region 100A and the second region 100B are device regions for forming a transistor.

The gate structure 102 is used to control the turning on or off of the conductive channel during device operation.

In this embodiment, the gate structure 102 is located on the substrate 100, and the gate structure 102 spans the channel protruding portion 101 and covers part of the top and part of the side wall of the channel protruding portion 101.

In this embodiment, the gate structure 102 includes a gate dielectric layer (not shown), and a gate electrode layer (not shown) covering the gate dielectric layer.

The source-drain doped layer 104 is used as a source region and a drain region of a transistor.

In this embodiment, the source-drain doped layer 104 is formed in the channel convex portion 101 at both sides of the gate structure 102 by an epitaxial process.

When the NMOS transistor is formed, the source-drain doped layer 104 includes a stress layer doped with N-type ions, where the stress layer is made of Si or SiC, and the stress layer provides a tensile stress for a channel region of the NMOS transistor, so that carrier mobility of the NMOS transistor is improved, and the N-type ions are P ions, as ions, or Sb ions; when forming the PMOS transistor, the source-drain doped layer 104 includes a stress layer doped with P-type ions, where the stress layer is made of Si or SiGe, and the stress layer provides compressive stress to the channel region of the PMOS transistor, so as to facilitate improving carrier mobility of the PMOS transistor, and the P-type ions are B ions, ga ions, or In ions.

Interlayer dielectric layer 103 is used to electrically isolate adjacent devices and also to occupy space for subsequently formed dielectric layers.

The top of the interlayer dielectric layer 103 is flush with the top of the gate structure 102, so that the flatness of the top surfaces of the interlayer dielectric layer 103 and the gate structure 102 is improved, and a process foundation is provided for subsequent process steps.

The material of the interlayer dielectric layer 103 is an insulating material, and the material of the interlayer dielectric layer 103 includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride and silicon oxycarbonitride. As an example, the material of the interlayer dielectric layer 103 is silicon oxide.

In this embodiment, in the step of providing the substrate, an etching stop layer 106 is further formed on the substrate to cover the top surface and the sidewalls of the source/drain doped layer 104 and the sidewalls of the channel protruding portion 101.

Specifically, in the subsequent process of forming the opening and the trench, the etching stop layer 106 protects the top surface and the side wall of the source-drain doped layer 104, so that the probability of damaging the source-drain doped layer 104 is reduced, and the performance of the semiconductor structure is improved.

In this embodiment, the material of the etch stop layer 106 includes one or both of silicon nitride and silicon oxynitride.

The hardness of the silicon nitride and silicon oxynitride materials is high, and the etching stop layer 106 is not easy to etch in the subsequent process of forming the openings and the grooves, so that the etching stop layer 106 has a good protection effect on the top surface and the side walls of the source-drain doped layer 104.

In this embodiment, in the step of providing the substrate, a gate cap layer 105 is further formed on top of the gate structure 102.

Specifically, in the subsequent process of forming the opening and the trench, the gate cap layer 105 protects the top of the gate structure 102, and meanwhile, in the subsequent process of forming the source-drain plug, the top of the gate cap layer 105 serves as a stop position, so that the top of the source-drain plug is flush with the top of the gate cap layer 105, the top surface flatness of the source-drain plug is improved, and the method is a basis for the subsequent semiconductor process.

In this embodiment, the material of the gate cap layer 105 includes one or more of silicon oxide, silicon nitride, and silicon oxynitride. As an example, the material of the gate cap layer 105 is silicon oxynitride.

Referring to fig. 10 to 11, an opening 108 penetrating the interlayer dielectric layer 103 is formed at an interface position of the source and drain doped layer 104 of the first region 100A and the source and drain doped layer 104 of the second region 100B.

Openings 108 provide a spatial location for subsequent dielectric layer formation.

In this embodiment, the step of forming the opening 108 includes: forming a hard mask layer 107 with a mask opening 108 on top of the interlayer dielectric layer 103, wherein the mask opening 108 is located at the junction position of the source-drain doped layer 104 of the first region 100A and the source-drain doped layer 104 of the second region 100B; the hard mask layer 107 is used as a mask, and the interlayer dielectric layer 103 at the junction position of the source/drain doped layer 104 of the first region 100A and the source/drain doped layer 104 of the second region 100B is removed along the mask opening 108, so as to form an opening 108 penetrating the interlayer dielectric layer 103.

It should be noted that, as an example, in the process of forming the opening, the opening 108 exposes the etching stop layer 106 closest to the side wall of the portion of the source/drain doped layer 104 at the boundary position of the first region 100A and the etching stop layer 106 closest to the side wall of the portion of the source/drain doped layer 104 at the boundary position of the second region 100B according to different process requirements of the top dimension of the source/drain plug to be formed later.

In this embodiment, the material of the hard mask layer 107 includes TiN, siN and SiO ₂ One or more of the following.

With TiN, siN and SiO ₂ As the material of the hard mask layer 107, the hardness of the material of the hard mask layer 107 is relatively high, and accordingly, in the process of removing the interlayer dielectric layer 103 at the junction position of the source-drain doped layer 104 of the first region 100A and the source-drain doped layer 104 of the second region 100B along the mask opening 108 by taking the hard mask layer 107 as a mask, the shape quality of the sidewall of the formed opening 108 is improved.

In this embodiment, the process of removing the interlayer dielectric layer 103 at the boundary position of the source-drain doped layer 104 of the first region 100A and the source-drain doped layer 104 of the second region 100B along the mask opening 108 includes a dry etching process.

The dry etching process is an anisotropic dry etching process. The anisotropic dry etching process has the characteristic of anisotropic etching, namely, the longitudinal etching rate is larger than the transverse etching rate, the anisotropic dry etching process has the characteristics of high process controllability, high pattern transfer precision and the like, and in the process of removing the interlayer dielectric layer 103 at the junction position of the source-drain doped layer 104 of the first region 100A and the source-drain doped layer 104 of the second region 100B, the anisotropic dry etching process is adopted, so that the probability of damaging the source-drain doped layer 104 on the side wall of the opening 108 is reduced, and meanwhile, the shape quality of the side wall of the opening 108 is improved, and the opening 108 provides a process basis for the subsequent formation of a dielectric layer.

Referring to fig. 12 to 13, a dielectric layer 110 is formed in the opening 108.

Specifically, the dielectric layer 110 is formed in the opening 108, and in the subsequent process of removing the interlayer dielectric layer 103 covering the source-drain doped layer 104 in the first region 100A and the second region 100B, the interlayer dielectric layer 103 covering the source-drain doped layer 104 in the first region 100A and the second region 100B can be removed cleanly by using the etching selection ratio between the dielectric layer 110 and the interlayer dielectric layer 103, so that the top surface and the side wall of the source-drain doped layer 104 are exposed, and correspondingly, in the subsequent process of forming the source-drain plug, the contact area between the source-drain plug and the source-drain doped layer 104 is increased, so that the contact resistance between the source-drain plug and the source-drain doped layer 104 is reduced, thereby improving the performance of the semiconductor structure.

In this embodiment, the step of forming the dielectric layer 110 includes: forming a dielectric material layer 109 on top of the interlayer dielectric layer 103, on top of the gate structure 102, and in the opening 108; with the top of the interlayer dielectric layer 103 as a stop position, the dielectric material layer 109 on the top of the interlayer dielectric layer 103 and the top of the gate structure 102 is removed, and the remaining dielectric material layer 109 located in the opening 108 is used as a dielectric layer 110.

It should be noted that, in the process of forming the dielectric layer 110, the dielectric layer 110 also covers the etching stop layer 106 closest to the side wall of the portion of the source/drain doped layer 104 at the boundary position of the first region 100A, and the etching stop layer 106 closest to the side wall of the portion of the source/drain doped layer 104 at the boundary position of the second region 100B.

In this embodiment, the dielectric material layer 109 is used as a material for forming the dielectric layer 110.

In this embodiment, the process of forming the dielectric material layer 109 includes a chemical vapor deposition process.

Specifically, the chemical vapor deposition process has the characteristics of fast deposition rate, good filling performance and the like, and the dielectric material layer 109 is formed by adopting the chemical vapor deposition process, so that the opening 108 can be filled with the dielectric material layer 109, and meanwhile, the probability of forming a cavity in the dielectric material layer 109 is reduced, thereby improving the performance of the semiconductor structure.

In this embodiment, the material of the dielectric layer 110 includes one or both of silicon oxide containing carbon and silicon oxynitride.

The carbon-containing silicon oxide and silicon oxynitride are both dielectric materials, after the source and drain plugs are formed subsequently, the dielectric layer 110 has an electrical isolation effect on adjacent source and drain plugs, meanwhile, the carbon-containing silicon oxide and silicon oxynitride have a higher etching selection ratio with the silicon oxide material selected for the interlayer dielectric layer 103, in the process of subsequently removing the interlayer dielectric layer 103 covering the source and drain doped layers 104 in the first region 100A and the second region 100B, the etching selection ratio between the dielectric layer 110 and the interlayer dielectric layer 103 is utilized to achieve the effect of completely removing the interlayer dielectric layer 103 covering the source and drain doped layers 104 in the first region 100A and the second region 100B, so that the top surface and the side wall of the source and drain doped layers 104 are all exposed, the contact area between the subsequently formed source and drain plugs and the source and drain doped layers 104 is increased, and the contact resistance between the source and drain plugs and the source and the drain doped layers 104 is further reduced.

In this embodiment, the process of removing the dielectric material layer 109 on top of the interlayer dielectric layer 103 and on top of the gate structure 102 includes a chemical mechanical polishing process with the top of the interlayer dielectric layer 103 as a stop position.

Referring to fig. 14, after forming the dielectric layer 110, the interlayer dielectric layer 103 covering the source and drain doped layers 104 in the first and second regions 100A and 100B is removed, and trenches 111 exposing top surfaces and sidewalls of the source and drain doped layers 104 are formed on top of the substrate of the first and second regions 100A and 100B.

Specifically, the trench 111 provides a spatial location for the subsequent formation of source drain plugs.

In this embodiment, the process of removing the interlayer dielectric layer 103 covering the source-drain doped layer 104 in the first region 100A and the second region 100B includes a wet etching process.

It should be noted that the wet etching process is an isotropic etching process, and has the characteristics of fast etching rate, low process cost, and the like, so that the interlayer dielectric layer 103 covering the source-drain doped layer 104 in the first region 100A and the second region 100B can be removed completely, and meanwhile, the wet etching process is easy to realize a larger etching selection ratio, thereby being beneficial to reducing the difficulty of etching the interlayer dielectric layer 103 covering the source-drain doped layer 104 in the first region 100A and the second region 100B and reducing the probability of damaging other film structures (such as the source-drain doped layer 104).

It should be noted that, in the process of removing the interlayer dielectric layer 103 covering the source/drain doped layer 104 in the first region 100A and the second region 100B, the etching selectivity of the interlayer dielectric layer 103 to the dielectric layer 110 should not be too small. If the etching selectivity of the interlayer dielectric layer 103 to the dielectric layer 110 is too small, the etched rate of the interlayer dielectric layer 103 is easy to be consistent with the etched rate of the dielectric layer 110, and accordingly, the dielectric layer 110 is easy to be removed in the process of removing the interlayer dielectric layer 103 covering the source-drain doped layer 104 in the first region 100A and the second region 100B, so that the dielectric layer 110 is damaged, and the performance of the semiconductor structure is further affected. For this reason, in the process of removing the interlayer dielectric layer 103 covering the source/drain doped layer 104 in the first region 100A and the second region 100B, the etching selectivity ratio of the interlayer dielectric layer 103 to the dielectric layer 110 is greater than 20:1.

referring to fig. 15, the etch stop layer 106 of the top surface and the sidewalls of the source drain doped layer 104 and the sidewalls of the channel protrusion 101 is removed.

It should be noted that, removing the top surface and the sidewall of the source-drain doped layer 104 and the etching stop layer 106 of the sidewall of the channel protruding portion 101 exposes the top surface and the sidewall of the source-drain doped layer 104, and increases the contact area between the source-drain doped layer 104 and the subsequently formed source-drain plug, thereby reducing the contact resistance between the source-drain doped layer 104 and the source-drain plug.

It should be further noted that, according to different process requirements of the top dimension of the source and drain plugs to be formed later, the etching stop layer 106 closest to the side wall of the portion of the source and drain doped layer 104 at the boundary position of the first region 100A and the etching stop layer 106 closest to the side wall of the portion of the source and drain doped layer 104 at the boundary position of the second region 100B may be left.

In this embodiment, the process of removing the top surface and the sidewall of the source/drain doped layer 104 and the etching stop layer 106 of the sidewall of the channel protrusion 101 includes a wet etching process.

It should be noted that the wet etching process is an isotropic etching process, and has the characteristics of fast etching rate, low process cost, and the like, and can clean the top surface and the side wall of the source/drain doped layer 104 and the etching stop layer 106 of the side wall of the channel protruding portion 101, and meanwhile, the wet etching process is easy to realize a larger etching selection ratio, thereby being beneficial to reducing the difficulty of etching the top surface and the side wall of the source/drain doped layer 104 and the etching stop layer 106 of the side wall of the channel protruding portion 101 and reducing the probability of damaging other film layers (such as the source/drain doped layer 104).

Referring to fig. 16, a silicide layer 112 is formed on the top surface and sidewalls of the source drain doped layer 104 and the sidewalls of the channel protrusion 101.

Specifically, the silicide layer 112 is used to further reduce the contact resistance between the source-drain doped layer 104 and a subsequently formed source-drain plug, thereby improving the performance of the semiconductor structure.

In this embodiment, the process of forming the silicide layer 112 includes an atomic layer deposition process.

Specifically, the atomic layer deposition process has better step coverage, and the silicide layer 112 is formed by adopting the atomic layer deposition process, so that the silicide layer can cover the top surface and the side wall of the source-drain doped layer 104 and the side wall of the channel convex part 101, correspondingly, after the source-drain plug is formed subsequently, the contact area between the source-drain plug and the silicide layer 112 is increased, and the contact resistance between the source-drain doped layer 104 and the subsequently formed plug is further reduced.

In this embodiment, the material of the silicide layer 112 includes one or more of TiSi, tiSiN, and TiSiON.

Specifically, tiSi, tiSiN and TiSiON are all metal silicides, which have a conductive function, so that the source-drain doped layer 104 and a subsequently formed source-drain plug can be electrically connected with each other, and meanwhile, the metal silicide has the function of reducing the contact resistance between the source-drain doped layer 104 and the subsequently formed source-drain doped layer 104, thereby improving the performance of the semiconductor structure.

Referring to fig. 17, a source-drain plug 116 is formed in the trench 111, the source-drain plug 116 covers the top surface and the sidewalls of the source-drain doped layer 104, and the source-drain plug 116 is electrically connected to the source-drain doped layer 104.

The source drain plugs 116 are electrically connected to the source drain doped layer 104 for electrically connecting the source drain doped layer 104 to an external circuit or other interconnect structure.

In this embodiment, the step of forming the source drain plugs 116 includes: forming a conductive material layer on top of the dielectric layer 110, on top of the gate cap layer 105, and in the trench 111; with the top of the gate cap layer 105 as a stop position, the conductive material layer on top of the dielectric layer 110 and the top of the gate cap layer 105 is removed, and the remaining conductive material layer in the trench 111 serves as a source drain plug 116.

In this embodiment, the process of forming the conductive material layer includes a chemical vapor deposition process.

In this embodiment, the process of removing the conductive material layer on top of the dielectric layer 110 and on top of the gate cap layer 105 includes a chemical mechanical polishing process.

In this embodiment, the source/drain plug 116 is made of tungsten. The lower resistivity of tungsten is beneficial to improving the signal delay of the back RC, improving the processing speed of the chip, reducing the resistance of the source drain plug 116 and correspondingly reducing the power consumption. In other embodiments, the source-drain plug may be made of a conductive material such as molybdenum or ruthenium.

Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.

Claims

1. A semiconductor structure, comprising:

a substrate comprising a first region and a second region;

a channel boss on top of the substrate;

a gate structure on the substrate and crossing the channel projection;

the grid side wall layer is positioned on the side wall of the grid structure;

the source-drain doped layers are positioned in channel convex parts at two sides of the grid structure;

the source-drain plug is positioned on the substrate exposed by the grid structure and covers the top surface and the side wall of the source-drain doped layer and the side wall of the channel protruding part, and the source-drain plug is electrically connected with the source-drain doped layer;

an etching stop layer positioned on a part of side walls of the source-drain doping layer closest to the boundary position of the first region and a part of side walls of the source-drain doping layer closest to the boundary position of the second region;

the dielectric layer is positioned at the junction position of the source-drain doping layer of the first region and the source-drain doping layer of the second region, and covers the etching stop layer, the side wall of the gate structure and the side wall of the source-drain plug, and the top of the dielectric layer is flush with the top of the source-drain plug.

2. The semiconductor structure of claim 1, wherein the semiconductor structure further comprises: and the silicide layer is positioned between the source-drain doping layer and the source-drain plug and between the source-drain plug and the channel convex part.

3. The semiconductor structure of claim 2, wherein the material of the silicide layer comprises one or more of TiSi, tiSiN, and TiSiON.

4. The semiconductor structure of claim 1, wherein the semiconductor structure further comprises: the grid cap layer is positioned on the top of the grid structure, and the top of the grid cap layer is flush with the top of the source-drain plug.

5. The semiconductor structure of claim 1, wherein the channel protrusions are a stacked structure comprising one or more channel layers spaced apart in a direction normal to the substrate surface;

or,

and a fin part is raised at the top of the substrate, and the fin part which is close to the height of one side of the top of the fin part is used as the channel raised part.

6. A method of forming a semiconductor structure, comprising:

providing a substrate, wherein a channel protruding part is formed on the top of the substrate, a grid structure crossing the channel protruding part is formed on the substrate, the grid structure covers part of the top and part of the side wall of the channel protruding part, an active drain doping layer is formed in the channel protruding part on two sides of the grid structure, an interlayer dielectric layer is formed on the substrate exposed by the grid structure, the interlayer dielectric layer covers the active drain doping layer and the side wall of the grid structure and is flush with the top of the grid structure, and the substrate comprises a first region and a second region along the direction perpendicular to the extending direction of the channel protruding part;

Forming an opening penetrating through the interlayer dielectric layer at the junction position of the source-drain doping layer of the first region and the source-drain doping layer of the second region;

forming a dielectric layer in the opening;

removing the interlayer dielectric layer covering the source-drain doped layer in the first region and the second region after the dielectric layer is formed, and forming grooves exposing the top surfaces and the side walls of the source-drain doped layer on the top of the substrate in the first region and the second region;

and forming a source-drain plug in the groove, wherein the source-drain plug covers the top surface and the side wall of the source-drain doped layer, and the source-drain plug is electrically connected with the source-drain doped layer.

7. The method of forming a semiconductor structure of claim 6, wherein the step of forming the opening comprises: forming a hard mask layer with a mask opening at the top of the interlayer dielectric layer, wherein the mask opening is positioned at the junction position of the source-drain doping layer of the first region and the source-drain doping layer of the second region; and removing the interlayer dielectric layer at the junction position of the source-drain doping layer of the first region and the source-drain doping layer of the second region along the mask opening by taking the hard mask layer as a mask, so as to form an opening penetrating through the interlayer dielectric layer.

8. The method of forming a semiconductor structure according to claim 7, wherein the material of the hard mask layer comprises TiN, siN and SiO ₂ One or more of the following.

9. The method of forming a semiconductor structure of claim 6, wherein forming the dielectric layer comprises: forming a dielectric material layer on top of the interlayer dielectric layer, on top of the gate structure and in the opening; and taking the top of the interlayer dielectric layer as a stop position, removing the dielectric material layers at the top of the interlayer dielectric layer and the top of the grid structure, and taking the rest dielectric material layers in the openings as the dielectric layers.

10. The method of forming a semiconductor structure of claim 9, wherein the process of forming the layer of dielectric material comprises a chemical vapor deposition process.

11. The method of forming a semiconductor structure of claim 6, wherein the material of the dielectric layer comprises one or both of carbon-containing silicon oxide and silicon oxynitride.

12. The method of forming a semiconductor structure of claim 6, wherein removing an interlayer dielectric layer in said first and second regions overlying said source and drain doped layers comprises a wet etch process.

13. The method of forming a semiconductor structure as claimed in claim 6, wherein in the process of removing the interlayer dielectric layer covering the source-drain doped layer in the first region and the second region, an etching selectivity ratio of the interlayer dielectric layer to the dielectric layer is greater than 20:1.

14. the method of forming a semiconductor structure of claim 6, wherein in said step of providing a substrate, an etch stop layer is further formed on said substrate covering top and sidewalls of said source and drain doped layer and sidewalls of said channel boss;

after forming the trench, before forming the source-drain doped layer, the method further comprises: and removing the top surface and the side wall of the source-drain doped layer and the etching stop layer of the side wall of the channel convex part.

15. The method of forming a semiconductor structure of claim 14, wherein the process of removing the etch stop layer of the source drain doped layer top surface and sidewalls, and the channel lobe sidewall comprises a wet etch process.

16. The method of forming a semiconductor structure of claim 14, wherein the material of the etch stop layer comprises one or more of silicon nitride and silicon oxynitride.

17. The method of forming a semiconductor structure of claim 14, wherein after removing said etch stop layer of said source drain doped layer top and sidewalls and said channel lobe sidewall, prior to forming said source drain plug, further comprising: and forming silicide layers on the top surface and the side walls of the source-drain doped layer and the side walls of the channel convex parts.

18. The method of forming a semiconductor structure of claim 17, wherein the material of the silicide layer comprises one or more of TiSi, tiSiN, and TiSiON.

19. The method of forming a semiconductor structure of claim 6, wherein in the step of providing a substrate, a gate cap layer is further formed on top of the gate structure;

the step of forming the source drain plug comprises the following steps: forming a conductive material layer on top of the dielectric layer, on top of the gate cap layer, and in the trench; and taking the top of the gate cap layer as a stop position, removing the dielectric layer top and the conductive material layer on the top of the gate cap layer, and taking the rest conductive material layer in the groove as the source-drain plug.

20. The method of forming a semiconductor structure of claim 6, wherein the channel projection is a stacked structure comprising one or more channel layers spaced apart along a normal to the substrate surface;

or,