CN110120415B - Semiconductor structure and forming method thereof - Google Patents

Semiconductor structure and forming method thereof Download PDF

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Publication number
CN110120415B
CN110120415B CN201810138907.2A CN201810138907A CN110120415B CN 110120415 B CN110120415 B CN 110120415B CN 201810138907 A CN201810138907 A CN 201810138907A CN 110120415 B CN110120415 B CN 110120415B
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fin
insulating layer
layer
forming
dummy gate
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CN110120415A (en
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王楠
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

A semiconductor structure and a forming method thereof are provided, wherein the forming method comprises the following steps: providing a substrate and at least two fin parts protruding out of the substrate, wherein an isolation layer is arranged on the substrate exposed out of the fin parts, the isolation layer covers partial side walls of the fin parts, a pseudo gate crossing the fin parts is arranged on the isolation layer, and the pseudo gate covers partial top and partial side walls of the fin parts; forming a dielectric layer on the isolation layer, wherein the dielectric layer covers the side wall of the pseudo gate; removing part of the dummy gate, exposing part of the tops of part of the fin parts, and forming an opening penetrating the thickness of the dielectric layer in the dielectric layer; and forming an insulating layer filling the opening. The invention can form the semiconductor structure with the channel region quantity meeting the requirement on the basis of a plurality of positions capable of forming the channel region, thereby simplifying the technological process for forming the semiconductor structure with the channel region with specific quantity.

Description

Semiconductor structure and forming method thereof
Technical Field
The present invention relates to the field of semiconductor manufacturing technologies, and in particular, to a semiconductor structure and a method for forming the same.
Background
In semiconductor manufacturing, as the feature size of integrated circuits continues to decrease, the channel length of MOSFETs has correspondingly continued to decrease. However, as the channel length of the device is shortened, the distance between the source and the drain of the device is also shortened, so that the control capability of the gate to the channel is deteriorated, and short-channel effects (SCE) are more likely to occur.
The fin field effect transistor (FinFET) has outstanding performance in the aspect of inhibiting short channel effect, and the grid electrode of the FinFET can control the fin part at least from two sides, so that compared with a planar MOSFET, the grid electrode of the FinFET has stronger channel control capability, and the short channel effect can be well inhibited.
However, the process for forming the semiconductor structure in the prior art still needs to be improved.
Disclosure of Invention
The invention provides a semiconductor structure and a forming method thereof, which can form the semiconductor structure with the channel region quantity meeting the requirement on the basis of a plurality of positions capable of forming the channel region, thereby simplifying the process method for forming the semiconductor structure with the channel region with the specific quantity.
To solve the above problems, the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate and at least two fin parts protruding out of the substrate, wherein an isolation layer is arranged on the substrate exposed out of the fin parts, the isolation layer covers partial side walls of the fin parts, a pseudo gate crossing the fin parts is arranged on the isolation layer, and the pseudo gate covers partial top and partial side walls of the fin parts; forming a dielectric layer on the isolation layer, wherein the dielectric layer covers the side wall of the pseudo gate; removing part of the dummy gate, exposing part of the tops of part of the fin parts, and forming an opening penetrating the thickness of the dielectric layer in the dielectric layer; and forming an insulating layer filling the opening.
Optionally, the fin portion includes a first fin portion and a second fin portion adjacent to the first fin portion; the dummy gate comprises a first dummy gate part covering the top and the side wall of the first fin part and a second dummy gate part covering the top and the side wall of the second fin part; and in the step of removing part of the dummy gate, removing the second part of the dummy gate and reserving the first part of the dummy gate.
Optionally, the process method for removing the second portion of the dummy gate includes: forming a photoresist layer covering the top of the first part of the dummy gate, wherein the photoresist layer exposes the top of the second part of the dummy gate; removing the second part of the dummy gate by taking the photoresist layer as a mask; and removing the photoresist layer.
Optionally, before forming the dielectric layer, the method further includes: forming first grooves in the first fin portions on two sides of the dummy gate; forming second grooves in the second fin portions on two sides of the dummy gate; and forming a stress layer which is filled in the first groove and the second groove which are positioned on the same side of the pseudo gate.
Optionally, the stress layer is formed by using a selective epitaxial growth process.
Optionally, the distance between the first fin portion and the second fin portion is 30nm to 40 nm.
Optionally, after the forming the insulating layer, the method further includes: removing the second part of the dummy gate, and forming a through hole penetrating the thickness of the dielectric layer in the dielectric layer; and forming a grid electrode which is filled in the through hole.
Optionally, the fin portion further includes a third fin portion adjacent to the second fin portion, and the second fin portion is located between the first fin portion and the third fin portion; the dummy gate further comprises a third portion of the dummy gate covering the top and the sidewalls of the third fin portion; and in the process of removing part of the dummy gate, removing the third part of the dummy gate or reserving the third part of the dummy gate.
Optionally, the opening exposes a part of the top and a part of the sidewall of the part of the plurality of fins; after forming the opening, and before forming the insulating layer, the method further includes: and removing the fin part higher than the top of the isolation layer to enable the top of the remaining fin part to be flush with the top of the isolation layer.
Optionally, after removing the fin portion higher than the top of the isolation layer and before forming the insulating layer, the method further includes: and removing part of the fin part exposed from the opening to enable the top of the remaining fin part to be lower than the top of the isolation layer.
Optionally, after removing the fin portion higher than the top of the isolation layer and before forming the insulating layer, the method further includes: and removing the fin parts exposed by the opening until the surface of the substrate is exposed.
Optionally, the insulating layer comprises a first insulating layer and a second insulating layer; the first insulating layer covers the bottom and the side wall of the opening; the second insulating layer covers the surface of the first insulating layer, and the top of the second insulating layer is flush with the top of the dielectric layer; the density of the first insulating layer is greater than that of the second insulating layer.
Optionally, the first insulating layer is formed by an atomic layer deposition process.
Optionally, the second insulating layer is formed by a fluid chemical vapor deposition process.
Optionally, the insulating layer is made of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, or silicon oxycarbonitride.
Accordingly, the present invention also provides a semiconductor structure comprising: the device comprises a substrate and at least two fin parts protruding out of the substrate; the isolation layer is positioned on the substrate with the exposed fin part and covers partial side walls of the fin part; the dummy gate is positioned on the isolation layer and transversely spans part of the fin parts, and the dummy gate covers part of the top and part of the side wall of the fin parts; the insulating layer is positioned on the tops of the residual fin parts and is adjacent to the pseudo gate; and the dielectric layer is positioned on the isolation layer and covers the side wall of the insulating layer and the side wall of the pseudo gate.
Optionally, the fin portion includes a first fin portion and a second fin portion adjacent to the first fin portion, the dummy gate crosses the first fin portion, and the insulating layer covers a portion of the top and a portion of the sidewall of the second fin portion.
Optionally, the first grooves are located in the first fin portions on two sides of the dummy gate; the second grooves are positioned in the second fin parts on two sides of the insulating layer; filling stress layers of the first groove and the second groove which are positioned on the same side of the pseudo gate; the dielectric layer covers the surface of the stress layer.
Optionally, the distance between the first fin portion and the second fin portion is 30nm to 40 nm.
Optionally, the insulating layer comprises a first insulating layer and a second insulating layer; the first insulating layer covers the top of the fin part and the side wall of the dielectric layer; the second insulating layer covers the surface of the first insulating layer, and the top of the second insulating layer is flush with the top of the dielectric layer; the density of the first insulating layer is greater than that of the second insulating layer.
Compared with the prior art, the technical scheme of the invention has the following advantages:
in the technical scheme of the semiconductor structure forming method provided by the invention, the top positions of the fin parts covered by the dummy gates can be used for forming the channel regions, and the number of the positions for forming the channel regions is multiple because the number of the fin parts is at least two. And removing part of the dummy gate, exposing part of the tops of part of the fin parts, forming an opening penetrating the thickness of the dielectric layer in the dielectric layer, and forming an insulating layer filling the opening, wherein the insulating layer can prevent the channel region on the top surface of the fin part covered by the insulating layer from being opened, so that the number of the channel regions of the semiconductor structure meets the requirement, and the process for forming the semiconductor structure with a specific number of the channel regions is facilitated to be simplified.
In an alternative scheme, the distance between the first fin portion and the second fin portion is 30 nm-40 nm, and the distance between the first fin portion and the second fin portion is proper, so that on one hand, a stress layer filled in the first groove and the second groove which are located on the same side of the dummy gate is favorably formed, and further the contact area between the stress layer and a subsequently formed conductive plug is favorably increased, and therefore the contact resistance between the stress layer and the conductive plug can be reduced; on the other hand, in the subsequent process of removing the second part of the dummy gate and the second fin part with partial thickness, the first fin part can be prevented from being etched.
In an alternative, after forming the opening and before forming the insulating layer, the forming method further includes: and removing the fin part higher than the top of the isolation layer to enable the top of the remaining fin part to be flush with the top of the isolation layer. And forming an insulating layer filled in the opening subsequently, wherein the removal of the fin part higher than the top of the insulating layer is beneficial to improving the volume of the insulating layer material, and is further beneficial to improving the electrical insulating property between the insulating layer and the top of the residual fin part, so that the probability of electric leakage at the top of the residual fin part can be reduced.
Drawings
Fig. 1 to 13 are schematic structural diagrams corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention.
Detailed Description
As is apparent from the background art, the process for forming the semiconductor structure in the prior art still needs to be improved.
The reason for this analysis is: when a plurality of semiconductor structures are formed and the number of channel regions of the plurality of semiconductor structures is different, the process methods for forming the plurality of semiconductor structures are independent from each other, and each semiconductor structure is formed from the same initial state, so that the process is complicated and the process time is long.
In order to solve the above problems, the present invention provides a method for forming a semiconductor structure, including: the number of the fin parts is at least two, an isolation layer is arranged on the substrate exposed out of the fin parts, and a pseudo gate crossing the fin parts is arranged on the isolation layer; forming a dielectric layer on the isolation layer, wherein the dielectric layer covers the side wall of the pseudo gate; removing part of the dummy gate, exposing part of the tops of part of the fin parts, and forming an opening penetrating the thickness of the dielectric layer in the dielectric layer; and forming an insulating layer filling the opening.
Wherein, the number of positions for forming the channel region is multiple because the number of the fin parts is at least two. By removing part of the dummy gate, exposing part of the tops of part of the fins and forming the insulating layer filled in the opening, the purpose of preventing the opening of the position where the channel region can be formed by part of the fins is achieved, the number of the formed channel regions meets the requirement, and therefore the process steps of forming the semiconductor structure with the specific number of the channel regions can be simplified.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 1 to 13 are schematic structural diagrams illustrating a semiconductor structure forming process according to an embodiment of the invention.
Most of the transistors of a Static Random Access Memory (SRAM) are fin field effect transistors, and in this embodiment, the formed semiconductor structure is used for manufacturing the SRAM. In other embodiments, the formed semiconductor structure may be used to fabricate other devices.
Referring to fig. 1 to fig. 3, fig. 1 is a schematic structural diagram of a corresponding stage in a process of forming an SRAM structure, fig. 2 is a schematic structural diagram of a cross section of the SRAM structure shown in fig. 1 along a direction A1a2, and fig. 3 is a schematic structural diagram of a cross section of the SRAM structure shown in fig. 1 along a direction B1B 2.
Providing a substrate 200 (as shown in fig. 2) and at least two fin portions protruding from the substrate 200, where the number of the fin portions is at least two, an isolation layer 230 is arranged on the substrate 200 where the fin portions are exposed, the isolation layer 230 covers partial sidewalls of the fin portions, a dummy gate crossing the fin portions is arranged on the isolation layer 230, a dielectric layer 240 is formed on the isolation layer 230 by the dummy gate, and the dielectric layer 240 covers sidewalls of the dummy gate.
The substrate 200 has two sets of component regions thereon, each set of component regions including a pull-up region 101, a pull-down region 102, and a transfer gate region 103. The pull-up region 101 is used for forming a pull-up transistor, the pull-down region 102 is used for forming a pull-down transistor, and the transfer gate region 103 is used for forming a transfer gate transistor.
The dummy gates are arranged on the top and the side walls of part of the fins, and the part of the fins are fin structures. In this embodiment, the ratio of the number of fin structures included in the pull-up region 101, the pull-down region 102, and the transfer gate region 103 is 1:2: 2.
In this embodiment, the pull-up region 101 includes a fin structure and a dummy gate corresponding to the fin structure; the pull-down region 102 includes two fin structures and dummy gates corresponding to the two fin structures; the transfer gate region 103 includes two fin structures and dummy gates corresponding to the two fin structures.
The fin structures are located at positions where channel regions can be formed, and in the embodiment, the number of the fin structures is multiple, so that the number of the positions where channel regions can be formed is multiple.
In this embodiment, the fin portion includes a first fin portion 210 and a second fin portion 220 adjacent to the first fin portion 210. The first fin portion 210 and the second fin portion 220 are used for forming the transfer gate region 103 and the pull-down region 102.
In this embodiment, the fin portion further includes a pull-up fin portion 230 adjacent to the second fin portion 220, and the second fin portion 220 is located between the first fin portion 210 and the pull-up fin portion 230. The pull-up fin 230 is used to form the pull-up region 101.
In this embodiment, the fin portion is made of silicon. In other embodiments, the material of the fin portion may also be germanium, silicon carbide, gallium arsenide, or indium gallium arsenide.
In this embodiment, the dummy gates include a first dummy gate 310 and a second dummy gate 320, and the first dummy gate 310 crosses over the first fin 210 and the second fin 220 to form the transfer gate region 103; the second dummy gate 320 spans over the first fin 210 and the second fin 220 to form the pull-down region 102; in addition, the second dummy gate 320 also crosses over the pull-up fin 230, thereby forming the pull-up region 101.
In this embodiment, the first dummy gate 310 includes a first dummy gate portion 311 covering a top and sidewalls of the first fin 210 and a second dummy gate portion 312 covering a top and sidewalls of the second fin 220.
In this embodiment, the dummy gate is made of amorphous silicon. In other embodiments, the material of the dummy gate may also be polysilicon or amorphous carbon.
In this embodiment, an oxide layer 330 (refer to fig. 2 or fig. 3) is disposed between the dummy gate and the fin portion, the oxide layer 330 covers a portion of the top and a portion of the sidewall of the fin portion, and the dummy gate covers a surface of the oxide layer 330.
In this embodiment, the substrate 200 is made of silicon. In other embodiments, the material of the substrate may also be germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, and in addition, the substrate can also be a silicon-on-insulator substrate or a germanium-on-insulator substrate.
The isolation layer 230 is made of silicon oxide, silicon nitride or silicon oxynitride. In this embodiment, the isolation layer 230 is made of silicon oxynitride.
In this embodiment, the dielectric layer 240 is made of silicon oxide. In other embodiments, the material of the dielectric layer may also be silicon nitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride, or boron carbonitride.
In this embodiment, before forming the dielectric layer, the method further includes: forming first grooves (not shown) in the first fin portions 210 on two sides of the first dummy gate 310; forming second grooves (not shown) in the second fins 220 on both sides of the first dummy gate 310; and forming a stress layer 250 filling the first groove and the second groove on the same side of the first dummy gate 310.
In this embodiment, the stress layer 250 is formed by a selective epitaxial growth process.
In this embodiment, the stress layer 250 includes a first stress layer located in the first groove and a second stress layer located in the second groove; and the top of the first stress layer is higher than the top of the first fin 210, and the top of the second stress layer is higher than the top of the second fin 220.
In the process of forming the stress layer 250, since the distance between the first fin 210 and the second fin 220 is small, the first stress layer and the second stress layer grow together at a spatial position higher than the top of the first fin 210 and the top of the second fin 220, so as to form the stress layer 250.
And forming a conductive plug at the top of the stress layer 250, and forming the stress layer 250 filling the first groove and the second groove on the same side of the first dummy gate 310, which is helpful for increasing the contact area between the conductive plug and the stress layer 250, so that the contact resistance between the conductive plug and the stress layer 250 can be reduced.
If the distance between the first fin portion 210 and the second fin portion 220 is too large, the first stress layer and the second stress layer are formed separately, and then a conductive plug is formed on the top of the first stress layer and the top of the second stress layer, so that the contact area between the conductive plug and the first stress layer and the contact area between the conductive plug and the second stress layer are small, and the contact resistance is large. If the distance between the first fin portion 210 and the second fin portion 220 is too small, the first fin portion 210 is easily etched in the subsequent process of removing the dummy gate second portion 312 and the second fin portion 220 with a partial thickness. In this embodiment, the distance between the first fin portion 210 and the second fin portion 220 is 30nm to 40 nm.
In other embodiments, the ratio of the number of fin structures included in the pull-up region, the pull-down region and the transfer gate region may also be 1:3: 3. Taking the pull-down region including three fin structures as an example for description, specifically, the pull-up region includes one fin structure and a dummy gate corresponding to the fin structure; the pull-down region comprises three fin structures and pseudo gates corresponding to the two fin structures; the transmission gate region comprises three fin structures and dummy gates corresponding to the two fin structures.
And a third fin part is arranged between the second fin part and the pull-up fin part, the third fin part is adjacent to the second fin part, and the second fin part is positioned between the first fin part and the third fin part.
The first dummy gate crosses the first fin portion, the second fin portion and the third fin portion to form the transmission gate region; the first dummy gate comprises a first portion of the dummy gate and a second portion of the dummy gate, and further comprises a third portion of the dummy gate covering the top and the side wall of the third fin portion. The second dummy gate crosses the first fin portion, the second fin portion and the third fin portion to form the pull-down region; in addition, the second dummy gate also spans across the pull-up fin portion, thereby forming the pull-up region.
Referring to fig. 4 to 5, fig. 4 is a schematic cross-sectional view along a direction A1a2 (refer to fig. 1), and fig. 3 is a schematic cross-sectional view along a direction B1B2 (refer to fig. 1). And removing part of the dummy gate to expose part of the tops of part of the fins, and forming an opening 410 penetrating through the thickness of the dielectric layer 240 in the dielectric layer 240.
In this embodiment, the dummy gate second portion 312 (refer to fig. 2 or fig. 3) is removed, an opening 410 penetrating the thickness of the dielectric layer 240 is formed in the dielectric layer 240, and the opening 410 exposes a portion of the top and a portion of the sidewall of the second fin 220.
In this embodiment, the process of removing the dummy gate second portion 312 and forming the opening 410 includes: forming a photoresist layer 400 covering the top of the dummy gate first portion 311 and the top of the second dummy gate 320, wherein the photoresist layer 400 exposes the top of the dummy gate second portion 312; removing the dummy gate second portion 312 by using the photoresist layer 400 as a mask to expose the oxide layer 330 covering the top and sidewall surfaces of the second fin portion 220; the exposed oxide layer 330 is removed to form the opening 410.
In this embodiment, after the opening 410 is formed, the photoresist layer 400 is remained. The photoresist layer 400 is used as a mask to remove the exposed portion of the thickness of the second fin portion 220 of the opening 410.
In this embodiment, the opening 410 exposes a portion of the top and a portion of the sidewall of the second fin portion 220, which facilitates the subsequent removal of a portion of the thickness of the second fin portion 220, and helps to prevent the top of the second fin portion 220 from leaking electricity.
In other embodiments, the fin portion further includes a third fin portion adjacent to the second fin portion, and the first dummy gate further includes a third portion of the dummy gate covering a top and sidewalls of the third fin portion. And in the process of removing the second dummy gate, removing the third part of the dummy gate or reserving the third part of the dummy gate.
Referring to fig. 6 to 7, fig. 6 is a schematic cross-sectional structure along a direction A1a2 (refer to fig. 1), and fig. 7 is a schematic cross-sectional structure along a direction B1B2 (refer to fig. 1). The fin portion higher than the top of the isolation layer 230 is removed, so that the top of the remaining fin portion is flush with the top of the isolation layer 230.
In this embodiment, the photoresist layer 400 is used as a mask to remove a portion of the thickness of the second fin 220 exposed by the opening 410, so that the top of the remaining second fin 220 is flush with the top of the isolation layer 230.
In this embodiment, a wet isotropic etching process is used to remove a portion of the thickness of the second fin portion 220 exposed by the opening 410. And after the wet isotropic etching process is finished, removing the photoresist layer 400.
An insulating layer filled in the opening 410 is formed subsequently, and the second fin portion 220 exposed from the opening 410 and higher than the top of the isolation layer 230 is removed, so that the volume of the opening 410 is increased, a larger space is provided for the insulating layer, the electrical insulation between the insulating layer and the second fin portion 220 is improved, and the probability of electric leakage at the top of the second fin portion 220 can be reduced.
In other embodiments, after removing the fin portion higher than the top of the isolation layer, the method further includes: and removing part of the fin part exposed from the opening to enable the top of the remaining fin part to be lower than the top of the isolation layer. The top of the remaining fin portion is lower than the top of the isolation layer, so that the volume of the opening is further increased, the volume of an insulation layer material formed subsequently can be increased, and the electrical insulation performance between the insulation layer and the second fin portion is further improved.
In addition, in order to completely avoid electric leakage at the top of the fin portion covered by the subsequent insulating layer, in another other embodiment, after the fin portion higher than the top of the isolation layer is removed, the fin portion exposed by the opening is removed until the surface of the substrate is exposed.
It should be noted that, in another embodiment, after a portion of the dummy gate is removed and the opening is formed, a subsequent process of forming an insulating layer is directly performed, that is, the top and the sidewalls of the fin portion exposed by the opening are remained.
Referring to fig. 8 to 9, fig. 8 is a schematic cross-sectional structure along a direction A1a2 (refer to fig. 1), and fig. 9 is a schematic cross-sectional structure along a direction B1B2 (refer to fig. 1). An insulating layer 500 filling the opening 410 (refer to fig. 6 or fig. 7) is formed.
The insulating layer 500 serves to electrically insulate a portion of the positions where the number of the positions can be used for forming the channel regions, and then a voltage is applied to the formed semiconductor structure, so that the channel regions on the top surfaces of the fin portions covered by the insulating layer 500 can be prevented from being opened, and then gates are formed at the positions where the remaining number of the positions can be used for forming the channel regions, so that the semiconductor structure with the number of the channel regions meeting the requirement is obtained.
In this embodiment, the insulating layer 500 includes a first insulating layer 510 and a second insulating layer 520; the first insulating layer 510 covers the bottom and sidewalls of the opening 410 (refer to fig. 6); the second insulating layer 520 covers the surface of the first insulating layer 510, and the top of the second insulating layer 520 is flush with the top of the dielectric layer 240; the density of the first insulating layer 510 is greater than the density of the second insulating layer 520.
Since the density of the first insulating layer 510 is greater than that of the second insulating layer 520, the first insulating layer 510 can enhance the bonding capability between the second insulating layer 520 and the fin portion, which is helpful for improving the interface characteristic between the insulating layer 500 and the fin portion and improving the insulating performance of the insulating layer 500.
In this embodiment, the insulating layer 500 is made of silicon oxide, that is, the first insulating layer 510 and the second insulating layer 520 are made of silicon oxide. In other embodiments, the material of the insulating layer may also be silicon nitride, silicon oxynitride, silicon oxycarbide, or silicon oxycarbonitride.
In this embodiment, the first insulating layer 510 is formed by an atomic layer deposition process. The atomic layer deposition process forms the first insulating layer 510 with good step coverage at the bottom corner of the opening 410 (refer to fig. 6), which helps to improve compactness of the first insulating layer 510.
If the thickness of the first insulating layer 510 is too small, the effect of the first insulating layer 510 on enhancing the bonding capability between the second insulating layer 520 and the fin portion is affected, resulting in poor interface characteristics between the insulating layer 500 and the fin portion; if the thickness of the first insulating layer 510 is too large, the process time for forming the first insulating layer 510 is too long, which may unnecessarily extend the process time for forming the semiconductor structure. In this embodiment, the thickness of the first insulating layer 510 is 3nm to 8 nm.
In this embodiment, the second insulating layer 520 is formed by a fluid chemical vapor deposition process. In other embodiments, the second insulating layer may also be formed using a high aspect ratio chemical vapor deposition process (HARP).
Referring to fig. 10 and 11, fig. 10 is a schematic cross-sectional view along a direction A1a2 (refer to fig. 1), and fig. 11 is a schematic cross-sectional view along a direction B1B2 (refer to fig. 1). And removing the dummy gate first part 311, and forming a through hole 610 penetrating through the thickness of the dielectric layer 240 in the dielectric layer 240.
The vias 610 provide spatial locations for subsequently formed gates.
In this embodiment, in the process of removing the dummy gate first portion 311, the method further includes: the second dummy gate 320 is removed.
The process method for removing the dummy gate first portion 311 and the second dummy gate 320 and forming the via 610 includes: forming a mask layer (not shown) covering the top of the insulating layer 500, wherein the mask layer exposes the top of the dummy gate first portion 311 and the top of the second dummy gate 320; removing the dummy gate first portion 311 and the second dummy gate 320 by using the mask layer as a mask to expose the oxide layer 330 covering the surfaces of the first fin portion 210 and the second fin portion 220; and removing the exposed oxide layer 330 to form the through hole 610.
In this embodiment, the first dummy gate portion 311 and the second dummy gate 320 are removed by a wet isotropic etching process.
In other implementations, after removing the first portion of the dummy gate and the second dummy gate, the exposed oxide layer is retained as a gate oxide layer of a subsequently formed semiconductor structure.
Referring to fig. 12 and 13, fig. 12 is a schematic cross-sectional view along a direction A1a2 (refer to fig. 1), and fig. 13 is a schematic cross-sectional view along a direction B1B2 (refer to fig. 1). A gate 700 filling the via 610 (refer to fig. 10 or 11) is formed.
The gate 700 covers the top of the remaining number of locations available for forming channel regions, and a voltage is subsequently applied to the formed semiconductor structure, and channels are present on the top surface of the fin covered by the gate 700, so that the number of channel regions meets the requirements.
In this embodiment, before forming the gate 700, the method further includes: forming an interface layer 620 at the bottom of the via 610; forming a high-k gate dielectric layer 630 on the top of the interfacial layer 620 and the sidewall of the through hole 610; and forming a work function layer 640 covering the surface of the high-k gate dielectric layer 630, wherein the top of the work function layer 640 is lower than the top of the dielectric layer 240. A gate 700 filling the through hole 610 is formed on the surface of the work function layer 640.
The interfacial layer 620 may improve the interfacial basis of the high-k gate dielectric layer 630, thereby improving the bonding ability of the high-k gate dielectric layer 630 to the fin.
In this embodiment, the interface layer 620 is made of silicon oxide. In other embodiments, the material of the interface layer 620 may also be germanium oxide or silicon germanium containing oxygen.
In this embodiment, the interfacial layer 620 is formed by a chemical oxidation method. In other embodiments, the interfacial layer may also be formed using a thermal oxidation process or an atomic layer deposition process.
In this embodiment, the material of the high-k gate dielectric layer 630 is HfO2(ii) a In other embodiments, the material of the high-k gate dielectric layer may also be HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, or ZrO2。
The work function layer 640 includes a P-type work function layer (not shown) and an N-type work function layer (not shown) for adjusting a threshold voltage of a subsequently formed semiconductor structure.
In this embodiment, the P-type work function layer is made of TiN. In other embodiments, the material of the P-type work function layer may also be TaN, TiSiN, or TaSiN.
In this embodiment, the material of the N-type work function layer is TiAl; in other embodiments, the material of the N-type work function layer may also be TaAl, TiAlC, AlN, TiAlN, or TaAlN.
The gate 700 is made of Cu, W, Al or Ag. In this embodiment, the gate 700 is made of Cu.
In this embodiment, after the gate 700 is formed, the pull-up region 101 includes a fin structure and the gate 700 corresponding to the fin structure; the pull-down region 102 includes two fin structures and gates 700 corresponding to the two fin structures; the transfer gate region 103 includes one fin structure and the gate 700 corresponding to the two fin structures.
In the substrate 200 provided above, the transfer gate region 103 includes two fin structures, and this embodiment realizes that the SRAM structure in which the transfer gate region 103 includes one fin structure is formed on the basis that the transfer gate region 103 includes two fin structures, which is helpful to simplify the formation process and shorten the process time.
In other embodiments, the above-mentioned provided substrate has a transfer gate region including three fin structures, and an SRAM structure having a transfer gate region including one or two fin structures may be formed on the basis that the transfer gate region includes three fin structures.
In summary, the top positions of the fins covered by the dummy gate may be used for forming the channel region, and since the number of the fins is at least two, there are a plurality of positions that can be used for forming the channel region. Removing part of the dummy gate, exposing part of the tops of part of the number of fin portions, forming an opening 410 penetrating the thickness of the dielectric layer 240 in the dielectric layer 240, and forming an insulating layer 500 filling the opening 410, wherein the insulating layer 500 can prevent the channel region on the top surface of the fin portion covered by the insulating layer 500 from being opened, and then forming a gate at the position where the rest number of fin portions can be used for forming the channel region, so that the number of the channel regions of the semiconductor structure meets the requirement.
Referring to fig. 8, the present invention also provides a semiconductor structure obtained by the above forming method, the semiconductor structure including: the structure comprises a substrate 200 and at least two fin parts protruding out of the substrate 200; an isolation layer 230 on the substrate 200 with the exposed fin, wherein the isolation layer 230 covers a part of the sidewall of the fin; a dummy gate 311 located on the isolation layer 230 and crossing a part of the number of fins, wherein the dummy gate 311 covers a part of the top and a part of the sidewall of the number of fins; an insulating layer 500 on top of the remaining number of fin portions, the insulating layer 500 being adjacent to the dummy gate 311; a dielectric layer 240 on the isolation layer 230, wherein the dielectric layer 240 covers sidewalls of the insulating layer 500 and sidewalls of the dummy gate 311.
In this embodiment, the fin portion includes a first fin portion 210 and a second fin portion 220 adjacent to the first fin portion 210, the dummy gate 311 crosses over the first fin portion 210, and the insulating layer 500 covers a portion of the top and a portion of the sidewall of the second fin portion 220.
In this embodiment, the distance between the first fin portion 210 and the second fin portion 220 is 30nm to 40 nm.
In this embodiment, the first grooves (not shown) in the first fin portions 210 on both sides of the dummy gate 311; second recesses in the second fin portions 220 at both sides of the insulating layer 500; filling stress layers of a first groove and a second groove which are positioned on the same side of the dummy gate 311; the dielectric layer 240 covers the surface of the stress layer.
In this embodiment, the insulating layer 500 includes a first insulating layer 510 and a second insulating layer 520; the first insulating layer 510 covers the top of the second fin portion 220 and the sidewalls of the dielectric layer 240; the second insulating layer 520 covers the surface of the first insulating layer 510, and the top of the second insulating layer 520 is flush with the top of the dielectric layer 240; the density of the first insulating layer 510 is greater than the density of the second insulating layer 520.
The insulating layer 500 serves to electrically insulate a portion of the number of locations where channel regions may be formed, thereby preventing the channel regions on the top surface of the second fin 220 covered by the insulating layer 500 from being opened.
Since the density of the first insulating layer 510 is greater than that of the second insulating layer 520, the first insulating layer 510 can enhance the bonding capability between the second insulating layer 520 and the fin portion, which is helpful for improving the interface characteristic between the insulating layer 500 and the fin portion and improving the insulating performance of the insulating layer 500.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims (19)

1. A method for forming a semiconductor structure, comprising:
providing a substrate and at least two fin parts protruding out of the substrate, wherein an isolation layer is arranged on the substrate exposed out of the fin parts, the isolation layer covers partial side walls of the fin parts, a pseudo gate crossing the fin parts is arranged on the isolation layer, and the pseudo gate covers partial top and partial side walls of the fin parts;
forming a dielectric layer on the isolation layer, wherein the dielectric layer covers the side wall of the pseudo gate;
removing part of the dummy gate, exposing part of the tops of part of the fin parts, and forming an opening penetrating the thickness of the dielectric layer in the dielectric layer;
forming an insulating layer filling the opening;
the fin part comprises a first fin part and a second fin part adjacent to the first fin part; the dummy gate comprises a first dummy gate part covering the top and the side wall of the first fin part and a second dummy gate part covering the top and the side wall of the second fin part; and in the step of removing part of the dummy gate, removing the second part of the dummy gate and reserving the first part of the dummy gate.
2. The method for forming a semiconductor structure according to claim 1, wherein the process for removing the second portion of the dummy gate comprises: forming a photoresist layer covering the top of the first part of the dummy gate, wherein the photoresist layer exposes the top of the second part of the dummy gate; removing the second part of the dummy gate by taking the photoresist layer as a mask; and removing the photoresist layer.
3. The method of forming a semiconductor structure of claim 1, wherein prior to forming the dielectric layer, further comprising: forming first grooves in the first fin portions on two sides of the dummy gate; forming second grooves in the second fin portions on two sides of the dummy gate; and forming a stress layer which is filled in the first groove and the second groove which are positioned at two sides of the pseudo gate.
4. The method for forming a semiconductor structure according to claim 3, wherein the stress layer is formed using a selective epitaxial growth process.
5. The method as claimed in claim 1, 3 or 4, wherein the first fin portion and the second fin portion have a pitch of 30nm to 40 nm.
6. The method of forming a semiconductor structure of claim 1, further comprising, after forming the insulating layer: removing the second part of the dummy gate, and forming a through hole penetrating the thickness of the dielectric layer in the dielectric layer; and forming a grid electrode which is filled in the through hole.
7. The method of claim 1, wherein the fin further comprises a third fin adjacent to the second fin, the second fin being between the first fin and the third fin; the dummy gate further comprises a third portion of the dummy gate covering the top and the sidewalls of the third fin portion; and in the process of removing part of the dummy gate, removing the third part of the dummy gate or reserving the third part of the dummy gate.
8. The method of claim 1, wherein the opening exposes a portion of a top and a portion of sidewalls of the portion of the number of fins; after forming the opening, and before forming the insulating layer, the method further includes: and removing the fin part higher than the top of the isolation layer to enable the top of the remaining fin part to be flush with the top of the isolation layer.
9. The method of claim 8, wherein after removing the fin above the top of the isolation layer and before forming the insulating layer, further comprising: and removing part of the fin part exposed from the opening to enable the top of the remaining fin part to be lower than the top of the isolation layer.
10. The method of claim 8, wherein after removing the fin above the top of the isolation layer and before forming the insulating layer, further comprising: and removing the fin parts exposed by the opening until the surface of the substrate is exposed.
11. The method for forming a semiconductor structure according to claim 1, wherein the insulating layer comprises a first insulating layer and a second insulating layer; the first insulating layer covers the bottom and the side wall of the opening; the second insulating layer covers the surface of the first insulating layer, and the top of the second insulating layer is flush with the top of the dielectric layer; the density of the first insulating layer is greater than that of the second insulating layer.
12. The method of forming a semiconductor structure of claim 11, wherein the first insulating layer is formed using an atomic layer deposition process.
13. The method of claim 11, wherein the second insulating layer is formed using a fluid chemical vapor deposition process.
14. The method for forming a semiconductor structure according to claim 1 or 11, wherein a material of the insulating layer is silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, or silicon oxycarbonitride.
15. A semiconductor structure, comprising:
the device comprises a substrate and at least two fin parts protruding out of the substrate;
the isolation layer is positioned on the substrate with the exposed fin part and covers partial side walls of the fin part;
the dummy gate is positioned on the isolation layer and transversely spans part of the fin parts, and the dummy gate covers part of the top and part of the side wall of the fin parts;
the insulating layer is positioned on the tops of the residual fin parts and is adjacent to the pseudo gate;
and the dielectric layer is positioned on the isolation layer and covers the side wall of the insulating layer and the side wall of the pseudo gate.
16. The semiconductor structure of claim 15, wherein the fin comprises a first fin and a second fin adjacent to the first fin, the dummy gate spans the first fin, and the insulating layer covers a portion of a top and a portion of sidewalls of the second fin.
17. The semiconductor structure of claim 16, wherein first recesses in the first fin on both sides of the dummy gate; the second grooves are positioned in the second fin parts on two sides of the insulating layer; filling stress layers of the first groove and the second groove which are positioned at two sides of the pseudo gate; the dielectric layer covers the surface of the stress layer.
18. The semiconductor structure of claim 16 or 17, wherein a pitch of the first fin and the second fin is between 30nm and 40 nm.
19. The semiconductor structure of claim 15, wherein the insulating layer comprises a first insulating layer and a second insulating layer; the first insulating layer covers the top of the fin part and the side wall of the dielectric layer; the second insulating layer covers the surface of the first insulating layer, and the top of the second insulating layer is flush with the top of the dielectric layer; the density of the first insulating layer is greater than that of the second insulating layer.
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