CN110120415A - Semiconductor structure and forming method thereof - Google Patents
Semiconductor structure and forming method thereof Download PDFInfo
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- CN110120415A CN110120415A CN201810138907.2A CN201810138907A CN110120415A CN 110120415 A CN110120415 A CN 110120415A CN 201810138907 A CN201810138907 A CN 201810138907A CN 110120415 A CN110120415 A CN 110120415A
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- 238000000034 method Methods 0.000 title claims abstract description 60
- 239000004065 semiconductor Substances 0.000 title claims abstract description 54
- 238000000926 separation method Methods 0.000 claims abstract description 52
- 239000000758 substrate Substances 0.000 claims abstract description 33
- 230000036961 partial effect Effects 0.000 claims abstract description 29
- 239000000463 material Substances 0.000 claims description 28
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 17
- 229920002120 photoresistant polymer Polymers 0.000 claims description 15
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 10
- 229910052710 silicon Inorganic materials 0.000 claims description 9
- 239000010703 silicon Substances 0.000 claims description 9
- 238000009413 insulation Methods 0.000 claims description 8
- 230000003447 ipsilateral effect Effects 0.000 claims description 8
- 239000000377 silicon dioxide Substances 0.000 claims description 7
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 5
- 238000005137 deposition process Methods 0.000 claims description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 5
- HMDDXIMCDZRSNE-UHFFFAOYSA-N [C].[Si] Chemical compound [C].[Si] HMDDXIMCDZRSNE-UHFFFAOYSA-N 0.000 claims description 4
- 239000012530 fluid Substances 0.000 claims description 3
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 3
- 230000000717 retained effect Effects 0.000 claims description 2
- 238000000280 densification Methods 0.000 claims 2
- 238000007740 vapor deposition Methods 0.000 claims 1
- 230000005540 biological transmission Effects 0.000 description 15
- 238000010586 diagram Methods 0.000 description 15
- 230000015572 biosynthetic process Effects 0.000 description 6
- 230000000694 effects Effects 0.000 description 6
- 230000005611 electricity Effects 0.000 description 4
- 238000002955 isolation Methods 0.000 description 4
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 3
- 238000010292 electrical insulation Methods 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 229910052732 germanium Inorganic materials 0.000 description 3
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- 229910010271 silicon carbide Inorganic materials 0.000 description 3
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 3
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 2
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 2
- MCMNRKCIXSYSNV-UHFFFAOYSA-N Zirconium dioxide Chemical compound O=[Zr]=O MCMNRKCIXSYSNV-UHFFFAOYSA-N 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
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- 229910052733 gallium Inorganic materials 0.000 description 2
- 229910052738 indium Inorganic materials 0.000 description 2
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 2
- 230000002401 inhibitory effect Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 230000003068 static effect Effects 0.000 description 2
- 229910017083 AlN Inorganic materials 0.000 description 1
- 229910052582 BN Inorganic materials 0.000 description 1
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- PZNSFCLAULLKQX-UHFFFAOYSA-N Boron nitride Chemical compound N#B PZNSFCLAULLKQX-UHFFFAOYSA-N 0.000 description 1
- 229910004129 HfSiO Inorganic materials 0.000 description 1
- 229910004490 TaAl Inorganic materials 0.000 description 1
- 229910004491 TaAlN Inorganic materials 0.000 description 1
- 229910004166 TaN Inorganic materials 0.000 description 1
- 229910004200 TaSiN Inorganic materials 0.000 description 1
- 229910010038 TiAl Inorganic materials 0.000 description 1
- 229910010041 TiAlC Inorganic materials 0.000 description 1
- 229910010037 TiAlN Inorganic materials 0.000 description 1
- 229910008482 TiSiN Inorganic materials 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical group [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 229910003481 amorphous carbon Inorganic materials 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- YBMRDBCBODYGJE-UHFFFAOYSA-N germanium oxide Inorganic materials O=[Ge]=O YBMRDBCBODYGJE-UHFFFAOYSA-N 0.000 description 1
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(IV) oxide Inorganic materials O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- QRXWMOHMRWLFEY-UHFFFAOYSA-N isoniazide Chemical compound NNC(=O)C1=CC=NC=C1 QRXWMOHMRWLFEY-UHFFFAOYSA-N 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
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- PVADDRMAFCOOPC-UHFFFAOYSA-N oxogermanium Chemical compound [Ge]=O PVADDRMAFCOOPC-UHFFFAOYSA-N 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
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- 238000004904 shortening Methods 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
Abstract
A kind of semiconductor structure and forming method thereof, forming method includes: the fin for providing substrate and protruding from the substrate, the quantity at least two of the fin, there is separation layer on the substrate that the fin exposes, the separation layer covers the fin partial sidewall, there are the pseudo- grid across the fin, the puppet grid cover the atop part and partial sidewall of the fin on the separation layer；Dielectric layer, the dielectric layer covering pseudo- grid side wall are formed on the separation layer；The part pseudo- grid are removed, the atop part of exposed portion quantity fin forms the opening for running through the thickness of dielectric layers in the dielectric layer；Form the insulating layer for filling the full opening.The present invention can form channel region quantity satisfactory semiconductor structure on the basis of multiple positions for forming channel region, so as to simplify the technical process for the semiconductor structure for forming certain amount of channel region.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors more particularly to a kind of semiconductor structure and forming method thereof.
Background technique
In semiconductor fabrication, as integrated circuit feature size persistently reduces, the channel length of MOSFET also it is corresponding not
It is disconnected to shorten.However, the distance between device source electrode and drain electrode also shorten therewith with the shortening of device channel length, lead to grid
It is extremely deteriorated to the control ability of channel, short-channel effect (SCE:short-channel effects) is easier to occur.
Fin formula field effect transistor (FinFET) has performance outstanding, the grid of FinFET in terms of inhibiting short-channel effect
Best can control fin from two sides less, thus compared with planar MOSFET, control of the grid of FinFET to channel
Ability is stronger, can be good at inhibiting short-channel effect.
But the process for forming semiconductor structure in the prior art is still to be improved.
Summary of the invention
Problems solved by the invention is to provide a kind of semiconductor structure and forming method thereof, can form channel multiple
The satisfactory semiconductor structure of channel region quantity is formed on the basis of the position in area, forms certain amount of ditch so as to simplification
The process of the semiconductor structure in road area.
To solve the above problems, the present invention provides a kind of method for forming semiconductor structure, comprising: provide substrate and protrude from
The fin of the substrate, the quantity at least two of the fin have separation layer, institute on the substrate that the fin exposes
It states separation layer and covers the fin partial sidewall, there is the pseudo- grid across the fin, the puppet grid covering on the separation layer
The atop part and partial sidewall of the fin；Dielectric layer, the dielectric layer covering pseudo- grid are formed on the separation layer
Side wall；The part pseudo- grid are removed, the atop part of exposed portion quantity fin is formed in the dielectric layer through described
The opening of thickness of dielectric layers；Form the insulating layer for filling the full opening.
Optionally, the fin includes the first fin and second fin adjacent with first fin；The puppet grid packet
Include the Wei Shan first part for covering the first fin atop part and side wall and covering the second fin atop part and side
The pseudo- grid second part of wall；In the step of removing the part pseudo- grid, the pseudo- grid second part is removed, the pseudo- grid are retained
First part.
Optionally, the process for removing the pseudo- grid second part includes: to form the covering Wei Shan first part top
The photoresist layer in portion, the photoresist layer expose at the top of the pseudo- grid second part；Using the photoresist layer as exposure mask, institute is removed
State pseudo- grid second part；Remove the photoresist layer.
Optionally, before forming the dielectric layer, further includes: form first in first fin of the pseudo- grid two sides
Groove；The second groove is formed in second fin of the pseudo- grid two sides；It is completely ipsilateral positioned at the pseudo- grid to form filling
The stressor layers of first groove and the second groove.
Optionally, the stressor layers are formed using selective epitaxial growth process.
Optionally, the spacing of first fin and the second fin is 30nm~40nm.
Optionally, after forming the insulating layer, further includes: the removal pseudo- grid second part, the shape in the dielectric layer
At the through-hole for running through the thickness of dielectric layers；Form the grid for filling the full through-hole.
Optionally, the fin further includes the third fin adjacent with second fin, and second fin is located at institute
It states between the first fin and the third fin；The puppet grid further include the puppet for covering the third fin atop part and side wall
Grid Part III；In removal part during the pseudo- grid, removes the pseudo- grid Part III or retain the puppet grid third
Part.
Optionally, the opening exposes the atop part and partial sidewall of the partial amt fin；It is opened described in formation
After mouthful, and before forming the insulating layer, further includes: removal is higher than the fin at the top of the separation layer, makes described in residue
It is flushed at the top of fin at the top of the separation layer.
Optionally, it after removal is higher than the fin at the top of the separation layer, and before forming the insulating layer, also wraps
Include: the fin for the exposing that is open described in removal segment thickness makes at the top of the remaining fin lower than the separation layer top.
Optionally, it after removal is higher than the fin at the top of the separation layer, and before forming the insulating layer, also wraps
Include: the fin that the removal opening is exposed is until expose the substrate surface.
Optionally, the insulating layer includes the first insulating layer and second insulating layer；It is opened described in the first insulating layer covering
Mouth bottom and side wall；The second insulating layer covers first surface of insulating layer, and second insulating layer top and institute
It states and is flushed at the top of dielectric layer；The consistency of first insulating layer is greater than the consistency of the second insulating layer.
Optionally, first insulating layer is formed using atom layer deposition process.
Optionally, the second insulating layer is formed using fluid chemistry gas-phase deposition.
Optionally, the material of the insulating layer is silica, silicon nitride, silicon oxynitride, silicon oxide carbide or carbon silicon oxynitride.
Correspondingly, the present invention also provides a kind of semiconductor structures, comprising: substrate and the fin for protruding from the substrate, institute
State the quantity at least two of fin；Separation layer on the substrate that the fin exposes, the separation layer cover institute
State fin partial sidewall；Across the pseudo- grid of partial amt fin on the separation layer, the puppet grid cover the part
The atop part and partial sidewall of quantity fin；Insulating layer on fin atop part described in volume residual, it is described exhausted
Edge layer and the pseudo- grid are adjacent；Dielectric layer on the separation layer, the dielectric layer cover the insulating layer sidewalls and
The puppet grid side wall.
Optionally, the fin includes the first fin and second fin adjacent with first fin, and the puppet grid are horizontal
Across first fin, the insulating layer covers the second fin atop part and partial sidewall.
Optionally, the first groove in first fin of the pseudo- grid two sides；Positioned at the insulating layer two sides
Second fin in the second groove；Filling is completely located at the stress of ipsilateral the first groove and the second groove of the pseudo- grid
Layer；The dielectric layer covers the stress layer surface.
Optionally, the spacing of first fin and the second fin is 30nm~40nm.
Optionally, the insulating layer includes the first insulating layer and second insulating layer；First insulating layer covers the fin
Portion top and the dielectric layer side wall；The second insulating layer covers first surface of insulating layer, and the second insulating layer
It is flushed at the top of top and the dielectric layer；The consistency of first insulating layer is greater than the consistency of the second insulating layer.
Compared with prior art, technical solution of the present invention has the advantage that
In the technical solution of method for forming semiconductor structure provided by the invention, the fin top position of pseudo- grid covering is available
In forming channel region, due to the quantity at least two of the fin, thus the position of channel region can be used to form with multiple.
The part pseudo- grid are removed, the atop part of exposed portion quantity fin forms in the dielectric layer and runs through the medium
The opening of thickness degree, and the insulating layer for filling the full opening is formed, the insulating layer can be avoided to be covered by the insulating layer
Fin top surface channel region open, so that the quantity of the channel region of semiconductor structure be made to meet demand, help to simplify
Form the technical process of the semiconductor structure of certain amount of channel region.
In optinal plan, the spacing of first fin and the second fin is 30nm~40nm, first fin and the
The spacing of two fins is appropriate, on the one hand, contributes to form filling and is completely located at ipsilateral the first groove and the second groove of the pseudo- grid
Stressor layers, and then be conducive to increase the contact area of the stressor layers with the conductive plunger being subsequently formed, so as to reduce
Contact resistance between the stressor layers and conductive plunger；On the other hand, in the pseudo- grid second part of subsequent removal and segment thickness the
During two fins, it can be avoided first fin and etched.
In optinal plan, after forming the opening, and before forming the insulating layer, the forming method further include: go
Except the fin being higher than at the top of the separation layer, make to flush at the top of the remaining fin with the separation layer top.Subsequent shape
At the insulating layer for filling the full opening, the fin that removal is higher than at the top of separation layer helps to improve the body of the insulating layer material
Product, and then the electrical insulation capability between the insulating layer and the remaining fin top is helped to improve, so as to reduce residue
The probability to leak electricity at the top of the fin.
Detailed description of the invention
Fig. 1 to Figure 13 is the corresponding structural schematic diagram of each step in one embodiment of method for forming semiconductor structure of the present invention.
Specific embodiment
It can be seen from background technology that the process for forming semiconductor structure in the prior art is still to be improved.
It analyzes its reason to be: when forming multiple semiconductor structures, and the channel region quantity of the multiple semiconductor structure
When with difference, the process for forming the multiple semiconductor structure is mutually indepedent, forms each semiconductor structure from phase
Same original state starts, and causes technical process cumbersome, the process time is long.
To solve the above-mentioned problems, the present invention provides a kind of method for forming semiconductor structure, comprising: the quantity of fin is at least
It is two, there is separation layer on the substrate that the fin exposes, there are the pseudo- grid across the fin on the separation layer；Institute
It states and forms dielectric layer on separation layer, the dielectric layer covering pseudo- grid side wall；Remove the part pseudo- grid, exposed portion quantity
The atop part of a fin forms the opening for running through the thickness of dielectric layers in the dielectric layer；It is formed and is opened described in filling completely
The insulating layer of mouth.
Wherein, due to the quantity at least two of the fin, thus the quantity that can be used to form the position of channel region is
It is multiple.By the removal part pseudo- grid, the atop part of exposed portion quantity fin, and form the insulation of filling full gate mouth
Layer realizes the purpose that the position for preventing partial amt that from can forming channel region is opened, the quantity for the channel region to be formed is made to meet demand,
So as to simplify the processing step for the semiconductor structure for forming certain amount of channel region.
To make the above purposes, features and advantages of the invention more obvious and understandable, with reference to the accompanying drawing to the present invention
Specific embodiment be described in detail.
Fig. 1 to Figure 13 is the structural schematic diagram that the semiconductor structure that one embodiment of the invention provides forms process.
The transistor of static random access memory (Static Random Access Memory, SRAM) is mostly fin
Field effect transistor, in the present embodiment, the semiconductor structure of formation is for making SRAM.In other embodiments, the half of formation
Conductor structure can also be used for making other devices.
Referring to figs. 1 to Fig. 3, wherein Fig. 1 is the structural schematic diagram of SRAM structure-forming process respective stage, Fig. 2 Fig. 1
Shown in SRAM structure along the direction A1A2 the schematic diagram of the section structure, Fig. 3 be SRAM structure cuing open along the direction B1B2 shown in FIG. 1
Face structural schematic diagram.
Substrate 200 (as shown in Figure 2) is provided and protrudes from the fin of the substrate 200, the quantity of the fin is at least
Two, there is separation layer 230 on the substrate 200 that the fin exposes, the separation layer 230 covers fin part side
Wall, has the pseudo- grid across the fin on the separation layer 230, and the puppet grid form dielectric layer on the separation layer 230
240, the dielectric layer 240 covers the pseudo- grid side wall.
There are two group parts regions, every group parts region includes pull-up region 101, drop-down area 102 on the substrate 200
And transmission area of grid 103.Wherein, the pull-up region 101, which is used to form, pulls up transistor, and the drop-down area 102 is used for
Pull-down transistor is formed, the transmission area of grid 103 is used to form transmission gridistor.
There are the pseudo- grid, the part fin is fin structure at the top of the fin of part and on side wall.The present embodiment
In, the ratio for the fin structure quantity that the pull-up region 101, the drop-down area 102 and the transmission area of grid 103 include
Example is 1:2:2.
In the present embodiment, the pull-up region 101 includes a fin structure and the corresponding pseudo- grid of the fin structure；Institute
Stating drop-down area 102 includes two fin structures and the corresponding pseudo- grid of described two fin structures；The transmission area of grid 103
Including the corresponding pseudo- grid of two fin structures and described two fin structures.
It is the position that can be used to form channel region at the fin structure position, in the present embodiment, the fin structure
Quantity is multiple, thus the quantity that can be used to form the position of channel region is multiple.
In the present embodiment, the fin includes the first fin 210 and second fin adjacent with first fin 210
220.First fin 210 and the second fin 220 are used to form the transmission area of grid 103 and the drop-down area 102.
In the present embodiment, the fin further includes the pull-up fin 230 adjacent with second fin 220, and described second
Fin 220 is between first fin 210 and the pull-up fin 230.The pull-up fin 230 is used to form on described
Draw region 101.
In the present embodiment, the material of the fin is silicon.In other embodiments, the material of the fin can also be
Germanium, SiGe, silicon carbide, GaAs or gallium indium.
In the present embodiment, the puppet grid include the first pseudo- grid 310 and the second pseudo- grid 320, and the described first pseudo- grid 310 are across institute
The first fin 210 and the second fin 220 are stated, to form the transmission area of grid 103；Described second pseudo- grid 320 are across described
First fin 210 and the second fin 220, to form the drop-down area 102；In addition, the described second pseudo- grid 320 are also across described
Fin 230 is pulled up, to form the pull-up region 101.
In the present embodiment, the described first pseudo- grid 310 include the pseudo- grid for covering 210 atop part of the first fin and side wall
The pseudo- grid second part 312 of first part 311 and covering 220 atop part of the second fin and side wall.
In the present embodiment, the material of the puppet grid is amorphous silicon.In other embodiments, the material of the pseudo- grid can be with
For polysilicon or amorphous carbon.
There is oxide layer 330 (referring to Fig. 2 or Fig. 3), the oxide layer in the present embodiment, between the puppet grid and the fin
The atop part and partial sidewall of the 330 covering fins, the puppet grid cover 330 surface of oxide layer.
In the present embodiment, 200 material of substrate is silicon.In other embodiments, the material of the substrate can also be
Germanium, SiGe, silicon carbide, GaAs or gallium indium, in addition, the substrate can also be silicon substrate or insulation on insulator
Germanium substrate on body.
The material of the separation layer 230 is silica, silicon nitride or silicon oxynitride.In the present embodiment, the separation layer 230
Material be silicon oxynitride.
In the present embodiment, the material of the dielectric layer 240 is silica.In other embodiments, the material of the dielectric layer
Material can also be silicon nitride, silicon carbide, carbonitride of silicium, carbon silicon oxynitride, silicon oxynitride, boron nitride or boron carbonitrides.
In the present embodiment, before forming the dielectric layer, further includes: first fin in the described first 310 two sides of pseudo- grid
The first groove (not shown) is formed in portion 210；It is formed in second fin 220 of the described first 310 two sides of pseudo- grid
Second groove (not shown)；It forms filling and is completely located at ipsilateral the first groove and the second groove of the described first pseudo- grid 310
Stressor layers 250.
In the present embodiment, the stressor layers 250 are formed using selective epitaxial growth process.
In the present embodiment, the stressor layers 250 include the first stressor layers in first groove and are located at described
The second stressor layers in second groove；And it is higher than 210 top of the first fin, second stress at the top of first stressor layers
Layer top is higher than 220 top of the second fin.
During forming stressor layers 250, due between first fin 210 and second fin 220
Away from small, at the spatial position for being higher than 210 top of the first fin and 220 top of the second fin, first stressor layers with
Second stressor layers are grown together, to form the stressor layers 250.
It is subsequent that conductive plunger is formed at the top of the stressor layers 250, it is completely ipsilateral positioned at the described first pseudo- grid 310 to form filling
The first groove and the second groove stressor layers 250, help to improve the contact surface of the conductive plunger Yu the stressor layers 250
Product, so as to reduce the contact resistance of the conductive plunger and the stressor layers 250.
If the spacing of first fin 210 and the second fin 220 is excessive, discrete first stressor layers and institute are formed
The second stressor layers are stated, it is subsequent to form conductive plunger at the top of first stressor layers and at the top of second stressor layers, it is described to lead
The contact area of electric plug and first stressor layers and second stressor layers is small, causes contact resistance big.If described first
The spacing of fin 210 and the second fin 220 is too small, the described in the subsequent removal pseudo- grid second part 312 and segment thickness
During two fins 220, it is easy that first fin 210 is caused to etch.In the present embodiment, 210 He of the first fin
The spacing of second fin 220 is 30nm~40nm.
In other embodiments, the fin that the pull-up region, the drop-down area and the transmission area of grid include
The ratio of number of structures can also be 1:3:3.It is illustrated, has so that the drop-down area includes three fin structures as an example below
Body, the pull-up region includes a fin structure and the corresponding pseudo- grid of the fin structure；The drop-down area includes three
A fin structure and the corresponding pseudo- grid of described two fin structures；The transmission area of grid includes three fin structures and described
The corresponding pseudo- grid of two fin structures.
Also there is third fin, the third fin and second fin between second fin and the pull-up fin
Portion is adjacent, and second fin is between first fin and the third fin.
Described first pseudo- grid form the transmission area of grid across first fin, the second fin and third fin；
Described first pseudo- grid further include covering the third fin atop part in addition to including Wei Shan first part and pseudo- grid second part
And the pseudo- grid Part III of side wall.The second pseudo- grid are across first fin, the second fin and third fin, described in formation
Drop-down area；In addition, the second pseudo- grid are also across the pull-up fin, to form the pull-up region.
With reference to Fig. 4 to Fig. 5, wherein Fig. 4 is along the schematic diagram of the section structure in A1A2 (referring to Fig. 1) direction, and Fig. 3 is edge
The schematic diagram of the section structure in B1B2 (referring to Fig. 1) direction.Remove the part pseudo- grid, the part top of exposed portion quantity fin
Portion forms the opening 410 for running through 240 thickness of dielectric layer in the dielectric layer 240.
In the present embodiment, the pseudo- grid second part 312 (referring to Fig. 2 or Fig. 3), the shape in the dielectric layer 240 are removed
At the opening 410 for running through 240 thickness of dielectric layer, the opening 410 exposes 220 atop part of the second fin and part
Side wall.
In the present embodiment, removing the pseudo- grid second part 312, forming the process of the opening 410 includes: to be formed
Cover the photoresist layer 400 at 311 top of Wei Shan first part and second pseudo- 320 top of grid, the photoresist layer 400
Expose pseudo- 312 top of grid second part；It is exposure mask with the photoresist layer 400, removes the pseudo- grid second part 312,
Expose the oxide layer 330 for covering 220 atop part of the second fin and sidewall surfaces；The oxide layer 330 exposed is removed,
Form the opening 410.
In the present embodiment, after forming the opening 410, retain the photoresist layer 400.It is subsequent with the photoresist layer
400 remove the second fin 220 described in the segment thickness that the opening 410 is exposed for exposure mask.
In the present embodiment, the opening 410 exposes 220 atop part of the second fin and partial sidewall, convenient for subsequent
The second fin 220 described in segment thickness is removed, helps avoid leaking electricity at the top of second fin 220.
It is aforementioned that the fin further includes the third fin adjacent with second fin in other embodiments, and described
One pseudo- grid further include the pseudo- grid Part III for covering third fin atop part and side wall.In the process for removing the described second pseudo- grid
In, it removes the pseudo- grid Part III or retains the pseudo- grid Part III.
With reference to Fig. 6 to Fig. 7, wherein Fig. 6 is along the schematic diagram of the section structure in A1A2 (referring to Fig. 1) direction, and Fig. 7 is edge
The schematic diagram of the section structure in B1B2 (referring to Fig. 1) direction.Removal is higher than the fin at 230 top of separation layer, makes residue
At the top of the fin with flushed at the top of the separation layer 230.
It is exposure mask with the photoresist layer 400 in the present embodiment, removes described in the segment thickness that the opening 410 is exposed
Second fin 220, make remaining second fin, 220 top with flushed at the top of the separation layer 230.
In the present embodiment, removed described in the segment thickness that the opening 410 is exposed using wet process isotropic etching technique
Second fin 220.After the wet process isotropic etching technique, the photoresist layer 400 is removed.
Be subsequently formed the insulating layer of the full opening 410 of filling, remove it is that the opening 410 is exposed, be higher than the isolation
Second fin 220 at 230 top of layer is conducive to the volume for improving the opening 410, to provide more for the insulating layer
Big spatial position helps to improve the electrical insulation capability between the insulating layer and second fin 220, so as to reduce
The probability to leak electricity at the top of second fin 220.
In other embodiments, after removal is higher than the fin at the top of the separation layer, further includes: removal segment thickness
The fin that the opening is exposed makes to be lower than at the top of the separation layer at the top of the remaining fin.Make low at the top of remaining fin
Facilitate to further increase the volume of the opening at the top of the separation layer, and then the body for the insulating layer material being subsequently formed can be improved
Product, is conducive to further improve the electrical insulation capability between the insulating layer and second fin.
In addition, thoroughly to avoid the fin top of the subsequent insulating layer covering from leaking electricity, in other another realities
It applies in example, after removal is higher than the fin at the top of the separation layer, removes the fin that the opening is exposed until exposing
The substrate surface.
It should be noted that in another embodiment, the removal part pseudo- grid after forming the opening, directly carry out
It is subsequently formed the technique of insulating layer, that is, retains fin top and side wall that the opening is exposed.
With reference to Fig. 8 to Fig. 9, wherein Fig. 8 is along the schematic diagram of the section structure in A1A2 (referring to Fig. 1) direction, and Fig. 9 is edge
The schematic diagram of the section structure in B1B2 (referring to Fig. 1) direction.Form the insulating layer of the full opening 410 (referring to Fig. 6 or Fig. 7) of filling
500。
The effect of the insulating layer 500 is the position electrical isolation for making partial amt can be used to form channel region, subsequent to shape
At semiconductor structure apply voltage, the channel region that can be avoided the fin top surface that the insulating layer 500 covers is opened, after
Continue and form grid at the position that volume residual can be used to form channel region, to obtain channel region quantity satisfactory half
Conductor structure.
In the present embodiment, the insulating layer 500 includes the first insulating layer 510 and second insulating layer 520；First insulation
510 covering of layer, 410 (the referring to Fig. 6) bottom of opening and side wall；The second insulating layer 520 covers first insulating layer
510 surfaces, and the top of the second insulating layer 520 with flushed at the top of the dielectric layer 240；The cause of first insulating layer 510
Density is greater than the consistency of the second insulating layer 520.
Since the consistency of first insulating layer 510 is greater than the consistency of the second insulating layer 520, thus described the
One insulating layer 510 can play the role of enhancing the binding ability between the second insulating layer 520 and the fin, help to change
The interfacial characteristics being apt between the insulating layer 500 and the fin improve the insulation performance of the insulating layer 500.
In the present embodiment, the material of the insulating layer 500 is silica, i.e., described first insulating layer 510 and the second insulation
The material of layer 520 is silica.In other embodiments, the material of the insulating layer can also for silicon nitride, silicon oxynitride,
Silicon oxide carbide or carbon silicon oxynitride.
In the present embodiment, first insulating layer 510 is formed using atom layer deposition process.The atom layer deposition process
Step coverage of the first insulating layer 510 formed at opening 410 (the referring to Fig. 6) bottom corners is good, helps to mention
The consistency of high first insulating layer 510.
If the thickness of first insulating layer 510 is too small, influence first insulating layer 510 to second insulating layer 520 with
The reinforcing effect of binding ability between fin causes the interfacial characteristics between the insulating layer 500 and the fin poor；If described first
The thickness of insulating layer 510 is excessive, and the process time for forming first insulating layer 510 is too long, to the work for forming semiconductor structure
The skill time causes unnecessary extension.In the present embodiment, first insulating layer 510 with a thickness of 3nm~8nm.
In the present embodiment, the second insulating layer 520 is formed using fluid chemistry gas-phase deposition.In other embodiments
In, the second insulating layer can also be formed using high-aspect-ratio chemical vapor deposition process (HARP).
With reference to Figure 10 and Figure 11, wherein Figure 10 is the schematic diagram of the section structure along A1A2 (referring to Fig. 1) direction, Tu11Wei
The schematic diagram of the section structure along B1B2 (referring to Fig. 1) direction.The Wei Shan first part 311 is removed, in the dielectric layer 240
Form the through-hole 610 for running through 240 thickness of dielectric layer.
The through-hole 610 provides spatial position to be subsequently formed grid.
In the present embodiment, during removing Wei Shan first part 311, further includes: the pseudo- grid of removal described second
320。
Removing the Wei Shan first part 311 and the second pseudo- grid 320, forming the process of through-hole 610 includes: shape
At the mask layer (not shown) for covering 500 top of insulating layer, the mask layer exposes the Wei Shan first part 311
Top and second pseudo- 320 top of grid；Using the mask layer as exposure mask, the Wei Shan first part 311 and described are removed
Two pseudo- grid 320, expose the oxide layer 330 for covering first fin 210 and 220 part of the surface of the second fin；Removal dew
The oxide layer 330 out forms the through-hole 610.
In the present embodiment, the Wei Shan first part 311 and described second are removed using wet process isotropic etching technique
Pseudo- grid 320.
In other implementations, after removing the Wei Shan first part and the second pseudo- grid, retain the oxidation of exposing
Layer, the gate oxide as the semiconductor structure being subsequently formed.
With reference to Figure 12 and Figure 13, wherein Figure 12 is the schematic diagram of the section structure along A1A2 (referring to Fig. 1) direction, Tu13Wei
The schematic diagram of the section structure along B1B2 (referring to Fig. 1) direction.Form the grid of the full through-hole 610 (referring to Figure 10 or Figure 11) of filling
Pole 700.
The grid 700, which covers volume residual, can be used to form the top of channel zone position, subsequent partly leading to formation
Body structure applies voltage, and there are channels for the fin top surface that the grid 700 covers, so that the quantity of channel region be made to accord with
It closes and requires.
In the present embodiment, before forming the grid 700, further includes: form boundary layer 620 in 610 bottom of through-hole；?
620 top of boundary layer and 610 side wall of the through-hole form high-k gate dielectric layer 630；It is formed and covers the high-k gate dielectric layer
The work-function layer 640 on 630 surfaces, lower than 240 top of dielectric layer at the top of the work-function layer 640.In the work-function layer
640 surfaces form the grid 700 for filling the full through-hole 610.
The boundary layer 620 can improve the interface basis of the high-k gate dielectric layer 630, so that the high k grid can be improved
The binding ability of dielectric layer 630 and the fin.
In the present embodiment, the material of the boundary layer 620 is silica.In other embodiments, the boundary layer 620
Material can also be germanium oxide or the SiGe containing oxygen element.
In the present embodiment, the boundary layer 620 is formed using chemical oxidation method.In other embodiments, it can also adopt
The boundary layer is formed with thermal oxidation technology or atom layer deposition process.
In the present embodiment, the material of the high-k gate dielectric layer 630 is HfO2；In other embodiments, the high k grid are situated between
The material of matter layer can also be HfSiO, HfSiON, HfTaO, HfTiO, HfZrO or ZrO2。
The work-function layer 640 includes P-type workfunction layer (not shown) and N-type workfunction layer (not shown),
For adjusting the threshold voltage for the semiconductor structure being subsequently formed.
In the present embodiment, the material of the P-type workfunction layer is TiN.In other embodiments, the P-type workfunction layer
Material can also be TaN, TiSiN or TaSiN.
In the present embodiment, the material of the N-type workfunction layer is TiAl；In other embodiments, the N-type workfunction layer
Material can also be TaAl, TiAlC, AlN, TiAlN or TaAlN.
The material of the grid 700 is Cu, W, Al or Ag.In the present embodiment, the material of the grid 700 is Cu.
In the present embodiment, after forming the grid 700, the pull-up region 101 includes a fin structure and the fin
The corresponding grid 700 of formula structure；The drop-down area 102 includes two fin structures and the corresponding grid of described two fin structures
Pole 700；The transmission area of grid 103 includes a fin structure and the corresponding grid 700 of described two fin structures.
The transmission area of grid 103 having on the substrate 200 of aforementioned offer includes two fin structures, and the present embodiment is realized
It includes fin knot that transmission area of grid 103 is formed on the basis of transmitting area of grid 103 and including two fin structures
The SRAM structure of structure helps to simplify formation process process, shortens the process time.
In other embodiments, the transmission area of grid having on the substrate of aforementioned offer includes three fin structures, then
It includes one or two fin knot that transmission area of grid can be formed on the basis of transmitting area of grid and including three fin structures
The SRAM structure of structure, concrete technology method can refer to the present embodiment, repeat no more.
To sum up, the fin top position of pseudo- grid covering can be used to form channel region, since the quantity of the fin is at least
Two, thus can be used to form the position of channel region with multiple.The part pseudo- grid are removed, exposed portion quantity fin
Atop part forms the opening 410 for running through 240 thickness of dielectric layer in the dielectric layer 240, and it is full described to form filling
The insulating layer 500 of opening 410, the insulating layer 500 can be avoided the ditch of the fin top surface covered by the insulating layer 500
Road Qu Kaiqi, it is subsequent that grid is formed at the position that volume residual can be used to form channel region, to make semiconductor structure
The quantity of channel region meets demand.
Referring to Fig. 8, the present invention also provides a kind of semiconductor structure obtained using above-mentioned forming method, the semiconductor junctions
Structure includes: substrate 200 and the fin for protruding from the substrate 200, the quantity at least two of the fin；Positioned at the fin
The separation layer 230 on the substrate 200 exposed, the separation layer 230 cover the fin partial sidewall；Positioned at the isolation
Across the pseudo- grid 311 of partial amt fin on layer 230, the puppet grid 311 cover the part top of the partial amt fin
Portion and partial sidewall；Insulating layer 500 on fin atop part described in volume residual, the insulating layer 500 and the puppet
Grid 311 are adjacent；Dielectric layer 240 on the separation layer 230, the dielectric layer 240 cover 500 side wall of insulating layer
And 311 side wall of the pseudo- grid.
In the present embodiment, the fin includes the first fin 210 and second fin adjacent with first fin 210
220, it is described puppet grid 311 across first fin 210, the insulating layer 500 cover 220 atop part of the second fin and
Partial sidewall.
In the present embodiment, the spacing of first fin 210 and the second fin 220 is 30nm~40nm.
In the present embodiment, the first groove in first fin 210 of 311 two sides of the pseudo- grid (does not show in figure
Out)；The second groove in second fin 220 of 500 two sides of insulating layer；Filling is completely located at the pseudo- grid 311
The stressor layers of ipsilateral the first groove and the second groove；The dielectric layer 240 covers the stress layer surface.
In the present embodiment, the insulating layer 500 includes the first insulating layer 510 and second insulating layer 520；First insulation
510 covering of layer, 220 top of the second fin and 240 side wall of the dielectric layer；The second insulating layer 520 covers described first
510 surface of insulating layer, and the top of the second insulating layer 520 with flushed at the top of the dielectric layer 240；First insulating layer
510 consistency is greater than the consistency of the second insulating layer 520.
The effect of the insulating layer 500 is the position electrical isolation for making partial amt can be used to form channel region, to avoid
The channel region for 220 top surface of the second fin that the insulating layer 500 covers is opened.
Since the consistency of first insulating layer 510 is greater than the consistency of the second insulating layer 520, thus described the
One insulating layer 510 can play the role of enhancing the binding ability between the second insulating layer 520 and the fin, help to change
The interfacial characteristics being apt between the insulating layer 500 and the fin improve the insulation performance of the insulating layer 500.
Although present disclosure is as above, present invention is not limited to this.Anyone skilled in the art are not departing from this
It in the spirit and scope of invention, can make various changes or modifications, therefore protection scope of the present invention should be with claim institute
Subject to the range of restriction.
Claims (20)
1. a kind of method for forming semiconductor structure characterized by comprising
Substrate is provided and protrudes from the fin of the substrate, the quantity at least two of the fin, the institute that the fin exposes
Stating has separation layer on substrate, the separation layer covers the fin partial sidewall, has on the separation layer across the fin
The pseudo- grid in portion, the puppet grid cover the atop part and partial sidewall of the fin；
Dielectric layer, the dielectric layer covering pseudo- grid side wall are formed on the separation layer；
The part pseudo- grid are removed, the atop part of exposed portion quantity fin is formed in the dielectric layer through described
The opening of thickness of dielectric layers；
Form the insulating layer for filling the full opening.
2. method for forming semiconductor structure as described in claim 1, which is characterized in that the fin include the first fin and with
The second adjacent fin of first fin；The puppet grid include the pseudo- grid the of covering the first fin atop part and side wall
The pseudo- grid second part of a part and covering the second fin atop part and side wall；In removal part the step of the pseudo- grid
In, the pseudo- grid second part is removed, the Wei Shan first part is retained.
3. method for forming semiconductor structure as claimed in claim 2, which is characterized in that the work of the removal pseudo- grid second part
Process includes: the photoresist layer to be formed and be covered at the top of the Wei Shan first part, and the photoresist layer exposes the pseudo- grid the
Two atop parts；Using the photoresist layer as exposure mask, the pseudo- grid second part is removed；Remove the photoresist layer.
4. method for forming semiconductor structure as claimed in claim 2, which is characterized in that before forming the dielectric layer, further includes:
The first groove is formed in first fin of the pseudo- grid two sides；It is formed in second fin of the pseudo- grid two sides
Second groove；Form the stressor layers that filling is completely located at ipsilateral the first groove and the second groove of the pseudo- grid.
5. method for forming semiconductor structure as claimed in claim 4, which is characterized in that use selective epitaxial growth process shape
At the stressor layers.
6. the method for forming semiconductor structure as described in claim 2,4 or 5, which is characterized in that first fin and second
The spacing of fin is 30nm~40nm.
7. method for forming semiconductor structure as claimed in claim 2, which is characterized in that after forming the insulating layer, further includes:
The pseudo- grid second part is removed, forms the through-hole for running through the thickness of dielectric layers in the dielectric layer；Form the full institute of filling
State the grid of through-hole.
8. method for forming semiconductor structure as claimed in claim 2, which is characterized in that the fin further includes and described second
The adjacent third fin of fin, second fin is between first fin and the third fin；The puppet grid are also
Pseudo- grid Part III including covering the third fin atop part and side wall；In removal part during the pseudo- grid,
It removes the pseudo- grid Part III or retains the pseudo- grid Part III.
9. method for forming semiconductor structure as described in claim 1, which is characterized in that the opening exposes the partial amt
The atop part and partial sidewall of a fin；After forming the opening, and before forming the insulating layer, further includes: removal is high
The fin at the top of the separation layer makes to flush at the top of the remaining fin with the separation layer top.
10. method for forming semiconductor structure as claimed in claim 9, which is characterized in that removal is higher than at the top of the separation layer
The fin after, and before forming the insulating layer, further includes: the fin for the exposing that is open described in removal segment thickness,
Make at the top of the remaining fin lower than the separation layer top.
11. method for forming semiconductor structure as claimed in claim 9, which is characterized in that removal is higher than at the top of the separation layer
The fin after, and before forming the insulating layer, further includes: the fin that the removal opening is exposed is until expose institute
State substrate surface.
12. method for forming semiconductor structure as described in claim 1, which is characterized in that the insulating layer includes the first insulation
Layer and second insulating layer；First insulating layer covers the open bottom and side wall；Described in the second insulating layer covering
First surface of insulating layer, and flushed at the top of the second insulating layer at the top of the dielectric layer；The densification of first insulating layer
Degree is greater than the consistency of the second insulating layer.
13. method for forming semiconductor structure as claimed in claim 12, which is characterized in that formed using atom layer deposition process
First insulating layer.
14. method for forming semiconductor structure as claimed in claim 12, which is characterized in that using fluid chemistry vapor deposition work
Skill forms the second insulating layer.
15. the method for forming semiconductor structure as described in claim 1 or 12, which is characterized in that the material of the insulating layer is
Silica, silicon nitride, silicon oxynitride, silicon oxide carbide or carbon silicon oxynitride.
16. a kind of semiconductor structure characterized by comprising
Substrate and the fin for protruding from the substrate, the quantity at least two of the fin；
Separation layer on the substrate that the fin exposes, the separation layer cover the fin partial sidewall；
Across the pseudo- grid of partial amt fin on the separation layer, the puppet grid cover the partial amt fin
Atop part and partial sidewall；
Insulating layer on fin atop part described in volume residual, the insulating layer and the pseudo- grid are adjacent；
Dielectric layer on the separation layer, the dielectric layer cover the insulating layer sidewalls and the pseudo- grid side wall.
17. semiconductor structure as claimed in claim 16, which is characterized in that the fin includes the first fin and with described the
The second adjacent fin of one fin, the puppet grid cover second fin part across first fin, the insulating layer
Top and partial sidewall.
18. semiconductor structure as claimed in claim 17, which is characterized in that first fin positioned at the pseudo- grid two sides
The first interior groove；The second groove in second fin of the insulating layer two sides；Filling is completely located at the pseudo- grid
The stressor layers of ipsilateral the first groove and the second groove；The dielectric layer covers the stress layer surface.
19. the semiconductor structure as described in claim 17 or 18, which is characterized in that between first fin and the second fin
Away from for 30nm~40nm.
20. semiconductor structure as claimed in claim 16, which is characterized in that the insulating layer includes the first insulating layer and second
Insulating layer；First insulating layer covers at the top of the fin and the dielectric layer side wall；Described in the second insulating layer covering
First surface of insulating layer, and flushed at the top of the second insulating layer at the top of the dielectric layer；The densification of first insulating layer
Degree is greater than the consistency of the second insulating layer.
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