CN105244379A - Semiconductor device and manufacturing method thereof - Google Patents
Semiconductor device and manufacturing method thereof Download PDFInfo
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- CN105244379A CN105244379A CN201410328588.3A CN201410328588A CN105244379A CN 105244379 A CN105244379 A CN 105244379A CN 201410328588 A CN201410328588 A CN 201410328588A CN 105244379 A CN105244379 A CN 105244379A
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Abstract
A semiconductor device comprises fin structures, source regions, channels, drain regions, gate stacks, and gate spacers. The fin structures are distributed on a substrate in an extending way along a first direction, and the material of the fin structures is different from that of the substrate. The source regions, the channels and the drain regions are distributed in the tops of the fin structures in an extending way along the first direction. The gate stacks are distributed on the channels in an extending way along a second direction. The gate spacers are distributed at the two sides of the gate stacks along the first direction. According to the semiconductor device and a manufacturing method thereof of the invention, device fin structures made of different materials are grown in an epitaxial way in the small grooves of the substrate, upward propagation of interface defects is inhibited in the grooves with appropriate depth-to-width ratio, the reliability of the device is improved, and the carrier mobility in the channel regions of the device is increased effectively.
Description
Technical field
The present invention relates to a kind of semiconductor device and manufacture method thereof, particularly relate to a kind of FinFET based on Ge material (FinFET) and manufacture method thereof.
Background technology
Along with dimensions of semiconductor devices continues to reduce, the mobility strengthening channel carrier becomes very important technology.Properties of materials different in the design of substrate stressor layers is different, and such as lattice constant, dielectric constant, energy gap, particularly carrier mobility etc., as shown in table 1 below.
Table 1
From table 1, in these possible backing materials above-mentioned, Ge has the highest hole mobility and higher electron mobility, uses Ge greatly will strengthen carrier mobility as the substrate of semiconductor device, thus can manufacture large scale integrated circuit (LSIC) faster.
In addition, from table 1, Ge also has the lattice constant close with Si material, therefore Ge can relatively easily on integrated Si substrate conventional in semiconductor processing, make, without the need to making the significant improvement semiconductor device that just energy manufacturing property is better for technique, while improving performance, to also reduce cost.
On the other hand, in order to the challenge that the continuous miniaturization tackling semiconductor device brings, propose multiple high performance device, particularly in current sub-20nm technology, three-dimensional multi-gate device (FinFET or Tri-gate) is main device architecture, and this structure enhances grid control ability, inhibits electric leakage and short-channel effect.
Such as, the MOSFET of double gate SOI structure is compared with traditional single grid body Si or SOIMOSFET, short-channel effect (SCE) can be suppressed and leak to cause induced barrier reduction (DIBL) effect, there is lower junction capacitance, raceway groove light dope can be realized, adjusting threshold voltage can be carried out by the work function arranging metal gates, the drive current of about 2 times can be obtained, reduce the requirement for effective gate oxide thickness (EOT).And tri-gate devices is compared with double-gated devices, gate wraps channel region end face and two sides, grid control ability is stronger.Further, loopful has more advantage around nano wire multi-gate device.
But, due to the lattice constant of Ge and Si still variant, when forming small size device, particularly FinFET (FinFET), being difficult to adopt Ge material to form fin structure completely, being therefore difficult to the channel region carrier mobility effectively strengthening FinFET further.Further, Ge and Si interface can make the small size device based on Ge of extension on Si there is the problem of reliability decrease due to the defect that lattice mismatch exists.
Summary of the invention
Therefore, the object of the invention is to improve FinFET channel region carrier mobility further to improve semiconductor device electric property and reliability.
The invention provides a kind of semiconductor device, comprising: fin structure, extend distribution in substrate along first direction, wherein the material of fin structure is different from substrate material; Source region, channel region, drain region, in fin structure top, extend distribution along first direction; Gate stack, extends distribution along second direction on channel region; Grid curb wall, in the both sides of gate stack along first direction.
Wherein, fin structure have charge into substrate surface to lower process.
Wherein, the material of fin structure comprises Ge, GaAs, GaN, InGaN, InGaAs, InP, AlGaN and combination thereof.
Wherein, the top in source region, drain region has lifting source region and lifting drain region, has the material different from fin structure with to channel region stress application.
Wherein, the material in lifting source region and lifting drain region comprises SiGe, GeSn, SiC, SiGeC, SiGeSn, SiSn and combination thereof.
Wherein, the middle part of fin structure comprises break-through stop-layer further, and break-through stop-layer is the doped region contrary with channel region conduction type or insulator.
Wherein, gate stack comprises the gate insulator of hafnium and the grid conducting layer of metal material.
The invention also discloses a kind of method, semi-conductor device manufacturing method, comprising: substrate formed along first direction extend distribution the first fin structure and the first fin structure between shallow trench isolation from; Etching removal first fin structure, shallow trench isolation between leave the first groove; In the first groove, epitaxial growth is different from the semi-conducting material of substrate, forms the second fin structure; Second fin structure is formed along second direction extend distribution gate stack and be positioned at the source-drain area of gate stack along first direction both sides, the part constituting channel district of the second fin structure below gate stack structure.
Wherein, comprise further during etching formation the first groove, form depression in the first channel bottom etched substrate.
Wherein, wet etching etched substrate is adopted to form the first groove.
Wherein, taking a step forward of etching removal first fin structure comprises, clean first fin structure top.
Wherein, comprise further after epitaxial growth second fin structure, return and carve shallow trench isolation from the top to expose the second fin structure.
Wherein, form taking a step forward of gate stack and comprise, adopt vertical and/or angle-tilt ion to be infused in the middle part of the second fin structure and form break-through stop-layer.
Wherein, B, In, BF are selected from for nFinFET injection
2dopant, or pFinFET injected be selected from the dopant of As, P, form the doped region contrary with channel region conduction type and form break-through stop-layer; Or, inject the dopant the break-through stop-layer of annealing reaction formation insulator that are selected from C, N, O.
Wherein, the step of formation gate stack, source-drain area comprises further: on the second fin structure, form the false grid heap superimposition grid curb wall extending distribution along second direction; In the second fin structure top formation lightly-doped source drain region of grid curb wall along first direction both sides; In top epitaxial growth lifting source drain region, lightly-doped source drain region; Remove the stacking formation gate openings of false grid; The gate insulator of hafnium and the grid conducting layer of metal material is deposited in gate openings.
Wherein, the material of the second fin structure comprises Ge, GaAs, GaN, InGaN, InGaAs, InP, AlGaN and combination thereof.
Wherein, the material in lifting source drain region comprises SiGe, GeSn, SiC, SiGeC, SiGeSn, SiSn and combination thereof.
According to semiconductor device of the present invention and manufacture method thereof, the device fin chip architecture of epitaxial growth different materials fine recesses from substrate, prevent boundary defect upwards to propagate, improve the reliability of device, and effectively improve the channel region carrier mobility of device.
Accompanying drawing explanation
Technical scheme of the present invention is described in detail referring to accompanying drawing, wherein:
Fig. 1 to Figure 17 respectively illustrates the schematic diagram according to each step of manufacturing method of semiconductor device of the present invention.
Embodiment
Describe feature and the technique effect thereof of technical solution of the present invention in detail in conjunction with schematic embodiment referring to accompanying drawing, disclose and improve FinFET channel region carrier mobility further to improve Ge fin FinFET and the manufacture method thereof of semiconductor device electric property and reliability.It is pointed out that structure like similar Reference numeral representation class, term " first " used in the application, " second ", " on ", D score etc. can be used for modifying various device architecture or processing step.These modify the space of not hint institute's modification device architecture or processing step unless stated otherwise, order or hierarchical relationship.
With reference to the cutaway view of Fig. 1, form mask graph PR on substrate 1.Substrate 1 can be the semiconductor silicon based substrate that on body Si, insulating barrier, Si (SOI) etc. is conventional, or body Ge, ge-on-insulator (GeOI), also can be the compound semiconductor substrate such as SiGe, GaAs, GaN, can also be the dielectric substrate such as sapphire, SiC, AlN, the electric property of the concrete semiconductor device that it will make the selection gist of substrate needs and sets.In the present invention, the semiconductor device lifted of embodiment is such as the FinFET based on CMOS technology, therefore considers from the angle with other process compatibles and cost control, and preferred body silicon or SOI are as the material of substrate 1.Adopt the techniques such as spin coating, spraying, silk screen printing, CVD, the top surface of substrate 1 forms mask material and adopts traditional exposure/etching technics to form the parallel multiple mask graph PR extending (perpendicular to paper) along first direction.Mask graph PR can be the soft masks of photoresist, can also be the hardmask of nitride, oxide or its stacked structure (such as ONO structure).
With reference to the cutaway view of Fig. 2, with mask graph PR for mask, etched substrate 1, defines multiple parallel along the first direction fin structure 1F holded up vertically upward from substrate 1 top surface, and leave groove 1T between multiple fin structure 1F.Etching technics preferably adopts anisotropic lithographic method, such as, adopt fluorine-based dry plasma etch, RIE, or adopts TMAH, KOH wet etching.Preferably, control etching parameters, make the depth-to-width ratio of fin 1F or groove 1T be greater than 5:1 and be preferably greater than 10:1.
With reference to the cutaway view of Fig. 3, in the groove 1T between fin structure 1F, fill insulant forms isolation structure.Preferably, first adopt the dry process such as plasma etching, ashing or adopt the wet processing of oxidant and acid solution mixture to eliminate mask graph PR.Then, adopt in high-aspect-ratio depositing operation (HARP), high density plasma chemical vapor deposition technique (HDPCVD) or the groove 1T of chemical vapor deposition method (flowableCVD) between multiple fin structure 1F that can flow to fill and define insulating material 2.Insulating material 2 is silica, silicon oxynitride or low-K material such as, and wherein low-k materials includes but not limited to organic low-k materials (such as containing the organic polymer of aryl or polynary ring), inorganic low-k material (such as amorphous carbon nitrogen film, polycrystalline boron nitrogen film, fluorine silex glass, BSG, PSG, BPSG), porous low k material (such as two silicon three oxygen alkane (SSQ) hole, Quito low-k materials, porous silica, porous SiOCH, mix C silicon dioxide, mix F porous amorphous carbon, porous diamond, porous organic polymer).Now, because fin structure 1F exists projection relative to substrate 1, the top of the insulating material 2 formed is made also to have corresponding projection in corresponding position, fin structure 1F top.
With reference to the cutaway view of Fig. 4, flatening process is performed to insulating material 2, until expose fin structure 1F top.Flatening process can be CMP, or for insulating material 2 and the Etch selectivity of fin structure 1F perform return carving technology (etch-back).Stay between fin structure 1F, occupy the isolation structure that the insulating material 2 of original groove 1T position constitutes device, also referred to as shallow trench isolation from (STI).
With reference to the cutaway view of Fig. 5, selective etch removes fin structure 1F.The anisotropic etching technics of preferred employing, such as fluorine-based dry plasma etch or RIE, or adopt wet corrosion technique.In a preferred embodiment of the invention, the fin structure 1F for Si material adopts the alkaline corrosion liquid of the trimethylammonium hydroxide (dTMAH) of dilution, defines the groove 1T ' with good vertical sidewall.Because each crystal orientation of Si substrate is different for the corrosion rate of TAMH, such as (111) crystal face is the slowest, therefore finally can define the groove 1R of the inclination along (111) crystal face in substrate 1, this depth of groove such as only 1 ~ 5nm.Preferably, before dTMAH corrodes Si fin 1F, first adopt the end face of dilute hydrofluoric acid (dHF) cleaning (duration such as 30 seconds) fin structure 1F of 100:1 volume ratio, to remove the primary oxide in surface to improve subsequent etching selectivity and speed.
With reference to the cutaway view of Fig. 6, selective epitaxial growth device material 3 in groove 1T '.Adopt the techniques such as MOCVD, MBE, ALD, HDPCVD, epitaxial growth device material 3 in groove 1T ' between STI and the groove 1R of channel bottom, its material such as Ge, but also can be the GaAs in table 1, or other compound semiconductor materials unlisted in table 1, such as GaN, InGaN, InGaAs, InP, AlGaN etc.Due to the oxide that STI material is insulation, therefore epitaxial growth only starts from groove 1R until cross STI top to form projection, and this process is also referred to as selective epitaxial growth.It should be noted that, in this process, because extension grows from the groove 1R with inclined side, therefore the thin device material of the leading accumulated growth in bottom constitutes the nucleating layer that the thick device material of filling is continued in top, the defect such as dislocation, lattice mismatch of device material and Si interface will be confined near former groove 1R, or 1/3 of the STI height/groove 1T ' degree of depth can not be crossed, ensure that the growth quality of top device material layer is good.
With reference to the cutaway view of Fig. 7, flatening process process is adopted to device material (such as Ge layer), expose STI top.Such as adopt CMP or return carving technology, eliminating the device material 3 more than STI top, make the device material stayed constitute the fin structure 3F of device.Fin structure 3F top shown in Fig. 7 and the fin structure 1F shown in Fig. 4 are conformal substantially, just fin structure 1F is only for limiting the shape of fin structure 3F, STI, therefore in fact fin structure 1F can adopt the naming rule of similar rear grid technique and be called pseudo-fin structure (dummyfin) or sacrifice fin structure, the fin structure 3F that the device material different from substrate 1 material finally stayed is formed can be called final fin structure or true fin structure, for the formation of channel region and the restriction source-drain area position of future device.Fin structure 3F has the part of charging in substrate 1 identical with groove 1R shape, as mentioned above, is eliminated the defect propagation of device material (such as Ge layer), improve device reliability by this part.
With reference to the cutaway view of Fig. 8, etching removes a part of STI, exposes fin structure 3F.For STI material, can anisotropic dry etch process be selected, or adopt dHF, dBOE (the slowly-releasing etching agent of dilution) wet etching to remove a part of STI.The height of the fin structure 3F exposed can depend in FinFET the pattern needs that surround grid and determine.In a preferred embodiment of the invention, the height of the fin structure 3F exposed is less than or equal to 1/2 of fin 3F height.
With reference to the cutaway view of Fig. 9, optional, in the middle part of fin structure 3F, form break-through stop-layer (PTS) 4.Preferably, vertical and/or angle-tilt ion injection can be adopted, dopant implant ion in the middle part of fin structure 3F, with after annealing activator impurity, defining and the fin structure 3F material of usual intrinsic, doping type, break-through stop-layer 4 that concentration is different, reducing the leakage current of FinFET along vertical substrates direction for suppressing.In a preferred embodiment of the invention, B, In, BF can be injected for nFinFET
2deng dopant, the dopant such as As, P is injected for pFinFET, thus and form pn between the upper and lower material of fin structure 3F and tie thus suppress to leak by back-biased diode.In addition, in another preferred embodiment of the present invention, C, N, O etc. can also be injected easily and the Doped ions of the material generation chemical reaction of fin structure 3F, adopt high annealing (such as 600 to 900 degrees Celsius) to make the material of Doped ions and fin structure 3F react the PTS4 forming insulator (such as oxide, silicon nitride, carbide etc.) after injection, cut off the leakage path between substrate by insulator 4 thus.The dosage of injection, energy, angle and annealing temperature can be adjusted, the position of conservative control PTS4.In a preferred embodiment of the invention, PTS4 end face flushes with STI end face, and fin structure 3F by the channel region (channel) for the formation of device, is therefore denoted as 3C in the region on PTS4 top.In another preferred embodiment of the present invention, PTS4 bottom surface is higher than the end face of substrate 1.
With reference to the cutaway view of Figure 10, on device, deposition forms dummy grid stack layer 5.Adopt the techniques such as PECVD, HDPCVD, MBE, ALD, evaporation, oxidation, sputtering, whole device deposited by dummy grid insulating barrier 5A and dummy grid conductive layer 5B.Layer 5A material such as silica, layer 5B material such as polysilicon, amorphous silicon, microcrystal silicon, polycrystalline germanium, amorphous germanium, amorphous carbon etc., both materials select to improve the Etch selectivity with surrounding other materials.Stack layer 5 completely covers top and the sidewall at fin structure 3F top (3C), and covers the top of STI.
With reference to the top view of Figure 11, carry out graphically to dummy grid stack layer 5, form the dummy grid stacked structure extended along second direction BB (in Figure 10 and Figure 11 horizontal left and right directions), expose the top 3C of the fin structure 3F along first direction AA (vertical paper direction in Figure 10, in Figure 11 in paper above-below direction) both sides.
With reference to the top view of Figure 12, at the both sides formation grid curb wall 6 of dummy grid stacked structure 5A/5B along first direction AA.Such as first adopt the technique such as PECVD, sputtering to form the insulating dielectric materials such as silicon nitride, silicon oxynitride, diamond like carbon amorphous carbon (DLC), then adopt anisotropic etch process eliminate horizontal component and only on dummy grid stacked structure 5 both sides, remain grid curb wall 6.
With reference to the top view of Figure 13, in fin structure 3F top 3C, dummy grid stacked structure 5 both sides define lightly-doped source drain region 3L (comprising source region 3LS and the drain region 3LD of LDD structure).B, In, BF are injected for pFinFET
2deng dopant, nFinFET is injected to the dopants (forming the lightly-doped source drain region contrary with PTS4 doped region doping type) such as As, P.The technique such as spike annealing, short annealing is adopted to activate dopant implant agent subsequently.
With reference to the top view of Figure 14, form source-drain area.Preferably, adopt the solution corrosions such as dHF to clean the top of lightly-doped source drain region 3LS/3LD, remove the native oxide of injection, annealing process.In an embodiment of the invention, form heavily doped source-drain area 3HS/3HD at dummy grid stacked structure 5 along the both sides of first direction by improving dopant dosage, Implantation Energy etc., the type injecting ion is identical with LDD structure, is that concentration is higher.Preferably, in another embodiment, the lifting source drain region of unlike material that adopted selective epitaxial growth technology at lightly-doped source drain region Epitaxial growth, and adopt in-situ doped technology to define high concentration simultaneously.Lifting source drain region is by controlling material type, and such as, NMOS for Ge raceway groove adopts SiGe, SiGeC, SiC etc.; PMOS for Ge raceway groove adopts GeSn (when fin structure/channel region is other materials outside Ge, other materials such as GeSn, SiGeSn, SiSn can be adopted), different stress can be applied to the fin channel district 3C below dummy grid stacked structure 5, thus effectively increase channel region carrier mobility.
With reference to Figure 15 A, it illustrates the cutaway view that the first direction AA line along Figure 14 obtains.The cutaway view of Figure 15 B then for obtaining along the second direction BB line of Figure 14, consistent with Fig. 1 to Fig. 9 direction.From Figure 15 B, the epitaxially grown lifting source drain region 3HS/3HD comprising stress encloses side and the top of the lightly-doped source drain region 3LS/3LD of LDD structure, is such as rhombus or diamond in the accompanying drawings.
With reference to the cutaway view along second direction BB of Figure 16, whole device forms interlayer dielectric layer (ILD) 7.Such as adopt the technique such as spin coating, spraying, silk screen printing, CVD to form the ILD7 of low-k materials, include but not limited to organic low-k materials (such as containing the organic polymer of aryl or polynary ring), inorganic low-k material (such as amorphous carbon nitrogen film, polycrystalline boron nitrogen film, fluorine silex glass, BSG, PSG, BPSG), porous low k material (such as two silicon three oxygen alkane (SSQ) hole, Quito low-k materials, porous silica, porous SiOCH, mix C silicon dioxide, mix F porous amorphous carbon, porous diamond, porous organic polymer).Preferably, CMP planarization ILD7 is adopted until expose dummy grid conductive layer 5B top.
With reference to the cutaway view along second direction BB of Figure 17, grid technique after continuing.Such as, selective etch removes dummy grid conductive layer 5B and dummy grid insulating barrier 5A, in ILD7, leave gate openings.Adopt the technique such as HDPCVD, MOCVD, MBE, ALD, the gate insulator 8A of deposited high-k material and the grid conducting layer 8B of metal material successively in gate openings.Wherein, high-g value includes but not limited to nitride (such as SiN, AlN, TiN), metal oxide (is mainly subgroup and lanthanide element oxide, such as MgO, Al
2o
3, Ta
2o
5, TiO
2, ZnO, ZrO
2, HfO
2, CeO
2, Y
2o
3, La
2o
3), nitrogen oxide (as HfSiON); Perovskite Phase oxide (such as PbZr
xti
1-xo
3(PZT), Ba
xsr
1-xtiO
3(BST)).Grid conducting layer 8B then can be polysilicon, poly-SiGe or metal, wherein metal can comprise the alloy of the metal simple-substances such as Co, Ni, Cu, Al, Pd, Pt, Ru, Re, Mo, Ta, Ti, Hf, Zr, W, Ir, Eu, Nd, Er, La or these metals and the nitride of these metals, also can doped with elements such as C, F, N, O, B, P, As with regulatory work function in grid conducting layer 8B.Also form the barrier layer (not shown) of nitride between grid conducting layer 8B and gate insulator 8A preferably by conventional methods such as PVD, CVD, ALD, barrier layer material is M
xn
y, M
xsi
yn
z, M
xal
yn
z, M
aal
xsi
yn
z, wherein M is Ta, Ti, Hf, Zr, Mo, W or other element.More preferably, grid conducting layer 8B and barrier layer not only adopt lamination layer structure stacked up and down, the dopant implant Rotating fields mixed can also be adopted, also the material namely forming grid conducting layer 8B and barrier layer is deposited on gate insulator 8A simultaneously, and therefore grid conducting layer comprises the material on above-mentioned barrier layer.Afterwards, etching ILD7 forms the contact hole exposing lifting source drain region 3HD/3HS further, fills the metals such as W, Al, Cu, Ti, Ta, Mo, metal alloy, metal nitride etc. and form contact plug 9B in contact hole.And in contact hole, further preferably form nickel based metal silicide 9A before this to reduce contact resistance.
Finally, define of the present invention novel FinFET as shown in figure 17, it comprises: on substrate 1 along first direction extend multiple fin structure 3F, wherein fin structure 3F have charge into substrate 1 surface to lower process, fin 3F material is different from substrate 1 material; There is in the middle part of fin structure 3F break-through stop-layer 4, for have dopant and from the back-biased doped region of other partially conductive types of fin structure 3F different formation PN junction, or for insulating material form insulator; Fin structure 3F top comprises the light dope source region 3LS, channel region 3C, the lightly doped drain 3LD that extend distribution along first direction; There is above the 3C of channel region the gate stack 8 of the gate insulator 8A of high-g value and the grid conducting layer 8B of metal material; Gate stack 8 both sides have grid curb wall; Lightly-doped source drain region 3LD/3LS has the lifting source drain region 3HS/3HD that stress can be provided to channel region 3C of unlike material; Lifting source drain region has metal silicide 9A and contact plunger 9B, be embedded in interlayer dielectric layer 7.The concrete material of all parts and technique as mentioned above, do not repeat them here.
According to semiconductor device of the present invention and manufacture method thereof, the device fin chip architecture of epitaxial growth different materials fine recesses from substrate, prevent boundary defect upwards to propagate, improve the reliability of device, and effectively improve the channel region carrier mobility of device.
Although the present invention is described with reference to one or more exemplary embodiment, those skilled in the art can know without the need to departing from the scope of the invention and make various suitable change and equivalents to technological process.In addition, can be made by disclosed instruction and manyly may be suitable for the amendment of particular condition or material and not depart from the scope of the invention.Therefore, object of the present invention does not lie in and is limited to as realizing preferred forms of the present invention and disclosed specific embodiment, and disclosed device architecture and manufacture method thereof will comprise all embodiments fallen in the scope of the invention.
Claims (17)
1. a semiconductor device, comprising:
Fin structure, extend distribution in substrate along first direction, wherein the material of fin structure is different from substrate material;
Source region, channel region, drain region, in fin structure top, extend distribution along first direction;
Gate stack, extends distribution along second direction on channel region;
Grid curb wall, in the both sides of gate stack along first direction.
2. semiconductor device as claimed in claim 1, wherein, fin structure have charge into substrate surface to lower process.
3. semiconductor device as claimed in claim 1, wherein, the material of fin structure comprises Ge, GaAs, GaN, InGaAs, InP, InGaN, AlGaN and combination thereof.
4. semiconductor device as claimed in claim 1, wherein, the top in source region, drain region has lifting source region and lifting drain region, has the material different from fin structure with to channel region stress application.
5. semiconductor device as claimed in claim 4, wherein, the material in lifting source region and lifting drain region comprises SiGe, GeSn, SiC, SiGeC, SiGeSn, SiSn and combination thereof.
6. semiconductor device as claimed in claim 1, wherein, the middle part of fin structure comprises break-through stop-layer further, and break-through stop-layer is the doped region contrary with channel region conduction type or insulator.
7. semiconductor device as claimed in claim 1, wherein, gate stack comprises the gate insulator of hafnium and the grid conducting layer of metal material.
8. a method, semi-conductor device manufacturing method, comprising:
Substrate formed along first direction extend distribution the first fin structure and the first fin structure between shallow trench isolation from;
Etching removal first fin structure, shallow trench isolation between leave the first groove;
In the first groove, epitaxial growth is different from the semi-conducting material of substrate, forms the second fin structure;
Second fin structure is formed along second direction extend distribution gate stack and be positioned at the source-drain area of gate stack along first direction both sides, the part constituting channel district of the second fin structure below gate stack structure.
9. method as claimed in claim 8, wherein, comprises further during etching formation the first groove, forms depression in the first channel bottom etched substrate.
10. method as claimed in claim 8, wherein, adopts wet etching etched substrate to form the first groove.
11. methods as claimed in claim 8, wherein, taking a step forward of etching removal first fin structure comprises, clean first fin structure top.
12. methods as claimed in claim 8, wherein, comprise after epitaxial growth second fin structure further, return and carve shallow trench isolation from the top to expose the second fin structure.
13. methods as claimed in claim 8, wherein, form taking a step forward of gate stack and comprise, and adopt vertical and/or angle-tilt ion to be infused in the middle part of the second fin structure and form break-through stop-layer.
14. as the method for claim 13, wherein, injects be selected from B, In, BF for nFinFET
2dopant, or pFinFET injected be selected from the dopant of As, P, form the doped region contrary with channel region conduction type and form break-through stop-layer; Or, inject the dopant the break-through stop-layer of annealing reaction formation insulator that are selected from C, N, O.
15. methods as claimed in claim 8, wherein, the step of formation gate stack, source-drain area comprises further: on the second fin structure, form the false grid heap superimposition grid curb wall extending distribution along second direction; In the second fin structure top formation lightly-doped source drain region of grid curb wall along first direction both sides; In top epitaxial growth lifting source drain region, lightly-doped source drain region; Remove the stacking formation gate openings of false grid; The gate insulator of hafnium and the grid conducting layer of metal material is deposited in gate openings.
16. methods as claimed in claim 8, wherein, the material of the second fin structure comprises Ge, GaAs, GaN, InGaAs, InP, InGaN, AlGaN and combination thereof.
17. as the method for claim 15, and wherein, the material in lifting source drain region comprises SiGe, GeSn, SiC, SiGeC, SiGeSn, SiSn and combination thereof.
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| CN105448985A (en) * | 2014-08-14 | 2016-03-30 | 中国科学院微电子研究所 | Semiconductor device and manufacturing method thereof |
| CN106206318A (en) * | 2016-08-12 | 2016-12-07 | 中国科学院微电子研究所 | A kind of fin formula field effect transistor and preparation method thereof |
| CN107026083A (en) * | 2016-02-02 | 2017-08-08 | 中芯国际集成电路制造(上海)有限公司 | The manufacture method of semiconductor device |
| CN108831926A (en) * | 2018-06-11 | 2018-11-16 | 中国科学院微电子研究所 | Semiconductor devices and its production method |
| CN109817637A (en) * | 2017-11-22 | 2019-05-28 | 旺宏电子股份有限公司 | Semiconductor structure and its manufacturing method for three-dimensional storage element |
| CN112447593A (en) * | 2019-08-30 | 2021-03-05 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
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| CN105448985A (en) * | 2014-08-14 | 2016-03-30 | 中国科学院微电子研究所 | Semiconductor device and manufacturing method thereof |
| CN107026083A (en) * | 2016-02-02 | 2017-08-08 | 中芯国际集成电路制造(上海)有限公司 | The manufacture method of semiconductor device |
| CN106206318A (en) * | 2016-08-12 | 2016-12-07 | 中国科学院微电子研究所 | A kind of fin formula field effect transistor and preparation method thereof |
| CN106206318B (en) * | 2016-08-12 | 2019-06-11 | 中国科学院微电子研究所 | A kind of fin formula field effect transistor and preparation method thereof |
| CN109817637A (en) * | 2017-11-22 | 2019-05-28 | 旺宏电子股份有限公司 | Semiconductor structure and its manufacturing method for three-dimensional storage element |
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| CN108831926A (en) * | 2018-06-11 | 2018-11-16 | 中国科学院微电子研究所 | Semiconductor devices and its production method |
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