CN104112666A - Semiconductor device and method for manufacturing the same - Google Patents

Semiconductor device and method for manufacturing the same Download PDF

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Publication number
CN104112666A
CN104112666A CN201310142130.4A CN201310142130A CN104112666A CN 104112666 A CN104112666 A CN 104112666A CN 201310142130 A CN201310142130 A CN 201310142130A CN 104112666 A CN104112666 A CN 104112666A
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fin
substrate
layer
barrier layer
break
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殷华湘
张永奎
朱慧珑
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Institute of Microelectronics of CAS
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Institute of Microelectronics of CAS
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Priority to CN201310142130.4A priority Critical patent/CN104112666A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

The invention discloses a semiconductor device and a manufacturing method thereof, comprising the following steps: forming a plurality of fins and trenches extending in a first direction on a substrate; forming an isolation layer in the trench; forming a punch-through barrier layer in the fin and/or at an interface of the fin and the substrate; and etching the isolation layer to expose part of the fins, and forming shallow trench isolation by the rest isolation layer. According to the semiconductor device and the manufacturing method thereof, the punch-through barrier layer is formed in the fin and below the shallow trench isolation, so that the parasitic channel effect is effectively inhibited, the required thickness of the shallow trench isolation can be reduced, and the reliability of the device is improved.

Description

Semiconductor device and manufacture method thereof
Technical field
The present invention relates to a kind of semiconductor device and manufacture method thereof, particularly relate to and a kind ofly can effectively suppress parasitic channel effect and can reduce three-dimensional multi-gate FinFET and the manufacture method thereof of shallow trench isolation from desired thickness.
Background technology
In current sub-20nm technology, three-dimensional multi-gate device (FinFET or Tri-gate) is main device architecture, this structural reinforcing grid control ability, suppressed electric leakage and short-channel effect.
For example, the MOSFET of double gate SOI structure is compared with traditional single grid body Si or SOI MOSFET, can suppress short-channel effect (SCE) and leak to cause induced barrier reduction (DIBL) effect, there is lower junction capacitance, can realize raceway groove light dope, can carry out adjusting threshold voltage by the work function that metal gates is set, can obtain the drive current of approximately 2 times, reduce the requirement for effective gate oxide thickness (EOT).And tri-gate devices is compared with double-gated devices, grid has surrounded channel region end face and two sides, and grid control ability is stronger.Further, loopful has more advantage around nano wire multiple-grid device.
Existing FinFET structure and manufacture method generally include: in body Si or SOI substrate, etching forms the multiple parallel fin and the grooves that extend along first direction; In groove, fill insulant forms shallow trench isolation from (STI); At fin top and side wall deposition be generally thinner (for example only 1～5nm) false grid insulating barrier of silica, on false grid insulating barrier, deposition is generally the false grid layer of polysilicon, amorphous silicon; Etching false grid layer and false grid insulating barrier, form the false grid extending along second direction stacking, and wherein second direction is preferably perpendicular to first direction; Be stacked as mask with false grid, fin carried out to shallow doping formation lightly doped drain structure (LDD) and cause induced barrier reduction effect to suppress leakage; Both sides along first direction deposition the etching stacking at false grid form grid curb wall; On the fin of the both sides along first direction of grid curb wall, the identical or close material of epitaxial growth forms source-drain area, preferably adopt SiGe, SiC etc. higher than the material of Si stress to improve carrier mobility; On wafer, deposit interlayer dielectric layer (ILD); It is stacking that etching is removed false grid, leaves gate trench in ILD; In gate trench, deposit the gate insulator of high k material and the grid conducting layer of metal/metal alloy/metal nitride.Further, etching ILD forms drain contact hole, source; In order to reduce source-drain contact resistance, in drain contact hole, source, form metal silicide; Fill metal/metal nitride and form contact plug.
But for example, along with FinFET technology node continues reduction (22nm is following), STI thickness is corresponding to be reduced, the insulation isolation effect variation between fin and STI makes easily to occur causing component failure by parasitic channel between the fin below STI.
Summary of the invention
From the above mentioned, the object of the invention is to overcome above-mentioned technical difficulty, propose a kind of new FinFET structure and manufacture method thereof, can effectively suppress parasitic channel effect and can reduce shallow trench isolation from desired thickness.
For this reason, the invention provides a kind of method, semi-conductor device manufacturing method, comprising: on substrate, form the multiple fins and the groove that extend along first direction; In groove, form separator; In fin and/or fin and substrate interface place form break-through barrier layer; Etching separator is with expose portion fin, residue separator form shallow trench isolation from.
Wherein, the step of formation fin and groove further comprises: on substrate, form hard mask layer; Taking hard mask layer as mask, etched substrate forms fin and groove.
Wherein, the step that forms break-through barrier layer further comprises: carry out Implantation, make the element injecting be distributed in fin and/or fin and substrate interface place; Annealing, makes the element injecting react formation break-through barrier layer with fin and/or substrate.
Wherein, the element of injection at least comprises oxygen.
Wherein, the element of injection also comprises N, C, F, P, Cl, As, B, In, Sb, Ga, Si, Ge and combination thereof.
Wherein, form shallow trench isolation from after further comprise: on fin, form along the false grid of second direction extension stacking; The side along first direction stacking at false grid forms grid curb wall and source-drain area; On device, form interlayer dielectric layer; Removal false grid is stacking, leaves gate trench in interlayer dielectric layer; In gate trench, form gate stack; Etching interlayer dielectric layer forms the contact hole in source of exposure drain region; In contact hole, form metal silicide and contact plug.
Wherein, source-drain area comprises epitaxially grown lifting source-drain area.
The present invention also provides a kind of semiconductor device, comprising: multiple fins, are positioned on substrate and along first direction and extend; Shallow trench isolation from, between multiple fins; Break-through barrier layer, is arranged in fin and/or fin and substrate interface place.
Wherein, break-through barrier layer is high-doped zone.
Wherein, in high-doped zone, doping has N, C, F, P, Cl, As, B, In, Sb, Ga, Si, Ge and combination thereof.
Wherein, break-through barrier layer is silica.
According to semiconductor device of the present invention and manufacture method thereof, in fin and shallow trench isolation from below form break-through barrier layer, effectively suppressed parasitic channel effect and can reduce shallow trench isolation from desired thickness, thereby improved device reliability.
Brief description of the drawings
Describe technical scheme of the present invention in detail referring to accompanying drawing, wherein:
Fig. 1 to Fig. 9 is the generalized section according to the each step of FinFET manufacture method of the present invention;
Figure 10 is according to FinFET device architecture perspective view of the present invention.
Embodiment
The feature and the technique effect thereof that describe technical solution of the present invention in detail referring to accompanying drawing and in conjunction with schematic embodiment, disclose and can effectively suppress parasitic channel effect and can reduce three-dimensional multi-gate FinFET and the manufacture method thereof of shallow trench isolation from desired thickness.It is pointed out that structure like similar Reference numeral representation class, term " first " used in the application, " second ", " on ", D score etc. can be used for modifying various device architectures or manufacturing process.These modify the space, order or the hierarchical relationship that not imply unless stated otherwise institute's modification device architecture or manufacturing process.
It should be noted that, each accompanying drawing middle and upper part part is that device is along (the fin bearing of trend of first direction in Figure 10 below, bearing of trend is leaked in source, also be Y-Y ' axis) cutaway view, mid portion is that device is along second direction (gate stack bearing of trend, perpendicular to first direction, also be X-X ' axis) the cutaway view of gate stack center line, bottom part is device along being parallel to second direction and being positioned at the cutaway view that the position (being also X1-X1 ' axis) that (has certain distance on first direction) outside gate stack obtains.
As shown in Figure 1, form the groove 1G between multiple fin structure 1F and the fin structure extending along first direction on substrate 1, wherein first direction is following device channel region bearing of trend (Y-Y ' axis in Figure 10).Substrate 1 is provided, substrate 1 needs and choose reasonable according to device purposes, can comprise monocrystalline silicon (Si), monocrystal germanium (Ge), strained silicon (Strained Si), germanium silicon (SiGe), or compound semiconductor materials, for example gallium nitride (GaN), GaAs (GaAs), indium phosphide (InP), indium antimonide (InSb), and carbon back semiconductor for example Graphene, SiC, carbon nanotube etc.For with the consideration of CMOS process compatible, substrate 1 is preferably body Si.Preferably, on substrate 1, form hard mask 2 by the process deposits such as LPCVD, PECVD, material is for example silica, silicon nitride, silicon oxynitride and combination thereof.Taking hard mask 2 as mask, photoetching/etched substrate 1 forms the fin 1F that between multiple groove 1G along the parallel distribution of first direction and groove 1G, remaining substrate 1 material forms in substrate 1.The preferred anisotropic etching of etching, for example plasma dry etching, reactive ion etching (RIE) or Tetramethylammonium hydroxide (TMAH) wet etching, make the depth-to-width ratio of groove 1G be preferably more than 5:1.
As shown in Figure 2, in the groove 1G between fin 1F by PECVD, HDPCVD, RTO(rapid thermal oxidation), to fill material be for example the separator 3 of silica, silicon oxynitride, silicon hydroxide, organic substance etc. to the process deposits such as spin coating, FlowCVD.Preferably, after Fig. 2, before Fig. 3, further carry out CMP, return the flatening process such as quarters, to separator 3 planarizations until exposure hard mask layer 2.
As shown in Figure 3, below separator 3, in substrate 1, form STI break-through barrier layer (STI PTSL) 4.After hard mask layer 2 is exposed in the planarization of structure shown in Fig. 2, carry out Implantation, can comprise N, C, F, P, Cl, As, B, In, Sb, Ga, Si, Ge etc. and combination thereof.Carry out subsequently annealing, for example, at 500～1200 degrees Celsius of lower heat treatment 1ms～10min, the element injecting is reacted with fin 1F and substrate 1, form the break-through barrier layer 4 of highly doped (doped with the silica of above-mentioned element).In one embodiment of the invention, control Implantation Energy and dosage, make break-through barrier layer 4 be only distributed in fin 1F bottom with substrate 1 interface as STI break-through barrier layer 4A, be enough to effectively completely cut off the leakage current between channel region in fin 1F, source-drain area and adjacent fin active area.But, in another preferred embodiment of the present invention, control Implantation Energy and dosage, make except layer 4A, also further in fin 1F, form channel punchthrough barrier layer 4B, as shown in Figure 3, further to suppress channel region by the leakage of STI side.Layer 4B material can be identical with layer 4A material, also can comprise the different component (but at least comprising oxygen) in above-mentioned element.Layer 4B can form (different elements inject degree of depth difference) from simultaneously disposable injection of layer 4A, also can be successively the injection of twice different depth, dosage, for example first dark distance is injected and is formed a layer 4A, rear shallow distance is injected and is formed a layer 4B, vice versa.In addition,, except above-mentioned highly doped break-through barrier layer, also can inject a large amount of oxygen (O) to form silica-based insulating barrier using as break-through barrier layer (above-mentioned impurity also can further adulterate in this silicon oxide layer).It should be noted that channel punchthrough barrier layer 4B can set arbitrarily apart from the height at fin 1F top (or bottom), is preferably 1/3～1/2 of fin 1F oneself height in one embodiment of the invention.STI break-through barrier layer 4A and channel punchthrough barrier layer 4B thickness are for example 5～30nm.The width of layer 4A (along first and/or second direction) set according to whole device active region width, the width of layer 4B is identical with fin 1F, also the width of layer 4A is obviously greater than the width of layer 4B.
As shown in Figure 4, selective etch separator 3, forms groove 1G again, exposes a fin 1F part.Can adopt photoetching offset plate figure or other hard mask graphs, select anisotropic lithographic method, for example plasma dry etching, RIE, etching separator 3, makes remaining separator 3 form shallow trench isolation from (STI) 3.Preferably, the degree of depth of groove 1G, is also the distance at STI3 distance from top fin 1F top, is more than or equal to the distance at 4B distance from top fin 1F top, channel punchthrough barrier layer, to suppress the break-through between channel region completely.Subsequently, wet etching has been removed hard mask 2.
As shown in Figure 5, form the false grid stacked structure 5 extending along second direction at fin 1F top.On whole device, form false grid insulating barrier 5A and false grid material layer 5B by techniques such as LPCVD, PECVD, HDPCVD, UHVCVD, MOCVD, MBE, ALD, thermal oxidation, chemical oxidation, evaporation, sputters, and preferably further comprise hard mask layer 5C.Layer 5A is for example silica, and layer 5B is for example polysilicon, amorphous silicon, amorphous carbon, silicon nitride etc., and layer 5C is for example silicon nitride.To there is the mask plate perpendicular to the rectangular aperture of the second direction of first direction, photoetching/etching (similarly successively, etching is anisotropic, preferably plasma dry etching, RIE) hard mask layer 5C, false grid material layer 5B and false grid insulating barrier 5A, form the false grid stacking 5 extending along second direction at fin 1F top.As shown in Fig. 5 top and middle part, the stacking 5(5C/5B/5A of false grid) be only distributed in along within the scope of the certain width of X-X ' axis, X1-X1 ' the axis place outside certain distance does not distribute.
As shown in Figure 6, form side wall 6 at the sidewall of multiple false grids stacking 5.Preferably, form side wall before first taking false grid stacking 5 as mask, light dope is carried out in fin 1F top, comprise the shallow injection of multi-angle or molecular dopant, diffusing, doping etc., formed lightly-doped source drain region (LDD structure) 1LS and 1LD at fin 1F top.Subsequently, on whole device, form spacer material layer 6 by techniques such as LPCVD, PECVD, HDPCVD, UHVCVD, MOCVD, MBE, ALD, evaporation, sputters, its material such as silicon nitride, silicon oxynitride, silica, containing silicon oxide carbide, amorphous carbon, low-k materials, diamond like carbon amorphous carbon (DLC) etc. and combination thereof.In one embodiment of the invention, preferred nitrogen SiClx.Subsequently, adopt the etching technics of the anisotropy (sidewall and bottom etch rate ratio are as being more than or equal to 1:3) that isotropism or side etching are less, the RIE that for example adjusts carbon fluorine base gas carbon fluorine ratio makes the over etching (over-etch for sidewall and bottom, OE) less, leave side wall 6 at the sidewall along first direction of false grid stacking 5.Subsequently alternatively, on fin 1F, leaked 1HS and 1HD by epitaxial growth lifting source on the region outside stacking 5 cover parts of false grid.For example, by techniques such as PECVD, MOCVD, MBE, ALD, thermal decomposition, evaporation, sputters, above fin 1F top light doping section 1LS and 1LD, epitaxial growth promotes drain region 1HD and promotes source region 1HS.Wherein, promoting source-drain area 1HS/1HD material can be identical with substrate 1, fin 1F, for example, be Si, also can material difference, for example there is more heavily stressed SiGe, Si:C, Si:H, SiSn, GeSn, SiGe:C etc. and combination thereof.Preferably, when leak in epitaxial growth lifting source, carry out carrying out Implantation and heavy doping after in-situ doped or extension, make lifting source leak 1HD/1HS and there is the impurity concentration of leaking 1LD/1LS higher than lightly-doped source.Subsequently, annealing is to activate the impurity of doping.
As shown in Figure 7, on whole device, form contact etching stop layer (CESL) 7A and interlayer dielectric layer (ILD) 7B.Preferably, first on device, can omit by the contact etching stop layer 7A(of the technique formation silicon nitrides such as PECVD, HDPCVD, sputter).Subsequently, by spin coating, spraying, silk screen printing, CVD, the techniques such as PVD form silica, the ILD7B of low-k materials, wherein low-k materials includes but not limited to organic low-k materials (for example containing the organic polymer of aryl or polynary ring), inorganic low-k materials (for example amorphous carbon nitrogen film, polycrystalline boron nitrogen film, fluorine silex glass, BSG, PSG, BPSG), porous low k material (for example two silicon three oxygen alkane (SSQ) hole, Quito low-k materials, porous silica, porous SiOCH, mix C silicon dioxide, mix F porous amorphous carbon, porous diamond, porous organo polysilica compound).Subsequently, adopt CMP, return quarters etc. technique planarization ILD7B and hard mask layer 5C until the false grid material layer 5B of exposure false grid stacking 5.
As shown in Figure 8, remove false grid stacking 5, in ILD7B, leave gate trench 7G.Can adopt wet etching, for example hot phosphoric acid is for silicon nitride, TMAH is for polysilicon, amorphous silicon, strong acid (sulfuric acid, nitric acid) and strong oxidizer (ozone, hydrogen peroxide) combine for amorphous carbon, DLC, HF base corrosive liquid (dilution HF or BOE, BOE is slowly-releasing etching agent, NH4F and HF mixed solution) is for silica, remove thus false grid material layer 5B and false grid insulating barrier 5A, until expose fin 1F top.In addition, also can adopt the anisotropic dry etching X-X ' axis of second direction (only along), regulate the proportioning of carbon fluorine base gas, make bottom etch rate be greater than sidewall etch rate (etching ratio is as being greater than 5:1 preferred 10～15:1), etching forms the gate trench 7G of vertical sidewall pattern thus.
As shown in Figure 9, in gate trench 7G, form gate stack 8.Adopt the techniques such as PECVD, HDPCVD, MOCVD, MBE, ALD, evaporation, sputter, in gate trench 7G, formed gate stack 8.Gate stack 8 at least comprises the gate insulator 8A of high k material and the grid conducting layer 8B of metal_based material.High k material includes but not limited to comprise and is selected from HfO 2, HfSiO x, HfSiON, HfAlO x, HfTaO x, HfLaO x, HfAlSiO x, HfLaSiO xhafnium sill (wherein, each material is according to multi-element metal component proportion and chemical valence difference, and oxygen atom content x can rationally adjust, for example can be 1～6 and be not limited to integer), or comprise and be selected from ZrO 2, La 2o 3, LaAlO 3, TiO 2, Y 2o 3rare earth based high K dielectric material, or comprise Al 2o 3, with the composite bed of its above-mentioned material.Grid conducting layer 6B can be polysilicon, poly-SiGe or metal, wherein metal can comprise metal simple-substance or the alloy of these metals and the nitride of these metals such as Co, Ni, Cu, Al, Pd, Pt, Ru, Re, Mo, Ta, Ti, Hf, Zr, W, Ir, Eu, Nd, Er, La, also can be doped with elements such as C, F, N, O, B, P, As with regulatory work function in grid conducting layer 8B.The barrier layer (not shown) that also preferably forms nitride between grid conducting layer 8B and gate insulator 8A by conventional methods such as PVD, CVD, ALD, barrier layer material is M xn y, M xsi yn z, M xal yn z, M aal xsi yn z, wherein M is Ta, Ti, Hf, Zr, Mo, W or other element.
After this, can adopt rear grid technique further to complete device manufacture (following parts are all not shown).For example, adopt the techniques such as PECVD, evaporation, sputter to form the cap rock of silicon nitride, and adopt method planarized gate stacking 9 and the cap rock such as CMP, time quarter, until expose ILD7B.On device, form the 2nd ILD, and etching the 2nd ILD forms the drain contact hole, source that exposes lifting source leakage 1HD/1HS.Evaporation in contact hole, sputter, MOCVD, MBE, ALD form metal level (not shown), metal and the metal alloys such as its material such as Ni, Pt, Co, Ti, W.1ms～the 10min that anneals under 250～1000 degrees Celsius, makes Si element reaction contained in metal or metal alloy and source-drain area form metal silicide, to reduce contact resistance.By techniques such as PECVD, MOCVD, evaporation, sputters, in contact hole, form metal, metal alloy and metal nitride thereof, wherein metal can comprise W, Al, Ti, Au, Ag, Mo, Cu and combination thereof.Each layer of metal straight of planarization, to exposing the 2nd ILD, formed contact plug.
The final device architecture perspective view forming as shown in figure 10, cutaway view as shown in Figure 9, device comprises: the multiple fins that extend along first direction on substrate, extend (crossing with first direction and preferably vertical) and crossed over the grid of each fin along second direction, be positioned at grid along the grid curb wall on the fin of the both sides of first direction and source-drain area, wherein, in fin and/or fin and substrate interface place has break-through barrier layer.All the other all parts structures and parameter, material all describe in detail in method, do not repeat them here.
According to semiconductor device of the present invention and manufacture method thereof, in fin and shallow trench isolation from below form break-through barrier layer, effectively suppressed parasitic channel effect and can reduce shallow trench isolation from desired thickness, thereby improved device reliability.
Although with reference to one or more exemplary embodiments explanation the present invention, those skilled in the art can know without departing from the scope of the invention device architecture is made to various suitable changes and equivalents.In addition, can make and manyly may be suitable for the amendment of particular condition or material and not depart from the scope of the invention by disclosed instruction.Therefore, object of the present invention does not lie in and is limited to as the disclosed specific embodiment for realizing preferred forms of the present invention, and disclosed device architecture and manufacture method thereof will comprise all embodiment that fall in the scope of the invention.

Claims (11)

1. a method, semi-conductor device manufacturing method, comprising:
On substrate, form the multiple fins and the groove that extend along first direction;
In groove, form separator;
In fin and/or fin and substrate interface place form break-through barrier layer;
Etching separator is with expose portion fin, residue separator form shallow trench isolation from.
2. method, semi-conductor device manufacturing method as claimed in claim 1, wherein, the step that forms fin and groove further comprises: on substrate, form hard mask layer; Taking hard mask layer as mask, etched substrate forms fin and groove.
3. method, semi-conductor device manufacturing method as claimed in claim 1, wherein, the step that forms break-through barrier layer further comprises: carry out Implantation, make the element injecting be distributed in fin and/or fin and substrate interface place; Annealing, makes the element injecting react formation break-through barrier layer with fin and/or substrate.
4. method, semi-conductor device manufacturing method as claimed in claim 3, wherein, the element of injection comprises N, C, F, P, Cl, As, B, In, Sb, Ga, Si, Ge and combination thereof.
5. method, semi-conductor device manufacturing method as claimed in claim 3, wherein, the element of injection comprises oxygen.
6. method, semi-conductor device manufacturing method as claimed in claim 1, wherein, form shallow trench isolation from after further comprise:
On fin, form the false grid extending along second direction stacking;
The side along first direction stacking at false grid forms grid curb wall and source-drain area;
On device, form interlayer dielectric layer;
Removal false grid is stacking, leaves gate trench in interlayer dielectric layer;
In gate trench, form gate stack;
Etching interlayer dielectric layer forms the contact hole in source of exposure drain region;
In contact hole, form metal silicide and contact plug.
7. method, semi-conductor device manufacturing method as claimed in claim 6, wherein, source-drain area comprises epitaxially grown lifting source-drain area.
8. a semiconductor device, comprising:
Multiple fins, are positioned on substrate and along first direction and extend;
Shallow trench isolation from, between multiple fins;
Break-through barrier layer, is arranged in fin and/or fin and substrate interface place.
9. semiconductor device as claimed in claim 8, wherein, break-through barrier layer is high-doped zone.
10. semiconductor device as claimed in claim 9, wherein, high-doped zone comprises N, C, F, P, Cl, As, B, In, Sb, Ga, Si, Ge and combination thereof.
11. semiconductor device as claimed in claim 8, wherein, break-through barrier layer is silica.
CN201310142130.4A 2013-04-22 2013-04-22 Semiconductor device and method for manufacturing the same Pending CN104112666A (en)

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US9735155B2 (en) 2015-12-14 2017-08-15 International Business Machines Corporation Bulk silicon germanium FinFET
CN107919325A (en) * 2016-10-10 2018-04-17 中芯国际集成电路制造(上海)有限公司 The manufacture method of fin formula field effect transistor
CN108574009A (en) * 2017-03-07 2018-09-25 中芯国际集成电路制造(上海)有限公司 Fin field effect pipe and forming method thereof

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Application publication date: 20141022