CN104218081A - Semiconductor device and manufacture method thereof - Google Patents

Semiconductor device and manufacture method thereof Download PDF

Info

Publication number
CN104218081A
CN104218081A CN201310215648.6A CN201310215648A CN104218081A CN 104218081 A CN104218081 A CN 104218081A CN 201310215648 A CN201310215648 A CN 201310215648A CN 104218081 A CN104218081 A CN 104218081A
Authority
CN
China
Prior art keywords
gate
source
layer
gate stack
metal layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201310215648.6A
Other languages
Chinese (zh)
Inventor
殷华湘
钟汇才
朱慧珑
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Institute of Microelectronics of CAS
Original Assignee
Institute of Microelectronics of CAS
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Institute of Microelectronics of CAS filed Critical Institute of Microelectronics of CAS
Priority to CN201310215648.6A priority Critical patent/CN104218081A/en
Publication of CN104218081A publication Critical patent/CN104218081A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66515—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned selective metal deposition simultaneously on the gate and on source or drain
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

The invention discloses a semiconductor device and a manufacture method thereof. The semiconductor device comprises a substrate, a gate stack arranged on the substrate, a source region, a drain region and a metal contact layer; the source region and the drain region are arranged on two sides of the gate stack; the metal contact layer is arranged on the source region and the drain region. The source-drain contact structure is controlled through self-alignment of isolation structures on the sides of a gate, source-drain contact resistance is effectively decreased, and reliability of the semiconductor device is improved meanwhile.

Description

Semiconductor device and manufacture method thereof
Technical field
The present invention relates to a kind of semiconductor device and manufacture method thereof, particularly relate to a kind of three-dimensional multi-gate FinFET and the manufacture method thereof with fully self aligned contact structures.
Background technology
In current sub-20nm technology, three-dimensional multi-gate device (FinFET or Tri-gate) is main device architecture, and this structure enhances grid control ability, inhibits electric leakage and short-channel effect.
Such as, the MOSFET of double gate SOI structure is compared with traditional single grid body Si or SOI MOSFET, short-channel effect (SCE) can be suppressed and leak to cause induced barrier reduction (DIBL) effect, there is lower junction capacitance, raceway groove light dope can be realized, adjusting threshold voltage can be carried out by the work function arranging metal gates, the drive current of about 2 times can be obtained, reduce the requirement for effective gate oxide thickness (EOT).And tri-gate devices is compared with double-gated devices, gate wraps channel region end face and two sides, grid control ability is stronger.Further, loopful has more advantage around nano wire multi-gate device.
Existing FinFET structure and manufacture method generally include: in body Si or SOI substrate, etching forms multiple parallel fin along first direction extension and groove; Ion implantation or dopant deposition layer performed to fin and anneals, in the middle part of fin, forming break-through barrier layer (PTSL) to suppress parasitic channel effect; Fill insulant in the trench, returns and carves with exposed portion fin, forms shallow trench isolation from (STI); Be generally thinner (such as only 1 ~ 5nm) false grid insulating barrier of silica at fin top and side wall deposition, on false grid insulating barrier, deposition is generally the false grid layer of polysilicon, amorphous silicon; Etching false grid layer and false grid insulating barrier, form the false grid extended along second direction stacking, wherein second direction is preferably perpendicular to first direction; Be stacked as mask with false grid, shallow doping formation lightly doped drain structure (LDD) carried out to fin and reduces effect to suppress leakage to cause induced barrier; Deposit in the both sides along first direction that false grid is stacking and etch and form grid curb wall; At the fin Epitaxial growth of the both sides along first direction of grid curb wall, identical or similar materials formation source-drain area, preferably adopts SiGe, SiC etc. higher than the material of Si stress to improve carrier mobility; Preferably, source-drain area is formed contact etching stop layer (CESL); At deposition on wafer interlayer dielectric layer (ILD); It is stacking that etching removes false grid, in ILD, leave gate trench; The gate insulator of deposited high-k material (HK) and the grid conducting layer of metal/metal alloy/metal nitride (MG) in gate trench, and the gate cap preferably including nitride material is to protect metal gates.Further, mask etching ILD is utilized to form source and drain contact hole, source of exposure drain region.Alternatively, in order to reduce source-drain contact resistance, in source and drain contact hole, form metal silicide.Fill metal/metal nitride and form contact plug, preferably filling rate is higher usually metal W, Ti.Due to the existence of CESL, grid curb wall, the metal W of filling, Ti meeting auto-alignment source-drain area, finally form contact plug, therefore this contact hole and contact plug structure are also referred to as self-aligned contacts (SAC).
But, it should be noted that in above-mentioned self aligned source and drain contact hole (SAC) etching process, because characteristic size continual reductions is to below 22nm, can also correspondingly for the region area forming contact hole reduce accordingly, this etching for contact hole proposes high requirement.Particularly when the ILD needed for device isolation insulation is thicker, need to improve the Etch selectivity of ILD and the grid curb wall of contiguous nitride silicon based material thus form the contact hole of high-aspect-ratio (HAR), these needs strictly accurately control etch process parameters.On the other hand, need too when etching contact hole to guarantee that contiguous contact isolation structure (grid curb wall, contact etching stop layer, ILD etc.) is not substantially etched thus improves reliability.
In sum, the manufacture method of existing SAC and adjacent isolation structures cannot effectively be guaranteed accurately control line size and guarantee reliability, urgently improves.
Summary of the invention
From the above mentioned, the object of the invention is to overcome above-mentioned technical difficulty, propose a kind of new FinFET structure and manufacture method thereof, by the self-aligned contact structure realizing low-resistivity of Simplified flowsheet low cost.
For this reason, the invention provides a kind of method, semi-conductor device manufacturing method, comprising: the source-drain area forming gate stack, gate stack both sides on substrate; Device forms interlayer dielectric layer, covers source-drain area and gate stack; Interlayer dielectric layer forms mask graph, there is opening, expose gate stack; With gate stack and mask graph for mask, etching interlayer dielectric layer, forms source and drain contact hole, source of exposure drain region; In source and drain contact hole, form contact metal layer, wherein adjacent contact metal layer is by gate stack automatism isolation.
Wherein, the step of formation grid, source-drain area comprises further: along multiple fin of first direction extension and groove on substrate; In the trench formed shallow trench isolation from; Fin forms the false grid extended along second direction stacking; The side along first direction stacking at false grid forms grid curb wall and source-drain area.
Wherein, comprise further after forming interlayer dielectric layer: remove false grid stacking, leave gate trench; Final gate stack is formed in gate trench.
Wherein, comprise taking a step forward of mask graph of formation: return and carve gate stack formation gate recess; Gate cap is formed in gate recess.
Wherein, comprise forming taking a step forward of interlayer dielectric layer: the contact etching stop layer forming the stacking and source-drain area of cover gate on device.
Wherein, gate stack comprises gate insulator, grid conducting layer, and is positioned at the grid curb wall of gate insulator and grid conducting layer side.
Wherein, the opening size of mask graph is greater than the size of source and drain contact hole.
Wherein, contact metal layer comprises the second contact metal layer of the first contact metal layer and top thereof.Wherein, the resistivity of the first contact metal layer is higher than the resistivity of the second contact metal layer.
Present invention also offers a kind of semiconductor device, comprise the contact metal layer on the gate stack on substrate, substrate, the source-drain area of gate stack both sides and source-drain area, it is characterized in that: contact metal layer is by gate stack automatism isolation.
Wherein, substrate has the shallow trench isolation between multiple fin and fin extended along first direction and extend from, gate stack along second direction and span each fin, source-drain area is positioned at gate stack along on the fin of the both sides of first direction.
Wherein, contact metal layer comprises the second contact metal layer of the first contact metal layer and top thereof.Wherein, the resistivity of the first contact metal layer is higher than the resistivity of the second contact metal layer.
Wherein, gate stack comprises gate insulator, grid conducting layer, and is positioned at the grid curb wall of gate insulator and grid conducting layer side.
Wherein, gate cap is comprised further above grid conducting layer.
Wherein, gate stack side comprises contact etching stop layer further.
Wherein, the first contact metal layer end face flushes with gate stack or gate cap end face.
According to semiconductor device of the present invention and manufacture method thereof, controlled the pattern of source and drain contact by the isolation structure autoregistration of gate side, effectively reduce source-drain contact resistance, and improve device reliability simultaneously.
Accompanying drawing explanation
Technical scheme of the present invention is described in detail referring to accompanying drawing, wherein:
Fig. 1 to Figure 15 is the generalized section according to each step of FinFET manufacture method of the present invention;
Figure 16 is the perspective schematic view according to FinFET of the present invention; And
Figure 17 is the indicative flowchart according to FinFET manufacture method of the present invention.
Embodiment
Describe feature and the technique effect thereof of technical solution of the present invention in detail in conjunction with schematic embodiment referring to accompanying drawing, disclose and can effectively reduce source-drain contact resistance and the three-dimensional multi-gate FinFET and the manufacture method thereof that improve device reliability simultaneously.It is pointed out that structure like similar Reference numeral representation class, term " first " used in the application, " second ", " on ", D score etc. can be used for modifying various device architecture or manufacturing process.These modify the space of not hint institute's modification device architecture or manufacturing process unless stated otherwise, order or hierarchical relationship.
It should be noted that, each accompanying drawing middle and upper part part is that device is along (the fin bearing of trend of first direction in Figure 16 below, source and drain bearing of trend, also i.e. Y-Y ' axis) cutaway view, mid portion is that device is along second direction (gate stack bearing of trend, perpendicular to first direction, also i.e. X-X ' axis) the cutaway view of gate stack center line, low portion is device along being parallel to second direction and being positioned at the cutaway view that the position that (first direction has certain distance) outside gate stack (also i.e. X1-X1 ' axis) obtains.
As shown in Figure 1, form the groove 1G between multiple fin structure 1F and fin structure extended along first direction on substrate 1, wherein first direction is future device channel region bearing of trend (Y-Y ' axis in Figure 16).Substrate 1 is provided, substrate 1 needs and choose reasonable according to device application, monocrystalline silicon (Si), monocrystal germanium (Ge), strained silicon (Strained Si), germanium silicon (SiGe) can be comprised, or compound semiconductor materials, such as gallium nitride (GaN), GaAs (GaAs), indium phosphide (InP), indium antimonide (InSb), and carbon-based semiconductors such as Graphene, SiC, carbon nanotube etc.For the consideration with CMOS technology compatibility, substrate 1 is preferably body Si.Preferably, form hard mask 2 on substrate 1 by process deposits such as LPCVD, PECVD, material is such as silica, silicon nitride, silicon oxynitride and combination thereof.With hard mask 2 for mask, photoetching/etched substrate 1, forms the fin 1F that between multiple groove 1G along the parallel distribution of first direction and groove 1G, remaining substrate 1 material is formed in substrate 1.Etch preferred anisotropic etching, such as plasma dry etch, reactive ion etching (RIE) or Tetramethylammonium hydroxide (TMAH) wet etching, make the depth-to-width ratio of groove 1G be preferably more than 5:1.
As shown in Figure 2, by PECVD, HDPCVD, RTO(rapid thermal oxidation in the groove 1G between fin 1F), spin coating, the process deposits such as FlowCVD fill the separator 3 that material is such as silica, silicon oxynitride, silicon hydroxide, organic substance etc.Preferably, after Fig. 2, taking a step forward of Fig. 3 perform CMP, return the flatening process such as quarters, to separator 3 planarization until exposure hard mask layer 2.
As shown in Figure 3, in fin 1F and/or bottom form STI break-through barrier layer (STIPTSL) 4.After hard mask layer 2 is exposed in the planarization of structure shown in Fig. 2, perform ion implantation, N, C, F, P, Cl, As, B, In, Sb, Ga, Si, Ge etc. and combination thereof can be comprised.Perform annealing subsequently, such as at 500 ~ 1200 degrees Celsius of lower heat treatment 1ms ~ 10min, the element of injection and fin 1F are reacted, forms the break-through barrier layer 4 of (such as doped with the silica of above-mentioned element) of highly doped (Si of doping above-mentioned material) or insulating material.In an embodiment of the invention, control Implantation Energy and dosage, only in fin 1F, define channel punchthrough barrier layer 4B, as shown in Figure 3, with the leakage suppressing channel region to pass through STI side.But, in another preferred embodiment of the present invention, control Implantation Energy and dosage, make break-through barrier layer 4 to be also distributed in bottom fin 1F with substrate 1 interface as STI break-through barrier layer 4A, with channel region in effectively isolated fin 1F, leakage current between source-drain area and adjacent fin active area.Layer 4B material can be identical with layer 4A material, also can comprise the different component (but at least comprising oxygen) in above-mentioned element.Layer 4B can be formed (it is different that different element injects the degree of depth) from layer 4A simultaneously disposable injection, also can the injection of successively twice different depth, dosage, and such as can first dark distance inject and form layer 4A, rear shallow distance injection formation layer 4B, vice versa.In addition, except above-mentioned highly doped break-through barrier layer, a large amount of oxygen (O) can also be injected to form the silica-based insulating barrier of oxidation using as break-through barrier layer (also can adulterate in this silicon oxide layer above-mentioned impurity further).It should be noted that the height of channel punchthrough barrier layer 4B distance fin 1F top (or bottom) can set arbitrarily, be preferably 1/3 ~ 1/2 of fin 1F oneself height in an embodiment of the invention.STI break-through barrier layer 4A and channel punchthrough barrier layer 4B thickness are such as 5 ~ 30nm.The width of layer 4A (along first and/or second direction) set according to whole device active region width, namely the width of layer 4B is then identical with fin 1F, and also the width of layer 4A is obviously greater than the width of layer 4B.
As shown in Figure 4, selective etch separator 3, forms groove 1G again, exposes a fin 1F part.Can adopt photoetching offset plate figure or other hard mask graphs, select anisotropic lithographic method, such as plasma dry etch, RIE, etching separator 3, makes remaining separator 3 constitute shallow trench isolation from (STI) 3.Preferably, the degree of depth of groove 1G, is also the distance at STI3 distance from top fin 1F top, is more than or equal to the distance at 4B distance from top fin 1F top, channel punchthrough barrier layer, to suppress the break-through between channel region completely.Subsequently, wet etching eliminates hard mask 2.
As shown in Figure 5, the false grid stacked structure 5 extended along second direction is formed at fin 1F top.Whole device forms false grid insulating barrier 5A and false grid material layer 5B by techniques such as LPCVD, PECVD, HDPCVD, UHVCVD, MOCVD, MBE, ALD, thermal oxidation, chemical oxidation, evaporation, sputterings, and preferably comprises hard mask layer 5C further.Layer 5A is such as silica, and layer 5B is such as polysilicon, amorphous silicon, amorphous carbon, silicon nitride etc., and layer 5C is such as silicon nitride.To have the mask plate of the rectangular aperture of the second direction perpendicular to first direction, photoetching/etching (similarly successively, etching is anisotropic, preferred plasma dry etch, RIE) hard mask layer 5C, false grid material layer 5B and false grid insulating barrier 5A, the false grid stacking 5 extended along second direction is formed at fin 1F top.As shown in Fig. 5 top and middle part, the stacking 5(5C/5B/5A of false grid) be only distributed in along within the scope of the one fixed width of X-X ' axis, X1-X1 ' the axis place outside certain distance does not distribute.
As shown in Figure 6, side wall 6 is formed at the sidewall of multiple false grid stacking 5.Preferably, before forming side wall, elder generation is with false grid stacking 5 for mask, carries out light dope, comprises the shallow injection of multi-angle or molecular dopant, diffusing, doping etc., define lightly-doped source drain region (LDD structure) 1LS and 1LD at fin 1F top to fin 1F top.Subsequently, whole device forms spacer material layer 6 by the technique such as LPCVD, PECVD, HDPCVD, UHVCVD, MOCVD, MBE, ALD, evaporation, sputtering, its material such as silicon nitride, silicon oxynitride, silica, containing silicon oxide carbide, amorphous carbon, low-k materials, diamond like carbon amorphous carbon (DLC) etc. and combination thereof.In an embodiment of the invention, preferred nitrogen SiClx.Subsequently, isotropism or side is adopted to etch the etching technics of less anisotropy (sidewall and bottom etch rate ratio are as being more than or equal to 1:3), such as the RIE of adjustment carbon fluorine base gas carbon fluorine ratio makes the over etching (over-etch for sidewall and bottom, OE) less, leave side wall 6 at the sidewall along first direction of false grid stacking 5.Subsequently alternatively, fin 1F is promoted source and drain 1HS and 1HD by the region Epitaxial growth outside stacking 5 cover parts of false grid.Such as by techniques such as PECVD, MOCVD, MBE, ALD, thermal decomposition, evaporation, sputterings, above light doping section 1LS and 1LD of fin 1F top, epitaxial growth promotes drain region 1HD and promotes source region 1HS.Wherein, promoting source-drain area 1HS/1HD material can be identical with substrate 1, fin 1F, such as, be Si, also can material different, such as there is more heavily stressed SiGe, Si:C, Si:H, SiSn, GeSn, SiGe:C etc. and combination thereof.Preferably, epitaxial growth promote carry out in-situ doped or extension while source and drain after carry out ion implantation and heavy doping, make to promote source and drain 1HD/1HS and there is impurity concentration higher than light dope source and drain 1LD/1LS.Subsequently, the impurity activating doping is annealed.
As shown in Figure 7, whole device is formed contact etching stop layer (CESL) 7A and interlayer dielectric layer (ILD) 7B.Preferably, first can be omitted by the contact etching stop layer 7A(of the technique formation silicon nitrides such as PECVD, HDPCVD, sputtering on device).Subsequently, pass through spin coating, spraying, silk screen printing, CVD, the techniques such as PVD form silica, the ILD7B of low-k materials, wherein low-k materials includes but not limited to organic low-k materials (such as containing the organic polymer of aryl or polynary ring), inorganic low-k material (such as amorphous carbon nitrogen film, polycrystalline boron nitrogen film, fluorine silex glass, BSG, PSG, BPSG), porous low k material (such as two silicon three oxygen alkane (SSQ) hole, Quito low-k materials, porous silica, porous SiOCH, mix C silicon dioxide, mix F porous amorphous carbon, porous diamond, porous organic polymer).Subsequently, adopt CMP, return the technique planarization ILD7B and hard mask layer 5C such as quarter until expose the false grid material layer 5B of false grid stacking 5.
As shown in Figure 8, remove false grid stacking 5, form gate trench 7C.Remove false grid stacking 5, wet etching can be adopted, such as hot phosphoric acid is for silicon nitride, TMAH is for polysilicon, amorphous silicon, and strong acid (sulfuric acid, nitric acid) and strong oxidizer (ozone, hydrogen peroxide) combination are for amorphous carbon, DLC, HF base corrosive liquid (dilution HF or BOE, BOE is slowly-releasing etching agent, NH4F and HF mixed solution) for silica, remove false grid material layer 5B and false grid insulating barrier 5A thus, until expose fin 1F top.In addition, also anisotropic dry etching (only along the X-X ' axis of second direction) can be adopted, regulate the proportioning of carbon fluorine base gas, make bottom etch rate be greater than sidewall etch rate (etching ratio is such as greater than 5:1 and preferred 10 ~ 15:1), etching forms the gate trench (not shown) of vertical sidewall pattern thus.
As shown in Figure 9, subsequently, adopt the techniques such as PECVD, HDPCVD, MOCVD, MBE, ALD, evaporation, sputtering, in gate trench 7C, define gate stack 8.Gate stack 8 at least comprises the gate insulator 8A of high-g value and the grid conducting layer 8B of metal_based material.High-g value includes but not limited to comprise and is selected from HfO 2, HfSiO x, HfSiON, HfAlO x, HfTaO x, HfLaO x, HfAlSiO x, HfLaSiO xhafnium sill (wherein, each material is different according to multi-element metal component proportion and chemical valence, and oxygen atom content x can Reasonable adjustment, such as, can be 1 ~ 6 and be not limited to integer), or comprise and be selected from ZrO 2, La 2o 3, LaAlO 3, TiO 2, Y 2o 3rare earth based high K dielectric material, or comprise Al 2o 3, with the composite bed of its above-mentioned material.Grid conducting layer 8B then can be polysilicon, poly-SiGe or metal, wherein metal can comprise the alloy of the metal simple-substances such as Co, Ni, Cu, Al, Pd, Pt, Ru, Re, Mo, Ta, Ti, Hf, Zr, W, Ir, Eu, Nd, Er, La or these metals and the nitride of these metals, also can doped with elements such as C, F, N, O, B, P, As with regulatory work function in grid conducting layer 8B.Also form the barrier layer (not shown) of nitride between grid conducting layer 8B and gate insulator 8A preferably by conventional methods such as PVD, CVD, ALD, barrier layer material is M xn y, M xsi yn z, M xal yn z, M aal xsi yn z, wherein M is Ta, Ti, Hf, Zr, Mo, W or other element.
As shown in Figure 10, at gate stack 8(8B) upper formation gate cap 8C.Preferably, anisotropic lithographic method is adopted to return quarter (etch-back) gate stack 8 particularly grid conducting layer 8B, gate recess is again formed (not shown in ILD7B, its degree of depth is less than grid conducting layer 8B thickness, such as only 1 ~ 10nm), in gate recess, fill gate cap 8C by LPCVD, PECVD, HDPCVD, evaporation, sputtering etc. common process subsequently.Layer 8C is used for the grill-protected stacks top when etching source and drain contact hole after a while and does not weather, preferably harder silicon nitride, silicon oxynitride, DLC, amorphous carbon etc. and combination thereof.Subsequently, cmp planarization metallization processes processing layer 8C is adopted until expose ILD7B.
As shown in figure 11, ILD7B is formed mask graph 9(can be exposure/photoetching formed photoetching offset plate figure, or silica, low k material formed hard mask layer figure), for limiting the position of source and drain contact hole.Mask graph 9 has opening 9A, exposes ILD7B top, and below is namely following needs the region forming source and drain contact hole, is also directly over source-drain area 1HS, 1HD.From Figure 11 top, mask graph opening 9A at least exposes the region above lifting source and drain 1HS/1HD, and preferably also expose gate stack 8A ~ 8C, in other words, mask graph opening 9A can adopt large scale photoetching/lithographic technique to be formed, such as i Lithography or UV photoetching, and need not e-beam lithography be adopted.It is consuming time that this is conducive to reducing costs shortening technique.In a preferred embodiment of the invention, opening 9A has the size being more than or equal to active area (not shown) in domain.
As shown in figure 12, etch ILD7B further, form the source and drain contact hole 7D of source of exposure drain region 1HS, 1HD.Preferably, adopt anisotropic etch process, such as plasma dry etch or RIE, etching ILD7B is to form the hole 7D with reduced size.In the process, because grid conducting layer 8B and gate insulator 8A is by parcels such as CESL7A, grid curb wall 6, gate cap 8C, therefore etch source and drain contact hole (and the metal level of sedimentary origin drain contact after a while) time without the need to worrying that gate stack 8 suffers erosion, affects, also without the need to applying extra meticulous mask, but the mask of the large-size shown in Figure 11 can be adopted, also namely the size of opening 9A is greater than the size of source and drain contact hole 7D.Therefore, the technique of the etching source and drain contact hole shown in Figure 11,12 is self aligned.In a preferred embodiment of the invention, ILD7B is silica base material matter, and CESL7A, grid curb wall 6 and gate cap 8C are nitride silicon based material, therefore can be easy be controlled etch rate by adjustment etching gas proportioning (in such as carbon fluorine base gas C, F atom number ratio) thus improved Etch selectivity, utilizes the etching stop layer of these layers as contact hole of nitride silicon based material.
As shown in figure 13, in source and drain contact hole 7D, the first contact metal layer 10A is formed.Such as by techniques such as MOCVD, MBE, ALD, evaporation, sputterings, define the first contact metal layer 10A.The preferred ductility of layer 10A is better, filling rate is higher and the material of relatively low cost, such as, comprise the metals such as W, Ti, Pt, Ta, Mo, the alloy of these metals and the corresponding nitride of these metals.The resistivity layer 10B relatively after a while of layer 10A is larger.Subsequently, adopt CMP, return the technique planarization first contact metal layer 10A such as quarter, until expose the CESL layer 7A at stacking 5 tops of false grid.In addition, preferably, before packed layer 10A, preferably on source-drain area, metal silicide (not shown) is formed to reduce contact resistance.Such as, evaporate in the contact hole, sputter, MOCVD, MBE, ALD form metal level (not shown), metal and the metal alloys such as its material such as Ni, Pt, Co, Ti, W.Anneal 1ms ~ 10min under 250 ~ 1000 degrees Celsius, makes Si element reaction contained in metal or metal alloy and source-drain area form metal silicide, to reduce contact resistance.As shown in Figure 13 top, the top of the first contact metal layer 10A flushes with the top of gate cap 8C, and adjacent self-aligned contacts (SAC) region realizes isolation by gate stack 8 and side wall thereof, CESL, is conducive to improving precision, Simplified flowsheet.
As shown in figure 14, whole device forms final top layer ILD7E.Similar with ILD7B, pass through spin coating, spraying, silk screen printing, CVD, the techniques such as PVD form silica, the ILD7E of low-k materials, wherein low-k materials includes but not limited to organic low-k materials (such as containing the organic polymer of aryl or polynary ring), inorganic low-k material (such as amorphous carbon nitrogen film, polycrystalline boron nitrogen film, fluorine silex glass, BSG, PSG, BPSG), porous low k material (such as two silicon three oxygen alkane (SSQ) hole, Quito low-k materials, porous silica, porous SiOCH, mix C silicon dioxide, mix F porous amorphous carbon, porous diamond, porous organic polymer).Preferably, each ILD layer 7B, 7E material is identical.Subsequently, in ILD7E, again form the source and drain contact hole 7F of exposure first contact metal layer 10A.
As shown in figure 15, the second contact metal layer 10B is formed in the source and drain contact hole 7F in ILD7E layer.Such as form the second contact metal layer 10B by techniques such as MOCVD, MBE, ALD, evaporation, sputterings.The material of layer 10B is different from layer 10A, the metal of preferred low resistivity.Layer 10A directly and silicon or Metal-silicides Contact, therefore pays the utmost attention to the material that filling rate is high, bond strength is high; Layer 10B contacts with the layer 10A of metal, therefore can pay the utmost attention to the material that resistivity is low, cost is low.In an embodiment of the invention, the material of the second contact metal layer 10B comprises the metals such as Cu, Al, Ag, Au, the alloy of these metals and the nitride of these metals.Subsequently, planarization layer 10B is until expose ILD7E.By the height/thickness of control ILD7E, the thickness of end layer 10B can be controlled.Preferably, make the end face of layer 10B higher than the end face of gate cap 8C in gate stack 8, to provide good low resistance source drain contact.
The device architecture perspective view of final formation as shown in figure 16, cutaway view as shown in figure 15, device comprises: along multiple fins that first direction extends on substrate, extend (crossing with first direction and preferably vertical) along second direction and span the gate stack of each fin, be positioned at grid along the source-drain area on the fin of the both sides of first direction, source-drain area has contact metal layer, and wherein, contact metal layer is by gate stack automatism isolation.Gate stack comprises gate insulator, grid conducting layer and gate cap, and gate stack also has grid curb wall and/or contact etching stop layer along the both sides of first direction.Wherein, contact metal layer comprises the first contact metal layer, and the end face of the first contact metal layer flushes with the end face of gate stack; First contact metal layer also has the second contact metal layer, and the end face of the second contact metal layer is higher than the end face (effectively can increase the volume of contacting metal thus reduce resistance) of gate stack; First contact metal layer is different from the second contact metal layer material.Preferably, the resistivity of the second contact metal layer is lower than the first contact metal layer (can improve filling rate and adhesion by the W layer of the high resistivity of bottom, reduce contact resistance by the Cu layer of the low-resistivity on upper strata).In addition, in fin and/or fin and substrate interface place has break-through barrier layer.All the other all parts structures and parameter, material all describe in detail in method, do not repeat them here.
In addition, although list FinFET in the embodiment of the present invention exemplarily, but technical scheme of the present invention also may be used for various planar MOSFET, as long as the contact of its source and drain comprises the different metal of upper and lower two layer resistivities.
According to semiconductor device of the present invention and manufacture method thereof, controlled the pattern of source and drain contact by the isolation structure autoregistration of gate side, effectively reduce source-drain contact resistance, and improve device reliability simultaneously.
Although the present invention is described with reference to one or more exemplary embodiment, those skilled in the art can know without the need to departing from the scope of the invention and make various suitable change and equivalents to device architecture.In addition, can be made by disclosed instruction and manyly may be suitable for the amendment of particular condition or material and not depart from the scope of the invention.Therefore, object of the present invention does not lie in and is limited to as realizing preferred forms of the present invention and disclosed specific embodiment, and disclosed device architecture and manufacture method thereof will comprise all embodiments fallen in the scope of the invention.

Claims (17)

1. a method, semi-conductor device manufacturing method, comprising:
Substrate is formed the source-drain area of gate stack, gate stack both sides;
Device forms interlayer dielectric layer, covers source-drain area and gate stack;
Interlayer dielectric layer forms mask graph, there is opening, expose gate stack;
With gate stack and mask graph for mask, etching interlayer dielectric layer, forms source and drain contact hole, source of exposure drain region;
In source and drain contact hole, form contact metal layer, wherein adjacent contact metal layer is by gate stack automatism isolation.
2. method, semi-conductor device manufacturing method as claimed in claim 1, wherein, the step of formation grid, source-drain area comprises further:
Along multiple fin of first direction extension and groove on substrate;
In the trench formed shallow trench isolation from;
Fin forms the false grid extended along second direction stacking;
The side along first direction stacking at false grid forms grid curb wall and source-drain area.
3. method, semi-conductor device manufacturing method as claimed in claim 2, wherein, comprises after forming interlayer dielectric layer: remove false grid stacking, leave gate trench further; Final gate stack is formed in gate trench.
4. method, semi-conductor device manufacturing method as claimed in claim 1, wherein, comprises taking a step forward of mask graph of formation: return and carve gate stack formation gate recess; Gate cap is formed in gate recess.
5. method, semi-conductor device manufacturing method as claimed in claim 1, wherein, comprises forming taking a step forward of interlayer dielectric layer: the contact etching stop layer forming the stacking and source-drain area of cover gate on device.
6. method, semi-conductor device manufacturing method as claimed in claim 1, wherein, gate stack comprises gate insulator, grid conducting layer, and is positioned at the grid curb wall of gate insulator and grid conducting layer side.
7. method, semi-conductor device manufacturing method as claimed in claim 1, wherein, the opening size of mask graph is greater than the size of source and drain contact hole.
8. method, semi-conductor device manufacturing method as claimed in claim 1, wherein, contact metal layer comprises the second contact metal layer of the first contact metal layer and top thereof.
9. method, semi-conductor device manufacturing method as claimed in claim 8, wherein, the resistivity of the first contact metal layer is higher than the resistivity of the second contact metal layer.
10. a semiconductor device, comprises the contact metal layer on the gate stack on substrate, substrate, the source-drain area of gate stack both sides and source-drain area, it is characterized in that: contact metal layer is by gate stack automatism isolation.
11. as the semiconductor device of claim 10, wherein, substrate has the shallow trench isolation between multiple fin and fin extended along first direction extend from, gate stack along second direction and span each fin, source-drain area is positioned at gate stack along on the fin of the both sides of first direction.
12. as the semiconductor device of claim 10, and wherein, contact metal layer comprises the second contact metal layer of the first contact metal layer and top thereof.
13. as the semiconductor device of claim 12, and wherein, the resistivity of the first contact metal layer is higher than the resistivity of the second contact metal layer.
14. as the semiconductor device of claim 10, and wherein, gate stack comprises gate insulator, grid conducting layer, and is positioned at the grid curb wall of gate insulator and grid conducting layer side.
15., as the semiconductor device of claim 14, wherein, comprise gate cap above grid conducting layer further.
16. as the semiconductor device of claim 14, and wherein, gate stack side comprises contact etching stop layer further.
17. as the semiconductor device of claim 12 or 14, and wherein, the first contact metal layer end face flushes with gate stack or gate cap end face.
CN201310215648.6A 2013-05-31 2013-05-31 Semiconductor device and manufacture method thereof Pending CN104218081A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201310215648.6A CN104218081A (en) 2013-05-31 2013-05-31 Semiconductor device and manufacture method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201310215648.6A CN104218081A (en) 2013-05-31 2013-05-31 Semiconductor device and manufacture method thereof

Publications (1)

Publication Number Publication Date
CN104218081A true CN104218081A (en) 2014-12-17

Family

ID=52099401

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201310215648.6A Pending CN104218081A (en) 2013-05-31 2013-05-31 Semiconductor device and manufacture method thereof

Country Status (1)

Country Link
CN (1) CN104218081A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105336787A (en) * 2014-08-15 2016-02-17 中国科学院微电子研究所 Semiconductor device and manufacturing method therefor
CN107039335A (en) * 2016-02-03 2017-08-11 中芯国际集成电路制造(上海)有限公司 The forming method of semiconductor structure
CN110797255A (en) * 2019-10-14 2020-02-14 长江存储科技有限责任公司 Thin film stack structure, three-dimensional memory and preparation method thereof

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6869850B1 (en) * 2002-12-20 2005-03-22 Cypress Semiconductor Corporation Self-aligned contact structure with raised source and drain
CN101068018A (en) * 2006-05-05 2007-11-07 台湾积体电路制造股份有限公司 Semiconductor device
US20100327363A1 (en) * 2008-05-22 2010-12-30 Panasonic Corporation Semiconductor device and method for fabricating the same
CN102024784A (en) * 2009-09-22 2011-04-20 台湾积体电路制造股份有限公司 Block contact plugs for mos devices
US20110147812A1 (en) * 2009-12-23 2011-06-23 Steigerwald Joseph M Polish to remove topography in sacrificial gate layer prior to gate patterning
CN102569396A (en) * 2010-12-29 2012-07-11 中国科学院微电子研究所 Transistor and manufacturing method thereof
US20120187505A1 (en) * 2011-01-25 2012-07-26 International Business Machines Corporation Self-aligned III-V MOSFET fabrication with in-situ III-V epitaxy and in-situ metal epitaxy and contact formation
CN102938416A (en) * 2011-08-16 2013-02-20 中国科学院微电子研究所 Semiconductor device and manufacturing method thereof

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6869850B1 (en) * 2002-12-20 2005-03-22 Cypress Semiconductor Corporation Self-aligned contact structure with raised source and drain
CN101068018A (en) * 2006-05-05 2007-11-07 台湾积体电路制造股份有限公司 Semiconductor device
US20100327363A1 (en) * 2008-05-22 2010-12-30 Panasonic Corporation Semiconductor device and method for fabricating the same
CN102024784A (en) * 2009-09-22 2011-04-20 台湾积体电路制造股份有限公司 Block contact plugs for mos devices
US20110147812A1 (en) * 2009-12-23 2011-06-23 Steigerwald Joseph M Polish to remove topography in sacrificial gate layer prior to gate patterning
CN102569396A (en) * 2010-12-29 2012-07-11 中国科学院微电子研究所 Transistor and manufacturing method thereof
US20120187505A1 (en) * 2011-01-25 2012-07-26 International Business Machines Corporation Self-aligned III-V MOSFET fabrication with in-situ III-V epitaxy and in-situ metal epitaxy and contact formation
CN102938416A (en) * 2011-08-16 2013-02-20 中国科学院微电子研究所 Semiconductor device and manufacturing method thereof

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105336787A (en) * 2014-08-15 2016-02-17 中国科学院微电子研究所 Semiconductor device and manufacturing method therefor
CN107039335A (en) * 2016-02-03 2017-08-11 中芯国际集成电路制造(上海)有限公司 The forming method of semiconductor structure
CN107039335B (en) * 2016-02-03 2019-09-27 中芯国际集成电路制造(上海)有限公司 The forming method of semiconductor structure
CN110797255A (en) * 2019-10-14 2020-02-14 长江存储科技有限责任公司 Thin film stack structure, three-dimensional memory and preparation method thereof

Similar Documents

Publication Publication Date Title
US9627214B2 (en) Stratified gate dielectric stack for gate dielectric leakage reduction
CN105470135B (en) Method, semi-conductor device manufacturing method
US8853788B2 (en) Replacement gate electrode with planar work function material layers
CN104112665B (en) Semiconductor devices and its manufacturing method
CN105489652B (en) Semiconductor devices and its manufacturing method
CN105428361B (en) Cmos device and its manufacturing method
CN105489651B (en) Semiconductor devices and its manufacturing method
CN105470133B (en) Method, semi-conductor device manufacturing method
CN103035712A (en) Semiconductor component and manufacture method thereof
CN104112667B (en) Semiconductor devices and its manufacturing method
CN105470256A (en) Cmos device and manufacturing method thereof
CN104124164B (en) Semiconductor devices and its manufacturing method
CN103811543B (en) Semiconductor devices and its manufacturing method
CN104124198B (en) Semiconductor devices and its manufacturing method
CN104112666A (en) Semiconductor device and manufacturing method thereof
CN104218081A (en) Semiconductor device and manufacture method thereof
CN105470136B (en) Method, semi-conductor device manufacturing method
CN104112668B (en) Semiconductor devices and its manufacturing method
CN103579315A (en) Semiconductor device and manufacturing method thereof
CN105336787B (en) Semiconductor devices and its manufacturing method
CN104143534B (en) Method, semi-conductor device manufacturing method
CN104332406A (en) Semiconductor device and manufacturing method thereof
CN104217949A (en) Semiconductor device and manufacture method thereof
CN105470286B (en) Semiconductor devices and its manufacturing method
CN105529327B (en) Cmos device and its manufacturing method

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
RJ01 Rejection of invention patent application after publication

Application publication date: 20141217

RJ01 Rejection of invention patent application after publication